JPH0833328A - Switching power supply - Google Patents

Abstract

PURPOSE:To realize a stabilized control by employing signals, each having a pulse width increasing or decreasing by an integral multiple of a minimum unit width, as the control signals for the input voltage to the primary winding and the voltage induced in the secondary winding. CONSTITUTION:An FET Q1 is switched by a PWM1 signal from a PWM control circuit 101 to induce a voltage V2 in the secondary winding N2. The voltage V2 is then divided through a voltage division circuit W1 and applied to an FBINI terminal. The level of divided voltage is determined for every output pulse of the PWM1 signal and the pulse width thereof is increased or decreased by a multiple of minimum width based on the level thus determined. On the other hand, an FET Q2 and a transistor Q3 are switched based on PWM signals from a PWM control circuit 104 and a synchronism detection circuit 103 to induce a voltage V1 in the secondary winding N3. The voltage V1 is then divided by resistors R3, R4 and the level of divided voltage is determined. Subsequently, the pulse width of the PWM signal is increased or decreased by an integral multiple of the minimum unit width based on the determined level thus realizing a stabilized control.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching power supply for controlling a voltage input to a primary winding and a voltage induced in a secondary winding of a transformer by a pulse width modulation method.

[0002]

2. Description of the Related Art Conventionally, there is a switching power supply that controls a voltage input to a primary winding of a transformer and a voltage induced in a secondary winding thereof by an analog pulse width modulation method.

There is also an attempt to digitize the control of the input voltage of the primary winding, but the control of the induced voltage of the secondary winding is an analog control because of the difficulty of making the control digital. Alternatively, a control method such as simple on / off control is used.

[0004]

However, if the above control method is used for controlling the induced voltage in the secondary winding, the control becomes unstable due to noise or the like. Further, the analog control is inferior in reliability such that a predetermined voltage cannot be obtained, and the cost required for the configuration of the analog control circuit is high.
Furthermore, it is difficult to synchronize the primary side and the secondary side. Furthermore, in combination with CPU etc.
If the CPU and the analog control circuit are incorporated into one chip so that the induced voltage on the secondary side can be controlled, the selection yield is lowered and the process is complicated, resulting in a very high manufacturing cost of the chip. .

An object of the present invention is to provide a switching power supply which can form an inexpensive control circuit and can perform stable control.

[0006]

According to the first aspect of the present invention,
A transformer having a primary winding and at least one secondary winding is provided, and a pulse width modulation method is applied to a voltage input to the primary winding and a voltage induced in the secondary winding. In a switching power supply that is controlled by each of the switching power supplies, as a control signal for the voltage input to the primary winding and the induced voltage of the secondary winding, a signal whose pulse width increases or decreases by an integral multiple of the minimum unit width is supplied. It is characterized by using.

According to a second aspect of the invention, in the switching power supply according to the first aspect, the control signal for the primary winding and the control signal for the secondary winding are synchronized with each other. To do.

According to a third aspect of the present invention, in the switching power supply according to the first or second aspect, the pulse width of the control signal for the secondary winding is the pulse width of the control signal for the primary winding. It is characterized by increasing and decreasing by an integral multiple of the minimum unit width within the period specified by.

According to a fourth aspect of the present invention, in the switching power supply according to the first or second aspect, the pulse width of the control signal for the secondary winding is the pulse width of the control signal for the primary winding. Within the period specified by and 1
It is characterized in that it is increased / decreased by an integral multiple of the minimum unit width with reference to the rising edge of the control signal for the secondary winding.

According to a fifth aspect of the present invention, in the switching power supply according to the first or second aspect, the pulse width of the control signal for the secondary winding is based on the rise of a synchronization signal supplied from the outside. It is characterized by increasing and decreasing by an integral multiple of the minimum unit width.

According to a sixth aspect of the present invention, in the switching power supply according to the fifth aspect, the synchronizing signal is synchronized with a control signal for the primary winding.

According to a seventh aspect of the present invention, in the switching power supply according to the fifth aspect, the synchronization signal is treated as an invalid signal for a predetermined period.

The invention according to claim 8 is the invention according to claim 3, 4, or 6.
Alternatively, in the switching power supply described in 7, the increase or decrease in the pulse width of the control signal for the primary winding is based on the voltage induced in the secondary winding or the partial voltage thereof induced in the secondary winding according to the switching operation for the primary winding. The pulse width of the control signal for the secondary winding is increased or decreased depending on the result of the comparison between either one and the reference voltage. The control for the secondary winding by the switching operation of the primary winding is determined according to the result of the comparison between one and the reference voltage for the one when the switching operation of the primary winding is ON. Is an on / off control in which the secondary side winding is controlled by a switching operation.
It is characterized in that the switching operation of the primary winding is an on-on control which is an on operation when the switching operation is on.

[0014]

In the switching power supply according to claim 1, a signal whose pulse width is an integral multiple of the minimum unit width is used as a control signal for the voltage input to the primary winding and the induced voltage in the secondary winding. Are used respectively.

In the switching power supply according to claim 2, 1
The control signal for the secondary winding and the control signal for the secondary winding are synchronized with each other.

In the switching power supply according to claim 3, 2
The pulse width of the control signal for the secondary winding increases or decreases by an integral multiple of the minimum unit width within the period defined by the pulse width of the control signal for the primary winding.

In the switching power supply according to claim 4, 2
The pulse width of the control signal for the secondary winding is within a period specified by the pulse width of the control signal for the primary winding and is an integral multiple of the minimum unit width with reference to the rising edge of the control signal for the primary winding. Increase or decrease.

In the switching power supply according to claim 5, 2
The pulse width of the control signal for the secondary winding increases or decreases by an integral multiple of the minimum unit width with reference to the rising edge of the synchronization signal supplied from the outside.

According to another aspect of the switching power supply of the present invention, the synchronizing signal is synchronized with the control signal for the primary winding.

In the switching power supply according to the seventh aspect, the synchronizing signal is treated as an invalid signal for a predetermined period.

In the switching power supply according to claim 8, 1
Comparison between the reference voltage corresponding to either the voltage or its partial voltage induced in the secondary winding according to the switching operation of the primary winding when the pulse width of the control signal for the secondary winding increases or decreases. The increase or decrease of the pulse width of the control signal for the secondary winding depends on the result of the comparison between either the induced voltage of the secondary winding or the divided voltage thereof and the reference voltage. Is determined by the switching operation of the primary winding, the control for the secondary winding is 1
The switching operation of the secondary winding is performed by on / off control that turns off when the switching operation of the secondary winding is on, and the switching operation of the secondary winding is controlled by the switching operation. When you turn on
It is performed by ON control.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 shows a first switching power supply of the present invention.
It is a block diagram which shows the structure of an Example.

As shown in FIG. 1, the switching power supply of this embodiment comprises a converter transformer (hereinafter referred to as a transformer) T1. The transformer T1 has a primary winding N1
And two secondary windings N2, N3.

The positive terminal of the DC power supply DC for supplying the voltage Vin is connected to one end of the primary winding N1.
The-terminal is connected to the reference potential. This voltage Vin
For example, a voltage obtained by full-wave rectifying a commercial power source and smoothing it with a capacitor C0 can be considered.

At the other end of the primary winding N1, the drain of the FET Q1 which is a switching element and the capacitor C1 are connected.
One end of is connected. The source of the FET Q1 and the other end of the capacitor C1 are connected to the reference potential. FE
The gate of TQ1 is connected to the output terminal of the drive circuit 102.

A diode D3 is provided at one end of the secondary winding N2.
Is connected to the anode and the other end is connected to a common reference potential (hereinafter, COM potential). A voltage V2 is induced in the secondary winding N2 according to the ratio with the number of windings of the primary winding N1.

The positive terminal of the smoothing capacitor C3 is connected to the cathode of the diode D3, and the negative terminal of the capacitor C3 is connected to the COM potential.

The voltage dividing circuit W1 arranged in parallel with the capacitor C3 is connected to the cathode of the diode D3. The voltage dividing circuit W1 divides the voltage V2 and outputs the divided voltage value to the PWM control circuit 101 as a feedback signal.

The PWN control circuit 101 has an input terminal FBI.
A feedback signal from the voltage dividing circuit W1 is taken in via N1, and a pulse signal whose pulse width is controlled (hereinafter referred to as PWM1 signal) is generated based on this feedback signal. The pulse width of the PWM1 signal is controlled to increase / decrease to an integral multiple of the minimum unit width according to the level of the feedback signal. PWM1 signal is output terminal PWM1O
Drive circuit 102 and synchronization detection circuit 103 via UT
Is output to In the present embodiment, the PWM control circuit 101 provided with the input terminal FBIN2 and the output terminal PWM2OUT is used as a spare terminal.

The drive circuit 102 turns on / off the FET Q1 based on the PWM1 signal, that is, performs a switching operation. The switching operation is performed so that the time defined by the ON pulse width of the PWM1 signal becomes the ON time of the FET Q1.

The synchronization detection circuit 103 is a PWM control circuit 1
The output timing of the PWM1 signal from 01 is detected, and a synchronization detection signal indicating the detection result is generated.

A diode D1 is provided at one end of the secondary winding N3.
Is connected to the anode and the other end is connected to the COM potential. A voltage V1 is induced in the secondary winding N3 according to the ratio with the number of windings of the primary winding N1.

The drain of the MOSFET Q2, which is a switching element, and one end of the resistor R1 are connected to the cathode of the diode D1. The source of the MOSFET Q2 includes a cathode of a flywheel diode D2 (hereinafter referred to as a diode D2) and a choke coil L1.
One end of is connected. The other end of the resistor R1 and one end of the resistor R2 are connected to the gate of the MOSFET Q2. The anode of the diode D2 is connected to the COM potential.

The + terminal of the smoothing capacitor C2 is connected to the other end of the choke coil L1. Capacitor C
The-terminal of 2 is connected to the COM potential.

The other end of the choke coil L1 is connected to one end of a resistor R3 arranged in parallel with the output capacitor C2, and the other end of the resistor R3 is connected to one end of a resistor R4. The other end of the resistor R4 is connected to the COM potential.

The resistors R3 and R4 cooperate with each other to divide the voltage V1, and the divided voltage is the Vin signal 10
It is taken into the PWM control circuit 104 as b. PWM
The control circuit 104 generates a pulse signal (hereinafter referred to as a PWM4 signal) whose pulse width is controlled based on the Vin signal 10b while synchronizing with the synchronization detection signal from the synchronization detection circuit 103. That is, the PWM4 signal is generated in synchronization with the PWM1 signal, and the pulse width of the PWM4 signal is controlled so as to increase or decrease to an integral multiple of the minimum unit width according to the level of the feedback signal. The PWM control circuit 104 cooperates with the synchronization detection circuit 103 to form a main synchronization sub PWM control circuit.

The PWM4 signal is given as a V (ct1) signal to the base of the transistor Q3 for driving the MOSFET Q2. As a protection measure for the transistor Q3, inserting a resistor in the base circuit of the transistor Q3 may be considered. The collector of the transistor Q3 is connected to the other end of the resistor R2, and its emitter is C
It is connected to the OM potential. Transistor Q3 is V
The on / off operation is performed based on the (ct1) signal, and the MOSFET Q2 performs a switching operation with the on / off operation of the transistor Q3. The time defined by the ON pulse width of the V (ct1) signal is the ON operation time of the transistor Q3, that is, the ON operation time of the MOSFET Q2.

Next, the main operation of the switching power supply of this embodiment will be described.

The FETQ1 performs a switching operation by the PWM1 signal from the PWM control circuit 101, and the FETQ1
The switching operation of 1 induces the voltage V2 in the secondary winding N2. The voltage V2 is divided by the voltage dividing circuit W1, and the divided voltage is FBI of the PWM control circuit 101.
It is given to the N1 terminal. PWM control circuit 101 is PWM
Judge the level of the divided voltage for each pulse output of 1 signal,
Based on the result of the determination, the pulse width of the PMW1 signal is controlled to increase or decrease by an integral multiple of the minimum unit width. This P
Feedback control described later is executed by controlling the pulse width of the WM1 signal, and a stable output voltage V2 is obtained.

On the other hand, the main synchronous sub-PWM composed of the PWM control circuit 104 and the synchronous detection circuit 103.
The PWM4 signal from the control circuit causes the FET Q2 and the transistor Q3 to perform a switching operation, and this switching operation induces a voltage V1 in the secondary winding N3. The voltage V1 is divided by the resistors R3 and R4,
This divided voltage is given to the PWM control circuit 104 as the Vin signal 10b. PWM control circuit 104 is PWM4
The level of the Vin signal 10b is determined for each pulse output of the signal, and the pulse width of the PMW4 signal is controlled to increase or decrease by an integral multiple of the minimum unit width based on the result of the determination.
Feedback control described later is executed by controlling the pulse width of the PWM4 signal, and a stable output voltage V1 is obtained.

Next, the configuration of the PWM control circuit 101 will be described with reference to the drawings. 2 to 4 are PWM control circuits 10 used in the switching power supply of FIG.
2 is a block diagram showing a configuration of No. 1.

The PWM control circuit 101 is shown in FIGS.
2, two analog type (including chopper type) comparators 51a and 51b and eight latches 1 to
8 and.

The comparator 51a is provided with the level of the feedback signal fetched from the FBIN1 terminal and the reference power source 5
The voltage Vref1 from 2a is compared, and a comparison signal indicating the result of the comparison is generated. Similarly, the comparator 52b compares the level of the feedback signal fetched from the FBIN2 terminal with the voltage Vref2 from the reference power source 52b,
A comparison signal indicating the result of the comparison is generated. As described above, in this embodiment, the FBIN2 terminal is provided as a spare input terminal, and the comparator 512b is provided as a spare comparator in advance with the installation of the FBIN2 terminal. Therefore, each device, which will be described later, connected to the input side and the output side of the comparator 51b has a spare F
It is a device corresponding to the BIN2 terminal.

The output of the comparator 51a is connected to the D terminal of a D flip-flop (hereinafter referred to as DFF) 28a. The Q bar terminal of the DFF 28a is connected to one input terminal of the AND gate 33a, and the Q terminal is connected to one input terminal of the AND gate 34a. DFF
CLK1 is taken into the clock terminal of 28a. PM is applied to the other input terminal of each AND gate 33a, 34a.
The signal lines of 1ONS are respectively connected.

Similarly, the output of the comparator 51b is DF
It is connected to the D terminal of F28b. Q of DFF28b
The bar terminal is connected to one input terminal of the AND gate 33b, and the Q terminal is connected to one input terminal of the AND gate 34b. CL is used for the clock terminal of DFF28b
K2 is captured. A signal line of PM2ONS is connected to the other input terminal of each AND gate 33b, 34b.

The output terminal of the AND gate 33a is connected to one of the input terminals of the OR gate 82, and is also connected to the UP1 signal input terminal of the detection circuit (shown as detection in the drawing) 61. The output terminal of the AND gate 33b is connected to the other one of the input terminals of the OR gate 82, and is also connected to the UP2 signal input terminal of the detection circuit (shown as detection in the drawing) 62. The other input terminal of the OR gate 82 is connected to the output terminal of the AND gate 72a. One of the input terminals of the AND gate 72a is connected to the signal line of ST1, and the other input terminal is connected to the signal line of PM1ONSS.

The output terminal of the AND gate 34a is connected to one of the input terminals of the OR gate 83 and also to the DW1 signal input terminal of the detection circuit 61. The output terminal of the AND gate 34b is connected to another one of the input terminals of the OR gate 83, and the DW2 of the detection circuit 62 is connected.
It is connected to the signal input terminal. The other input terminal of the OR gate 83 is connected to the output terminal of the AND gate 71a. One of the input terminals of the AND gate 71a is connected to the signal line of ST1B, and the other input terminal is connected to the signal line of PM1ONSS.

The output terminal of the OR gate 82 is connected to the signal control terminal of the clocked buffer (hereinafter referred to as BF) 20, and the output terminal of the OR gate 83 is B.F. F. It is connected to 19 signal control terminals.

Each latch 1-8 has a CPU (not shown).
The data bus 73 of B. F. An input terminal connected to the bus line 75 connected via 25 is provided.

The output terminal of the latch 1 (PWM1ONMAX) is connected to the inverter 54, and B. F. 1
1 to the bus line 65. The output terminal of the inverter 54 has a signal control terminal connected to the signal line of PM2OFS. F. It is connected to the bus line 64 via 17. The control terminal of the latch 1 is MA
The signal line of XSET1 is connected.

The output terminal of the latch 2 (PWM2ONMAX) is connected to the inverter 55, and B. F. 1
It is connected to the bus line 65 via 2. The output terminal of the inverter 55 has a signal control terminal connected to the signal line of PM1OFS. F. It is connected to the bus line 64 via 18. The control terminal of the latch 2 is MA
The signal line of XSET2 is connected.

The output terminal of the latch 3 (PWM1ON) is connected to the input terminal of the detection circuit 61, and B. F.
It is connected to the bus line 65 via 13. The detection circuit 61 comprises a digital value 1H detection circuit, and its output terminal is input to the reset terminal of the latch 3. The control terminal of the latch 3 is connected to the output terminal of the OR gate 45. One of the input terminals of the OR gate 45 is O
The signal line of N1SET is connected, and the output terminal of the AND gate 43 is connected to the other of its input terminals. The TEST signal line is connected to one of the input terminals of the AND gate 43, and the PM1ONS signal line is connected to the other of the input terminals.

The output terminal of the latch 4 (PWM2ON) is connected to the input terminal of the detection circuit 62, and B. F.
It is connected to the bus line 65 via 14. The detection circuit 62 is a digital value 1H detection circuit, and its output terminal is input to the reset terminal of the latch 4. The control terminal of the latch 4 is connected to the output terminal of the OR gate 46. One of the input terminals of the OR gate 46 is O
The signal line of N2SET is connected, and the output terminal of the AND gate 44 is connected to the other input terminal thereof. The TEST signal line is connected to one of the input terminals of the AND gate 44, and the PM2ONS signal line is connected to the other of the input terminals.

The output terminal of the latch 5 (PWM1 OFF) is B. F. It is connected to the bus line 65 via 15. The signal line of the CPUSET1 is connected to the control terminal of the latch 5.

The output terminal of the latch 6 (PWM2 OFF) is B. F. It is connected to the bus line 65 via 16. The signal line of CPUSET2 is connected to the control terminal of the latch 6. The output terminal of the latch 3 (PWM1ON) is connected to the input terminal of the detection circuit 61, and
B. F. It is connected to the bus line 65 via 13. The detection circuit 61 comprises a digital value 1H detection circuit, and its output terminal is input to the reset terminal of the latch 3. The control terminal of the latch 3 is connected to the output terminal of the OR gate 45. The signal line of ON1SET is connected to one of the input terminals of the OR gate 45, and the output terminal of the AND gate 43 is connected to the other of the input terminals. One of the input terminals of the AND gate 43 has a TEST
Signal line is connected to the other input terminal of PM1O
The NS signal line is connected.

The output terminal of the latch 4 (PWM2ON) is connected to the input terminal of the detection circuit 62, and B. F.
It is connected to the bus line 65 via 14. The detection circuit 62 is a digital value 1H detection circuit, and its output terminal is input to the reset terminal of the latch 4. The control terminal of the latch 4 is connected to the output terminal of the OR gate 46. One of the input terminals of the OR gate 46 is O
The signal line of N2SET is connected, and the output terminal of the AND gate 44 is connected to the other input terminal thereof. The TEST signal line is connected to one of the input terminals of the AND gate 44, and the PM2ONS signal line is connected to the other of the input terminals.

The output terminal of the latch 5 (PWM1 OFF) is B. F. It is connected to the bus line 65 via 15. The signal line of the CPUSET1 is connected to the control terminal of the latch 5.

The output terminal of the latch 6 (PWM2OFF) is B. F. It is connected to the bus line 65 via 16. The signal line of CPUSET2 is connected to the control terminal of the latch 6.

The output terminal of the latch 7 is B. F. 19 is connected to the bus line 64, and the output terminal of the latch 8 is B. F. It is connected to the bus line 64 via 20.

The bus lines 64 and 65 are connected to the corresponding input terminals of the adder (adder) 63, respectively. The output terminal of the adder 63 is P via the bus line 66.
It is connected to the input terminal of the WM1 latch 9, the input terminal of the PWM2 latch 10, the signal line of ADROUT, and the bus line 66 and B. F. Bus line 7 through 74
Connected to 5. The clock terminal of adder 63 has a T
The EST signal line is connected, and the carry terminal is CRY.
The OUT signal line is connected.

The output terminal of the PWM1 latch 9 has a signal control terminal connected to the signal line of the SUM1O via the bus line 67. F. It is connected to 23. PWM
The output terminal of the AND gate 40 is connected to the control terminal of the 1-latch 9, and each input terminal of the AND gate 40 is connected to TEST.
Signal line and CHG1 signal line.

Similarly, the output terminal of the PWM2 latch 10 has the signal control terminal SUM2 via the bus line 68.
B. connected to the O signal line. F. It is connected to 24. The output terminal of the AND gate 37 is connected to the control terminal of the PWM2 latch 10, and the input terminals of the AND gate 37 are connected to the signal line of TEST and the signal line of CHG2, respectively.

Each B. F. The output terminals of 23 and 24 are connected to one of the input terminals of the digital comparator 27 via the bus line 69. Digital comparator 2
The bus line 70 is connected to the other of the input terminals of 7. The output terminal of the digital comparator 27 is connected to one of the input terminals of the OR gate 401 and to one of the input terminals of the AND gate 42.

T is connected to the other input terminal of the OR gate 401.
The IM signal line is connected, and the output terminal of the OR gate 401 is connected to one of the input terminals of the AND gate 41. SUM1O is provided on the other input terminal of the AND gate 41.
Signal line is connected, and the output terminal of the AND gate 41 is
Synchronous T flip-flop (hereinafter, T
It is connected to the T terminal of 29).

The signal line of the TSET bar is connected to the clock terminal of the TFF 29, and the Q output terminal of the TFF 29 is PM.
It is connected to the W1OUT terminal and is also connected to the timing circuit 53.

S is applied to the other input terminal of the AND gate 42.
The signal line of UM2O is connected, and the output terminal of the AND gate 42 is connected to the T terminal of the synchronous TFF 30 that performs a toggle operation.

The signal line of the TSET bar is connected to the clock terminal of the TFF 30, and the Q output terminal of the TFF 30 is PM.
It is connected to the W2OUT terminal and is also connected to the timing circuit 53.

Timing circuit 53 includes an input terminal 81 for receiving the basic clock φ. The input terminal 81 is connected to the input terminal of a divide-by-2 circuit 59 (indicated by 1/2 in the figure) and the input terminal of a delay circuit 60 (indicated by delay in the figure). Divider circuit 59 is the basic clock φ
Is divided by 2, and the divided clock is output from the output terminal. Its output terminal is connected to the free-run counter 26 clock terminal. The output terminal of the delay circuit 60 is connected to the input terminal of the inverter 58, and
It is connected to the signal line of the T signal. The delay circuit 60 is provided with an input terminal connected to the Q output terminals of the TFFs 29 and 30. The delay time that can be generated by the delay circuit 60 is a time that is equal to or less than a half cycle of 0 to φ. The output terminal of the inverter 58 is connected to the signal line of the TSET bar signal.

The timing circuit 53 uses the TSET signal, T
Along with the SET bar signal, SUM1O, SUM2O, P
M1ONSS, PM1ONS, PM2ONS, PM1O
FS, PM2OFS, PM1OFO, PM2OFO, C
Each signal of HG1ON, CHG2ON, CHG1, and CHG2 is generated. In addition, SUM2O, PM2ONS, PM
The signals 2OFS, PM2OFO, CHG2ON, and CHG2 are backup signals corresponding to the backup terminal FBIN2.

The free-run counter 26 is composed of the divide-by-2 circuit 5.
A count operation is performed based on the divided clock from 9 and the output terminal for outputting the count value is connected to the input terminal of the digital comparator 27 and the DFF via the bus line 70.
It is connected to the input terminal of 400. A signal line for the TSET signal is connected to the clock terminal of the DFF 400, and its output terminal is B. F. It is connected to the input terminals of 21, 22.

B. F. The signal control terminal 21 is connected to the signal line of CHG2, and its output terminal is connected to the bus line 64. B. F. The signal control terminal of 22 is CHG1
Is connected to the signal line and the output terminal thereof is connected to the bus line 64.

The signal line for the CRYOUT signal is the adder 63
Of the D latches 31,
It is connected to the D terminal of 32.

The L terminal of the D latch 31 is an AND gate 38.
Of the AND gate 35, and its Q output terminal is connected to one of the input terminals of the AND gate 35 and the input terminal of the inverter 56. A signal line for the PM1OFS signal and a signal line for the TSET signal are connected to the respective input terminals of the AND gate 38. The signal line of the CHG1ON signal is connected to the other input terminal of the AND gate 35, and its output terminal is B. F. 11 signal control terminals.

Similarly, the L terminal of the D latch 32 is connected to the output terminal of the AND gate 39, and its Q output terminal is connected to one of the input terminals of the AND gate 36 and the input terminal of the inverter 57. A signal line for PM2OFS signal and a signal line for TSET signal are connected to the respective input terminals of the AND gate 39. A signal line for a CHG2ON signal is connected to the other input terminal of the AND gate 36, and its output terminal is a B.G. F. It is connected to 12 signal control terminals.

The output terminal of the inverter 56 is connected to one of the input terminals of the AND gate 47. A signal line for the CHG1ON signal is connected to the other input terminal of the AND gate 47, and its output terminal is connected to one of the input terminals of the OR gate 49. To the other input terminal of the OR gate 49, signal lines of PM1OFS signal and PM1ONS signal are connected. The output terminal of the OR gate 49 is a B.O.
F. 13 signal control terminals.

The output terminal of the inverter 57 is connected to one of the input terminals of the AND gate 48. A signal line for the CHG2ON signal is connected to the other input terminal of the AND gate 48, and its output terminal is connected to one of the input terminals of the OR gate 50. To the other input terminal of the OR gate 50, signal lines of PM2OFS signal and PM2ONS signal are connected. The output terminal of the OR gate 50 is a B.O.
F. It is connected to 14 signal control terminals.

B. F. PM1O is connected to the signal control terminal of 15.
The signal line of the FO signal is connected, and B. F. A signal line of PM2OFO signal is connected to 16 signal control terminals.

B. F. The signal control terminal of 25 has a DFF8
0 Q terminal is connected, and B. F. The Q-bar output terminal of the DFF 80 is connected to the signal control terminal of 74.

The DFF 80 is an FF for setting the flag of the CPU, and the D terminal of the DFF 80 has data (I) so that the data set from the CPU can be set to the flag.
/ O) signal line, and its L terminal is connected to the signal line for the address from the CPU.

Next, the operation of the PWM control circuit 101 will be described with reference to FIGS. 5 and 6. FIG. 5 is FIG.
6 is a timing chart of signals showing the basic timing of the operation of the PWM control circuit, and FIG. 6 is a flowchart schematically showing the processing operation of the PWM control circuit of FIG.

In this description, for simplification of description, all the latches, FFs, and counters are reset to 0H (hexadecimal zero) at the start of the operation.
The level of each signal of M, ST1, and ST1B is L. At that time, the latches 3 and 4 are reset to 1 and then C
The PU sets an off value of 7H or more in the latches 5 and 6, and sets a maximum on width required for the latches 1 and 2.

The free-run counter 26 counts up from 0 by 1 and operates so as to become 0 when FFH is reached.

First, the operation of generating the PWM1 signal will be described.

Referring to FIG. 6, first, when the data of the PWM1 latch 9 matches the value of the free-run counter 26 (step S401), the value of the free-run counter 26 at the time of match (falling of the TSET signal to the DFF 400). The sum of the value latched in (1) and the ON data (data indicating the pulse width) of the generated PWM1 signal is calculated by the adder 63, and the sum is held in the PWM1 latch 9 (step S402). That is, the ON data of the generated PWM1 signal is the value held in the latch 3, and CHG1
B. at the timing of the ON signal. F. The value of the latch 3 is given to the adder 63 when 13 becomes through. The sum calculated by the adder 63 is held in the PWM1 latch 9.

Next, when the data of the PWM1 latch 9 matches the value of the free-run counter 26 (step S40)
3), the value of the free-run counter 26 when it matches (D
The adder 63 calculates the sum of the value latched at the falling edge of the TSET signal in the FF 400) and the OFF data (data indicating separation) of the PWM1 signal to be generated, and this sum is held in the PWM1 latch 9 (step S40).
4). That is, the OFF data of the PWM1 signal to be generated is the value held in the latch 5, and the B.V. F. The value of the latch 5 is given to the adder 63 by making 15 through. Adder 63
The sum calculated in step 1 is held in the PWM1 latch 9.

Similarly, when the PWM2 signal is generated, first, the data of the PWM2 latch 10 and the value of the free-run counter 26 are compared (step S401). PWM
When the data of the 2 latch 10 matches the value of the free-run counter 26, the value of the free-run counter 26 at the time of the match (the value latched by the DFF 400 at the falling edge of the TSET signal) and the on-data (pulse of the PWM 2 signal) to be generated. The sum with the data indicating the width) is calculated by the adder 63, and the sum is held in the PWM2 latch 10 (step S40).
2). That is, the ON data of the generated PWM2 signal is the value held in the latch 4, and the B.B. F. The value of the latch 4 is given to the adder 63 when 14 becomes through. Adder 63
The sum calculated in step 1 is held in the PWM2 latch 10.

Next, when the data of the PWM2 latch 10 matches the value of the free-run counter 26 (step S4
03), the sum of the value of the free-run counter 26 (the value latched by the DFF 400 at the falling edge of the TSET signal) and the off-data (data indicating the separation) of the generated PWM2 signal is calculated by the adder 63. ,
This sum is held in the PWM2 latch 10 (step S
404). That is, the OFF data of the generated PWM2 signal is the value held in the latch 6, and PM2OFO
B. at the timing of the signal. F. The value of the latch 6 is given to the adder 63 by making 16 through. The sum calculated by the adder 63 is held in the PWM2 latch 10.

In terms of timing, the value of the PWM2 latch 10 (the value latched by the DFF400 at the falling edge of the TSET bar signal) and the value of the free-run counter 26 are compared with the value of the PWM2 latch 10 at the same timing. , A sum operation with the value of the latch 4 or the latch 6 is executed by the adder 63, and the timing at which the result of the operation can be held in the PWM2 latch 10 again is set. Similarly, PWM2
At the same timing as the coincidence comparison between the value of the latch 10 and the value of the free-run counter 26, the value of the PWM1 latch 9 (DF
The sum operation of the value latched at the falling edge of the TSET bar signal in F400) and the value of the latch 3 or the latch 5 is executed by the adder 63, and the timing at which the result of the operation can be held in the PWM1 latch 9 again It is set. However, the sum calculation processing of these must be the PWM1OUT terminal,
The next timing when the output value from the PWM2OUT terminal is inverted, the timing when the coincidence signal of the digital comparator 27 does not occur, that is, as shown in FIG. 4, CHG1O
It is executed only at the timing of each signal of N, CHG2ON, PM1OFO, and PM2OFO. Therefore, the set value data of the off-time register is set to 7H or more.

In the above control, B. F. 13, 1
4, 15, 16, 21, 22, 23, and 24 are controlled so as to be switched appropriately. As a basic control signal used for this switching control, as shown in FIG.
G1ON, CHG2ON, PM1OFO, PM2OF
O, CHG1, CHG2, SUM1O, and SUM2O signals are used.

The adder 63 operates so as to hold the result of the sum of the signals applied to its input terminal at the output terminal at each rising timing of the TSET signal and output the held value to the bus line 66. That is, the adder 63 has a configuration in which the normal adder and the DFF are integrated into one module.

The PMW1 latch 9 has TSET and CHG.
The control signal obtained from the result of the logical product with 1 is given through the AND gate 40, and the PMW2 latch 10 receives T
A control signal obtained from the result of the logical product of SET and CHG2 is given through the AND gate 37. B.
F. 23 and 24 have SUM1O and SUM2O, respectively.
And the above-described control can be operated in a time division manner.

Each signal of CHG1 and CHG2 corresponds to one cycle (φ is 3) of the next TSET signal in which the output values from the PWM1OUT terminal and the PWM2OUT terminal are inverted.
When the frequency is 2 MHz, it shows a timing of 31.25 nsec) and is expressed by the following equation.

[0093]

## EQU1 ## CHG1 = CHG1ON + PM1OFO (1)

[0094]

(2) CHG2 = CHG2ON + PM2OFO (2) The comparison result of the digital comparator 27 is output to the signal line 71, and the output signals TFF2 of the AND gates 41 and 42.
Sampling is given to the T terminals of 9 and 30 at the timing of the TSET bar signal, and the output thereof is inverted, so that proper PWM1 signal and PWM2 signal are output to the PWM1OUT terminal and the PWM2OUT terminal, respectively.

In this embodiment, all the latches, counters, comparators, and adders have an 8-bit structure, but they can have an arbitrary bit size.

Further, the timing example shown in FIG.
This is an example when data of 3H is set in each of the 1 latch 9 and the PWM 2 latch 10.

Further, when initializing each circuit, first, C
The PU turns on the flag that is the output of the DFF 80 and sets the B.P.
F. 25 to the through state, and B. F. 74 is set to a high impedance state. After that, the CPU sends the data set signals generated from the address signal and the strobe signal to MAXSET1, MAXSET2, ON1SET, ON.
Initial data is set in the latches 1 to 6 via the bus lines 73 and 75 in addition to the signal lines of 2SET, CPUSET1 and CPUSET2. After setting the initial data in the latches 1 to 6, the CPU sets the flag, which is the output of the DFF 80, to “0”, and then sets the B.B. F. 74 to the through state, and B.
F. 25 is in a high impedance state.

Next, after the sum of the value of the free-run counter 26 and the OFF data (data indicating the separation) of the generated PWM1 signal or PWM2 signal is held in the PWM1 latch 9 or the PWM2 latch 10 (step S404). The pulse widths of the PWM1 signal and the PWM2 signal are controlled (steps S405 and 407). In the control of this pulse width, PM1ONS and PM2ONS during the timing when the PWM1 signal and the PWM2 signal are off, in which the comparison result of the digital comparator 27 does not show the coincidence.
The calculation by the adder 63 is executed based on

In controlling the pulse width of the PWM1 signal, the comparison result by the comparator 51a indicates that the reference voltage Vref1 is FB.
When it is lower than the signal level input to the IN1 terminal, P
It operates so as to reduce the pulse width of the WM1 signal and the signal level input to the FBIN1 terminal, and the comparison result by the comparator 51a indicates that the reference voltage Vref1 is FBIN.
When the signal level input to one terminal is higher than PWM
FBIN1 operates to increase the pulse width of one signal.
Feedback control is performed so that the signal level input to the terminal automatically vibrates.

Specifically, the output value of the comparator 51a is sampled in the DFF 28a in synchronization with CMP.CLK1 (PM1OFS can be used as a substitute), and when the output value is "H", it is output from the Q terminal of the DFF 28a. When the output becomes "H" and the output value is "L", the DFF
The output from the Q terminal of 28a becomes "L".

The output from the Q terminal of the DFF 28a is "H".
, The gates 33a, 34a, 82 and 83 cause the B.I. F.
19 is selected to enter the through state, and B. F. 20 becomes a high impedance state.

On the other hand, when the output from the Q terminal of the DFF 28a is "L", each gate 33a, 34a, 8
2, 83 at the timing when PM1ONS becomes “H”. F. 20 is selected to be in the through state, and B.
F. 19 becomes a high impedance state.

That is, when the pulse width of the PWM1 signal is increased, the sum of the register value of the latch 8 in which 01H is written and the value of the latch 3 is calculated, and the sum is written again in the latch 3, and the value of the latch 3 is calculated. Is controlled to increase by one. P
FFH of the latch 7 when reducing the pulse width of the WM1 signal
The sum of the register value in which is written and the value of the latch 3 is calculated, the sum is written in the latch 3 again, and the value of the latch 3 is controlled to be decreased by one.

In controlling the pulse width of the PWM2 signal, the comparison result by the comparator 51b indicates that the reference voltage Vref2 is FB.
When it is lower than the signal level input to the IN2 terminal, P
It operates so as to reduce the pulse width of the WM2 signal and the signal level input to the FBIN2 terminal, and the comparison result by the comparator 51b indicates that the reference voltage Vref2 is FBIN.
When the signal level input to the two terminals is higher than the PWM
FBIN2 operates to increase the pulse width of the two signals.
Feedback control is performed so that the signal level input to the terminal automatically vibrates.

Specifically, the output value of the comparator 51b is sampled by the DFF 28b in synchronization with CMP.CLK2 (PM2OFS can be substituted), and when the output value is "H", it is output from the Q terminal of the DFF 28b. When the output becomes "H" and the output value is "L", the DFF
The output from the Q terminal of 28b becomes "L".

The output from the Q terminal of the DFF 28b is "H".
, The gates 33b, 34b, 82, and 83 cause the B.2 signal at the timing when PM2ONS becomes "H". F.
19 is selected to enter the through state, and B. F. 20 becomes a high impedance state.

On the other hand, when the output from the Q terminal of the DFF 28b is "L", each gate 33b, 34b, 8
2, 83 when the PM2ONS becomes “H”. F. 20 is selected to be in the through state, and B.
F. 19 becomes a high impedance state.

That is, when the pulse width of the PWM2 signal is increased, the sum of the register value of the latch 8 in which 01H is written and the value of the latch 4 is calculated, and the sum is written again in the latch 4 to obtain the value of the latch 4. Is controlled to increase by one. P
FFH of the latch 7 when reducing the pulse width of the WM2 signal
The sum of the register value in which is written and the value of the latch 4 is calculated, the sum is written again in the latch 4, and the value of the latch 4 is controlled to be decreased by one.

At the timing for the above control, the PW
The PM1ONS signal and the TSET signal are given to the latch 3 holding the control data of the pulse width of the M1 signal via the AND gate 43 and the OR gate 45.
F. A PM1ONS signal is given to 13 via an OR gate 49.

Similarly, the PM2ONS signal and the TSET signal are sent to the AND gate 44 and the OR gate 4 with respect to the latch 4 which holds the control data of the pulse width of the PWM2 signal.
6 through B.6. F. The PM2ONS signal is supplied to 14 through the OR gate 50.

CMP / CLK1 is a sampling signal synchronized with PM1ONS, and CMP / CLK2 is PM.
Any sampling signal synchronized with 2ONS may be used.

By changing the values of the latches 7 and 8, the pulse width to be increased / decreased can be appropriately selected.

Next, when the pulse width of each PWM1 signal and PWM2 signal becomes larger than a predetermined value (step S40).
5), pulse width limitation control is performed to make the pulse widths of the PWM1 signal and the PWM2 signal equal to a predetermined value (step S406). In this pulse width limitation control, the comparison result of the digital comparator 27 does not show a match,
The calculation by the adder 63 is executed based on PM1OFS and PM2OFS during the timing when the PWM1 signal and the PWM2 signal are off.

In the pulse width limitation control for the PWM1 signal, the value of the latch 3 and the inverted value of the value of the latch 1 (value of the maximum pulse width of the PWM1 signal) are added by the adder 63 at the timing of the PM1OFS signal, and the addition is performed. If the result has a carry, the D latch 31 is set to "1". If the addition result has no carry, the D latch 31 has a "0".
Is set.

At the timing of the above-mentioned latch, PWM1
Each signal of OFS and TSET is given to the D latch 31 via the AND gate 38. Once the output value from the Q terminal of the D latch 31 becomes "1", the AND gate 47 is turned off, the AND gate 35 is turned on, and the next CH
When the G1ON signal is input, the value of the latch 1 is output to the bus line 65 instead of the value of the latch 3.
That is, when the pulse width becomes larger than the value of latch 1,
A carry occurs in the addition result of the value of the latch 3 and the inverted value of the value of the latch 1, and by utilizing the occurrence of the carry, the pulse width of the PWM1 signal is made equal to the value held in the latch 1. You always have control.

When the output value from the Q terminal of the D latch 31 is "0", one of the inputs of the AND gate 47 becomes "H", the AND gate 35 is in the ON prohibition state, and the next CHG1ON signal is input. Latch 3
Is output to the bus line 65.

In the pulse width limitation control for the PWM2 signal, the value of the latch 4 and the inverted value of the value of the latch 2 (the maximum pulse width value of the PWM2 signal) are added by the adder 63 at the timing of the PM2OFS signal, and the addition is performed. If the result has a carry, the D latch 32 is set to "1". If the addition result has no carry, the D latch 32 is "0".
Is set.

At the timing of the above-mentioned latch, PWM2
The OFS and TSET signals are applied to the D latch 32 via the AND gate 39. Once the output value from the Q terminal of the D latch 32 becomes "1", the AND gate 48 is turned off and the AND gate 36 is turned on, and the next CHG2
When the ON signal is input, the value of the latch 2 is output to the bus line 65 instead of the value of the latch 4. That is, when the pulse width becomes larger than the value of the latch 2, a carry occurs in the addition result of the value of the latch 4 and the inverted value of the value of the latch 2, and by utilizing the occurrence of the carry, the carry is held in the latch 2. The control can always be performed so that the pulse width of the PWM2 signal becomes equal to the existing value.

When the output value from the Q terminal of the D latch 32 is "0", one of the inputs of the AND gate 48 becomes "H", the AND gate 36 is in the ON prohibition state, and the next CHG2ON signal is input. Latch 4
Is output to the bus line 65.

To control the output to these bus lines, latches 17, 18, B. F. 11, 12, 13, 1
4 are PM1OFS, PM2OFS, and CHG1 respectively.
It is controlled in synchronization with each signal of ON and CHG2ON.

The detection circuits 61 and 62 detect the "1" value of the latches 3 and 4, respectively, and when DW1 and DW2 are "1" and UP1 and UP2 are "0", the latches 3 and 4 are detected. The value of is always set to "1", and DW
1, DW2 changes from "1" to "0", and UP1, UP2
When "0" changes to "1", the latches 3 and 4 operate to cancel the setting of "1".

The minimum value control of the pulse width can be easily realized by the same method.

Next, the structure of the main synchronous sub PWM control circuit which is composed of the synchronous detection circuit 103 and the PWM control circuit 104 will be described with reference to the drawings. FIG. 7 is a block diagram showing the configuration of the main synchronous sub-PWM control circuit used in the switching power supply of FIG.

The main synchronous sub PWM control circuit has an analog comparator 12b as shown in FIG.

The comparator 12b outputs the Vin signal 10b.
Level (shown in FIG. 1) and voltage V from the reference power supply 11b
Compare with ref and generate a comparison signal indicating the result of the comparison.

The output of the comparator 12b is the DFF 13b.
It is connected to the D terminal of. The Q bar terminal of the DFF 13b is connected to the signal line of the ST1B signal and one of the input terminals of one AND gate forming the composite gate 14b,
The Q terminal is connected to the signal line of the STB signal and one of the input terminals of the other AND gate forming the composite gate 14b. The clock terminal of the DFF 13b is connected to the signal line of the data setting signal.

The C terminal (carry terminal) of the adder 63 is connected to the other input terminal of one AND gate constituting the composite gate 14b, and the C terminal of the adder 63 is connected to the other input terminal of the other AND gate. The terminals (carry terminals) are connected via the inverter 24b. The output terminal of each gate circuit is connected to the corresponding input terminal of the NOR gate, and the output terminal of the NOR gate is connected to one of the input terminals of the AND gate 15b.

The other one of the input terminals of the AND gate 15b is connected to the signal line of the system clock, and the other one of the input terminals is connected to the signal line of the data setting signal. The output terminal of the AND gate 15b is connected to the CLOCK terminal (latch clock input terminal) of the register 2b.

The register 2b is composed of an 8-bit register, and its data input terminal is AD to the output terminal of the adder 63.
It is connected via the ROUT signal line. Register 2
The output terminal of B.b is the input terminal of the inverter 4b and B.
F. It is connected to the input terminal of 3b.

B. F. The output terminal of 3b is connected to the input terminal of the adder 63 via the bus line 64. B.
F. The GATE terminal of 3b is connected to the signal line of the data setting signal.

The inverter 4b inverts the output value from the register 2b and outputs the inverted value from the output terminal.
The output terminal of the inverter 4b is connected to the preset data input terminal of a presettable binary counter (hereinafter referred to as a counter) 1b.

The counter 1b comprises an 8-bit up counter. The CLOCK terminal of the counter 1b is the DFF9
b connected to the Q and D terminals of the counter 1b
The OAD terminal is connected to the Q terminal of DFF7b. The carry output terminal of the counter 1b is connected to one of the input terminals of the AND gate 16b.

The DFF 9b divides the system clock fetched through the inverter 8b and supplies the divided clock to the counter 1b.

The DFF 7b is an FF for preventing the loading of data to the input terminal of the counter 1b and the rising of the clock from occurring at the same time, and the D terminal is connected to the output terminal of the OR gate 6b. The main circuit counter clock is supplied to the latch clock input terminal of the DFF 7b.

PW is connected to one of the input terminals of the OR gate 6b.
The M1OUT terminal is connected, and the Q terminal of an RS flip-flop (hereinafter referred to as RSFF) 5b is connected to the other input terminal.

An external trigger signal is supplied to the S terminal of the RSFF 5b, and its R terminal is connected to the signal of the main PWML period setting signal.

The Q terminal of the DFF 7b is connected to the other input terminal of the AND gate 16b. AND gate 1
The output terminal of 6b is connected to the S terminal of RSFF17b.

The main PWM is applied to the R terminal of the RSFF 17b.
The signal line of the L period setting signal is connected, and the PWM4 signal (main synchronization sub PWM) is output from the Q terminal thereof.

Next, the operation of the main synchronous sub PWM circuit will be described with reference to FIG. FIG. 8 is a timing chart of signals showing the basic timing of the operation of the main synchronous sub PWM control circuit of FIG.

After the system is reset, all Q output terminals of each bit of the register 2b become "L", and "H" is added to each data input bit of the counter 1b via the inverter 4b. . Then, consider the following operation under the condition that the output of the composite gate 14b is "H".

In this circuit, the OR gate 6b is provided with the "H" level PWM1 signal or the RSFF5 by the external trigger.
An "H" level signal is output to the Q terminal of b (in this embodiment, the external trigger level is considered to be "L" level).
In synchronization with the next rise of the main circuit counter clock, the output level from the Q terminal of the latch 7b becomes "H", and the level of the LOAD terminal of the counter 1b changes from "L" to "H". At that timing, the data input signal of the counter 1b is set in the counter 1b.

Then, in synchronism with the TSET signal, the count value of the counter 1b is increased in synchronization with the clock input to the CLOCK terminal of the counter 1b, and when the carry is output, the AND gate 16b is set to the "H" level. The PWM4 signal (main synchronous sub-PWM) at the “H” level is output from the Q terminal of the RSFF 17b (see a, c, d, h on time t1 in FIG. 8).

Note that the time chart of FIG. 8 is not the one immediately after the system reset, but the condition when the register 2b is 01H, and the time t after the system reset is t.
An event of 1 occurs at time t0.

After the output of the PWM4 signal (main synchronous sub-PWM) at the "H" level, the RS is turned on by the main PWML period setting signal generated in synchronization with the trailing edge of the PWM1 signal.
The FFs 5b and 17b are reset, and the PWM4 signal (main synchronization sub PWM) becomes the “L” level (see a, e, and h at time t2 in FIG. 8). At the same time, the counter 1b is loaded.

Next, during the "L" level period of the PWM1 signal, the data of the counter 2b is synchronized with the B.B. F. 3b is output to the bus 65, the adder 63 performs an operation under the feedback condition, and the new data after the operation is registered in the register 2b by the output of the AND gate 15b by the system clock and the data setting signal.
Is set to Whether the post-computation data is larger or smaller than the pre-computation data is determined by the PWM control circuit 101 depending on the output from the Q terminal of the DFF 13b corresponding to the output of the comparator 12b, but the description will be simplified. For this reason, considering that there is no increase or decrease in the pulse width of the PWM1 signal, all of the setting data is inverted by the inverter 4b. Therefore, if the setting data increases, from the start of counting by the counter 1b to the occurrence of a carry on the CARRY terminal. Is longer, and the rising time of the PWM4 signal is later than the rising time of the PWM1 signal. On the contrary, when the set data decreases, the time becomes earlier. P
When the “H” period of the WM4 signal becomes longer, the Vin signal 10b
Considering a system in which the voltage increases, the output of the DFF 13b becomes "H" when the voltage of the Vin signal 10b becomes larger than the reference voltage Vref, and the output of the DFF 13b becomes "L" in the opposite case. Therefore, in the operation of the adder 63, when the output of the DFF 13b is "H", the new setting data of the register 2b is increased so that the DFF is reversed.
When the output of 13b is “L”, the negative feedback control can be executed by selecting the data to be added so that the new setting data decreases, and in the present embodiment, it is configured to operate as such. ing. The increase / decrease value in this case is
Of course, it is an integral multiple of the ON pulse width of the minimum unit that can be increased or decreased.

Next, the operation of the main synchronous sub PWM control circuit will be described in detail.

First, P of the main synchronous sub PWM control circuit
The operation of the PWM control circuit 101 when generating the WM4 signal will be described.

As shown in FIG. 5, the timing circuit 53 outputs PM1ONS when the PWM1 signal is "L".
Output S signal. The data increasing / decreasing operation by the AND gates 71a, 72a and the like is similar to the data up / down of the latch 3.

In the main synchronous sub PWM circuit, PM
At the timing when the level of the 1ONSS signal is “H”, the value of the register 2b is B. F. When the ST1 signal output from the DFF 13b is “H”, which is output to the bus 65 to the adder 63 via 3b, the AND gate 72a outputs a “H” level signal, and the latches 7 to 01H cause the adder 63 to add 01H. When the ST1B signal is "H", the AND gate 71a outputs a "H" level signal and the latch 7 to FFH cause the adder 63 to supply the adder 63.
And the adder 63 performs a subtraction operation of 1. The value obtained as a result of this operation is latched in the register 2b at the falling edge of the TSET signal.

Next, the maximum value / minimum value limit control for the setting data of the register 2b will be described.

This control is performed by preventing the output of the AND gate 15b from becoming "H" by the output of the composite gate 14b, and the data loaded in the counter 1b during the "L" period of the PWM1 signal is All "H"
Can be prevented from changing from all "L" or all "L" to all "H".

First, the maximum value limit control will be described.

The setting data of the register 2b is all "L".
Then, at the rising edge of the data setting signal, the setting data is B. F. It is given to the adder 63 via 3b,
The adder 63 starts the calculation on the setting data.

Simultaneously with the start of this calculation, it is requested that the "H" level from the Q bar terminal of the DFF 13b, that is, the setting data of the register 2b be decreased to lengthen the "H" period of the PWM4 signal from the main synchronous sub PWM control circuit. When the information is output, the carry of the adder 63 becomes “0”,
The output level of the composite gate 14b becomes "L" by the output of the inverter 24b and the "H" level output from the Q bar terminal of the DFF 13b, and the output of the AND gate 15b is blocked by the data setting signal and the system clock. No trigger is supplied to the CLOCK terminal of the register 2b. As a result, the post-calculation data is not set in the register 2b, the state of all "L" is held, and the maximum value limit control is completed.

Next, the minimum value limit control will be described.

The setting data of the register 2b is all "H".
Then, at the rising edge of the data setting signal, the adder 6
At 3, the calculation for the setting data is started.

At the same time as the start of this calculation, the information to increase the "H" level from the Q terminal of the DFF 13b, that is, the setting data of the register 2b to shorten the "H" period of the PWM4 signal from the main synchronous sub-PWM control circuit. Is output, the PWM control circuit 104 causes the DFF 13b
Addition is performed on the data of all "H" in the register 2b by the output from the Q terminal of
The carry is output from.

Then, the logical product output of the carry and the output from the Q terminal of the DFF 13b produces a composite gate 14b.
Output level becomes "L", and the minimum value limit control is completed similarly to the maximum value limit control.

Therefore, in the present embodiment, with a simple configuration, the other rising edge of the PWM1 signal is used as a reference, and the rising time can be set so that the negative feedback control can be executed for the voltage of the Vin signal 10b. The output from the main synchronous sub PWM control circuit) is obtained, and further, maximum value limit and minimum value limit control of the PWM4 signal generated by the main synchronous sub PWM control circuit can be executed.

The main synchronization sub P in this embodiment is
Although the reset circuit is omitted in the WM control circuit,
At the time of system reset, the Q outputs of all the latches and FFs are set to the “L” level.

Next, the timing of the above-mentioned PWM control will be described with reference to the drawings. FIG. 9 is a time chart showing the timing of PWM control in the switching power supply of FIG.

As is apparent from FIG. 9, the PWM1 signal is turned on between α and β, and the PWM by the PWM1 signal
Control is performed and the PWM4 signal can be turned on only within this range (base signal of transistor Q3). Therefore,
It can be seen that in the period A, no current flows in the secondary winding N3, that is, no current flows in the diode D1, and the loss in the FET Q3 and the transformer T1 decreases. As a result, the costs of the FET Q3 and the transformer T1 can be reduced.

As described above, the voltage control is performed by increasing / decreasing the pulse width of the PWM signal by an integral multiple of the minimum unit width, so that the PWM control circuit 101 and the main synchronous sub PWM control circuit can be made into a digital circuit.
These control circuits can be easily configured as an LSI in which the CPU and the CPU are integrated into one chip. As a result, a large cost reduction can be realized.

Further, since the PWM control circuit 101 and the main synchronous sub-PWM control circuit operate in synchronization with each other, and a large fluctuation of the pulse width of the PWM signal does not occur instantly, the control is very stable and not affected by noise. Can be realized, the cost required for manufacturing the entire apparatus can be reduced, and large power control can be easily realized.

Further, the PWM control by the main synchronous sub PWM control circuit is performed by the PWM1 from the PWM control circuit 101.
Since it is performed based on the rising edge of the signal, the PWM control circuit 1
Only when the level of the PWM1 signal from 01 is "H",
It is possible to perform control such that the level of the PWM4 signal generated by the main synchronous sub PWM control circuit is "H".

Further, generally, in the on / on control in which the switching operation for the primary side of the transformer is the on operation and the switching operation for the secondary side is the on operation at some time, a large power output can be obtained. However, there is also a demerit that the output control range becomes smaller. In addition, the on / off control in which the switching operation for the secondary side is the off operation when the switching operation for the primary side of the transformer is the on operation has the advantage that the output control range can be increased. There is a disadvantage that it is difficult to obtain electric power output. Since each control method is selected so that the above-mentioned merits in each control can be exerted, and feedback control is performed based on the comparison result by the comparator, very stable, high power output control can be realized at low cost. can do.

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 10 is a block diagram showing the configuration of the second embodiment of the switching power supply of the present invention.

The switching power supply of this embodiment is provided with a transformer T1 as shown in FIG. The transformer T1 is provided with a primary winding N1 and two secondary windings N2 and N3.

The positive terminal of the DC power supply DC for supplying the voltage Vin is connected to one end of the primary winding N1.
The-terminal is connected to the reference potential. A smoothing capacitor C0 is connected between the + and-terminals of the DC power supply DC. As the voltage Vin, for example, a voltage obtained by full-wave rectifying a commercial power source and smoothing it by the capacitor C0 can be considered.

At the other end of the primary winding N1, the drain of the FET Q1 which is a switching element and the capacitor C1 are provided.
One end of is connected. The source of the FET Q1 and the other end of the capacitor C1 are connected to the reference potential. FE
The gate of TQ1 is connected to the output terminal of the drive circuit 102.

A diode D3 is provided at one end of the secondary winding N2.
Is connected to the anode of the diode D4, and the other end is connected to a common reference potential (hereinafter, COM potential). A voltage V2 is induced in the secondary winding N2 according to the ratio with the number of windings of the primary winding N1.

The positive terminal of the smoothing capacitor C3 is connected to the cathode of the diode D3, and the negative terminal of the capacitor C3 is connected to the COM potential.

A voltage dividing circuit W1 arranged in parallel with the capacitor C3 is connected to the cathode of the diode D3. The voltage dividing circuit W1 divides the voltage V2 and outputs the divided voltage value to the PWM control circuit 101 as a feedback signal.

A resistor R5 is provided at the cathode of the diode D4.
One end of is connected. The resistor R5 is a load resistor,
The other end is connected to the COM potential. A voltage V3 is generated across the resistor R5.

The PWM control circuit 101 has an input terminal FBI.
A feedback signal from the voltage dividing circuit W1 is taken in via N1, and a PWM1 signal whose pulse width is controlled is generated based on this feedback signal. The pulse width of the PWM1 signal is controlled to increase / decrease to an integral multiple of the minimum unit width according to the level of the feedback signal. PWM1
The signal is output from the drive circuit 102 through the output terminal PMW1OUT.
And output to the synchronization detection circuit 103.

The drive circuit 102 turns on / off the FET Q1 based on the PWM1 signal, that is, performs a switching operation. The time defined by the ON pulse width of the PWM1 signal is the ON time of the FET Q1.

The voltage V3 is taken into the comparator 801, and the comparator 801 receives the reference voltage V of the reference power source 802.
Th is compared with the voltage V3, and a comparison signal indicating the comparison result is generated. This comparison signal is given to the trigger control circuit 803 as an external trigger.

The trigger control circuit 803 receives the trigger signal at the necessary timing based on the external trigger and the synchronization detection circuit 1
Output to 03.

The synchronization detection circuit 103 is the PWN control circuit 1
The trigger signal from the trigger control circuit 803 is detected together with the output timing of the PWM1 signal from 01, and a synchronization detection signal indicating the detection result is generated.

A diode D1 is provided at one end of the secondary winding N3.
Is connected to the anode and the other end is connected to the COM potential. A voltage V1 is induced in the secondary winding N3 according to the ratio with the number of windings of the primary winding N1.

The cathode of the diode D1 is connected to the drain of the MOSFET Q2 which is a switching element and one end of the resistor R1. The source of the MOSFET Q2 includes a cathode of a flywheel diode D2 (hereinafter referred to as a diode D2) and a choke coil L1.
One end of is connected. The other end of the resistor R1 and one end of the resistor R2 are connected to the gate of the MOSFET Q2. The-terminal of the capacitor C3 is connected to the COM potential.

The anode of the diode D2 is connected to the COM potential.

The + terminal of the smoothing capacitor C2 is connected to the other end of the choke coil L1. Capacitor C
The-terminal of 2 is connected to the COM potential.

The other end of the choke coil L1 is connected to one end of a resistor R3 arranged in parallel with the output capacitor C2, and the other end of the resistor R3 is connected to one end of a resistor R4. The other end of the resistor R4 is connected to the COM potential.

The resistors R3 and R4 cooperate with each other to divide the voltage V1, and the divided voltage is the Vin signal 10
It is taken into the PWM control circuit 104 as b. PWM
The control circuit 104 generates a pulse signal (hereinafter referred to as a PWM4 signal) whose pulse width is controlled based on the Vin signal 10b while synchronizing with the synchronization detection signal from the synchronization detection circuit 103. That is, the PWM4 signal is generated in synchronization with the PWM1 signal, and the pulse width of the PWM4 signal is controlled so as to increase or decrease to an integral multiple of the minimum unit width according to the level of the feedback signal. The PWM control circuit 104 cooperates with the synchronization detection circuit 103 to form a main synchronization sub PWM circuit.

The PWM4 signal is given as a V (ct1) signal to the base of the transistor Q3 for driving the MOSFET Q2. If necessary, a resistor can be inserted in the base circuit of the transistor Q3 as a protection measure for the transistor Q3. The collector of the transistor Q3 is connected to the other end of the resistor R2, and its emitter is CO
It is connected to the M potential. Transistor Q3 has V (c
t1) ON / OFF operation based on the signal, and the transistor Q
With the on / off operation of the MOSFET 3, the MOSFET Q2 performs the switching operation. ON pulse width of the V (ct1) signal (H
The time defined by (level) is the ON operation time of the transistor Q3, that is, the ON operation time of the MOSFET Q2.

Next, the main operation of the switching power supply of this embodiment will be described.

The basic operation of the switching power supply of this embodiment is the same as the basic operation of the first embodiment, and only the different operation will be described.

In the first embodiment, the PWM4 signal is generated by the main synchronous sub-PWM control circuit with reference to the rising edge of the PWM1 signal from the PWM control circuit 101.
When the voltage V1 output induced in the secondary winding N3 is extracted as a large electric power, the time delay until the start of the ON operation due to the delay of the MOSFET Q2 and the transistor Q3 cannot be ignored.

Therefore, in this embodiment, the PWM control circuit 1
The voltage V appearing as a signal synchronized with the PWM1 signal of 01.
3 is compared with the reference voltage Vth by the comparator 801, and the comparison result is used as an external trigger to set the external trigger protect period in the main synchronous sub PWM control circuit described later. This signal is induced on the secondary side only during on / off control in which the secondary side is off when the primary side switching operation is on, and a trigger voltage is induced when the primary side is off.

Next, the synchronization detection circuit 103, the PWM control circuit 104, the external trigger control circuit 803, and the comparator 8
The configuration of the main synchronous sub PWM control circuit composed of 01 and 01 will be described with reference to the drawings. 11 is shown in FIG.
It is a block diagram which shows the structure of the main synchronous sub PWM control circuit used for the switching power supply of 0.

The main synchronous sub PWM control circuit is shown in FIG.
As shown in, it has an analog comparator 12b. In the present embodiment, the analog comparator 12
Although b is used, it is preferable to use a chopper type comparator instead.

The comparator 12b compares the level of the Vin signal 10b with the voltage Vref from the reference power source 11b,
A comparison signal indicating the result of the comparison is generated.

The output of the comparator 12b is the DFF 13b.
It is connected to the D terminal of. The Q bar terminal of the DFF 13b is connected to the signal line of the ST1B signal and one of the input terminals of one AND gate forming the composite gate 14b,
The Q terminal is connected to the signal line for the ST1 signal and one of the input terminals of the other AND gate forming the composite gate 14b. The clock terminal of the DFF 13b is connected to the signal line of the data setting signal.

The C terminal (carry terminal) of the adder 63 is connected to the other of the input terminals of the one AND gate that constitutes the composite gate 14b, and the C terminal of the adder 63 is connected to the other of the input terminals of the other AND gate. The terminals (carry terminals) are connected via the inverter 24b. The output terminal of each gate circuit is connected to the corresponding input terminal of the NOR gate, and the output terminal of the NOR gate is connected to one of the input terminals of the AND gate 15b.

The other one of the input terminals of the AND gate 15b is connected to the signal line of the system clock, and the other one of the input terminals is connected to the signal line of the data setting signal. The output terminal of the AND gate 15b is connected to the L terminal (latch input terminal) of the register 2b.

The register 2b is composed of an 8-bit register, and its data input terminals D _{0 to} D ₇ are connected to the output terminals of the adder 63 via the signal line of ADROUT. The data output terminals Q0 to Q7 of the register 2b are connected to the inverter 4
b input terminal and B. F. It is connected to the input terminal of 3b.

B. F. The output terminal of 3b is connected to the input terminal of the adder 63 via the bus line 64. B.
F. The GATE terminal of 3b is connected to the signal line of the data setting signal.

The inverter 4b inverts the output value from the register 2b and outputs the inverted value from the output terminal.
The output terminal of the inverter 4b is connected to the data input terminals D0 to D7 of the counter 1b.

The counter 1b comprises an 8-bit presettable binary up counter. CL of counter 1b
The OCK terminal is connected to the Q terminal and the D terminal of the DFF 9b, and the LOAD terminal of the counter 1b is connected to the Q terminal of the DFF 7b. The carry output terminal of the counter 1b is connected to one of the input terminals of the AND gate 16b.

The DFF 9b divides the system clock fetched through the inverter 8b and supplies the divided clock to the clock input terminal of the counter 1b.

The DFF 7b is an FF for preventing the unloading of data to the input terminal of the counter 1b and the rising of the clock at the same time, and its D terminal is connected to the output terminal of the OR gate 6b. A counter clock is supplied to the DFF 7b.

PW is connected to one of the input terminals of the OR gate 6b.
The M1OUT terminal is connected, and the Q terminal of an RS flip-flop (hereinafter referred to as RSFF) 5b is connected to the other input terminal.

The AND gate 2 is connected to the S terminal of the RSFF 5b.
The output terminal of 2b is connected, and its R terminal is the main PWM
The signal of the L period setting signal is connected.

The Q terminal of the DFF 7b is connected to the other input terminal of the AND gate 16b. AND gate 1
The output terminal of 6b is connected to the S terminal of RSFF17b.

Main PWM is applied to the R terminal of RSFF17b.
The signal line of the L period setting signal is connected, and the PWM4 signal (main synchronization sub PWM) is output from the Q terminal thereof.

The main circuit counter clock is taken into the frequency dividing circuit 19b via the inverter 23b. The frequency dividing circuit 19b divides the clock taken in via the inverter 23b and outputs the divided clock from the output terminal Qn. The RESET terminal of the frequency divider circuit 19b is PWM
It is connected to the output terminal PWM1OUT of the control circuit 101. The output terminal Qn of the frequency divider circuit 19b is the composite gate 2
1b is connected to one of the input terminals of the OR gate.

The composite gate 21b is composed of an AND gate and an OR gate. One of the input terminals of the AND gate is connected to the signal line of the main PWMH period setting signal, and the other of the input terminals is connected to the signal line of the system clock. The output terminal of the AND gate is connected to the other input terminal of the OR gate, and the output terminal of the OR gate is connected to the CLOCK terminal of the protect counter 18b.

[0209] The input terminal D0 of the protect counter 18b
To D7 are connected to the output terminals Q0 to Q7 of the register 25b, respectively. The protect counter 18b has a bit length that can be protected over the entire "L" period of the PWM1 signal based on the clock cycle of the frequency divider circuit 19b. The LOAD terminal of the protect counter 18b is connected to the output terminal PWM1OUT of the PWM control circuit 101, and the CARRY signal output terminal is connected to the S terminal of the RSFF 20b.

The input terminals D0 to D7 of the register 25b are C
It is connected to the data bus of PU, and the clock terminal is connected to the write line 26b for the specific address signal of the CPU.

The R terminal of the RSFF 20b is connected to the output terminal PWM1OUT of the PWM control circuit 101. R
The Q terminal of the SFF 20b is connected to one input terminal of the AND gate 22b, and the other input terminal of the AND gate 22b is connected to the signal line of the external trigger.

Next, the operation of the main synchronous sub-PWM circuit will be described with reference to FIGS. 12 and 13. 12 is a timing chart of signals showing the basic timing of the operation of the PWM control circuit of FIG. 10, and FIG. 13 is a time chart showing the timing of PWM control in the switching power supply of FIG.

At the rising edge of the PWM1 signal (main PWM) (time t4 in FIG. 12), the protect counter 18b enters the load state, and the frequency dividing circuits 19b and RS are connected.
The FF 20b is in the reset state and the Q of the RSFF 20b is
When the output level from the terminal becomes "L", the input of the external trigger from the AND gate 22b is blocked.

At the same time, the main PWMH period setting signal rises, and from this rising time, the required protection data from the CPU is protected by the logical product output with the system clock which rises after a half cycle of its own clock of the system clock. It is loaded into the counter 18b. This protect data is the data previously written in the register 25b by the CPU via the write line 26b.

When the PWM1 signal falls after loading the protect data, the load state of the protect counter 18b and the reset state of the frequency dividing circuit 19b and the RSFF 20b are released, and the output QN from the frequency dividing circuit 19b causes the protect counter 18b to count. The operation is started (see a at time t1 in FIG. 12). In the present embodiment, it is appropriate to set the frequency dividing circuit 19b to divide by 2 to 4.

After the count operation is started, the protect counter 18b outputs a carry, the output level from the Q terminal of the RSFF 20b becomes "H", and the protection by the AND gate 22b against the external trigger is released (FIG. 12).
(See e and f at time t2 in the middle).

Therefore, a required protect period can be set for the external trigger for controlling the rising of the PWM4 signal generated by the main synchronous sub PWM control circuit.
Operation control can be effectively performed by a trigger signal from the outside.

The off-time may be set so as to fall within the output range of V3 according to the change of the V3 signal.

When the above control is performed, the fall of the external trigger is delayed by Tγ time after the fall of the PWM1 signal, as shown in FIG.
The desired operation can be realized by setting the external trigger inhibition time Tβ by the trigger control circuit 803 so that T1>Tβ> Tγ so that 1 does not malfunction.

Then, by appropriately adjusting the reference voltage Vth, the comparison result between the voltage V3 output in synchronization with the gate signal of the FET Q1 and the reference voltage Vth is set to "H" immediately before the PWM1 signal rises. Can be substantially P
Since the operation of the counter for controlling the WM4 signal can be started, the delay time by the MOSFET Q2 and the transistor Q3 can be corrected as much as possible so that the PWM4 signal does not rise in the period A, and the degree of freedom in design is increased. In addition, the cost of the entire device can be reduced.

In each embodiment, the PWM control circuit 10
1 and the PWM control circuit 104 generate an PWM signal by using an adder and a free counter for timing synchronization, but the relationship is omitted in FIGS. 1 and 10.

[0222]

According to the switching power supply of the first aspect, the pulse width is an integral multiple of the minimum unit width as the control signal for the voltage input to the primary winding and the induced voltage of the secondary winding. Since the signals that increase and decrease are used respectively, the control circuit that generates each control signal can be digitized, an inexpensive control circuit can be configured, and stable control can be performed.

According to the switching power supply of the second aspect, the control signal for the primary winding and the control signal for the secondary winding are synchronized with each other, so that very stable control can be realized. it can.

According to the third aspect of the switching power supply, the pulse width of the control signal for the secondary winding is an integral multiple of the minimum unit width within the period defined by the pulse width of the control signal for the primary winding. Since the pulse width of the control signal for the secondary winding does not change instantly, the timing of loss is reduced, and high power control can be easily realized.

According to the switching power source of the fourth aspect, the pulse width of the control signal for the secondary winding is within the period defined by the pulse width of the control signal for the primary winding, and the primary winding is Since the rise and fall of the control signal with respect to the reference is increased / decreased by an integral multiple of the minimum unit width, very stable control can be realized.

According to the switching power source of the fifth aspect, the pulse width of the control signal for the secondary winding increases or decreases by an integral multiple of the minimum unit width with reference to the rising edge of the synchronizing signal supplied from the outside. The pulse width of the control signal for the secondary winding can be increased to the maximum limit value,
By reducing the number of windings of the transformer, high power control can be realized easily and at low cost.

According to the sixth aspect of the switching power supply, since the synchronizing signal is synchronized with the control signal for the primary winding, the degree of freedom in design can be increased.

According to the switching power supply of the seventh aspect, since the synchronizing signal is treated as an invalid signal for a predetermined period, a desired control operation can be easily realized without malfunction.

According to the eighth aspect of the switching power supply, the increase / decrease in the pulse width of the control signal for the primary winding is 1
It is determined according to the result of the comparison between either the voltage induced in the secondary winding or the divided voltage thereof according to the switching operation for the secondary winding and the reference voltage for the voltage.
The increase or decrease in the pulse width of the control signal for the secondary winding is determined according to the result of comparison between either the induced voltage of the secondary winding or the divided voltage thereof and the reference voltage for the induced voltage. The control of the secondary winding by the switching operation is ON / OFF control that is OFF operation when the switching operation of the primary winding is ON operation, and the control of the secondary winding by the switching operation is Since the ON / ON control turns ON when the switching operation of the primary winding turns ON, when a large load change occurs on the secondary side, the output can be easily changed by the characteristic of ON / ON control. It can be stabilized, and very stable switching power supply control can be easily realized at low cost.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a first embodiment of a switching power supply according to the present invention.

FIG. 2 is a PW used in the switching power supply of FIG.
3 is a block diagram showing a configuration of an M control circuit 101. FIG.

FIG. 3 is a PW used in the switching power supply of FIG.
3 is a block diagram showing a configuration of an M control circuit 101. FIG.

4 is a PW used in the switching power supply of FIG.
3 is a block diagram showing a configuration of an M control circuit 101. FIG.

5 is a timing chart of signals showing basic timing of the operation of the PWM control circuit 101 of FIG.

6 is a flowchart schematically showing the processing operation of the PWM control circuit 101 of FIG.

7 is a block diagram showing a configuration of a main synchronous sub PWM control circuit used in the switching power supply of FIG.

8 is a timing chart of signals showing the basic timing of the operation of the main synchronous sub-PWM control circuit in FIG.

9 is a time chart showing the timing of PWM control in the switching power supply of FIG.

FIG. 10 is a block diagram showing the configuration of a second embodiment of the switching power supply of the present invention.

11 is a block diagram showing a configuration of a main synchronous sub PWM control circuit used in the switching power supply of FIG.

12 is a timing chart of signals showing the basic timing of the operation of the main synchronous sub PWM control circuit of FIG.

13 is a time chart showing the timing of PWM control in the switching power supply of FIG.

[Explanation of symbols]

 1, ..., 8 Latch 1b Counter 2b Register 12b, 802 Comparator 18b Protect counter 19b Frequency divider circuit 26 Free-run counter 27 Digital comparator 51a, 51b Comparator 53 Timing circuit 101, 104 PWM control circuit 103 Sync detection circuit 801 Trigger control circuit Q1 FET Q2 MOSFET Q3 Transistor T1 Transformer

Claims (8)

[Claims] 1. A transformer having a primary winding and at least one secondary winding is provided, and a voltage input to the primary winding and a voltage induced in the secondary winding are provided. In a switching power supply that controls the pulse width by a pulse width modulation method, the pulse width is an integral multiple of the minimum unit width as a control signal for the voltage input to the primary winding and the induced voltage in the secondary winding. A switching power supply characterized by using increasing and decreasing signals respectively. 2. The switching power supply according to claim 1, wherein the control signal for the primary winding and the control signal for the secondary winding are synchronized with each other. 3. The pulse width of the control signal for the secondary winding is increased or decreased by an integral multiple of the minimum unit width within a period defined by the pulse width of the control signal for the primary winding. The switching power supply according to claim 1 or 2. 4. The pulse width of the control signal for the secondary winding is within a period defined by the pulse width of the control signal for the primary winding and rises of the control signal for the primary winding. The switching power supply according to claim 1 or 2, wherein the reference power is increased or decreased by an integral multiple of the minimum unit width. 5. The pulse width of the control signal for the secondary winding is increased or decreased by an integral multiple of the minimum unit width with reference to the rising edge of a synchronizing signal supplied from the outside. Item 2. The switching power supply according to item 2. 6. The switching power supply according to claim 5, wherein the synchronization signal is synchronized with a control signal for the primary winding. 7. The switching power supply according to claim 5, wherein the synchronization signal is treated as an invalid signal for a predetermined period. 8. The increase or decrease in the pulse width of the control signal for the primary winding is either a voltage induced in the secondary winding in accordance with a switching operation for the primary winding or a partial voltage thereof. It is determined according to the result of comparison between the secondary winding and the reference voltage. Is determined according to the result of comparison with a reference voltage for the secondary winding by the switching operation of the primary winding, and the switching operation of the primary winding is turned off when the switching operation of the primary winding is turned on. And the control of the secondary winding by the switching operation is ON / ON control that is ON operation when the switching operation of the primary winding is ON operation. Special Claims 3, 4, 6 or 7 to be collected
Switching power supply described.