JPH0429353A - Semiconductor device - Google Patents

Abstract

PURPOSE:To achieve monolithic integration by forming an insulating film partially on the bonding face of at least one of semiconductor substrates attached directly to partially interpose the insulating film therebetween. CONSTITUTION:When semiconductor substrates 1 are attached, a directly attached section and a section with an insulating film 2 interposed therebetween are formed. With the substrates thus laminated, vertical devices are formed in the section without the insulating film 2 and devices subjected to dielectric insulation are formed in the section with the insulating film 2, making a semiconductor device having devices of different characteristics in one semiconductor substrate. Thereby, even if the semiconductor device requires vertical power MOSFET's, such as photo MOS relays, and high-voltage-output-type solar cells consisting of a plurality of solar cells subjected to dielectric isolation and connected in series, the vertical power MOSFET's can be formed in the section without the insulating film 2 of the substrate and the high-voltage-output-type solar cells can be formed in the section with the insulating film 2.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to the surface quality of semiconductor single crystal substrates having different characteristics.

<Conventional technology> Semiconductor devices that utilize the characteristics of a single laminated structure substrate made by bonding the surfaces of multiple semiconductor single crystal substrates have been proposed since the 1970s, but have not been put to practical use due to technical problems. . However, in recent years, semiconductor manufacturing technology and peripheral technologies for semiconductor manufacturing, such as precision processing technology and measurement technology, have rapidly advanced, and the semiconductor devices described above are gradually coming into practical use.

The above-mentioned semiconductor devices include semiconductor devices mainly using a dielectric isolation method in which an insulating film such as an oxide film or nitride film is formed on the bonding interface of the semiconductor substrate, and a semiconductor device in which only the semiconductor substrate is stacked and the bonding surface of the substrate is stacked. There have been semiconductor devices such as high-voltage devices that take advantage of features such as the ability to rapidly change impurity concentrations.

<Problems to be Solved by the Invention> The conventional semiconductor device described above using a substrate bonded with semiconductor substrates is limited in the types of devices that can be formed on the substrate, and therefore has a limited use and range of application. Another problem is that the functional effects of the semiconductor device cannot be widely extended. For example, with conventional technology, it is not possible to fabricate series-connected high-voltage output solar cells or high-speed switching devices, which are more advantageous by using dielectric isolation, on a substrate on which a power MO5FET using the junction surface of a semiconductor substrate is fabricated. ,
I decided to use a different board.

An object of the present invention is to solve the problems of the conventional semiconductor device using a substrate to which a semiconductor substrate is bonded, and to provide a semiconductor device that has a wide range of applications and has great functional and economical effects using a substrate to which a semiconductor substrate is bonded. It is an object.

<Means for Solving the Problems> In the present invention, when bonding semiconductor substrates, the semiconductor substrates are bonded directly to a portion and to a portion via an insulating film.

By using the laminated substrate with the nine configurations described above, a vertical device is formed in the part where there is no insulating film, and a dielectric film separation (or outside the insulating film) is made in the part where the insulating film is interposed.
By forming these devices, a semiconductor device is obtained in which devices with different characteristics are formed on one semiconductor substrate.

Function> By using the laminated semiconductor substrate of the present invention as explained above, vertical power MO5 such as a photoMOS relay can be realized.
Even in semiconductor devices that require FETs and high-voltage output solar cells that are made by connecting multiple solar cells separated by insulating films in series,
A vertical power MO is installed on the part of the substrate that does not include an insulating film.
It can be manufactured by forming a 3FET and forming a high voltage output type solar cell in a portion with an insulating film interposed therebetween. First, photo M
Various semiconductor devices having devices with different characteristics such as OS relays can be easily configured.

<Example> Hereinafter, an example of the present invention will be described with reference to partially enlarged cross-sectional drawings.

In the embodiment of the present invention, the adhesion consists of two Si semiconductor single crystal substrates, one with an insulating film interposed and the other without an insulating film. e) MO3! Let me explain about J-Lee.

Conventionally, vertical power MO5FET of photoMOS relay
In addition, dielectric film-separated high-voltage output solar cells were fabricated on separate semiconductor substrates and then combined through packaging, which took a long time to fabricate and limited miniaturization and cost reduction. was there.

Embodiments of the present invention are first implemented as shown in FIG.
00) Formation of a photoresist film by photoetching and RIE (Rea) on a predetermined portion of the surface of the Si semiconductor substrate 1
A shallow step is formed using active ion etching (active ion etching) or the like, and an insulating film 2 of 5i02 is formed using thermal oxidation or low-temperature CVD.

Next, as shown in FIG. 8, the 5i03 film, which has become a convex part of the step part, can be removed by mechanical methods such as ping or polishing, or by the RIE technique described above. The exposed surface of the semiconductor 1 and the surface of the insulating film 2 are made flat in the substrate 1.

The semiconductor substrate 1 formed as described above has a specific resistance of 50 to
H
, 0, or mixed liquid with H2O2, the substrates 1 and 3 should be made so that even minute foreign matter does not adhere to the surfaces to be bonded, and
The substrates 1 and 2 to be bonded are heated at 800°C to 1800°C in a state where the crystal orientations of the substrates 1 and 2 are well matched and the substrates are densely stacked as shown in Fig. 4.
Heating was performed to directly and firmly bond the Si semiconductor substrate 1 and the Si semiconductor substrate 3.

In the above embodiments, the bonding surface of the Si semiconductor substrate 8 is only the semiconductor surface, but the insulating film described in connection with the substrate 1 can also be formed on this surface.

In general, Si semiconductor substrates have a thickness above a certain level, so S
i The semiconductor substrate 3 is processed into a flat layer of approximately 80 μm by mechanical methods such as polishing and rough force pinning, or chemical methods using KOH, NaOH, etc., and then thermal oxidation and plasma CVD. (Chmic
An insulating film 4 of υSiO□, Ni3N, etc. is formed by Al Vapor Deposition) or the like. Using the film 4 with an open pattern formed by photoetching at a predetermined position of the insulating film 4 as a mask, KOH is applied.

By forming grooves in the Si semiconductor substrate 8 as shown in FIG. 5 by etching with an alkaline etchant such as NaOH, an island of Si semiconductor single crystal of a predetermined shape is created on the insulating film 2. did.

Subsequently, the insulating film 4 is removed by etching, and thermal oxidation is performed again.
S is deposited on three Si semi-semiconductor surfaces under specified conditions by low-temperature CVD, etc.
iH. Thermal decomposition of SiC no. FIG. 6 shows a state in which a Si polycrystalline film 6 is deposited by hydrogen reduction. Furthermore, mechanical methods such as polishing and roughing, and H F
, HNOs, etc., to remove and planarize the Si polycrystalline film 6 and the insulating film 5 other than the portions filled in the grooves, and then remove 9Si by thermal oxidation or the like.
FIG. 7 shows the insulating film 7 of Oz formed.

The Si semiconductor substrate formed above is etched by 6-select etching, which is a photo-etching technique used to manufacture integrated circuits.
Openings with a predetermined pattern are formed in the i02 film 7, and using the photoresist used to form the openings and the 5io2 film 7 as a mask, a Si boron element is implanted under predetermined conditions by the Si semi-semiconductor substrate pressure ion implantation method. and p for forming the channel part of the vertical MO5 FET during the activation process.
-5i sea urchin/L/8. P-5i Gardry for High Withstand Voltage The above activation process is a long-time heat treatment in oxygen at about 1100'C, and a 5i02 film of several thousand λ is also formed in the opening. Vertical MO8FET channels were again formed in these 5i02 films by the method for forming openings described above, and patterned to provide openings in the source contact region and the region where the n-5i diffusion layer of the solar cell element was to be formed. 5i
Oa film 9 was used.

Next, a thermally oxidized 5iOz film with a thickness of approximately 1000λ and a poly-Si film produced by thermal decomposition of SiH4 were laminated on the gate part of the vertical MO5T, and unnecessary parts were removed using photoetching technology.
It was removed by selective etching such as ion etching to form a 5i02 gate insulating film 1O and a poly-Si film gate electrode 11 of a vertical MO8 FET.

Furthermore, by ion implantation method or thermal diffusion method,
A shallow n” Si diffusion layer 12.1 is formed in the source contact region of the vertical MO3FET and the region that becomes the light-receiving surface of the solar cell.
Vertical MO5 F which forms 2' and becomes unnecessary for subsequent processes.
n”Si diffusion layer 1 formed on the p-5i well of ET
The 5i02 film used as a mask for manufacturing 2 and the 5i02 film formed on the n''-5i diffusion layer 12.12' by the thermal diffusion method or activation heat treatment were selectively removed by the ching method. FIG.

Next, low temperature CVD method. After coating the surface of the Si semiconductor substrate with an insulating film 18 such as 5i02 by plasma CVD method or the like,
By the selective etching method described above, the electrode contact portion of the n''-5i diffusion layer 12 in the Saone region of the vertical MO5 FET,
After forming openings in a predetermined region of the p-5i diffusion layer 8 and a predetermined region of the p-Si guard ring 8',
A J thin film was formed by sputtering, electron beam evaporation, etc.

The formed A thin film is formed into a predetermined pattern of A wiring 1 using a photoetching technique 1 selective process/etching technique for A.
4 was formed. Further, the surface of the substrate on which the A wiring 14 was formed was covered with an insulating film 15. This insulating film 15 is
D. Can be formed from 5i02 or Si3N4 by plasma CVD.

Following the above, the aforementioned Aj! Using the same method as for forming the wiring 14, each solar cell is directly connected by forming an opening for the electrode connection part of the solar cell element and forming the wiring 16 in a predetermined pattern A to form a "high voltage output solar cell". Figure 1 shows this.

Incidentally, as shown in FIG. 1, the A wiring 16 to which a high voltage is applied is connected to the A wiring arranged above the p-3i gadling portion 8.

With the configuration shown in FIG. 1 as described above, a vertical MO5 FET and a high voltage output solar cell can be rationally formed on a single semiconductor substrate. )Became.

In addition, in the above embodiments of the present invention, only a part of the photoMOS relay configuration was shown, which can explain the present invention in detail.
It is easily conceivable that a peripheral circuit for improving the switching operation speed of the photoMOS relay may be formed on an island similar to the solar cell element.

In addition, in this example, the present invention is described as e) MO3! Although the description has been made using an optically driven semiconductor device having a high voltage section and a high output section, the present invention is applicable to the MO! The present invention is not limited to relays, but can be effectively used in smart power ICs and the like in which high-voltage, high-power, high-speed devices or circuits are formed on one substrate.

<Effects of the Invention> The present invention has a configuration in which a plurality of semiconductor single crystal substrates are bonded with an insulating film partially interposed therebetween, and the crystallinity and impurity concentration uniformity of each semiconductor substrate to be bonded is maintained. , monolithic integration is possible in which devices with good characteristics are formed on islands with good crystallinity separated by high-voltage junctions or insulating films.

Therefore, for example, in the case of photoMOS relays, (a) vertical power MO5FETs do not require the conventional expensive substrate with a thick epitaxial film, and can be formed from high-quality bulk crystals, resulting in good device characteristics. . 10. A high voltage output type solar cell in which a plurality of solar cell elements are connected in series can also be formed on islands with good crystallinity separated by an insulating film.

(Since 71 or more vertical power MO5FETs, solar cell elements, and their peripheral circuit elements are also manufactured on the same substrate, the manufacturing process can be shared.) Various devices can be integrated on a chip, and There are effects such as reduction in caging cost and miniaturization.

[Brief explanation of the drawing]

FIG. 1 is a partially enlarged sectional view of an embodiment of the present invention;
2 to 8 are partially enlarged sectional views showing the manufacturing process of the embodiment. 1.8... (100) Si semiconductor substrate, 2.4.5°7, 9.18.15... Insulating film, 6... Si polycrystalline film, 8.8', 8"...・p-5i diffusion layer, 10...
Gate insulating film, 11... polysilicon electrode, 12.1
2'...n-3i diffusion layer, 14.16...A wiring. Agent Patent Attorney Ume 1) Katsu C and 2 others) Figure 2 Figure 3 Figure 4! @51! ! ! ! 9f

Claims (1)

[Scope of Claims] 1. In a semiconductor device in which a semiconductor device is formed on a substrate with a laminated structure in which the surfaces of at least two semiconductor single crystal substrates are directly bonded, at least one semiconductor of the directly bonded semiconductor substrates is provided. A semiconductor device characterized in that a partial insulating film is formed on the bonding surface of a substrate, and the bonding is performed with the insulating film partially interposed. 2. In a semiconductor device formed using the laminated semiconductor substrate, a device having a vertical structure is formed in a portion of the semiconductor substrate where the insulating film is not interposed, and an insulating film separation is formed in a portion where the insulating film is interposed. 2. The semiconductor device according to claim 1, wherein a device is formed.