JPH04199664A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04199664A JPH04199664A JP33172490A JP33172490A JPH04199664A JP H04199664 A JPH04199664 A JP H04199664A JP 33172490 A JP33172490 A JP 33172490A JP 33172490 A JP33172490 A JP 33172490A JP H04199664 A JPH04199664 A JP H04199664A
- Authority
- JP
- Japan
- Prior art keywords
- heat sink
- semiconductor device
- resin
- dissipating plate
- heat dissipating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 229920005989 resin Polymers 0.000 claims abstract description 21
- 239000011347 resin Substances 0.000 claims abstract description 21
- 230000017525 heat dissipation Effects 0.000 claims description 18
- 239000004642 Polyimide Substances 0.000 claims description 4
- 229920006015 heat resistant resin Polymers 0.000 claims description 4
- 229920001721 polyimide Polymers 0.000 claims description 4
- 238000007789 sealing Methods 0.000 abstract description 24
- 239000000853 adhesive Substances 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract 1
- 230000001070 adhesive effect Effects 0.000 description 3
- 241000288673 Chiroptera Species 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000003779 heat-resistant material Substances 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、半導体装置に係わり更に詳しくは放熱板を持
ったパッケージの放熱板構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a heat sink structure of a package having a heat sink.
［従来の技術］
第４図（ａ）は、従来の放熱板を用いた半導体装置の斜
視図である。５はパッケージ６より露出した放熱板であ
る。４は、パッケージより露出した外部端子（リード）
である。[Prior Art] FIG. 4(a) is a perspective view of a semiconductor device using a conventional heat sink. 5 is a heat sink exposed from the package 6. 4 is the external terminal (lead) exposed from the package
It is.
第４図（ｂ）は、第４図（ａ）のｃ−ｃ′間にて切断し
た断面図の一例である。１は、放熱板５上に接着剤によ
り取り付けられた半導体素子で。FIG. 4(b) is an example of a sectional view taken along line c-c' in FIG. 4(a). 1 is a semiconductor element attached to a heat sink 5 with an adhesive.
半導体素子ｌに設けられたボンディングバットと、これ
に対応リード４とはそれぞれワイヤー２により接続され
ている。また、放熱板５とリード４の一部は絶縁板３に
接着剤にて取り付けられている。Bonding bats provided on the semiconductor element 1 and corresponding leads 4 are connected by wires 2, respectively. Furthermore, the heat sink 5 and a portion of the leads 4 are attached to the insulating plate 3 with adhesive.
上記のようにして接続された半導体素子１とは絶縁板３
．リード４及び放熱板５の一部は、エポキシ樹脂の如き
プラスチックによりパッケージ６にて封止される。The semiconductor element 1 connected as described above is the insulating plate 3
．． A portion of the leads 4 and the heat sink 5 are sealed in a package 6 with plastic such as epoxy resin.
第４図（Ｃ）は、絶縁板３の上にインナーリード７がプ
リント配線されているものであり、インナーリード７と
リード４はスルーホール８にて接続されているものであ
る。In FIG. 4(C), the inner leads 7 are printed and wired on the insulating plate 3, and the inner leads 7 and the leads 4 are connected through the through holes 8. In FIG.
このようにして形成されたパッケージ６から突出したリ
ード４は折り曲げられて端子とし、半導体装置が製造さ
れる。The leads 4 protruding from the package 6 thus formed are bent to form terminals, and a semiconductor device is manufactured.
〔発明が解決しようとする課題１
上記のような放熱板を有するパッケージでは放熱板の表
面が平であるため、封止の際の押えが不十分となり放熱
板の上に樹脂が回り込み放熱板の表面がパッケージの外
に露出されないといった課題があった。[Problem to be Solved by the Invention 1] In a package having a heat sink as described above, the surface of the heat sink is flat, so the pressure during sealing is insufficient and the resin wraps around the heat sink, causing the heat sink to close. There was a problem in that the surface was not exposed outside the package.
本発明では、上記の課題を解決するためになされたもの
で、品質の安定した封止が可能となりさらには、放熱特
性の優れた半導体装置を得ることを目的とするものであ
る。The present invention has been made to solve the above-mentioned problems, and aims to provide a semiconductor device that enables sealing with stable quality and has excellent heat dissipation characteristics.
［課題を解決するための手段］
本発明に係わる半導体装置は、リードフレームにパッケ
ージ表面に露出する放熱板を有し、その放熱板の表面を
残しインナーリードの一部及び放熱板の一部を樹脂等で
封止してなる半導体装置において、放熱板表面に口もし
くは０字型に２０ｕｍ以上の凸部を設け、さらに凸部の
中央部を口もしくは０字型に凹状態に削り取った放熱板
を有することを特徴とする。[Means for Solving the Problems] A semiconductor device according to the present invention has a heat sink exposed on the package surface in a lead frame, and a part of the inner lead and a part of the heat sink are left on the surface of the heat sink. In a semiconductor device sealed with resin, etc., a heat sink in which a convex portion of 20 um or more is provided in the shape of a hole or a letter 0 on the surface of the heat sink, and the center of the convex portion is shaved into a concave portion in the shape of a letter 0 or a hole. It is characterized by having the following.
また、リードフレームにパッケージ表面に露出する放熱
板を有し、その放熱板の表面を残しインナーリードの一
部及び放熱板の一部を樹脂等で封止してなる半導体装置
において、放熱板表面に口もしくは０字型に２０ｕｍ以
上の凸部を設け、さらに凸部の中央部を口もしくは０字
型に凹状態に削り取った放熱板を有し、放熱板凸部表面
にポリイミド等の耐熱性の樹脂またはテープを施した構
成となっているものである。In addition, in a semiconductor device in which a lead frame has a heat sink exposed on the package surface, and a part of the inner lead and a part of the heat sink are sealed with resin or the like while leaving the surface of the heat sink, the surface of the heat sink is It has a heat dissipation plate with a convex part of 20 um or more in the shape of an opening or a 0-shape, and the center part of the convex part is cut into a concave state in the shape of an opening or a 0-shape, and the surface of the convex part of the heat dissipation plate is made of heat-resistant material such as polyimide. The structure is coated with resin or tape.
［作 用］
本発明に係わる半導体装置は、リードフレームにパッケ
ージ表面に露出する放熱板を有し、その放熱板の表面を
残しインナーリードの一部及び放熱板の一部を樹脂等で
封止してなる半導体装置において、放熱板表面に口もし
くは０字型の凸部を設け、さらに凸部の中央部を口もし
くは０字型に凹状態に削り取った放熱板を有する構成と
なっているため、封止の際封止型にて押さえられる部分
は放Ｐ板の凸部のみであり、充分な押えが可能となり樹
脂漏れを低減できる。[Function] The semiconductor device according to the present invention has a heat dissipation plate exposed on the package surface in the lead frame, and a part of the inner lead and a part of the heat dissipation plate are sealed with resin or the like, leaving the surface of the heat dissipation plate. The semiconductor device has a structure in which a heat sink has a hole or a 0-shaped convex part on the surface of the heat sink, and the center part of the convex part is shaved into a concave shape or a 0-shape. During sealing, the only part that is pressed by the sealing mold is the convex part of the P-discharge plate, which allows sufficient pressing and reduces resin leakage.
また、放熱板表面凸部にポリイミド及び耐熱テープ等を
施すことにより封止時の押え圧のばらつきを吸収し安定
した封止が可能となり樹脂漏れが低減できる。Further, by applying polyimide, heat-resistant tape, etc. to the convex portions on the surface of the heat sink, variations in presser pressure during sealing can be absorbed, stable sealing can be achieved, and resin leakage can be reduced.
第１図（ａ）は、本発明の一実施例である凹凸を持った
放熱板を用いた半導体装置の斜視図である。第１図（ａ
）において、５は凹凸を持った放熱板であり、パッケー
ジ６の表面に放熱板５の一部は露出している。４はリー
ドである。第１図（ｂ）は、第１図（ａ）をＡ−Ａ′に
て切断した断面図であり、半導体素子１は半導体素子に
設けられたポンディングパッドはワイヤー２にてり−ド
４に接続されている。半導体素子１及びリード４放熱板
５の一部は、絶縁板３に接着剤にて取り付けられ樹脂６
にて封止されている。放熱板５は、外部段差２０ｕｍ以
上の凸形状となっており、さらにその中央部は２０ｕｍ
以上凹となっている。FIG. 1(a) is a perspective view of a semiconductor device using a heat dissipation plate with unevenness, which is an embodiment of the present invention. Figure 1 (a
), reference numeral 5 denotes a heat dissipation plate having unevenness, and a part of the heat dissipation plate 5 is exposed on the surface of the package 6. 4 is the lead. FIG. 1(b) is a cross-sectional view of FIG. 1(a) taken along line A-A'. It is connected to the. A part of the semiconductor element 1 and the leads 4 and the heat dissipation plate 5 are attached to the insulating plate 3 with adhesive and covered with resin 6.
It is sealed in. The heat dissipation plate 5 has a convex shape with an external level difference of 20 um or more, and the center part has a convex shape with an external level difference of 20 um or more.
It is more concave.
第２図は、本発明の樹脂封止前の半導体装置を封止金型
内にセットした状態を示した断面図である。放熱板５は
、絶縁板３及びリード４にて支えられており放熱板５の
表面は封止金型におしつけられている。このとき、放熱
板５は凸のみが封止金型に接触しているため接触面積が
小さく充分なりランプ力が得られ樹脂のしみだし及び漏
れを低減した樹脂封止が可能となる。FIG. 2 is a cross-sectional view showing the semiconductor device of the present invention set in a sealing mold before resin sealing. The heat sink 5 is supported by the insulating plate 3 and the leads 4, and the surface of the heat sink 5 is pressed into a sealing mold. At this time, since only the convex part of the heat dissipation plate 5 is in contact with the sealing mold, the contact area is small and sufficient, sufficient lamp power is obtained, and resin sealing with reduced resin seepage and leakage becomes possible.
さらに、第３図（ａ）は放熱板５にエポキシ等の耐熱樹
脂９を塗布した斜視図である。放熱板５の凸部に塗布さ
れた樹脂９は封止金型内でのクランプの際にクツション
となり放熱板の平坦度に関係なく安定したクランプが可
能となる。第３図（ｂ）は、同放熱板のＢ−Ｂ′で切断
した断面図である。Further, FIG. 3(a) is a perspective view of the heat sink plate 5 coated with a heat-resistant resin 9 such as epoxy. The resin 9 applied to the convex portions of the heat sink 5 acts as a cushion during clamping within the sealing mold, allowing stable clamping regardless of the flatness of the heat sink. FIG. 3(b) is a sectional view taken along line BB' of the heat sink.
［発明の効果］
本発明に係わる半導体装置は、リードフレームにパッケ
ージ表面に露出する放熱板を有し、その放熱板の表面を
残しインナーリードの一部及び放熱板の一部を樹脂等で
封止してなる半導体装置において、放熱板表面に口もし
くは０字型の凸部を設け、さらに凸部の中央部を口もし
くは０字型に凹状態に削り取った放熱板を有する構成と
なっているため、封止の際封止型にて押さえられる部分
は放熱板の凸部のみであり、充分な押えが可能となり樹
脂漏れを低減できる。[Effects of the Invention] A semiconductor device according to the present invention has a heat sink exposed on the package surface in a lead frame, and a part of the inner lead and a part of the heat sink are sealed with resin or the like, leaving the surface of the heat sink. In a semiconductor device formed by a semiconductor device, the heat sink has a configuration in which a hole or a 0-shaped convex portion is provided on the surface of the heat sink, and the center portion of the convex portion is shaved into a concave shape in the shape of a hole or a 0-shape. Therefore, the only part that is pressed by the sealing mold during sealing is the convex part of the heat sink, which allows sufficient pressing and reduces resin leakage.
また、放熱板表面凸部にポリイミド及び耐熱テープ等を
施すことにより封止時の押久圧のばらつきを吸収し安定
した封止が可能となり樹脂漏れが低減できる。Further, by applying polyimide, heat-resistant tape, etc. to the convex portions on the surface of the heat sink, variations in pressing pressure during sealing can be absorbed, stable sealing can be achieved, and resin leakage can be reduced.
第１図（ａ）は、本発明の一実施例である凹凸のある放
熱板を持った半導体装１の斜視図、第１図（′ｂ）は第
１図（ａ）のＡ−Ａ′断面図、第２図は本発明の樹脂封
止前の半導体装置を封止金型内にセットした状態を示す
断面図、第３図（ａ）は本発明の他の実施例を示すもの
で、放熱板に耐熱樹脂を塗布した状態を示す斜視図、第
３図（ｂ）は第３図（ａ）のＢ−Ｂ′断面図、第４図（
ａ）は従来技術の半導体装置放熱フィンを搭載した状態
を示す斜視図、第４図（ｂ）、第４図（ｃ）は第４図（
ａ）のｃ−ｃ′断面図。
１・・・半導体チップ
２・・・ワイヤー
３・・・絶縁板
４・ ・ ・リード
５・・・放熱板
６・・・パッケージ
７・・・インナーリード
８・・・スルーホール
９・・・耐熱樹脂
１０・・・放熱フィン
１１・・・封止型上
１２・・・封止型下
以上
出願人 セイコーエプソン株式会社
代理人 弁理士 鈴 木 喜三部（他１名）第３９（ｂ
）FIG. 1(a) is a perspective view of a semiconductor device 1 having an uneven heat dissipation plate according to an embodiment of the present invention, and FIG. 1('b) is an A-A' in FIG. 2 is a sectional view showing a semiconductor device of the present invention set in a sealing mold before resin encapsulation, and FIG. 3(a) is a sectional view showing another embodiment of the present invention. , a perspective view showing a state in which the heat sink is coated with heat-resistant resin, FIG. 3(b) is a sectional view taken along line BB' in FIG. 3(a), and FIG.
4(a) is a perspective view showing a state in which a conventional semiconductor device heat dissipation fin is mounted, FIG. 4(b) and FIG. 4(c) are FIG.
cc' sectional view of a). 1... Semiconductor chip 2... Wire 3... Insulating plate 4... Lead 5... Heat sink 6... Package 7... Inner lead 8... Through hole 9... Heat resistant Resin 10... Heat dissipation fin 11... Sealing mold upper 12... Sealing mold lower and above Applicant Seiko Epson Co., Ltd. Agent Patent attorney Kizobe Suzuki (1 other person) No. 39 (b)
)
Claims (2)
板を有し、その放熱板の表面を残しインナーリードの一
部及び放熱板の一部を樹脂等で封止してなる半導体装置
において、放熱板表面に□もしくは○字型に凸部を設け
、さらに凸部の中央部を□もしくは○字型に凹状態に削
り取った放熱板を有することを特徴とする半導体装置。(1) In a semiconductor device in which a lead frame has a heat sink exposed on the package surface, and a part of the inner lead and a part of the heat sink are sealed with resin or the like while leaving the surface of the heat sink, the heat sink 1. A semiconductor device comprising: a heat dissipation plate having a □ or ○-shaped convex portion on its surface, and further having a central portion of the convex portion cut into a □- or ○-shaped concave state.
板を有し、その放熱板の表面を残しインナーリードの一
部及び放熱板の一部を樹脂等で封止してなる半導体装置
において、放熱板表面に□もしくは○字型に凸部を設け
、さらに凸部の中央部を□もしくは○字型に凹状態に削
り取った放熱板を有し、放熱板凸部表面にポリイミド等
の耐熱性の樹脂またはテープを施したことを特徴とする
半導体装置。(2) In a semiconductor device in which a lead frame has a heat sink exposed on the package surface, and a part of the inner lead and a part of the heat sink are sealed with resin or the like, leaving the surface of the heat sink, the heat sink It has a heat dissipation plate with a □ or ○-shaped convex part on the surface, and the center part of the convex part is cut into a □ or ○-shaped concave state, and the surface of the convex part of the heat dissipation plate is made of heat-resistant resin such as polyimide. Or a semiconductor device characterized by being coated with tape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33172490A JP2841854B2 (en) | 1990-11-29 | 1990-11-29 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33172490A JP2841854B2 (en) | 1990-11-29 | 1990-11-29 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04199664A true JPH04199664A (en) | 1992-07-20 |
| JP2841854B2 JP2841854B2 (en) | 1998-12-24 |
Family
ID=18246889
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33172490A Expired - Fee Related JP2841854B2 (en) | 1990-11-29 | 1990-11-29 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2841854B2 (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0658935A3 (en) * | 1993-12-16 | 1996-07-10 | Seiko Epson Corp | Resin sealing type semiconductor device and method of making the same. |
| US5633529A (en) * | 1994-07-13 | 1997-05-27 | Seiko Epson Corporation | Resin sealing type semiconductor device and method of making the same |
| US5652461A (en) * | 1992-06-03 | 1997-07-29 | Seiko Epson Corporation | Semiconductor device with a convex heat sink |
| EP0732744A3 (en) * | 1995-03-17 | 1997-08-27 | Seiko Epson Corp | Resin sealing type semiconductor device and method of making the same |
| US5693984A (en) * | 1992-06-03 | 1997-12-02 | Seiko Epson Corporation | Semiconductor device having a heat radiator |
| US5719442A (en) * | 1994-11-11 | 1998-02-17 | Seiko Epson Corporation | Resin sealing type semiconductor device |
| US5801435A (en) * | 1995-02-27 | 1998-09-01 | Seiko Epson Corporation | Resin sealing type semiconductor device and method of making the same |
| JP2010199494A (en) * | 2009-02-27 | 2010-09-09 | Mitsubishi Electric Corp | Semiconductor device and manufacturing method of the same |
| JP2011159876A (en) * | 2010-02-02 | 2011-08-18 | Denso Corp | Method of manufacturing semiconductor device |
| JP2017034130A (en) * | 2015-08-03 | 2017-02-09 | エスアイアイ・セミコンダクタ株式会社 | Semiconductor device and manufacturing method of the same |
-
1990
- 1990-11-29 JP JP33172490A patent/JP2841854B2/en not_active Expired - Fee Related
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5652461A (en) * | 1992-06-03 | 1997-07-29 | Seiko Epson Corporation | Semiconductor device with a convex heat sink |
| US5653891A (en) * | 1992-06-03 | 1997-08-05 | Seiko Epson Corporation | Method of producing a semiconductor device with a heat sink |
| US5693984A (en) * | 1992-06-03 | 1997-12-02 | Seiko Epson Corporation | Semiconductor device having a heat radiator |
| US5891759A (en) * | 1993-12-16 | 1999-04-06 | Seiko Epson Corporation | Method of making a multiple heat sink resin sealing type semiconductor device |
| US5594282A (en) * | 1993-12-16 | 1997-01-14 | Seiko Epson Corporation | Resin sealing type semiconductor device and method of making the same |
| KR100296664B1 (en) * | 1993-12-16 | 2001-10-24 | 구사마 사부로 | Resin-encapsulated semiconductor device and manufacturing method thereof |
| EP0658935A3 (en) * | 1993-12-16 | 1996-07-10 | Seiko Epson Corp | Resin sealing type semiconductor device and method of making the same. |
| US5633529A (en) * | 1994-07-13 | 1997-05-27 | Seiko Epson Corporation | Resin sealing type semiconductor device and method of making the same |
| US5719442A (en) * | 1994-11-11 | 1998-02-17 | Seiko Epson Corporation | Resin sealing type semiconductor device |
| US5801435A (en) * | 1995-02-27 | 1998-09-01 | Seiko Epson Corporation | Resin sealing type semiconductor device and method of making the same |
| US5777380A (en) * | 1995-03-17 | 1998-07-07 | Seiko Epson Corporation | Resin sealing type semiconductor device having thin portions formed on the leads |
| EP0732744A3 (en) * | 1995-03-17 | 1997-08-27 | Seiko Epson Corp | Resin sealing type semiconductor device and method of making the same |
| JP2010199494A (en) * | 2009-02-27 | 2010-09-09 | Mitsubishi Electric Corp | Semiconductor device and manufacturing method of the same |
| JP2011159876A (en) * | 2010-02-02 | 2011-08-18 | Denso Corp | Method of manufacturing semiconductor device |
| JP2017034130A (en) * | 2015-08-03 | 2017-02-09 | エスアイアイ・セミコンダクタ株式会社 | Semiconductor device and manufacturing method of the same |
| CN106409694A (en) * | 2015-08-03 | 2017-02-15 | 精工半导体有限公司 | Semiconductor device and method of manufacturing the same |
| CN106409694B (en) * | 2015-08-03 | 2020-08-25 | 艾普凌科有限公司 | Semiconductor device and method for manufacturing the same |
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| Publication number | Publication date |
|---|---|
| JP2841854B2 (en) | 1998-12-24 |
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