JPH04112564A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04112564A JPH04112564A JP23211290A JP23211290A JPH04112564A JP H04112564 A JPH04112564 A JP H04112564A JP 23211290 A JP23211290 A JP 23211290A JP 23211290 A JP23211290 A JP 23211290A JP H04112564 A JPH04112564 A JP H04112564A
- Authority
- JP
- Japan
- Prior art keywords
- region
- type
- buried
- diffusion region
- diffusion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 238000009792 diffusion process Methods 0.000 claims abstract description 41
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 239000003990 capacitor Substances 0.000 claims description 6
- 238000002955 isolation Methods 0.000 abstract description 11
- 239000012535 impurity Substances 0.000 abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052710 silicon Inorganic materials 0.000 abstract description 6
- 239000010703 silicon Substances 0.000 abstract description 6
- 230000003190 augmentative effect Effects 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に半導体容量素子を有す
る半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device having a semiconductor capacitive element.
従来の半導体装置は第２図に示すように、Ｐ型シリコン
基板１１の表面に選択的にＮ”型埋込領域１を設け、Ｎ
＋型型埋領領域１びＰ型シリコン基板１１の表面に選択
的にＰ型不純物を導入してＰ゛型型埋領領域２びＰ＋型
素子分離領域２ａを設ける。次に、Ｎ＋型型埋領領域１
びＰ−“型埋込領域２及びＰ＋型素子分離領域２ａを含
む表面にＮ−型エピタキシャル領域６を形成する。次に
、Ｎ−型エピタキシャル領域６の表面にＰ型不純物を選
択的に導入してＰ＋型埋込領域２に達するコンタクト用
のＰ＋型拡散領域５及びＰ＋型素子分離領域２ａに達す
るＰ＋型素子分離領域５ａを夫々設ける。次に、Ｎ−型
エピタキシャル領域６の表面にＮ型不純物を選択的に導
入してＮ＋型拡散領域４を形成する。次に、全表面に設
けた絶縁膜７を介してＮ＋＋拡散領域４と対向させて設
けた電極９を設け、絶縁膜７に設けたコンタクトホール
によりＰ＋型拡散領域５及びＮ＋＋拡散領域４の夫々に
接続して電極８，１０を設ける。In the conventional semiconductor device, as shown in FIG. 2, an N'' type buried region 1 is selectively provided on the surface of a P type silicon substrate 11.
P-type impurities are selectively introduced into the surface of the +-type buried region 1 and the P-type silicon substrate 11 to provide a P''-type buried region 2 and a P+-type element isolation region 2a. Next, N+ type buried region 1
An N- type epitaxial region 6 is formed on the surface including the P- type buried region 2 and the P+ type element isolation region 2a. Next, P type impurities are selectively introduced into the surface of the N- type epitaxial region 6. Then, a P+ type diffusion region 5 for contact reaching the P+ type buried region 2 and a P+ type element isolation region 5a reaching the P+ type element isolation region 2a are provided respectively. A type impurity is selectively introduced to form an N+ type diffusion region 4. Next, an electrode 9 is provided facing the N++ diffusion region 4 through an insulating film 7 provided on the entire surface. Electrodes 8 and 10 are connected to the P+ type diffusion region 5 and the N++ diffusion region 4, respectively, through contact holes provided in the .
上述した従来の半導体装置は、接合容量を形成している
一導電型の第２の埋込領域２とＭＯＳ容量を形成してい
る逆導電型の拡散領域４との距離が製造上のばらつきが
あるため、第２の埋込領域２と拡散領域４が接触する場
合があり、この時第２の埋込領域２と拡散領域４との間
の接合容量値は所望の接合容量値と異なる値となり、本
来の設計容量値が得られないという欠点がある。In the conventional semiconductor device described above, the distance between the second buried region 2 of one conductivity type forming the junction capacitor and the diffusion region 4 of the opposite conductivity type forming the MOS capacitor is due to manufacturing variations. Therefore, the second buried region 2 and the diffusion region 4 may come into contact with each other, and in this case, the junction capacitance value between the second buried region 2 and the diffusion region 4 may be different from the desired junction capacitance value. Therefore, there is a drawback that the original design capacitance value cannot be obtained.
本発明の半導体装置は、−導電型半導体基板上に設けた
逆導電型の第１の埋込領域と、前記第１の埋込領域上に
設けた一導電型の第２の埋込領域と、前記第１及び第２
の埋込領域を含む表面に設けた逆導電型のエピタキシャ
ル領域と、前記エピタキシャル領域に設けて前記第２の
埋込領域に達する一導電型の第１の拡散領域と、前記第
１の拡散領域及び前記エピタキシャル領域にまたかつて
形成された逆導電型の第２の拡散領域と、前記エピタキ
シャル領域に設けて前記第２の埋込領域に達する一導電
型のコンタクト用領域と、前記第２の拡散領域上に設け
た絶縁膜上に前記第２の拡散領域と対向させて設けた容
量電極とを有する。The semiconductor device of the present invention includes a first buried region of an opposite conductivity type provided on a -conductivity type semiconductor substrate, and a second buried region of one conductivity type provided on the first buried region. , said first and second
an epitaxial region of an opposite conductivity type provided on a surface including a buried region, a first diffusion region of one conductivity type provided in the epitaxial region and reaching the second buried region, and the first diffusion region. and a second diffusion region of an opposite conductivity type previously formed in the epitaxial region, a contact region of one conductivity type provided in the epitaxial region and reaching the second buried region, and the second diffusion region. A capacitor electrode is provided on an insulating film provided on the region, facing the second diffusion region.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の断面図である。FIG. 1 is a sectional view of an embodiment of the present invention.
第１図に示すように、Ｐ型シリコン基板１１の表面に選
択的にＮ＋型型埋領領域１設け、Ｎ＋型型埋領領域１び
Ｐ型シリコン基板１１の表面に選択的にＰ型不純物を導
入してＰ“型埋込領域２及びＰ＋型素子分離領域２ａを
設ける。次に、Ｎ＋型型埋領領域１びＰ＋型埋込領域２
及びＰ＋型素子分離領域２ａを含む表面にＮ−型エピタ
キシャル領域６を成長し、Ｎ−型エピタキシャル領域６
の表面にＰ型不純物を選択的に導入してＰ”型埋込領域
２に達するＰ−型拡散領域３を形成する。As shown in FIG. 1, an N+ type buried region 1 is selectively provided on the surface of a P type silicon substrate 11, and a P type impurity is selectively added to the N+ type buried region 1 and the surface of the P type silicon substrate 11. is introduced to form a P" type buried region 2 and a P+ type element isolation region 2a. Next, an N+ type buried region 1 and a P+ type buried region 2 are formed.
The N- type epitaxial region 6 is grown on the surface including the P+ type element isolation region 2a, and the N- type epitaxial region 6 is grown.
A P- type diffusion region 3 reaching the P'' type buried region 2 is formed by selectively introducing P-type impurities into the surface of the P-type buried region 2 .
次に、Ｎ−型エピタキシャル領域６の表面にＰ型不純物
を選択的に導入してＰ＋型埋込領域２に達するコンタク
ト用のＰ＋型拡散領域５及びＰ＋型素子分離領域２ａに
達するＰ＋型素子分離領域５ａを設ける。次に、Ｐ−型
拡散領域３及びＮ型エピタキシャル領域６をまたいで選
択的にＮ＋＋拡散領域４を形成する。次に、全表面に設
けた酸化シリコン膜または窒化シリコン膜からなる絶縁
膜７を介してＮ＋＋拡散領域４と対向させた電極９を設
け、絶縁膜７に設けたコンタクトホールのＰ＋型拡散領
域５及びＮ＋＋拡散領域４の夫々に接続する電極８．１
０を設ける。Next, P type impurities are selectively introduced into the surface of the N- type epitaxial region 6 to form a P+ type diffusion region 5 for contact reaching the P+ type buried region 2 and a P+ type element reaching the P+ type element isolation region 2a. A separation region 5a is provided. Next, an N++ diffusion region 4 is selectively formed across the P- type diffusion region 3 and the N-type epitaxial region 6. Next, an electrode 9 is provided facing the N++ diffusion region 4 via an insulating film 7 made of a silicon oxide film or a silicon nitride film provided on the entire surface, and a P+ type diffusion region 5 in a contact hole provided in the insulating film 7 is provided. and an electrode 8.1 connected to each of the N++ diffusion region 4
Set 0.
ここで、Ｎ＋＋拡散領域４の直下にＰ−型拡散領域３を
形成することにより接合容量値の精度を向上できる効果
がある。Here, by forming the P- type diffusion region 3 directly under the N++ diffusion region 4, there is an effect that the accuracy of the junction capacitance value can be improved.
また、容量部は絶縁膜７を介して対向した電極７とＮ＋
＋拡散領域４からなるＭＯＳ容量部と、Ｎ＋型型埋領領
域１Ｐ＋型埋込領域２とのＰＮ接合からなる接合容量部
と、Ｐ−型拡散領域３とＮ＋＋拡散領域４とのＰＮ接合
からなる接合容量部との並列接続による静電容量の増加
が得られる。In addition, the capacitor portion is connected to the electrode 7 facing each other via the insulating film 7
From the MOS capacitance section consisting of the + diffusion region 4, the junction capacitance section consisting of the PN junction between the N+ type buried region 1P+ type buried region 2, and the PN junction between the P- type diffusion region 3 and the N++ diffusion region 4. The capacitance can be increased by parallel connection with the junction capacitance section.
以上説明したように本発明は、ＭＯＳ容量のＮ型不純物
拡散領域直下のＰ＋型埋込領域に達するＰ型拡散領域を
形成することにより、容量値の精度を高めるという効果
を有する。As described above, the present invention has the effect of increasing the accuracy of the capacitance value by forming the P type diffusion region that reaches the P+ type buried region directly under the N type impurity diffusion region of the MOS capacitor.
又、接合容量部を付加して素子領域を増加させずに並列
接続したときの容量値を増大させることができるという
効果を有する。Furthermore, there is an effect that the capacitance value when connected in parallel can be increased without increasing the element area by adding a junction capacitance section.
第１図は本発明の一実施例の断面図、第２図は従来の半
導体装置の一例を示す断面図である。
１・・・Ｎ＋型型埋領領域２・・・Ｐ＋型埋込領域、２
ａ・・・Ｐ＋型素子分離領域、３・・・Ｐ−型拡散領域
、４・・・Ｎ＋＋拡散領域、５・・・Ｐ”型拡散領域、
５ａ・・・Ｐ＋型素子分離領域、６・・・Ｎ−型エピタ
キシャル領域、
７・・・絶縁膜、
○・・電極、
・・Ｐ型シリコン基板。FIG. 1 is a sectional view of an embodiment of the present invention, and FIG. 2 is a sectional view of an example of a conventional semiconductor device. 1... N+ type buried region 2... P+ type buried region, 2
a...P+ type element isolation region, 3...P- type diffusion region, 4...N++ diffusion region, 5...P'' type diffusion region,
5a... P+ type element isolation region, 6... N- type epitaxial region, 7... Insulating film, ○... Electrode,... P type silicon substrate.
Claims (1)
領域と、前記第１の埋込領域上に設けた一導電型の第２
の埋込領域と、前記第１及び第２の埋込領域を含む表面
に設けた逆導電型のエピタキシャル領域と、前記エピタ
キシャル領域に設けて前記第２の埋込領域に達する一導
電型の第１の拡散領域と、前記第１の拡散領域及び前記
エピタキシャル領域にまたがって形成された逆導電型の
第２の拡散領域と、前記エピタキシャル領域に設けて前
記第２の埋込領域に達する一導電型のコンタクト用領域
と、前記第２の拡散領域上に設けた絶縁膜上に前記第２
の拡散領域と対向させて設けた容量電極とを有すること
を特徴とする半導体装置。A first buried region of an opposite conductivity type provided on a semiconductor substrate of one conductivity type, and a second buried region of one conductivity type provided on the first buried region.
a buried region, an epitaxial region of opposite conductivity type provided on the surface including the first and second buried regions, and a first epitaxial region of one conductivity type provided in the epitaxial region and reaching the second buried region. a second diffusion region of an opposite conductivity type formed across the first diffusion region and the epitaxial region; and a diffusion region of one conductivity provided in the epitaxial region and reaching the second buried region. The second diffusion layer is formed on the contact region of the mold and the insulating film provided on the second diffusion region.
What is claimed is: 1. A semiconductor device comprising: a capacitor electrode provided opposite to a diffusion region of the semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23211290A JPH04112564A (en) | 1990-08-31 | 1990-08-31 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23211290A JPH04112564A (en) | 1990-08-31 | 1990-08-31 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04112564A true JPH04112564A (en) | 1992-04-14 |
Family
ID=16934196
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23211290A Pending JPH04112564A (en) | 1990-08-31 | 1990-08-31 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04112564A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0822601A1 (en) * | 1996-07-30 | 1998-02-04 | STMicroelectronics S.r.l. | MOS capacitor with wide voltage and frequency operating ranges |
| JP2009182291A (en) * | 2008-02-01 | 2009-08-13 | Seiko Npc Corp | Variable capacitance device |
-
1990
- 1990-08-31 JP JP23211290A patent/JPH04112564A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0822601A1 (en) * | 1996-07-30 | 1998-02-04 | STMicroelectronics S.r.l. | MOS capacitor with wide voltage and frequency operating ranges |
| US6590247B2 (en) | 1996-07-30 | 2003-07-08 | Sgs-Thomson Microelectronics S.R.L. | MOS capacitor with wide voltage and frequency operating ranges |
| JP2009182291A (en) * | 2008-02-01 | 2009-08-13 | Seiko Npc Corp | Variable capacitance device |
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