JPS6124825B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor capacitive element suitable for application to a semiconductor integrated circuit in which a transistor as a circuit element is formed, and the number of manufacturing steps is increased by providing this capacitive element. The present invention is designed so that such problems do not occur and, moreover, it can be configured as a large capacity capacitive element.

As a capacitive element used in such a semiconductor integrated circuit, there is one disclosed in Japanese Patent Publication No. 51-44068, for example. As shown in FIG.
A first electrode 4 is connected to region 1 and is formed over region 3 via an insulating layer, for example, a SiO ₂ layer 6, and a second electrode 5 is connected to regions 2 and 3. It is made up of In this way, between the first and second electrodes 4 and 5, the capacitance of the so-called MIS structure consisting of the electrode 4 - the insulating layer 6 - the region 3 and the regions 1 and 2 are formed.
The structure is such that the parasitic capacitance due to the junction J between the two is connected in parallel.

As described above, the present invention configures a capacitive element by the capacitance of the MIS structure and the junction capacitance.
Furthermore, it is an object of the present invention to provide a semiconductor capacitive element whose capacity is increased.

An example of the present invention will be described with reference to FIG.
In the illustrated example, a semiconductor capacitive element 12 according to the present invention and an NPN are used as circuit elements on a common semiconductor substrate 11.
2 shows an integrated circuit in which a transistor 13 is formed.
The semiconductor substrate 11 is formed by epitaxially growing a semiconductor layer 15 of a second conductivity type, N type in the illustrated example, on a semiconductor substrate 14 of a first conductivity type, P type in the illustrated example. One principal surface of the substrate 11, that is, the side having the semiconductor layer 15, has a depth across which an isolation region 16 having the same conductivity type as the substrate 14 reaches the substrate 14 by, for example, selective diffusion. Main surface 11 of
Facing a, it is formed, for example, in a grid pattern,
An NPN transistor 13 is formed in one island region 15A surrounded by this isolation region 16, and a semiconductor capacitive element 12 according to the present invention is formed in another island region 15B similarly surrounded by the isolation region 16. It consists of being done. 17 and 18
denotes a second conductivity type high concentration buried region formed as necessary in the portion where the transistor 13 and the capacitive element 12 are formed, respectively, and these buried regions 17 and 18 are epitaxial regions of the semiconductor layer 15 It can be formed by selective diffusion prior to growth. 19 is
A collector region of an NPN transistor, which is made up of a part of an N-type semiconductor layer 15. A P-type base region 20 is formed in a part of this collector region 19 by, for example, selective diffusion, and this base region An N-type emitter region 21 having a relatively high impurity concentration is formed on a portion of the semiconductor device 20 by, for example, selective diffusion. Further, on the collector region 19, a highly impurity-concentrated collector electrode lead-out region 22 can be formed simultaneously with the diffusion of the emitter region 21. 23, 24, 2
Reference numerals 5 denote an emitter electrode, a base electrode, and a collector electrode which are ohmicly deposited on the emitter region 21, the base region 20, and the high concentration region 22 of the collector region 19, respectively.

Further, in the other island region 15B, a first insulating film is formed such that a part thereof straddles the isolation region 16 at the same time as the base region 20 of the NPN transistor 13 is diffused.
A region 26 of a conductivity type is formed, and a region 27 of a second conductivity type is formed thereon simultaneously with the formation of the emitter region 21 of the transistor 13, for example, by selective diffusion.

In this way, a first region 28 of the first conductivity type is formed by a part of the isolation region 16 surrounding the island region 15B, the substrate 14 under the island region 15B, and the region 26. This first region 28 is formed, and a first region 28 made of a part of the semiconductor layer 15 is formed on the lower and upper sides of the region 26 extending along the main surface of the base body 11 sandwiching the region 26 in the thickness direction. 2nd conductivity type second region 29 and main surface 11 of base 11
A third region 27 of the second conductivity type facing a is formed separately. Further, a part of the second region 29 faces the main surface 11a of the base 11, and regions 21 and 27 are formed in the portion facing the main surface 11a, for example, by selective diffusion and at the same time, high concentration electrode extraction. A region 30 is formed.

And on this electrode extraction area 30,
The first electrode 31 is electrically connected to the second region 29, and the first electrode 31 is connected over the region 27 via an insulating layer 32 formed on the region 27. to form.

The insulating layer 32 here can be formed, for example, from an oxide SiO ₂ coating produced during the selective diffusion of the region 27 .
Further, a second electrode 33 is ohmicly connected to, for example, the isolation region 16 and region 26 of the first region 28 and to the third region 27 .

Reference numeral 34 designates a surface-protecting insulating layer formed on the surface (principal surface 11a) of the substrate 11 and made of, for example, a SiO ₂ film, which is formed as a diffusion mask during selective diffusion of each region, or formed during diffusion.

In this case, the isolation region 16, and hence the second electrode 33, are given the lowest potential, such as the ground potential.

The semiconductor capacitive element 12 of the present invention described above has a first electrode 31 between the first and second electrodes 31 and 33.
- Insulating layer 32 - Capacitance due to the MIS structure of region 27, and in parallel thereto, first region 28 and second region 29
junctions formed between regions 26 and 29, J ₁ between isolation regions 16 and 29, junctions J ₂ between regions 29 or buried regions 18 and substrate regions 14; The capacitance formed by each junction capacitance with J ₃ is configured.

As described above, according to the configuration of the present invention, the second region 29 is sandwiched between the substrate region 14 and the region 26 of the first region 28 in the thickness direction, so that the bonding area thereof is equal to that of the first region 28. The junction capacitance is significantly increased compared to the case shown in FIG. 1, and therefore the junction capacitance can be increased, and a capacitive element with a large capacitance is constructed. Further, the formation of the capacitive element 12 does not need to be performed through a special process, and can be formed simultaneously with the formation of each region of other circuit elements, such as the NPN type semiconductor element 13, thereby simplifying the manufacturing process. can.

In the example shown in FIG. 2, the capacitive element 1 is
2, in the examples shown in FIGS. 3 and 4, the PN junction generated in the diffusion region 26 corresponding to the so-called base region 20 of the transistor element 13 as explained in FIG. This is a case where a semiconductor capacitive element is configured with the junction capacitance of . In FIGS. 3 and 4, parts corresponding to those in FIG. 2 are given the same reference numerals, and parts corresponding to the transistor element 13 in FIG. 2 are omitted.

In FIG. 3, the region 26 is separated from the isolation region 16, and the base region 2 of the transistor 13 explained in FIG.
0, and similarly form the second region 27.
Emitter region 2 of transistor 13 explained in the figure
1, this region 27 extends outside the region 26 and becomes a part of the second region 29, that is, the island region 15.
A first electrode 31 is ohmically connected to the region 26 and is formed to face the region 27 with an insulating layer 32 in between. This is a case in which the second electrode 33 is ohmicly connected to the third region 27, and in this case also a capacitance is formed by the MIS structure formed by the electrode 31, the insulating layer 32, and the region 27. Also, a large-capacitance capacitive element is constructed by using the PN junction formed between the third region 27 and the second region 29, which are formed by sandwiching the region 26 in parallel with this in the thickness direction, as a junction capacitor. . area 2 here
It goes without saying that the connection between 7 and 29 can also be made by external connection.

Further, in the example of FIG. 4, the region 26 is formed so as to straddle a part of the isolation region 16,
The first electrode 31 is connected to the isolation region 16 and the third region 2 is connected via the insulating layer 32.
In other words, the insulating layer 32
This is a case in which the third region 27 is formed so as to straddle the third region 27 via the third region 27 .

[Brief explanation of the drawing]

FIG. 1 is an enlarged sectional view of a semiconductor capacitive element used for explaining the present invention, FIG. 2 is a sectional view of a main part of a semiconductor integrated circuit using a semiconductor capacitive element according to the present invention, and FIGS. FIG. 7 is a cross-sectional view showing another example of a capacitive element. 11 is a semiconductor substrate, 14 is a semiconductor substrate region thereof, 15 is a semiconductor layer, 11a is a main surface, 1
2 is a semiconductor capacitive element according to the present invention; 13 is a transistor element; 19, 20 and 21 are collector, base and emitter regions of the transistor element 13;
28 is a first region, 29 is a second region, 27 is a third region, and J ₁ , J ₂ and J ₃ are junctions.

Claims (1)

[Claims] 1. An island region of a second conductivity type surrounded by a region of a first conductivity type is provided in a semiconductor substrate, a first region of a first conductivity type is provided within the island region, and the first region is , having a region extending parallel to the main surface of the semiconductor substrate, and having a second conductivity type second conductivity type in the island region on the upper and lower sides thereof, respectively, by the region portion of the first region. 3 and the second area,
A first electrode connected to the first region is formed so as to straddle the third region via an insulating layer, and the second and third regions are electrically connected to each other. a second area in at least one of the areas.
A semiconductor capacitive element consisting of connected electrodes.