JP7252060B2 - Semiconductor light emitting device and manufacturing method thereof - Google Patents

Description

The present invention relates to a semiconductor light emitting device and its manufacturing method.

Semiconductor light-emitting devices, which started with red light-emitting diodes based on AlGaAs, have come to be able to handle all wavelengths such as visible light and infrared light. Among such semiconductor light emitting devices, when the emission wavelength is in the green to near-infrared region of 600 to 900 nm, it is common to use an AlGaAs or AlGaInP group III-V semiconductor for the light emitting layer. Further, when the emission wavelength is in the near-infrared region of 1000 nm to 2200 nm, an InGaAsP-based III-V group semiconductor containing In and P is generally used for the light emitting layer. Conventionally, when an InGaAsP-based III-V semiconductor layer such as an InP layer is epitaxially grown, the growth substrate and the InGaAsP-based III-V semiconductor layer containing In and P are lattice-matched. has been used as In particular, semiconductor light-emitting devices that emit infrared light with an emission wavelength of 750 nm or more are widely used in applications such as sensors, gas analysis, monitoring cameras, and health care of living bodies. Semiconductor light-emitting devices using InGaAsSb group III-V semiconductors containing Sb as semiconductor light-emitting layers emitting light in the far-infrared region of 2000 to 6000 nm are widely used in applications such as gas sensors.

2. Description of the Related Art In semiconductor light emitting devices used for light sources that emit not only infrared light but also ultraviolet light or visible light, there is a demand for higher output in order to reduce costs or increase mounting density.

By the way, since the light-emitting element made of the III-V group semiconductor material as described above has a small problem that the current from the electrode is difficult to spread in the horizontal direction, the shape of the n-electrode or p-electrode or the electrode wiring pattern is the group III nitride semiconductor material. It has a very simple shape compared to a light-emitting element using a solid semiconductor material. One of the methods for increasing the output power of semiconductor light emitting devices is to improve the external quantum efficiency by improving light extraction technology, as in Patent Document 1. In the technique of Patent Document 1, the intermediate electrode portion, which is the contact portion, is not arranged in alignment with the upper electrode portion, but is evenly dispersed with respect to the second conductivity type layer. The area ratio to the mold semiconductor layer is set to 3 to 9%.

Further, Patent Document 2 discloses that a semiconductor multilayer structure is grown on a growth substrate having a substrate off-angle within a range that can substantially maintain the crystallinity of the semiconductor multilayer structure, and an intermediate electrode portion that is a contact portion is provided. Disclosed are a semiconductor light emitting device and a method of making a semiconductor light emitting device that are evenly dispersed in a layer of a second conductivity type. Further, Patent Document 2 discloses an example in which dot-shaped intermediate electrodes are not arranged directly below the upper electrode.

JP 2011-129724 A JP 2009-206265 A

As in the techniques of Patent Documents 1 and 2, if the electrode area of the intermediate electrode or the upper electrode is reduced, the area that contributes to the extraction of light is increased, so the light emission output is generally increased. However, when the electrode area is reduced, the electrical resistance (forward voltage) for current flow increases, so the heat generation effect when a large current flows is too large to be ignored. Therefore, there arises a problem that the linear relationship between the current and the output, which is maintained when the current is low, greatly affects the factors for maintaining the relationship when the current is large. For example, when assuming use under high pulse current application conditions, the semiconductor light emitting device is required to have a sufficiently low voltage when a high current is applied and to maintain the linearity of the current-light output characteristics. .

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a semiconductor light-emitting device capable of suppressing a decrease in light-emitting output while maintaining the linearity of current-light output characteristics even when a large current is applied, and a method of manufacturing the same.

The inventors of the present invention focused on the positional relationship between the intermediate electrode and the upper surface electrode, and conducted further studies to find a way to solve the above-mentioned problems. As a result, a semiconductor light emitting device having a first conductivity type semiconductor layer, a semiconductor light emitting layer, a second conductivity type semiconductor layer, and an upper surface electrode in this order on a supporting substrate via a bonding layer including an intermediate electrode. , as an example of a mode in which the current flows relatively smoothly in the plane direction of the second conductivity type semiconductor layer in contact with the upper electrode, for example, the n-type semiconductor layer having a lower resistivity than the p-type semiconductor layer is replaced with the second conductivity type semiconductor When used in a layer, it was found that light emission (current density) is greater around the upper portion of the intermediate electrode than around the lower portion of the wiring portion of the upper electrode. The inventors have also found that when a large current is applied, evenly arranging the intermediate electrodes is effective for spreading the current relatively smoothly in the planar direction of the second conductivity type semiconductor layer. The inventors also found that the linearity between the current and the output is maintained by placing the intermediate electrode directly under the wiring portion having a specific short axis length (the maintenance rate of the light emission output is high). Completed.

That is, the gist and configuration of the present invention are as follows.
(1) A semiconductor light emitting device according to the present invention comprises a support substrate, a bonding layer including an intermediate electrode, and a first conductivity type semiconductor layer, a semiconductor light emitting layer, and a second conductivity type semiconductor layer each made of a Group III-V compound semiconductor. A semiconductor light emitting device having in this order,
having an upper surface electrode comprising a pad portion and a wiring portion on the main surface of the second conductivity type semiconductor layer;
The wiring part has a long body with a short axis length of 5 to 12 μm,
a region on the main surface other than the top electrode forming region in which the top electrode is formed is partitioned into a plurality of light extraction regions by the wiring portion;
The intermediate electrodes each have a plurality of island-shaped first intermediate electrodes and second intermediate electrodes, and on a projection plane obtained by vertically projecting the intermediate electrodes onto the main surface,
(a) the intermediate electrode includes the first intermediate electrode arranged such that the projections of the first intermediate electrode closest to each other in the division of the light extraction region are equidistantly spaced apart X;
(b) the intermediate electrode includes the second intermediate electrode arranged so that the projection of the second intermediate electrode and the wiring portion overlap;
(c) a proximity distance Y between the second intermediate electrode and the first intermediate electrode closest to the second intermediate electrode among the first intermediate electrodes is X/ ₂ or more and less than 3X/2;
It is characterized by
As a result, it is possible to provide a semiconductor light emitting device that suppresses a decrease in light output while maintaining the linearity of current-light output characteristics even when a large current is applied.

(2) In the semiconductor light emitting device according to the present invention, the intermediate electrode includes the first intermediate electrode and the second intermediate electrode arranged such that projections of the first intermediate electrode and the second intermediate electrode are out of the pad section. It is preferable to further include a second intermediate electrode.
Thereby, it is possible to provide a semiconductor light emitting device that further suppresses a decrease in light emission output.

(3) In the semiconductor light emitting device according to the present invention, it is preferable that the pad portion is provided in the central portion of the main surface.
Thereby, it is possible to provide a semiconductor light emitting device that further suppresses a decrease in light emission output.

(4) In the semiconductor light emitting device according to the present invention, in the relationship between the first intermediate electrode and the second intermediate electrode in at least one of the light extraction regions, the second intermediate electrode is placed second among the first intermediate electrodes. It is preferable to dispose the first intermediate electrode and the second intermediate electrode such that the distance _Y2 between the first intermediate electrode and the second intermediate electrode adjacent to the electrode and the distance _Y1 are the same. .
Thereby, it is possible to provide a semiconductor light emitting device that further suppresses a decrease in light emission output.

(5) In the semiconductor light emitting device according to the present invention, in the relationship between the first intermediate electrode and the second intermediate electrode at the boundary between all the light extraction regions and the wiring portion, The first intermediate electrode and the second intermediate electrode are arranged so that the proximity distance _Y2 between the first intermediate electrode second closest to the second intermediate electrode and the second intermediate electrode is the same as the proximity distance _Y1 . It is preferred to arrange the electrodes.
Thereby, it is possible to provide a semiconductor light emitting device that further suppresses a decrease in light emission output.

(6) In the semiconductor light-emitting device according to the present invention, it is preferable that the III-V group compound semiconductor is InGaAsP containing at least In and P, and that the semiconductor light-emitting layer has an emission central wavelength of 1000 to 2200 nm.
Thereby, it is possible to provide a semiconductor light emitting device that further suppresses a decrease in light emission output.

(7) A method for manufacturing a semiconductor light emitting device according to the present invention includes: a supporting substrate; a bonding layer including a plurality of island-shaped first intermediate electrodes and second intermediate electrodes; A method for manufacturing a semiconductor light-emitting device having a type semiconductor layer, a semiconductor light-emitting layer and a second conductivity type semiconductor layer in this order,
a semiconductor layer forming step of forming a semiconductor laminate including the second conductivity type semiconductor layer, the light emitting layer and the first conductivity type semiconductor layer on a substrate for growth;
a bonding layer forming step of bonding the support substrate and the semiconductor laminate via a bonding layer including the first intermediate electrode and the second intermediate electrode;
a growth substrate removing step of removing the growth substrate;
An upper electrode comprising a pad portion and a wiring portion is formed on the main surface of the semiconductor laminate from which the growth substrate has been removed, and a region on the main surface other than the upper electrode forming region in which the upper electrode is formed is: a step of forming an upper surface electrode partitioned into a plurality of light extraction regions by the wiring portion;
On a projection plane obtained by vertically projecting the first intermediate electrode and the second intermediate electrode with respect to the main surface,
(a) the first intermediate electrode is arranged such that the projections of the first intermediate electrode closest to each other in the division of the light extraction region are equidistantly spaced apart X;
(b) the second intermediate electrode is arranged such that the projection of the second intermediate electrode and the wiring portion overlap;
(c) a proximity distance Y between the second intermediate electrode and the first intermediate electrode closest to the second intermediate electrode among the first intermediate electrodes is X/ ₂ or more and less than 3X/2;
It is characterized by
As a result, even when a large current is applied, it is possible to manufacture a semiconductor light emitting device that suppresses a decrease in light emission output while maintaining the linearity of current-light output characteristics.

(8) In the method for manufacturing a semiconductor light emitting device according to the present invention, the first intermediate electrode and the second intermediate electrode are arranged such that projections of the first intermediate electrode and the second intermediate electrode are separated from the pad section. is preferably arranged.
This makes it possible to manufacture a semiconductor light emitting device that further suppresses a decrease in light emission output.

(9) In the method for manufacturing a semiconductor light emitting device according to the present invention, in the relationship between the first intermediate electrode and the second intermediate electrode in at least one of the light extraction regions, The first intermediate electrode and the second intermediate electrode are arranged such that the proximity distance _Y2 between the first intermediate electrode and the second intermediate electrode adjacent to the second intermediate electrode is the same as the proximity distance _Y1 . preferably.
This makes it possible to manufacture a semiconductor light emitting device that further suppresses a decrease in light emission output.

(10) In the method for manufacturing a semiconductor light emitting device according to the present invention, in the relationship between the first intermediate electrode and the second intermediate electrode at the boundary between all the light extraction regions and the wiring portion, the first intermediate electrode The first intermediate electrode and the second intermediate electrode are arranged such that the proximity distance _Y2 and the proximity distance _Y1 between the second intermediate electrode and the first intermediate electrode that is second closest to the second intermediate electrode are the same. A second intermediate electrode is preferably arranged.
This makes it possible to manufacture a semiconductor light emitting device that further suppresses a decrease in light emission output.

According to the present invention, it is possible to provide a semiconductor light-emitting device capable of suppressing a decrease in light-emitting output while maintaining the linearity of current-light output characteristics even when a large current is applied, and a method of manufacturing the same.

1 is a plan view of a preferred semiconductor light emitting device of the present invention; FIG. FIG. 1B is a schematic cross-sectional view of the semiconductor light emitting device of FIG. 1A taken along line II. FIG. 1B is a schematic cross-sectional view of the semiconductor light emitting device of FIG. 1A taken along line II-II. FIG. 4 is a plan view showing an example of a top electrode applicable to the present invention; It is a cross-sectional schematic diagram which shows an example of the manufacturing method of the semiconductor light-emitting device of this invention. It is a cross-sectional schematic diagram which shows an example of the manufacturing method of the semiconductor light-emitting device of this invention following FIG. It is a cross-sectional schematic diagram which shows an example of the manufacturing method of the intermediate electrode of this invention. FIG. 4 is a schematic cross-sectional view showing an example of the method for manufacturing the semiconductor light emitting device of the present invention following FIG. 3 ; FIG. 6 is a schematic cross-sectional view showing an example of the method for manufacturing the semiconductor light emitting device of the present invention following FIG. 5 ; 4 is a plan view after forming an intermediate electrode on the semiconductor layer in Example 1. FIG. FIG. 10 is a plan view after forming the upper surface electrode in Example 1; 4 is a projection plane in which the intermediate electrode in Example 1 is projected onto the surface of the n-type cladding layer. FIG. 7B is a plan view with detailed dimensional symbols. 2 is a plan photograph of the semiconductor light emitting device produced in Example 1 during light emission. 2 is a plan view of a semiconductor light emitting device manufactured in Comparative Example 1; FIG. 3 is a plan view of a semiconductor light emitting device produced in Comparative Example 2; FIG. FIG. 11 is a plan view of a semiconductor light emitting device fabricated in Example 6;

Prior to describing embodiments according to the present invention, the following points will be described in advance.
(definition)
First, in this specification, simply referring to a "III-V group compound semiconductor", its composition is represented by the general formula: (In _a Ga _b Al _c )(P _x As _y Sb _z ). Here, the following relationship holds for the composition ratio of each element. For Group III elements, the relationships c=1−a−b, 0≦a≦1, 0≦b≦1, and 0≦c≦1 are established. On the other hand, the relationships of z=1-xy, 0≤x≤1, 0≤y≤1, 0≤z≤1 are established for group V elements. As will be described later, the group III-V compound semiconductor layer in the semiconductor light-emitting layer contains at least one group III element selected from the group consisting of Al, Ga, and In, and selected from the group consisting of As, Sb, and P. It is configured by selecting one or more group V elements.

Further, in the present specification, when simply referred to as “InGaAsP” without specifying the composition ratio, the chemical composition ratio between the group III element (the sum of In and Ga) and the group V element (As, P) is 1 : 1 and the ratio of group III elements In and Ga and the ratio of group V elements As and P are indefinite. The composition ratio of each component such as InGaAsP or InGaAs can be measured by photoluminescence measurement, X-ray diffraction measurement, or the like. In addition, the "unavoidable contamination in manufacturing" referred to here means, in addition to unavoidable contamination in the manufacturing equipment using the raw material gas, the diffusion phenomenon of atoms at each layer interface during crystal growth or subsequent heat treatment. do.

Further, in this specification, a layer that electrically functions as p-type is referred to as a p-type semiconductor layer (sometimes abbreviated as “p-type layer”), and a layer that electrically functions as n-type is referred to as n-type. It is called a semiconductor layer (sometimes abbreviated as “n-type layer”). On the other hand, when specific impurities such as Zn, S, Sn, C, and Si are not intentionally added and do not function electrically as p-type or n-type, they are called “i-type” or “undoped”. . ^An undoped InGaAsP layer ^may contain unavoidable impurities during the manufacturing process. shall be dealt with herein. Also, the value of impurity concentration such as Zn or Sn is based on SIMS analysis.

In addition, the overall film thickness of each layer to be formed can be measured using an optical interference film thickness measuring instrument. Further, the film thickness of each layer can be calculated from cross-sectional observation of the grown layer using an optical interference film thickness measuring instrument and a transmission electron microscope. Moreover, when the film thickness of each layer is small like a superlattice structure, the film thickness can be measured using TEM-EDS. In the cross-sectional view, when a predetermined layer has an inclined surface, the maximum height from the flat surface of the layer immediately below the layer is used as the film thickness of the layer.

(semiconductor light emitting device)
Embodiments of the present invention will be exemplified in detail below with reference to the drawings. In principle, the same reference numerals are given to the same components, and redundant explanations are omitted. In each drawing, for convenience of explanation, the vertical and horizontal ratios of the substrate and each layer are exaggerated from their actual ratios. Among the configurations shown in FIGS. 1A to 1C, the correspondence relationship between the upper surface electrode 93 and the intermediate electrodes (general term for the first intermediate electrode 53a and the second intermediate electrode 53b) will be described in advance. The upper surface electrode 93 is composed of a pad portion 93d (generic name for the ohmic metal layer pad portion 93b and the pad electrode layer 93c) and a wiring portion 93a (also referred to as the wiring portion 93a of the ohmic metal layer 93e). For convenience of explanation, the ohmic metal layer pad portion 93b and the pad electrode layer 93c, which are the pad portion 93d (simply referred to as the pad portion) of the upper surface electrode 93, are indicated by hatching. FIG. 1A is a top view of one mode of the semiconductor light emitting device according to the present invention, viewed from the top electrode side in the film thickness direction. Further, for convenience of explanation, FIG. 1A shows a projection plane obtained by vertically projecting the first intermediate electrode 53a and the second intermediate electrode 53b with respect to the main surface of the second conductivity type semiconductor layer 31. A projection of the electrode 53a is indicated by a white circle, and a projection of the second intermediate electrode 53b is indicated by a black circle. FIG. 1B is a cross-sectional view of the semiconductor light emitting device taken along line II of FIG. 1A. FIG. 1C is a cross-sectional view of the semiconductor light emitting device taken along line II-II of FIG. 1A. Therefore, FIG. 1B shows, as an example, a state in which two first intermediate electrodes 53a are formed in the bonding layer 50 as intermediate electrodes. On the other hand, FIG. 1C shows, as an example, a state in which four second intermediate electrodes 53b are formed in the bonding layer 50 as intermediate electrodes.

Embodiments of the semiconductor light emitting device according to the present invention will be described below. As shown in FIGS. 1B and 1C, a semiconductor light emitting device 100 according to the present invention includes a supporting substrate 80 and a bonding structure including intermediate electrodes (first intermediate electrode 53a and second intermediate electrode 53b) on the supporting substrate 80. It has at least the layer 50 , the semiconductor laminate 30 on the bonding layer 50 , and the upper surface electrode 93 on the semiconductor laminate 30 . The semiconductor laminate 30 has at least a configuration in which a first conductivity type semiconductor layer 37, a semiconductor light emitting layer 35, and a second conductivity type semiconductor layer 31 made of III-V compound semiconductors are sequentially provided. The upper surface electrode 93 formed on the main surface portion 31C of the second conductivity type semiconductor layer 31 includes a wiring portion 93a and a pad portion 93d. Further, the wiring portion 93a has a long body with a short axis length of 5 to 12 μm. Further, as shown in FIGS. 1A to 1C, the main surface portion 31C of the second conductivity type semiconductor layer 31 has a plurality of light extraction regions formed by wiring portions 93a in regions other than the upper electrode forming region where the upper electrode 93 is formed. (In the example of FIG. 1A, light extraction areas S ₁ , S ₂ , S ₃ , S ₄ ). Further, the intermediate electrodes include first intermediate electrodes 53a and second intermediate electrodes 53b each formed like a plurality of islands. The bonding layer 50 includes a first contact portion 40a including a first intermediate electrode 53a and a contact layer portion 51a, a second contact portion 40b including a second intermediate electrode 53b and a contact layer portion 51a, and a dielectric layer 55. , a metal reflective layer 60 and a metal bonding layer 70 . Furthermore, as shown in FIG. 1A, the following three arrangement conditions ( The semiconductor light emitting device 100 includes a first intermediate electrode 53a, a second intermediate electrode 53b, a wiring portion 93a and a pad portion 93d arranged to satisfy a) to (c).
(a) The intermediate electrodes are arranged such that the projections of the first intermediate electrodes 53a closest to each other are equidistantly spaced X in the divisions of the light extraction regions _S1 , _S2 , _S3 , and _S4 . , including the first intermediate electrode 53a.
(b) The intermediate electrode includes the second intermediate electrode 53b arranged so that the projection of the second intermediate electrode 53b and the wiring portion 93a overlap.
(c) The proximity distance Y1 between the first intermediate electrode 53a closest to the second intermediate electrode 53b among the first intermediate electrodes 53a and the second intermediate electrode _53b is not less than X/2 and less than 3X/2.
Here, as shown in FIG. 1A, the first intermediate electrode 53a and the first intermediate electrode 53a closest to the second intermediate electrode 53b among the first intermediate electrodes 53a in at least the same light extraction regions S ₁ to S ₄ The proximity distance to the second intermediate electrode is denoted as proximity distance _Y1 . Furthermore, the proximity distance between the first intermediate electrode 53a and the second intermediate electrode 53b, which is the second closest to the second intermediate electrode 53b among the first intermediate electrodes 53a, is denoted as proximity distance _Y2 . W represents the minor axis length of the wiring portion 93a. In this specification, the phrase “divided into a plurality of light extraction regions” means that the wiring portion 93a is extended to the edge of the main surface of the second conductivity type semiconductor layer 31 along the longitudinal direction of the wiring portion 93a. It means to divide into areas that occur in time.

In the semiconductor light emitting device 100 according to the present invention, the semiconductor light emitting layer 35 is sandwiched between the first conductivity type semiconductor layer 37 and the second conductivity type semiconductor layer 31, so that the semiconductor light emitting layer 35 can be Inside, electrons and holes combine to emit light. A main surface portion 31C of the second conductivity type semiconductor layer 31 is the light extraction side of the semiconductor light emitting device.

If the semiconductor layer of the first conductivity type is p-type, the semiconductor layer of the second conductivity type will be n-type. Conversely, if the semiconductor layer of the first conductivity type is n-type, the semiconductor layer of the second conductivity type will be p-type. . A mode in which the semiconductor layer of the first conductivity type is p-type and the semiconductor layer of the second conductivity type is n-type will be described below.

In addition, as shown in FIGS. 1B and 1C, in the semiconductor light emitting device 100, a back surface electrode 91 may be formed on the back surface of the support substrate 80. FIG. Furthermore, a p-type cap layer 39 may be formed between the first conductivity type semiconductor layer 37 and the bonding layer 50 if necessary.

Hereinafter, each component of the semiconductor light emitting device of the present invention will be illustrated in detail with reference to FIGS. 1A to 1C.

<Intermediate electrode>
As shown in FIGS. 1A to 1C, in the present invention, the intermediate electrode is an electrode arranged inside the semiconductor light emitting device 100, more specifically inside the bonding layer 50. FIG. The intermediate electrode is arranged in the bonding layer 50 between the support substrate 80 and the semiconductor stack 30 including the semiconductor light-emitting layer 35 made of a group III-V compound semiconductor, and electrically connects the semiconductor stack 30 and the support substrate 80 together. Connecting. The intermediate electrode is composed of the first intermediate electrode 53a and the second intermediate electrode 53b, and the intermediate electrode in this specification is a generic term for the first intermediate electrode 53a and the second intermediate electrode 53b.

The first intermediate electrode 53a and the second intermediate electrode 53b have a so-called islands-in-the-sea structure in which a plurality of islands are formed in the bonding layer 50, respectively.

The first intermediate electrode 53a and the second intermediate electrode 53b in this specification will be described. In the plane of projection perpendicular to the main surface of the second conductivity type semiconductor layer on which the upper surface electrode 93 is formed, there is no overlap with the wiring portion 93a, and within the divisions of the light extraction regions (light extraction regions S ₁ to S _{4 )} . ) is called a first intermediate electrode 53a. In this projection plane, the intermediate electrode arranged so that the projection of the intermediate electrode and the wiring portion 93a overlap is referred to as a second intermediate electrode 53b. It is preferable that the center of the second intermediate electrode 53b coincides with the longitudinal centerline of the wiring portion 93a and is arranged directly under the wiring portion 93a. It corresponds to "overlapping". Further, even if the center of the second intermediate electrode 53b is positioned within a quarter of the short axis length in the short axis direction of the wiring portion 93a from the center line of the wiring portion 93a in the longitudinal direction, the projection of the intermediate electrode The body and the wiring part overlap". However, even if the projected body of the intermediate electrode and the wiring portion 93a are arranged close to each other and partly overlap with each other on the projection plane, the center of the second intermediate electrode 53b is the center of the wiring portion 93a in the longitudinal direction. Anything located beyond a quarter of the minor axis length in the minor axis direction of the wiring portion 93a from the line is treated as not corresponding to either the first intermediate electrode 53a or the second intermediate electrode 53b. Such an intermediate electrode is called a third intermediate electrode for convenience of explanation. In FIG. 9 showing a plan view (including projections of the intermediate electrodes) of Comparative Example 1, which will be described later, such a third intermediate electrode is indicated by a thick open circle.

The first intermediate electrode 53a and the second intermediate electrode 53b may each be of the same material, shape and size, or may be of different materials, shapes or sizes. The first intermediate electrode 53a and the second intermediate electrode 53b are preferably of the same material, shape and size. It is preferable that the first intermediate electrode 53a and the second intermediate electrode 53b differ only in their in-plane positional relationship.

The shape, material and size of the first intermediate electrode 53a and the second intermediate electrode 53b are not particularly limited as long as they have the function of electrically connecting the semiconductor laminate 30 and the support substrate 80 . For example, the shapes of the first intermediate electrode 53a and the second intermediate electrode 53b may be (substantially) cylindrical, (substantially) elliptical cylindrical, (substantially) conical, (substantially) truncated conical, and (substantially) elliptical conical. Trapezoidal, (regular) triangular prismatic, (regular) quadrangular prismatic, (regular) polygonal prismatic, indefinite, etc., and (substantially) cylindrical or (substantially) truncated conical are preferred.

The cross-sectional shape of the intermediate electrode may be trapezoidal in cross-sectional view as shown in FIGS. 1B, 1C and step D of FIG. In other words, the shape of the intermediate electrode may be rectangular in the cross-sectional view, or may have rounded corners. As described above, the size of the "intermediate electrode" in the present invention indicates the maximum size when the intermediate electrode is viewed from above (the base of the maximum area in the case of a trapezoid in the sectional view). Therefore, the maximum cross-sectional length of the intermediate electrode, that is, the maximum length of the cross section obtained by cutting the first intermediate electrode 53a or the second intermediate electrode 53b in the plane direction of the semiconductor stacked body 30, depends on the size of the wiring portion 93a and the length of the upper surface electrode 93. Although it can be changed as appropriate depending on the shape or position, it is preferably 0.2 to 8 μm, for example. Specifically, the maximum diameter d ₁ of the first intermediate electrode 53a and the maximum diameter d ₂ of the second intermediate electrode shown in FIG. 7C shown in the examples described later correspond to the maximum length of the intermediate electrode.

Furthermore, although the shape of the cross section in the plane direction of each of the first intermediate electrode 53a and the second intermediate electrode 53b is not particularly limited, a circular or elliptical diameter is preferable.

Further, for example, the number of first intermediate electrodes 53a per chip of the semiconductor light emitting device is preferably 56 to 104.

Further, for example, it is preferable that the number of the second intermediate electrodes 53b per chip of the semiconductor light emitting device is 8 to 12.

<Top electrode>
As shown in FIGS. 1A to 1C, in the present invention, the upper electrode 93 is arranged on the semiconductor laminate 30 including the semiconductor light emitting layer 35 made of a III-V compound semiconductor, and can be electrically connected to the outside. electrode. The polarities of the intermediate electrode and the upper electrode 93 are different, and light is emitted in the semiconductor light emitting layer 35 by flowing a current between the intermediate electrode and the upper electrode 93 . The upper surface electrode 93 is composed of a pad portion 93d and a wiring portion 93a. More specifically, the upper surface electrode 93 is composed of a pad portion 93d and a wiring portion 93a extending outwardly from the pad portion 93d and electrically connected to the pad portion. The pad portion 93d is a circular or polygonal electrode portion that is used for bump bonding or wire bonding for conducting electricity from the outside. On the other hand, the wiring portion 93a is a portion where a fine wire of the (wiring) electrode extends from the pad portion 93d. In order to form such a top electrode 93, an ohmic metal layer 93e including an ohmic metal layer pad portion 93b and a wiring portion 93a connected to the ohmic metal layer pad portion 93b is formed, and then the ohmic metal layer 93e is formed. A pad electrode layer 93c is formed on the ohmic metal layer pad portion 93b.

As the shape of the wiring part 93a, in addition to the X shape shown in FIG. FIG. 1D (ii)), various shapes such as Z-shape and S-shape (see, for example, FIG. 1D). Further, the short axis length (also referred to as the line width of the wiring portion 93a) W of the elongated body of the wiring portion 93a is 5 to 12 μm, preferably 5 to 9 μm. If the thickness is less than 5 μm, although light output (Po) is improved due to difficulty in blocking light, the forward voltage (contact resistance) increases and the linearity of the current-light output characteristics (Po maintenance rate) decreases. be. On the other hand, when the thickness exceeds 12 μm, the effect of lowering the light extraction efficiency due to blocking of light exceeds the effect of lowering the forward voltage (contact resistance). Therefore, when the short axis length W exceeds 12 μm, the Po maintenance factor increases, but the light emission output (Po) decreases significantly, and the WPE (Wall-Plug Efficiency) decreases. Moreover, the elongated body is not limited to a straight line, and may have a curved shape, or may have a wavy shape such as a sine wave.

<Aspects of Intermediate Electrode, Top Electrode, and Light Extraction Region>
In the semiconductor light emitting device 100 of the present invention, a projection plane obtained by vertically projecting the first intermediate electrode 53a and the second intermediate electrode 53b onto the main surface of the second conductivity type semiconductor layer (eg, n-type semiconductor layer) 31 is assumed. An example of a diagram is FIG. 1A. As shown in FIG. 1A, the main surface of the second-conductivity-type semiconductor layer 31 has a region other than the upper electrode forming region (solid line portion) where the upper electrode 93 is formed. It is partitioned into a plurality of light extraction areas S ₁ , S ₂ , S ₃ and S ₄ . Further, as described above, as the intermediate electrodes, the projecting bodies of the first intermediate electrode 53a and the projecting bodies of the second intermediate electrode 53b are each formed in a plurality of island shapes. In the present embodiment, the projection of the first intermediate electrode and the projection of the second intermediate electrode on the main surface of the second conductivity type semiconductor layer 31 are the first electrodes actually formed on the metal reflective layer 60 . They correspond to the intermediate electrode 53a and the second intermediate electrode 53b, respectively. Therefore, the positions of the first intermediate electrode 53a and the second intermediate electrode 53b on the plane of the projection on the projection plane and the planes of the first intermediate electrode 53a and the second intermediate electrode 53b on the metal reflective layer 60 Consistent with the position above. In this specification, the first intermediate electrode 53a is assumed to match the projection plane of the first intermediate electrode 53a, and the second intermediate electrode 53b is assumed to match the projection plane of the second intermediate electrode 53b. In the figure, the projection of the first intermediate electrode 53a is indicated by a white circle, and the projection of the second intermediate electrode 53b is indicated by a black circle.

In the semiconductor light emitting device 100 of the present invention, assuming a projection plane obtained by vertically projecting the first intermediate electrode 53a and the second intermediate electrode 53b with respect to the main surface of the second conductivity type semiconductor layer 31, the arrangement condition (a ) to (c), the first intermediate electrode 53a, the second intermediate electrode 53b, and the upper surface electrode 93 are arranged in the bonding layer 50, respectively. By arranging the semiconductor light emitting device 100 at positions satisfying the arrangement conditions (a) to (c) in this way, the linearity between the current and the output in the semiconductor light emitting device 100 is maintained.

Hereinafter, an example of the form and positional relationship of the wiring portion 93a, the pad portion 93d, the light extraction region, the first intermediate electrode 53a and the second intermediate electrode 53b will be described more specifically with reference to FIG. 1A.

<<Form and Positional Relationship Between Wiring Portion, Pad Portion, and Light Extraction Region>>
In FIG. 1A, a circular pad portion 93d is provided in the central portion of the main surface of the second conductivity type semiconductor layer 31, and four elongated wiring portions extend radially outward from the pad portion 93d. 93a is extended. The long wiring portion 93a divides the main surface area (inside the two-dot chain line) other than the upper electrode formation area into four light extraction areas S ₁ to S ₄ .

In FIG. 1A, the wiring part 93a which has four elongated bodies was illustrated for convenience of explanation. However, if the wiring portion 93a is electrically connected to the pad portion 93d, and the thin wire including the elongated body extends from the connection point with the pad portion 93d, the shape of the wiring portion 93a and the number of elongated bodies are There are no particular restrictions.

In FIG. 1A, the light extraction regions S ₁ to S ₄ , which are regions other than the upper electrode forming region (inside the two-dot chain line), are drawn symmetrically with respect to the pad portion 93d. The number, shape, and area of the light extraction regions are not particularly limited as long as they can be divided into light extraction regions. However, from the viewpoint of manufacturing efficiency, intermediate electrode arrangement, or current diffusion, it is preferable that the light extraction region exhibits symmetry with respect to the pad portion 93d. The term "symmetry with respect to the pad section" as used herein means that the first intermediate electrodes arranged in different light extraction regions are symmetrical with respect to the pad section. Therefore, when symmetrical operation is performed on the first intermediate electrodes in at least one light extraction region with the pad portion as a reference, it is preferable that the arrangement of the first intermediate electrodes before and after the symmetrical operation match. Such symmetric operations include translation operations, rotation operations, reversal operations, mirror operations, and the like.

Next, the arrangement conditions (a) to (c) and the preferred arrangement condition (d) will be described with reference to FIGS. 1A to 1C. The projections (white circles) of the first intermediate electrode 53a and the projections (black circles) of the second intermediate electrode 53b are arranged so as to satisfy arrangement conditions (a) to (c), preferably arrangement conditions (a) to (d). ), a first intermediate electrode 53a and a second intermediate electrode 53b are formed in the bonding layer 50, respectively.

<<Arrangement condition (a)>>
Arrangement condition (a) is as described above. Here, in other words, the arrangement condition (a) is such that the projections (white circles) of the first intermediate electrodes 53a that are closest to each other in the same light extraction region are equidistantly spaced X apart. , the first intermediate electrode 53a is arranged. However, when two or more light extraction regions are straddled, for example, the projection of the first intermediate electrode 53a existing in the light extraction region S ₁ (white circle) and the projection of the first intermediate electrode 53a (white circle) _.

In addition, on the main surface of the second conductivity type semiconductor layer 31, the projections (white circles) of the first intermediate electrode 53a are arranged at an equal distance X, and the pattern is symmetrical about the pad portion 93d. Thus, it is preferable that a plurality of first intermediate electrodes 53a be arranged in the bonding layer 50. As shown in FIG. Being symmetrical about the pad portion 93d means that the first intermediate electrodes 53a within a specific light extraction region (for example, S ₃ ) partitioned by the wiring portion 93a extending from the pad portion 93d are considered as one group. In this case, it means that the arrangement of (the projection of) the first intermediate electrodes 53a in each group is symmetrical (rotationally symmetrical or linearly symmetrical) with respect to the pad portion 93d. In this case, the (projections of) the first intermediate electrodes 53a need only be arranged at an equidistant interval X within the same group, and the (projections of) the first intermediate electrodes 53a belonging to different groups within different regions. ) need not be equidistant.

<<Arrangement condition (b)>>
Arrangement condition (b) is as described above. Here, in other words, the second intermediate electrode 53b is arranged in the bonding layer 50 so that the projection (black circle) of the second intermediate electrode 53b and the wiring portion 93a overlap. In FIG. 1A, two second intermediate electrodes 53b are arranged to overlap each other for one elongated wiring portion 93a. In addition, "the projection of the second intermediate electrode 53b and the wiring portion 93a overlap" here means that the second intermediate electrode 53b overlaps with the wiring portion 93a in the same manner as the above-described difference between the first intermediate electrode and the second intermediate electrode. The center of the projection (black circle) is positioned within one quarter of the short axis length (5 to 12 μm) of the wiring portion 93a in the short axis direction from the center line of the wiring portion 93a in the longitudinal direction. More preferably, the center of the projection (black circle) of the two intermediate electrodes 53b coincides with the center line. Note that FIG. 1A shows an example in which two second intermediate electrodes 53b are provided for one elongated wiring portion 93a. is not particularly limited.

<<Placement condition (c)>>
Arrangement condition (c) is as described above. Here, in other words, the arrangement condition (c) is a projection of the second intermediate electrode 53b (black circle) and a projection of the first intermediate electrode 53a (white circle) closest to the projection of the second intermediate electrode 53b. ), the first intermediate electrode _53a and the second intermediate electrode 53b are arranged in the bonding layer 50 so that the proximity distance Y1 to the circle) is greater than or equal to X/2 and less than 3X/2. Also, the proximity distance Y ₁ is preferably X or more and less than 3X/2. Furthermore, when there are a plurality of second intermediate electrodes 53b, the proximity distance Z between the projections (black circles) of adjacent second intermediate electrodes 53b is the same as the projection (white circles) of the closest first intermediate electrode 53a. ) is preferably the same as the interval X between the .

When specifically designing the arrangement of the first intermediate electrode 53a and the second intermediate electrode 53b, the positional relationship between both intermediate electrodes may be considered as follows. That is, the projections (white circles) of the first intermediate electrodes 53a are arranged at equal intervals X in one group in the light extraction region partitioned by the wiring portion 93a, and the first intermediate electrode 53a is placed at a position close to the wiring portion 93a. When there is a projection (white circle) of one intermediate electrode 53a, a second intermediate electrode 53b ( ), the newly arranged second intermediate electrode 53b (black circle) may be close to and partially overlap with the first intermediate electrode 53a. In this case, the first intermediate electrodes 53a corresponding to projections (white circles) of the first intermediate electrodes 53a arranged in advance at positions close to the wiring portion 93a may be thinned out. By doing so, the first intermediate electrode 53a is integrated into the second intermediate electrode 53b, and the proximity distance Y1 between the first intermediate electrode 53a and the second intermediate electrode 53b adjacent to the first intermediate electrode _53a is X/ It is possible to easily satisfy the condition that the second intermediate electrode 53b is not arranged at a position where the number is 2 or less. In this way, the total number of the first intermediate electrodes and the second intermediate electrodes (that is, the area of the intermediate electrodes) may be reduced.

<<placement condition (d)>>
As a preferred form of the semiconductor light emitting device 100 according to the present invention, in addition to the above arrangement conditions (a) to (c), the first intermediate electrode 53a and the second intermediate electrode are arranged so as to satisfy the following arrangement condition (d). 53b, wiring portion 93a and pad portion 93d may be arranged. That is, the semiconductor light emitting device 100 according to the present invention has four arrangement conditions (a ) to (d), the first intermediate electrode 53a, the second intermediate electrode 53b, the wiring portion 93a, and the pad portion 93d are preferably provided.

-Placement condition (d)-
The intermediate electrodes further include the first intermediate electrode 53a and the second intermediate electrode 53b arranged so that the respective projections (open circles, black circles) of the first intermediate electrode 53a and the second intermediate electrode 53b are out of the pad portion 93d. It is preferable to include (arrangement condition (d)). In other words, as shown in FIG. 1A, the first intermediate electrode 53a and the second intermediate electrode 53b are arranged so that the respective projections (white circles, black circles) of the first intermediate electrode 53a and the second intermediate electrode 53b do not overlap the pad portion 93d. Preferably, two intermediate electrodes 53b are arranged in the bonding layer 50 . This is because the area of the pad portion 93d is large, and unlike the wiring portion 93a, the emitted light under the pad portion 93d is blocked and the light is not extracted.

In addition, the fact that projections (white circles, black circles) of the first intermediate electrode 53a and the second intermediate electrode 53b do not overlap the pad portion 93d (or are out of the pad portion 93d) means that the pad portion 93d, for example, It means that the centers of projections (open circles, black circles) of the first intermediate electrode 53a and the second intermediate electrode 53b do not exist within the ohmic metal layer pad portion 93b in FIG. 1A.

<<Positional relationship between the first intermediate electrode and the second intermediate electrode>>
In a preferred embodiment of the present invention, the first intermediate electrode closest to the second intermediate electrode 53b among the plurality of first intermediate electrodes 53a in at least the same light extraction region (for example, any one of S ₁ to S ₄ ) It is preferable to dispose the first intermediate electrode 53a and the second intermediate electrode 53b at positions where the proximity distance _Y1 between the electrode 53a and the second intermediate electrode 53b is the largest. Further, in a more preferred embodiment of the present invention, the first intermediate electrode 53a and the second intermediate electrode 53b are arranged at positions where the close distance Y ₁ is the largest in all the light extraction regions (S ₁ to S ₄ ). is preferred.

That is, in the preferred embodiment described above, the proximity distance Y ₁ is the maximum for a state in which the plurality of first intermediate electrodes 53a are arranged in at least the same light extraction region (for example, any one of S ₁ to S ₄ ). A configuration in which the second intermediate electrode 53b is arranged at a larger position (for example, when the first intermediate electrode is arranged at a corner of a regular polygon, a configuration in which the second intermediate electrode is arranged at the geometric center of the regular polygon) ) and intends to satisfy all of the above arrangement conditions (a) to (c).

As one specific mode of arranging the first intermediate electrode 53a and the second intermediate electrode 53b at the position where the proximity distance Y ₁ is the largest, at least one light extraction region (for example, S ₁ to S ₄ In the relationship between the first intermediate electrode 53a and the second intermediate electrode 53b, the first intermediate electrode 53a closest to the second intermediate electrode 53b among the first intermediate electrodes 53a and the second intermediate electrode 53b The first intermediate electrode 53a and the second intermediate electrode 53b may be arranged so that the proximity distance _Y2 to the intermediate electrode _53b and the proximity distance Y1 are the same.

As described above, by arranging the first intermediate electrode 53a and the second intermediate electrode 53b at the position where the proximity distance Y ₁ is the largest, a more excellent light emission output is exhibited, and even when a large current is applied, , the effect of suppressing a decrease in light output is further improved.

Referring to FIG. 7C, which is an example of a semiconductor light emitting device 100 manufactured in Examples described later, for a preferred form of arranging the first intermediate electrode 53a and the second intermediate electrode 53b at the position where the proximity distance Y ₁ is the largest. and explain. In FIG. 7C, wiring portions 93a and pad portions 93d are provided, and projections (white circles and black circles) of the first intermediate electrode 53a and the second intermediate electrode 53b are displayed in the same manner as in FIG. 1A referred to above. there is In the light extraction region S ₁ , the second intermediate electrodes 53b arranged on the wiring portion 93a and the first intermediate electrodes 53a arranged at equal intervals meet the above arrangement conditions (a) to (d). are arranged according to As a preferred form of the first intermediate electrode 53a and the second intermediate electrode 53b in the present invention, the positional relationship between the first intermediate electrode 53a and the second intermediate electrode 53b will be described first.

In FIG. 7C, the first intermediate electrode closest to the second intermediate electrode 53b _x among the first intermediate electrodes 53a is the first intermediate electrode _53ai . Among the first intermediate electrodes 53a, the first intermediate electrode that is second closest to the second intermediate electrode 53b _x is the first intermediate electrode 53a _j . In addition, the first intermediate electrode closest to any second intermediate electrode 53b _y other than the second intermediate electrode 53b _x is the first intermediate electrode 53 _am , and the second intermediate electrode 53 b _y is next closest. The first intermediate electrode is the first intermediate electrode 53a _n . Therefore, the proximity distance between the second intermediate electrode 53b _x and the first intermediate electrode 53a _i closest to the second intermediate electrode 53b _x among the first intermediate electrodes 53a is Y ₁ (here, Y _1ix ). Also, the proximity distance between the first intermediate electrode 53a _j and the second intermediate electrode 53b _x that is second closest to the second intermediate electrode 53b _x is Y ₂ (represented by Y _2jx for the sake of explanation). In this case, the relationship Y _1ix ≤Y _2jx is established. Similarly, the proximity distance Y1 between the second intermediate electrode 53b _y and the first intermediate electrode 53a _m is expressed as _Y1mx , and the proximity distance _Y2 between the second intermediate electrode 53b _y and the first intermediate electrode 53a _{n is} expressed as When expressed as Y _2nx , the relationship Y _1mx ≤ Y _2nx holds.

In a preferred embodiment of the present invention, the intermediate electrode is formed between the first intermediate electrode 53a _i closest to the second intermediate electrode 53b _x among the plurality of first intermediate electrodes 53a and the second intermediate electrode 53b _x . The first intermediate electrode 53a _i and the second intermediate electrode 53b _x arranged at the position where the proximity distance Y ₁ is the largest are included.

（上記式中、Ｙ_1ixは、第１中間電極５３ａ_iと前記交点に配置された第２中間電極５３ｂ_xとの近接距離を表わし、Ｙ_2jxは、第１中間電極５３ａ_jと前記交点に配置された第２中間電極５３ｂ_xとの近接距離を表わす。
また、Ｙ_1myは、第１中間電極５３ａ_mと前記交点に配置された第２中間電極５３ｂ_yとの近接距離を表わし、Ｙ_2nyは、第１中間電極５３ａ_nと前記交点に配置された第２中間電極５３ｂ_yとの近接距離を表わす。）を満たすように、第２中間電極５３ｂ_x、第１中間電極５３ａ_i及び第１中間電極５３ａ_jを配置する。 Here, "arranging the first intermediate electrode and the second intermediate electrode at the position where the value of the proximity distance _Y1 between the first intermediate electrode and the first intermediate electrode is the largest" means the following conditions (I) and It refers to arranging the first intermediate electrode 53a _i and the second intermediate electrode 53b _x so as to satisfy the condition (II).
_Condition (I): n first intermediate electrodes (53a ₁ , 53a ₂ , 53a _{3 .} . . 53a _i , _{53a j . n . _} A second intermediate electrode 53b _x is arranged at an intersection with a straight line along the .
Condition (II): The two first intermediate electrodes other than the combination of the first intermediate electrode 53a _i and the first intermediate electrode 53a _j are defined as the first intermediate electrode 53a _m and the first intermediate electrode 53a _n , and the first intermediate electrode 53a _m and the first intermediate electrode 53a _n at the intersection of a straight line passing through the center of the line segment connecting the first intermediate electrode 53a n and perpendicular to the line segment and a straight line along the longitudinal direction of the wiring portion 93a. 53b _y is positioned and
The following three expressions:

(In the above formula, Y _1ix represents the proximity distance between the first intermediate electrode 53a _i and the second intermediate electrode 53b _x arranged at the intersection, and Y _2jx represents the proximity distance between the first intermediate electrode 53a _j and the intersection. It represents the close distance to the second intermediate electrode 53b _x .
_Y1my represents the close distance between the first intermediate electrode 53a _m and the second intermediate electrode 53b _y arranged at the intersection, and _Y2ny represents the proximity distance between the first intermediate electrode 53a _n and the second intermediate electrode 53b y arranged at the intersection. 2 represents the close distance to the intermediate electrode 53b _y . ), the second intermediate electrode 53b _x , the first intermediate electrode 53a _i and the first intermediate electrode 53a _j are arranged.

The above condition (I) is a necessary condition when arranging the second intermediate electrode 53b _x so as to maximize the proximity distance Y ₁ . That is, as shown in FIG. 7C, the condition where Y _1ix and Y _2jy are the same is the necessary condition for maximizing the proximity distance Y ₁ . In addition, the above condition (II) defines the relationship between the second intermediate electrode 53b _x , the first intermediate electrode 53a _i , and the first intermediate electrode 53a _j , and all the first intermediate electrodes and the second intermediate electrode other than the combination of It is indicated by a second intermediate electrode 53b _y , a first intermediate electrode 53a _m , and a first intermediate electrode 53a _n . Therefore, the proximity distance Y _1ix of the combination of the second intermediate electrode 53b _x , the first intermediate electrode 53a _i , and the first intermediate electrode 53a _j is defined to be equal to or less than the proximity distance Y _1my of the other combination.

Moreover, the conditions (I) and (II) are applied to at least one of the same light extraction regions S ₁ to S ₄ on the top surface, but are applied to all light extraction regions on the top surface. You may

From the above, as a preferred mode of arranging the second intermediate electrode and the first intermediate electrode so as to satisfy the above conditions (I) and (II), at least one of the light extraction regions S ₁ to S ₄ In the relationship between the first intermediate electrode 53a and the second intermediate electrode 53b, the proximity distance between the second intermediate electrode 53b and the first intermediate electrode 53a that is second closest to the second intermediate electrode 53b among the first intermediate electrodes 53a For example, the first intermediate electrode and the second intermediate electrode are arranged so that Y ₂ (Y _2jx in FIG. 7C) and the close distance Y ₁ (Y _1ix in FIG. 7C) are the same.

Further, as another preferred mode of arranging _the second intermediate electrode and the first intermediate electrode, the first intermediate electrode _53a and the second In relation to the intermediate electrodes 53b, the close distance Y ₂ (Y _2jx ) and the proximity distance Y ₁ (Y _1ix in FIG. 7C).

In at least one of the light extraction regions S ₁ to S ₄ , the first intermediate electrode 53a _j closest to the second intermediate electrode 53b _x among the first intermediate electrodes 53a and the second intermediate electrode 53b _x The first intermediate electrode and the second intermediate electrode are arranged so that the proximity distance Y ₂ (Y _2jx in FIG. 7C) and the proximity distance Y ₁ (Y _1ix in FIG. 7C) are the same. There are a plurality of first intermediate electrodes 53a that are closest to the second intermediate electrodes 53b and that have a proximity distance _Y1 with respect to the two intermediate electrodes 53b. In other words, in a preferred embodiment of the present invention, two or more first intermediate electrodes 53a closest to the second intermediate electrode 53b having the same proximity distance Y ₁ with respect to one second intermediate electrode 53b are They exist within the same light extraction regions S ₁ to S ₄ .

Although the distance X between the projections of the first intermediate electrodes 53a that are closest to each other can be changed as appropriate, it is preferably 20 to 40 μm, more preferably 25 to 35 μm.

<Joining layer>
The bonding layer 50 includes the first intermediate electrode 53a and the second intermediate electrode 53b described above, and optionally includes a metal bonding layer 70, a metal reflective layer 60, and a dielectric layer 55. Specific examples are shown in FIGS. 1B and 1C. These figures show the bonding layer 50 as a similar configuration. More specifically, the bonding layer 50 includes a plurality of dielectric layers provided inside such that both ends of electrically connectable contact portions (collective term for the first contact portion 40a and the second contact portion 40b) are exposed from the surface. A metal reflective layer 60 and a metal bonding layer 70 are stacked on the body layer 55 so as to be in contact with the intermediate electrodes (the first intermediate electrode 53a and the second intermediate electrode 53b) in the contact portions 40a and 40b. Preferably. The dielectric layer 55, the metal reflective layer 60, and the metal bonding layer 70, which are preferred constituents of the bonding layer 50, are described below.

<<dielectric layer>>

As shown in FIGS. 1B and 1C, the dielectric layer 55 is a layer made of a dielectric material penetrated from one surface to the other surface by a plurality of contact portions 40a and 40b. Therefore, both ends of the plurality of contact portions 40 a , 40 b , 40 are exposed from both surfaces of the dielectric layer 55 . The plurality of contact portions 40a, 40b and 40 are respectively a contact layer portion 51a in contact with the semiconductor laminate 30 (for example, a p-type layer) and a first intermediate electrode 53a and a second electrode 53a in contact with the contact layer portion 51a. It is composed of an intermediate electrode 53b and an intermediate electrode. For example, as shown in FIG. 1B, the first intermediate electrode 53a is sandwiched between the contact layer portion 51a and the metal reflective layer 60. As shown in FIG. Similarly, the second intermediate electrode 53b is sandwiched between the contact layer portion 51a and the metal reflective layer 60, as shown in FIG. 1C. The intermediate electrodes (the first intermediate electrode 53a and the second intermediate electrode 53b) are in contact with the semiconductor laminate 30 (eg, p-type layer) via the contact layer portion 51a. Therefore, the intermediate electrodes (the first intermediate electrode 53 a and the second intermediate electrode 53 b ) can electrically connect the first conductivity type semiconductor layer 37 and the metal reflective layer 60 .

<<Metal reflective layer>>
The metal reflective layer 60 forms a reflective surface that reflects light, can be electrically connected to the semiconductor stack 30 via intermediate electrodes (the first intermediate electrode 53a and the second intermediate electrode 53b), and can be used for metal bonding, which will be described later. It is a layer that can be bonded to the layer 70 .

<<Metal Bonding Layer>>
The metal bonding layer 70 is a layer bonded to the metal reflective layer 60, and the metal bonding layer 70 and the metal reflective layer 60 may be integrated by bonding. In order to facilitate bonding between the metal reflective layer 60 and the metal bonding layer 70, the metal of the outermost layer on the metal bonding layer 70 side and the metal of the outermost layer of the metal reflective layer 60 on the metal bonding layer 70 side are the same. is preferred.

<Supporting substrate>
Since the support substrate 80 uses a bonding method (see Japanese Patent Application Laid-Open No. 2018-006495), which will be described later, there is no particular limitation in relation to the lattice constant of the semiconductor laminate 30 formed thereon. Suitable materials for the support substrate 80 include, for example, semiconductor materials such as Si materials, metal materials such as Mo, W or Kovar, and known submount substrates using heat-dissipating insulating substrates such as sintered AlN. materials. Further, the support substrate 80 preferably exhibits conductivity.

<Preferred Embodiment of Semiconductor Laminate Layer>
The first conductivity type semiconductor layer 37 and the second conductivity type semiconductor layer 31 are preferably InGaAsP containing at least In and P, most preferably InP. The semiconductor light-emitting layer 35 is preferably a semiconductor light-emitting layer that emits light with an emission center wavelength of 1000 to 2200 nm, and more preferably a layer made of InGaAsP containing at least In and P. Furthermore, in the semiconductor light emitting device 100, when the main surface of the second conductivity type semiconductor layer 31 is used as the light extraction surface, it is preferable that the concave-convex pattern is a random rough surface.

In the semiconductor light emitting device 100 , the light emitted from the semiconductor light emitting layer 35 is roughly divided into light L ₁ directed toward the semiconductor layer 31 of the second conductivity type and light L ₂ directed toward the semiconductor layer 37 of the first conductivity type. In this embodiment, the surface of the second conductivity type semiconductor layer 31 where L ₁ and L ₂ are emitted to the outside (mainly the atmosphere or resin. A protective film that buffers the refractive index difference may be interposed) A region excluding the upper electrode 93 is called a "light extraction surface". When the conductivity type of the semiconductor layer 37 of the first conductivity type is the n-type, the semiconductor layer 31 of the second conductivity type is the p-type. Conversely, when the conductivity type of the first conductivity type semiconductor layer 37 is p-type, the second conductivity type semiconductor layer 31 is n-type.

It is also preferable to leave the etching stop layer 20 between the second conductivity type semiconductor layer 31 and the upper electrode 93 including the pad portion 93d and the wiring portion 93a.

Moreover, it is also preferable that the semiconductor light emitting device 100 further has a protective film on the light extraction surface excluding the upper surface electrode 93 (the pad portion 93d and the wiring portion 93a). SiO ₂ , SiN, ITO, AlN, and the like can be used for the protective film, and SiO ₂ is particularly preferred. The protective film has the effect of suppressing the refractive index difference between the second conductivity type semiconductor layer 31 and the air, thereby enhancing light extraction. A protective film may be provided to protect the side surfaces of the semiconductor light emitting element 100 including the side surfaces of the first conductivity type semiconductor layer 37, the semiconductor light emitting layer 35, and the second conductivity type semiconductor layer 31. FIG.

Each step for manufacturing the junction-type semiconductor light emitting device 100 according to the preferred embodiment of the present invention will be sequentially described below with reference to FIGS. In the present embodiment, for convenience of explanation, a method of manufacturing the semiconductor light emitting device 100 will be explained as viewed from the cross section taken along line II-II in FIG. 1A, which is a top view of the semiconductor light emitting device 100. FIG. 2 to 6 show the second intermediate electrode 53b among the intermediate electrodes. Since the same concept applies to the first intermediate electrode 53a, redundant description will be omitted in principle for the purpose of simplifying the description. For convenience of explanation, a manufacturing method using an InGaAsP-based material for the semiconductor light emitting layer 35 will be explained as an example. However, the semiconductor light-emitting layer 35 of the present invention is not limited to the InGaAsP-based material. The structure can also be applied to a semiconductor laminate having a known light-emitting layer.

<Method for Manufacturing Semiconductor Light Emitting Device>
A method for manufacturing a semiconductor light emitting device according to the present invention is a semiconductor layer forming a semiconductor laminate 30 including a second conductivity type semiconductor layer 31 , a semiconductor light emitting layer 35 and a first conductivity type semiconductor layer 37 on a growth substrate 10 . a bonding layer forming step of bonding the support substrate 80 and the semiconductor laminate 30 via the bonding layer 50 including the first intermediate electrode 53a and the second intermediate electrode 53b; a step of removing the growth substrate 10, and forming the upper surface electrode 93 including the pad portion 93d and the wiring portion 93a on the main surface of the semiconductor laminate 30 from which the growth substrate 10 has been removed; an upper surface electrode forming step in which regions other than the main surface are partitioned into a plurality of light extraction regions (S ₁ to S ₄ ) by wiring portions 93a; The intermediate electrodes (the first intermediate electrode 53a and the second intermediate electrode 53b) and the upper surface electrode are arranged so as to satisfy the following arrangement conditions (a) to (c) on the plane of vertical projection of the intermediate electrode and the second intermediate electrode). 93 are placed.
(a) The first intermediate electrodes 53a are arranged such that the projections (black circles) of the first intermediate electrodes 53a closest to each other in the division of the light extraction regions (S ₁ to S ₄ ) are equidistantly spaced X apart. be.
(b) The second intermediate electrode 53b is arranged so that the projection of the second intermediate electrode 53b and the wiring portion 93a overlap.
(c) The proximity distance Y1 between the first intermediate electrode 53a closest to the second intermediate electrode 53b among the first intermediate electrodes 53a and the second intermediate electrode _53b is not less than X/2 and less than 3X/2.

In other words, the manufacturing method according to the present invention has a semiconductor layer forming step, a bonding layer forming step, a growth substrate removing step, and a top electrode forming step, which will be described later in detail, and the above arrangement conditions (a) to ( The intermediate electrodes (the first intermediate electrode 53a and the second intermediate electrode 53b) and the upper surface electrode 93 are arranged so as to satisfy c). Moreover, it is preferable that the method for manufacturing the semiconductor light emitting device 100 further includes a surface roughening treatment step, the details of which will be described below, if necessary. Further, the bonding layer forming step preferably includes a contact portion forming step, a dielectric layer forming step, a metal reflective layer forming step, a bonding step, and a support substrate forming step, which will be described in detail below.

In the method for manufacturing the semiconductor light emitting device 100, in addition to the above arrangement conditions (a) to (c), the intermediate electrodes (the first intermediate electrode 53a and the second intermediate electrode 53b) are arranged so as to further satisfy the following arrangement condition (d). ) and a top electrode 93 are preferably disposed.
The arrangement condition (d) is, as described above, the first intermediate electrode 53a arranged such that the respective projections (white circles, black circles) of the first intermediate electrode 53a and the second intermediate electrode 53b are out of the pad portion 93d. and the second intermediate electrode 53b.

In the following manufacturing method, the case where the conductivity type of the first conductivity type semiconductor layer 37 is p-type and the second conductivity type semiconductor layer 31 is n-type will be described as an example.

First, the outline of the method for manufacturing a semiconductor light emitting device according to the present invention will be described with reference to FIGS. 2 to 6. FIG. In the semiconductor layer process, as shown in steps A to C of FIG. A conductive semiconductor layer 31 (hereinafter referred to as an n-type cladding layer 31 for convenience of explanation), a semiconductor light emitting layer 35, and a first conductivity type semiconductor layer 37 as a p-type cladding layer (hereinafter for convenience of explanation, a p-type cladding layer 37 ) are sequentially formed to form a semiconductor laminate 30 . A p-type cap layer 39 may be formed on the p-type clad layer 37 if necessary.

Next, in the bonding layer forming step, as shown in steps D to F of FIG. For example, a contact portion forming step for forming the second contact portion 40b) is performed. At this time, in the step of forming the p-type contact portion (for example, the second contact portion 40b), first, the contact layer 51 made of the III-V group compound semiconductor is formed on the semiconductor laminate 30. As shown in FIG. An ohmic metal portion is formed as a second intermediate electrode 53b (included in the intermediate electrode) on a portion of the contact layer 51, and an exposed region E1 is left on the surface of the contact layer 51. As shown in FIG. Further, as shown in steps D and E of FIG. 3, the contact layer 51 in the exposed region E1 is removed until the surface of the semiconductor laminate 30 is exposed, leaving the second intermediate electrode 53b and the contact layer portion 51a. Along with forming the second contact portion 40b, the exposed surface E2 of the semiconductor stacked body 30 is formed.

In the dielectric layer forming step in the bonding layer forming step, the dielectric layer 55 is formed on at least a portion of the exposed surface E2 of the semiconductor laminate 30 as shown in step F of FIG. Then, in the metal reflective layer forming step in the bonding layer forming step, as shown in step G of FIG. A metal reflective layer 60 is formed. Next, in the supporting substrate forming step in the bonding layer forming step, as shown in step H of FIG. 5, after providing the metal bonding layer 70 on one surface of the supporting substrate 80 Thus, the support substrate 80 is bonded to the metal reflective layer 60 via the metal bonding layer 70 to form the bonding layer 50 . Then, in the substrate removing step, as shown in step I of FIG. 6, the growth substrate 10 is removed.

After that, as shown in step J of FIG. 6, after the top electrode forming step of forming the top electrode 93, a mesa structure is formed along the scheduled cutting line for separating the semiconductor light emitting device 100 into individual pieces. Furthermore, after forming the back surface electrode 91, if necessary, a surface roughening process is performed to protect the electrodes 91 and 93 and form a plurality of irregularities on the light extraction surface. Thus, the semiconductor light emitting device 100 according to the preferred embodiment of the present invention can be manufactured. The formation of the upper surface electrode 93 and the rear surface electrode 91 may be performed after the surface roughening process. Thus, the semiconductor light emitting device 100 according to the preferred embodiment of the present invention can be manufactured. The details of each of the above steps will be sequentially described below.

<Semiconductor layer forming process>
As shown in step A of FIG. 2, in the semiconductor layer forming process, first, a growth substrate 10 is prepared. Since the p-type cladding layer 37 and the n-type cladding layer 31 are formed in this embodiment, it is preferable to use a substrate (InP substrate in the case of InGaAsP system) that can be lattice-matched with each semiconductor layer as the growth substrate 10 . Examples of the InP substrate include generally available n-type InP substrates, high-resistance (also called semi-insulating) InP substrates (for example, Fe-doped, specific resistance of 1×10 ⁶ Ω·cm or more), and p-type InP substrates. Any of the substrates can be used. For convenience of explanation, a preferred embodiment using an n-type InP substrate as the growth substrate 10 will be described below.

Next, as shown in step B of FIG. 2, an etching stop layer 20 of III-V compound semiconductor is formed on the growth substrate 10 . As described above, the etching stop layer 20 of the group III-V compound semiconductor only needs to have etching selectivity with respect to the growth substrate 10, and for an InP substrate, for example, InGaAs can be used as the etching stop layer. Alternatively, InGaAsP can be used as the etching stop layer. The etching stop layer 20 of the III-V compound semiconductor can be used when removing the growth substrate 10 by etching in the substrate removing step. When an n-type InP substrate is used as the growth substrate 10, it is preferable that the etching stop layer 20 of the group III-V compound semiconductor is n-type in combination with the conductivity type of the growth substrate. When InGaAs is used for the etching stop layer 20 of the group III-V compound semiconductor, the In composition ratio in the group III elements is preferably 0.3 to 0.7 in order to lattice match the n-type InP substrate and InGaAs. It is preferable to use InGaAs with an In composition ratio of 0.5 to 0.6, more preferably.

Subsequently, a semiconductor laminate 30 is formed by sequentially forming an n-type clad layer 31, a semiconductor light-emitting layer 35, and a p-type clad layer 37 on the etching stop layer 20 of the III-V compound semiconductor. Since the semiconductor light emitting layer 35 is sandwiched between the n-type clad layer 31 and the p-type clad layer 37, it is preferably a layer made of an InGaAsP-based III-V group compound semiconductor containing at least In and P. The semiconductor laminate 30 can have a double hetero (DH) structure or a multiple quantum well (MQW) structure in which a semiconductor light emitting layer 35 is sandwiched between an n-type clad layer 31 and a p-type clad layer 37 . It is more preferable that the semiconductor light emitting layer 35 has a multi-quantum well structure in order to improve light output by suppressing crystal defects. The multiple quantum well structure can be formed by alternately repeating well layers 35W and barrier layers 35B. The well layer 35W may be made of InGaAsP, and the barrier layer 35B is preferably made of InGaAsP or InP having a bandgap larger than that of the well layer 35W. By providing such a semiconductor laminate 30, the emission wavelength of the semiconductor light emitting device 100 can be set to a desired wavelength in the near-infrared region. For example, by changing the composition of the InGaAsP group III-V compound, the emission peak wavelength can be set to 1000 to 1650 nm. The emission peak wavelength can be adjusted to 1000 to 2200 nm by adjusting the composition difference of the layers and applying strain to the well layer. Further, when the component composition of the well layer 35W is expressed as _{InxwGa1 -xwAsywP1 - yw} , 0.5≤xw≤1 and 0.5≤yw≤1, and 0.5≤yw≤1. It is preferable that 6≦xw≦0.8 and 0.3≦yw≦1.

The total thickness of the semiconductor stack 30 is not limited, but can be, for example, 2 μm to 15 μm. Also, the thickness of the p-type cladding layer 37 is not limited, but can be, for example, 1 μm to 5 μm. Furthermore, the thickness of the semiconductor light-emitting layer 35 is not limited, but can be, for example, 100 nm to 1000 nm. Also, the thickness of the n-type cladding layer 31 is not limited, but can be, for example, 0.8 μm to 10 μm. When the semiconductor light emitting layer 35 has a quantum well structure, the film thickness of the well layer 35W can be set to 3 nm to 15 nm, the film thickness of the barrier layer 35B can be set to 5 nm to 15 nm, and the number of sets of both is 3. ~50.

Also, the semiconductor laminate 30 preferably has a p-type cap layer 39 made of InGaAsP containing at least In and P on the p-type cladding layer 37 . By providing the p-type cap layer 39, lattice mismatch can be alleviated. Although the film thickness of the p-type cap layer 39 is not limited, it can be, for example, 50 to 200 nm. In the following embodiments, for convenience of explanation, the outermost layer of the semiconductor laminate 30 is the p-type cap layer 39 . The surface layer may be the n-type clad layer 31 .

Although not shown, the semiconductor laminate 30 has i-type InP spacer layers between the n-type cladding layer 31 and the semiconductor light-emitting layer 35 and between the semiconductor light-emitting layer 35 and the p-type cladding layer 37, respectively. is also preferred. By providing the i-type InP spacer layer, it is possible to prevent dopant diffusion. Although the film thickness of the i-type InP spacer layer is not limited, it can be, for example, 50 to 400 nm. Further, in the semiconductor laminate 30, between the n-type cladding layer 31 and the etching stop layer 20 of the III-V compound semiconductor, n-type InGaAsP having a composition ratio different from that of the etching stop layer 20 of the III-V compound semiconductor is provided. It may have further layers.

An example in which the central emission wavelength of light emitted from the semiconductor light emitting layer 35 of the semiconductor laminate 30 is set to 1000 to 2200 nm will be described below. A known manufacturing method can be appropriately adopted depending on the emission central wavelength of the semiconductor light emitting layer 35 to be used. Each layer of the semiconductor laminate 30 can be formed by epitaxial growth, for example, a metal organic chemical vapor deposition (MOCVD) method, a molecular beam epitaxy (MBE) method, a sputtering method, or the like. It can be formed by a known thin film growth method. For example, trimethylindium (TMIn) as an In source, trimethylgallium (TMGa) as a Ga source, arsine (AsH ₃ ) as an As source, and phosphine (PH ₃ ) as a P source are used in a predetermined mixing ratio. By vapor-phase growth using a carrier gas, an InGaAsP layer can be formed with a desired thickness depending on the growth time. Other epitaxially grown InGaAsP layers, such as the etching stop layer 20 of the III-V compound semiconductor, can be formed by the same method. If the layers are to be doped p-type or n-type, additional dopant source gases may be used as desired. Further, each layer constituting the semiconductor laminate can be appropriately doped with the above-described n-type dopant or p-type dopant (Zn, C, etc.).

<Joining layer forming step>
The bonding layer forming step includes a contact portion forming step, a dielectric layer forming step, a metal reflective layer forming step, a bonding step, and a support substrate forming step. Each step included in the bonding layer forming step will be described below with reference to FIGS. 2 to 4. FIG.

<<Contact part forming process>>
In the contact part forming process, as shown in step C of FIG. A p-type contact layer 51 can be formed on the p-type cap layer 39 . The p-type contact layer 51 is a layer in contact with the intermediate electrode (the first intermediate electrode 53a and the second intermediate electrode 53b) and in contact with the intermediate electrode interposed between the intermediate electrode and the semiconductor laminate 30, Any composition may be used as long as the contact resistance with the intermediate electrode is smaller than that of the semiconductor laminate 30. For example, a p-type InGaAs layer can be used. Although the film thickness of the contact layer portion 51a is not limited, it can be, for example, 50 nm to 200 nm.

Next, as shown in step D of FIG. 3, a second intermediate electrode 53b is formed on a portion of the contact layer 51 and an exposed region E1 is left on the surface of the contact layer 51. Next, as shown in FIG. The second intermediate electrode 53b eventually becomes an intermediate electrode, and the intermediate electrodes including the second intermediate electrode 53b and the first intermediate electrode (not shown) meet the above arrangement conditions (a) to (c), preferably They are formed in an island-like pattern according to the arrangement conditions (a) to (d). When a p-type InGaAs layer is used as the p-type contact layer 51, for example, Au, AuZn, AuBe, AuTi, etc. can be used as the second intermediate electrode 53b, and it is also preferable to use a laminated structure of these. For example, Au/AuZn/Au can be the intermediate electrodes (first intermediate electrode and second intermediate electrode, respectively). The film thickness (or total film thickness) of the intermediate electrodes (each of the first intermediate electrode and the second intermediate electrode) is not limited, but can be, for example, 300 nm to 1300 nm, more preferably 350 nm to 800 nm.

Here, for example, a resist pattern is formed on the surface of the contact layer 51 so as to comply with the arrangement conditions (a) to (c), preferably the arrangement conditions (a) to (d), and the second intermediate electrode 53b is formed. is vapor-deposited, and the resist pattern is lifted off to form an exposed region E1 on the surface of the contact layer 51 . Alternatively, a predetermined metal layer may be formed on the entire surface of the contact layer 51, a mask may be formed on the metal layer, and etching may be performed to form the second intermediate electrode 53b. In either case, as shown in step D of FIG. That is, an exposed region E1 can be formed.

Further, in the contact portion forming step, the contact layer 51 in the exposed region E1 is removed until the surface of the semiconductor laminate 30 is exposed, thereby forming the second contact portion 40b including the second intermediate electrode 53b and the contact layer portion 51a. At the same time, an exposed surface E2 of the semiconductor laminate 30 is formed (Step E in FIG. 3). That is, the contact layer 51 other than the previously formed second intermediate electrode 53b is etched until the surface of the p-type cap layer 39, which is the outermost layer of the semiconductor laminate 30, is exposed to form a contact layer portion 51a. For example, a resist mask may be formed on the second intermediate electrode 53b and its vicinity (approximately 2 to 5 μm), and the exposed region E1 of the contact layer 51 may be wet-etched with a tartaric acid-hydrogen peroxide system or the like. In addition, wet etching can also be performed using an inorganic acid-hydrogen peroxide-based or an organic acid-hydrogen peroxide-based etchant. Further, when forming the exposed region E1, if a mask is formed on the predetermined metal layer and the second intermediate electrode 53b is formed by etching, the etching may be performed continuously.

The second contact portion 40b in step E of FIG. 3 is composed of a second intermediate electrode (ohmic electrode portion) 53b and a contact layer portion 51a. Therefore, the second intermediate electrode 53b in the second contact portion 40b in step E of FIG. 3 corresponds to the second intermediate electrode 53b in FIG. 1B. Further, as described above, FIGS. 2 to 6 showing each step of the method for manufacturing the semiconductor light emitting device 100 are viewed from the cross section taken along line II-II in FIG. 1A, which is a top view of the semiconductor light emitting device 100 according to the present invention. 1 is a diagram showing each step of the method for manufacturing the semiconductor light emitting device 100 of FIG. Therefore, when explaining the method of manufacturing the semiconductor light emitting device 100 using a cross-sectional view corresponding to the cross section taken along the line II of FIG. 1A, the second intermediate electrode 53b shown in FIG. A first intermediate electrode 53a is formed in the same manner as above, and instead of the second contact portion 40b in FIGS. 3-6, the first contact portion 40a shown in FIG. 1B is formed in the same manner as above. can be understood as

The thickness of the contact portion 40 corresponds to the total thickness of the contact layer portion 51a and the intermediate electrode, and can be 350 nm to 1500 nm, more preferably 400 to 1000 nm.

<<Dielectric Layer Forming Process>>
In the dielectric layer forming step, the dielectric layer 55 is formed on at least a portion of the exposed surface E2 of the semiconductor laminate 30 (Step F in FIG. 3). Such a dielectric layer 55 can be formed, for example, as follows.

First, the dielectric layer 55 is formed on the entire surface of the semiconductor laminate 30 so as to cover the semiconductor laminate 30 and the second contact portion 40b. As a film forming method, known techniques such as plasma CVD and sputtering can be applied. Then, on the surface of the deposited dielectric layer 55 above the second contact portion 40b, when the dielectric on the second contact portion 40b is formed on the dielectric layer 55, a mask is formed as desired. Then, the dielectric on the contact portion may be removed by etching or the like. For example, buffered hydrofluoric acid (BHF) or the like can be used to wet etch the dielectric over the contacts.

Incidentally, referring to step F in FIG. 3, as shown in FIG. 4, the dielectric layer 55 is formed on a portion of the exposed surface E2 of the semiconductor laminate 30, and the periphery of the second contact portion 40b is exposed. It is also preferable to provide a gap between the dielectric layer 55 and the second contact portion 40b as the portion E3. Such dielectric layer 55 and exposed portion E3 can be formed, for example, as follows. First, a dielectric layer 55 is formed on the entire surface of the semiconductor laminate 30, and a window pattern is formed on the surface of the formed dielectric layer 55 above the second contact portion 40b so as to completely surround the second contact portion 40b. is formed with a resist. In this case, it is preferable that the window pattern has a width of about 1 to 5 μm with respect to the length of the second contact portion 40b in the width direction and the lengthwise direction. Using the resist pattern thus formed, the dielectric around the second contact portion 40b is removed by etching, thereby forming the dielectric layer 55 and forming the exposed portion E3 around the second contact portion 40b.

In order to reliably obtain this shape, the width V ₁ of the exposed portion E3 is preferably 0.5 μm or more and 5 μm or less, more preferably 1 μm or more and 3.5 μm or less (see FIG. 4). The relationship between the film thickness H1 of the dielectric layer ₅₅ formed by the dielectric layer forming process and the film thickness _H2 of the contact portion 40 is not particularly limited, but as shown in _FIG . H ₂ is preferred. By doing so, the bonding between the metal reflective layer 60 and the metal bonding layer 70 can be performed more reliably. In particular, when the exposed portion E3 is provided and H ₁ >H ₂ , if the metal reflective layer 60 is formed so as to fill the gap, Voids can occur.

Here, it is also preferable that the contact area ratio of the dielectric layer 55 contacting the semiconductor laminate 30 is 80% or more and 97% or less. This is because light absorption by the contact portion can be suppressed by reducing the area of the contact portion 40 and increasing the area of the dielectric layer 55 . The contact area ratio can be measured in the state of the wafer, and when the contact area ratio is back calculated from the state of the semiconductor light emitting device after singulation, the semiconductor layer ( It may be calculated by assuming that the width of the region where the dielectric layer was present is 20 to 30 μm on one side (40 to 60 μm on both sides).

SiO ₂ , SiN, ITO, AlN, or the like can be used as the dielectric layer 55, and it is particularly preferable that the dielectric layer 55 is made of SiO ₂ . This is because SiO ₂ is easily etched with BHF or the like.

<<Metal reflective layer forming process>>
In the metal reflective layer forming step, the metal reflective layer 60 that reflects the light emitted from the semiconductor light emitting layer 35 is formed on the dielectric layer 55 and the second contact portion 40b (Step G in FIG. 5). When the exposed portion E3 is formed in the dielectric layer forming step, the metal reflective layer 60 is also formed on the exposed portion E3. For the metal reflective layer 60, a DBR, a metal reflective layer, a photonic crystal, a refractive index difference due to partial voids, etc., can all be used. Therefore, it is preferable to use the metal reflective layer 60 . Although Au, Al, Pt, Ti, Ag, etc. can be used for the metal reflective layer 60, it is particularly preferable to use Au as the main component. In this case, in the composition of the metal reflective layer 60, Au preferably accounts for more than 50% by mass, more preferably 80% by mass or more. The metal reflective layer 60 can include a plurality of metal layers, but when it includes a metal layer made of Au (hereinafter referred to as “Au metal layer”), the total thickness of the metal reflective layer 60 includes the Au metal layer. A layer thickness greater than 50% is preferred. For example, the metal reflective layer 60 may be a single layer made of only Au, or the metal reflective layer 60 may include two or more Au metal layers. In order to reliably perform bonding in the subsequent bonding step, it is preferable that the outermost layer of the metal reflective layer 60 (the surface opposite to the semiconductor laminate 30) be an Au metal layer. For example, metal layers of Al, Au, Pt, and Au can be formed in this order on the dielectric layer 55, the exposed portion E3, and the contact portion 40 to form the metal reflective layer 60. FIG. The thickness of one Au metal layer in the metal reflective layer 60 can be, for example, 400 nm to 2000 nm, and the thickness of the metal layer made of a metal other than Au can be, for example, 5 nm to 200 nm. The metal reflective layer 60 can be formed by depositing a film on the dielectric layer 55, the exposed portion E3 and the contact portion 40 by a general technique such as vapor deposition.

<Joining process>>
In the bonding step, the support substrate 80 provided with the metal bonding layer 70 on the surface thereof is bonded to the metal reflective layer 60 via the metal bonding layer 70 (step H in FIG. 5). The metal bonding layer 70 may be formed in advance on the surface of the support substrate 80 by sputtering, vapor deposition, or the like. The metal bonding layer 70 and the metal reflective layer 60 are placed opposite to each other and bonded together, and then heated and compressed at a temperature of about 250.degree. C. to 500.degree.

Metals such as Ti, Pt, and Au, or metals that form a eutectic alloy with gold (Sn, etc.) can be used for the metal bonding layer 70 that bonds to the metal reflective layer 60, and these are laminated. is preferred. For example, the metal bonding layer 70 can be formed by laminating Ti with a thickness of 400 nm to 800 nm, Pt with a thickness of 5 nm to 20 nm, and Au with a thickness of 700 to 1200 nm in this order from the surface of the support substrate 80 . In order to facilitate bonding between the metal reflective layer 60 and the metal bonding layer 70, the outermost layer on the metal bonding layer 70 side is an Au metal layer, and the metal layer on the metal bonding layer 70 side of the metal reflective layer 60 is also Au. As such, it is preferable to perform Au-to-Au bonding by Au—Au diffusion.

A conductive Si substrate, for example, can be used as the support substrate 80, and a conductive GaAs substrate or a Ge substrate may also be used. In addition to the semiconductor substrate described above, a metal substrate may be used, and a submount substrate using a heat-dissipating insulating substrate such as sintered AlN may also be used. Although the thickness of the support substrate 80 varies depending on the material used, it can be 100 μm or more and 500 μm or less, and if it is a Si substrate or a GaAs substrate, it can be handled with a thickness of less than 180 μm. A Si substrate is particularly preferable in consideration of heat dissipation, brittleness, and cost.

<Substrate removal process>>
In the substrate removing step, the growth substrate 10 is removed as shown in step I of FIG. The growth substrate 10 can be removed by wet etching using, for example, diluted hydrochloric acid, and the etching stop layer 20 of the group III-V compound semiconductor can be used as the end point of the wet etching. When removing the etching stop layer 20 of the group III-V compound semiconductor, wet etching may be performed with, for example, a sulfuric acid-hydrogen peroxide-based etchant.

<Upper surface electrode forming process>
In the step of forming the upper surface electrode in the present invention, as in step J in FIG. A pad electrode layer 93c is formed thereon. The main surface of the second conductivity type semiconductor layer 31 is partitioned into a plurality of light extraction regions by the wiring portion 93a that is part of the ohmic metal layer 93e.

Further, the intermediate electrodes (the first intermediate electrode 53a and the second intermediate electrode 53b) are vertically projected onto the main surface of the second conductivity type semiconductor layer (for example, n-type semiconductor layer) 31 partitioned in the light extraction region. Assuming a projection plane, the upper surface electrode 93 and the intermediate electrodes (the first intermediate electrode 53a and the second The intermediate electrode 53b) and the upper electrode 93 are arranged respectively.

Upper surface electrode 93 includes wiring portion 93a and pad portion 93d. The wiring portion 93a is formed for the purpose of spreading the current supplied from the pad portion 93d to the light emitting region of the semiconductor light emitting element as much as possible, and is an ohmic contact between the second conductivity type semiconductor layer 31 with which the upper surface electrode 93 is in contact. formed by an ohmic metal layer that forms a

In the top electrode forming step, the semiconductor etching stop layer 20 exposed by removing the growth substrate 10 is used as a contact layer to form the top electrode thereon, and the semiconductor etching stop layer 20 is completely removed. There is also a method of forming an upper surface electrode directly on the second conductivity type semiconductor layer 31 . For example, if InGaAs is used as the etching stop layer 20, InGaAs is preferably used as the n-type contact layer. When InGaAs is used as the etching stop layer 20, it is preferable to employ the latter method and remove the InGaAs of the etching stop layer 20 other than the region where the upper electrode is to be formed. When an n-type InGaAs layer is used as the n-type contact layer, metals such as Ti, Pt, Au, and Ge or alloys containing these metals (AuGe system, TiPtAu system) can be used as the ohmic metal layer. . Furthermore, other than the above metals, metals (such as Sn) that form a eutectic alloy with Au can be used, and it is also preferable to use a laminated structure of these. As the pad metal layer, for example, metals such as Ti, Pt, Ag, and Au, or general metals such as metals (such as Sn) that form a eutectic alloy with gold can be used. It is also preferred to use structures.

Moreover, when the support substrate 80 is conductive, a step of forming a back surface electrode 91 on the back surface of the support substrate 80 may be further included. The formation of the back surface electrode 91 and the upper surface electrode 93 can be performed using a known technique such as sputtering, electron beam evaporation, or resistance heating.

Prior to surface roughening in a post-process that is performed as necessary, the epitaxially formed semiconductor laminate 30 may be mesa-etched along the dividing lines for singulation. As described above, FIGS. 2 to 6 show the method for manufacturing the semiconductor light emitting device 100 when viewed from the cross section along line II-II in FIG. 1A. , and the semiconductor light emitting device 100 shown in FIG. 1C are the same.

<Roughening treatment step>
In the manufacturing method according to the present invention, the surface roughening treatment step is a step that is performed as necessary, and surface roughening by machining, wet etching, and dry etching can be performed singly or in combination. It is preferable that the uneven pattern of the n-type cladding layer 31 has a surface roughness Ra of 0.03 μm or more and is roughened randomly.

<Protective film forming process>
In the manufacturing method according to the present invention, the step of forming a protective film is a step that is performed as necessary. form a film. After that, the resist is lifted off to expose the upper electrode.

As a method for forming the protective film, known methods such as plasma CVD method and sputtering method can be applied. When the resist is not formed on the upper electrode in advance, a mask is formed after forming the protective film, and the protective film on the upper electrode is removed by etching using buffered hydrofluoric acid (BHF) or the like. .

Although not shown, the manufacturing method according to the present embodiment preferably further includes a grinding step of grinding the thickness of the support substrate 80 to within the range of 80 μm or more and less than 200 μm. In this embodiment, a Si substrate can be used as the support substrate 80. In this case, even if the support substrate 80 is ground to a thickness of less than 200 μm, no breakage occurs. Furthermore, the thickness of the support substrate 80 can be ground to 150 μm or less, or can be ground to 100 μm or less. However, if the support substrate 80 is ground to a thickness of less than 80 μm, even a Si substrate may be damaged, so the lower limit of the thickness is preferably set to 80 μm. Moreover, if the thickness of the support substrate 80 is 80 μm or more, the semiconductor light emitting device 100 can be sufficiently handled.

After the above steps, the semiconductor light emitting device 100 is obtained through a step of device separation by a dicing method or a scribing method along the mesa-etched dividing lines for separation into individual pieces. The dividing line may be square, parallelogram, or rectangular, and the chip size may be small (200 to 400 μm on one side), medium (400 to 800 μm on one side), or large (800 to 2000 μm on one side). .

In this embodiment, the conductivity type of the first conductivity type semiconductor layer 37 is p-type, and the second conductivity type semiconductor layer 31 is n-type. is reversible.

Further, if the intermediate electrode and the top electrode have the above-described configuration, the III-V group compound semiconductor layer may be changed from InGaAsP to, for example, AlGaAs, AlInGaP, or InGaAsSb.

Further, by using a part of the p-type cap layer 39 as the contact layer portion 51a, the contact portions 40a and 40b composed of the intermediate electrodes (ohmic electrode portions) 53a and 53b and the contact layer portion 51a can be The form of the contact portions 40a and 40b may be changed to include only the intermediate electrodes (ohmic electrode portions) 53a and 53b.

(Example 1)
EXAMPLES The present invention will be described in more detail below using examples, but the present invention is not limited to the following examples.

<Semiconductor layer forming process>
First, an n-type In _0.57 Ga _0.43 As etching stop layer (thickness: 20 nm) and an n-type InP cladding layer (thickness: : 2000 nm), an i-type InP spacer layer (thickness: 100 nm), a semiconductor light-emitting layer having a quantum well structure with an emission wavelength of 1300 nm (total thickness: 138 nm), and an i-type InP spacer layer (thickness: 138 nm). : 320 nm), a p-type InP cladding layer (thickness: 4.8 μm) and a p-type In _0.8 Ga _0.20 As _0.5 P _0.5 cap layer (thickness: 50 nm) as a first conductivity type semiconductor layer, and one of the junction layers. As a part, a p-type In _0.57 Ga _0.43 As contact layer (thickness: 101 nm) was sequentially formed by MOCVD. In forming the semiconductor light-emitting layer having the quantum well structure, an InP barrier layer having a thickness of 8 nm is first formed, and then an In _0.74 Ga _0.26 As _0.5 P _0.5 well layer (thickness: 5 nm) and an InP barrier layer (thickness: 5 nm) are formed. Thickness: 8 nm) were alternately laminated to make a total of 10.5 sets. Note that "10.5 sets" means that lamination is started from the InP barrier layer and finally the InP barrier layer is provided, and the layer adjacent to the i-type InP spacer layer is the InP barrier layer.

<Joining layer forming step>
On the p-type In _0.57 Ga _0.43 As contact layer in the semiconductor laminate produced above, p A type ohmic electrode portion (Au/AuZn/Au, total film thickness: 530 nm, intermediate electrode) was formed. In forming this pattern, a resist pattern was formed, then a p-type ohmic electrode was vapor-deposited, and the resist pattern was lifted off. In addition, the external size of FIG. 7A was 380 μm square. In FIG. 7A, the pad portion 93d of the upper electrode, the wiring portion 93a, and the light extraction regions S ₁ to S ₄ partitioned by the wiring portion 93a, which are formed in a post-process, are indicated by two-dot chain lines at locations to be formed. ing. Furthermore, in FIG. 7A, the first intermediate electrode 53a is indicated by a white circle, and the second intermediate electrode 53b is indicated by a black circle.

With respect to the state in which the intermediate electrode was formed on the laminate, the semiconductor laminate layer was observed from above using an optical microscope. As a result, each of the p-type ohmic electrode portions formed in this example had a circular shape with a diameter of 5 μm. The interval X was 35 μm, and the center-to-center distance between the closest first intermediate electrodes was 40 μm. The diameter of the intermediate electrode (p-type ohmic electrode portion) refers to the maximum length of the maximum cross section in the planar direction of the semiconductor laminate layer.

The inter-electrode distance (Y ₁ ) between the first intermediate electrode and the second intermediate electrode closest to the first intermediate electrode was 28 μm. Furthermore, the distance (Z) between the closest second intermediate electrodes arranged below the wiring portion is 35 μm, and the center-to-center distance between the closest second intermediate electrodes is 40 μm, which is 380 μm square. The area ratio of the intermediate electrode (p-type ohmic electrode portion) was 0.87%. The distance between the first intermediate electrode and the outer periphery of the chip was 49 μm.

The dimensions of the semiconductor laminate in which the intermediate electrodes are laminated in Example 1 are L ₁ =L ₂ =380 μm, X=35 μm, Y ₁ =28 μm, Y ₂ =28 μm, referring to the dimension symbols shown in FIG. 7A. , Z = 35 µm, the diameter of the first intermediate electrode d ₁ = 5 µm, the diameter of the second intermediate electrode d ₂ = 5 µm, d ₃ = 13.5 µm, and the distance d _ee = 49 µm between the outer circumference of the chip and the first intermediate electrode. rice field. Therefore, as shown in FIG. 7A, there are seven intermediate electrodes with a diameter of 5 μm, six intermediate electrodes with a 35 μm interval X, two corner lengths (d ₃ ) of 13.5 μm, and the first intermediate electrode. 49 μm separation distance (d _ee ) between and the chip outer periphery and two electrode widths of 5 μm add up to an external size of 380 μm (L ₁ =L ₂ ).

Next, using the intermediate electrode (p-type ohmic electrode portion) as a mask, the p-type In _0.57 Ga _0.43 As contact layer other than the portion where the ohmic electrode portion is formed is removed by tartaric acid-hydrogen peroxide wet etching. bottom. Thereafter, a dielectric layer (thickness: 700 nm) made of SiO ₂ was formed on the entire surface of the p-type In _0.80 Ga _0.20 As _0.50 P _0.50 cap layer by plasma CVD. Then, a window pattern with a width of 3 μm was formed in the upper region of the intermediate electrode (p-type ohmic electrode portion) with a resist, and the intermediate electrode (p-type ohmic electrode portion) and its periphery were formed. The dielectric layer was removed by wet etching with BHF to expose the p-type In _0.80 Ga _0.20 As _0.50 P _0.50 cap layer. At this time, the thickness H ₁ (700 nm) of the dielectric layer on the p-type In _0.80 Ga _0.20 As _0.50 P _0.50 cap layer is equal to that of the p-type contact layer (thickness: 100 nm) and the intermediate electrode (p-type ohmic electrode portion). (Thickness: 530 nm), the height H ₂ (630 nm) of the contact portion was 70 nm higher. In this state, when the semiconductor layer of the wafer was observed from above using an optical microscope, the contact area ratio of the dielectric layer (SiO ₂ ) was 95.8%.

Next, a metal reflective layer (Al/Au/Pt/Au) was formed by vapor deposition on the entire surface of the p-type In _0.80 Ga _0.20 As _0.50 P _0.50 cap layer. Thus, a bonding layer having an intermediate electrode was formed on the semiconductor laminate. The film thickness of each metal layer of the metal reflective layer was 10 nm, 650 nm, 100 nm and 900 nm in order. On the other hand, a metal bonding layer (Ti/Pt/Au) was formed on a conductive Si substrate (thickness: 300 μm) serving as a support substrate. The film thickness of each metal layer of the metal bonding layer was 650 nm, 10 nm, and 900 nm in order.

The metal reflective layer and the metal bonding layer were arranged opposite to each other, and heat compression bonding was performed at 300° C. to bond the support substrate having the metal reflective layer and the metal bonding layer to form the bonding layer.

<Growth substrate removal step>
Then, the InP substrate, which is the growth substrate, was removed by wet etching with diluted hydrochloric acid.

<Upper surface electrode forming process>
Au (thickness: 10 nm)/Ge (thickness: 33 nm)/Au (thickness: 57 nm)/Ni (thickness: 34 nm)/Au ( Film thickness: 800 nm)/Ti (film thickness: 100 nm)/Au (film thickness: 1000 nm) were formed by forming a resist pattern, vapor-depositing an n-type electrode, and lifting off the resist pattern. Further, a pad electrode layer (Ti (thickness: 150 nm)/Pt (thickness: 100 nm)/Au (thickness: 2500 nm)) is formed as a pad electrode layer on the ohmic metal layer pad portion, and the top electrode pattern is shown in FIG. 7B. as shown in At this time, the diameter of the pad electrode layer was 105 μm. The formed intermediate electrodes are as shown in FIG. 7B (plan view) and FIG. 7C (projection plane). At this time, the ohmic metal layer, which is a part of the upper electrode, includes an ohmic metal layer pad portion and a length extending outwardly from the ohmic metal layer pad portion and electrically connected to the ohmic metal layer pad portion. It is composed of a length-shaped wiring portion. The diameter _dp of the ohmic metal layer pad portion was 115 μm, and the minor axis length W of the wiring portion was 8 μm. The minor axis length W of the wiring portion and the diameter _dp of the main body portion in the examples were measured using a digital microscope (VHX-2000, manufactured by Keyence Corporation).

Note that in FIG. 7B, the already formed intermediate electrodes (the first intermediate electrode and the second intermediate electrode) are indicated by hidden lines (dotted lines). As in FIG. 7A, the external size of FIG. 7B is 380 μm square. FIG. 7C is a diagram in which the plan view of the intermediate electrode (p-type ohmic electrode portion) shown in FIG. 7A and the plan view of the upper surface electrode shown in FIG. 7B are superimposed. That is, FIG. 7C is a diagram showing a state of the semiconductor light emitting device observed on the same plane viewed from the stacking direction (that is, a state in which the intermediate electrode is projected onto the main surface of the n-type InP clad layer). For convenience of explanation, in FIG. 7C, the projection of the first intermediate electrode 53a is indicated by a white circle, and the projection of the second intermediate electrode 53b is indicated by a black circle.

In this example, the intermediate electrode and the upper electrode were arranged so as to satisfy the following arrangement conditions (a) to (d).
(a) The first intermediate electrodes are arranged such that the projections of the first intermediate electrodes closest to each other in the division of the light extraction region are equidistantly spaced X apart.
(b) The second intermediate electrode was arranged so that the projection of the second intermediate electrode and the wiring portion overlapped.
(c) The proximity distance Y1 between the first intermediate electrode closest to the second intermediate electrode among the first intermediate electrodes and the second intermediate electrode was X/ ₂ or more and less than 3X/2.
(d) The first intermediate electrode and the second intermediate electrode were arranged such that the respective projections of the first intermediate electrode and the second intermediate electrode were separated from the pad portion.

As shown in FIG. 7D, the dimensions of the semiconductor light emitting device manufactured in Example 1 are: external size (L ₁ =L ₂ )=380 μm, X=35 μm, Y ₁ =28 μm, Y ₂ =28 μm, Z= 35 μm, the diameter of the first intermediate electrode d ₁ =5 μm, the diameter of the second intermediate electrode d ₂ =5 μm, d ₃ =13.5 μm, and the distance d _ee =49 μm between the outer periphery of the chip and the first intermediate electrode. Table 1 shows a list of X, Y ₁ , Y ₂ , and W, which are the dimensions of the semiconductor light emitting devices fabricated in Examples 1 to 6.

<Dicing process>
Next, a dicing line was formed by removing the semiconductor layer between each element (width: 60 μm) by mesa etching. After that, a back electrode (Ti (thickness: 10 nm)/Pt (thickness: 50 nm)/Au (thickness: 200 nm)) was formed on the back side of the Si substrate. After that, a protective film is formed on the upper surface electrode, and the surface of the light extraction surface of the n-type InP clad layer corresponding to the upper surface of the second conductivity type semiconductor layer is roughened (1300 nm fine pattern roughening). gone. Finally, individual chips were separated by dicing, and the semiconductor light emitting device according to Example 1 was manufactured. FIG. 8 shows a metallurgical microscope photograph of the semiconductor light-emitting device produced in Example 1 during light emission. The chip size after dicing was 350 μm×350 μm.

(Example 2)
In Example 1, while maintaining the distance X between the first intermediate electrodes, the first intermediate electrodes in the light extraction region are moved in parallel to change the distance d _ee between the outer periphery of the chip and the first intermediate electrodes from 49 μm to 40 μm. A semiconductor light-emitting device according to Example 2 was fabricated in the same manner as in Example 1, except that Y ₁ and Y ₂ were changed to the values shown in Table 2.

In the semiconductor light emitting device fabricated in Example 2, the proximity distance (Y ₁ ) between the first intermediate electrode and the second intermediate electrode is 33 μm, and the first intermediate electrode second closest to the second intermediate electrode and the second intermediate electrode are adjacent to each other. The proximity distance (Y ₂ ) between the two intermediate electrodes was 34 μm, and the distance (Z) between the second intermediate electrodes was 35 μm.

(Comparative example 1)
Except for the fact that the intermediate electrodes were arranged at the positions of the vertices of equilateral triangles with an interval X on one side over the entire surface excluding the pad portions regardless of overlapping with the wiring portions, and the pattern was not symmetrical about the pad portions. A semiconductor light-emitting device according to Comparative Example 1 was manufactured in the same manner as in Example 1, with the first intermediate electrode, the wiring portion and the pad portion arranged as shown in FIG. In FIG. 9, a third intermediate electrode is formed that partially overlaps with the wiring portion but does not satisfy the above-mentioned "the projection of the intermediate electrode overlaps with the wiring portion". there is The semiconductor light emitting device of Comparative Example 1 does not have a second intermediate electrode that satisfies the arrangement conditions (b) and (c).

(Comparative example 2)
In order to prevent the projection of the wiring portion and the intermediate electrode from overlapping each other, the third intermediate electrodes in FIG. A semiconductor light-emitting device according to Comparative Example 2 was produced in the same manner as in Comparative Example 1. The semiconductor light emitting device of Comparative Example 2 also does not satisfy the arrangement conditions (b) and (c).

<Evaluation of output and Vf>
Each of the semiconductor light emitting devices produced in Examples 1 and 2 and Comparative Examples 1 and 2 was mounted on a transistor outline header (TO-18) using silver paste, and the top electrode was bonded using gold wire. Then, the light emission output (Po) and forward voltage (Vf) of Examples 1 and 2 and Comparative Examples 1 and 2 were measured by applying currents of 20 mA and 100 mA, respectively. An integrating sphere was used to measure the luminescence output (Po). Further, the forward voltage (Vf) was the voltage value of a constant current voltage device (manufactured by ADC Corporation: model number 6243) when 20 mA was applied. Each of the above measurements was performed on 10 samples, and the average values are shown in Table 2.

The "Po maintenance rate" in Tables 2 to 4 indicates the linearity of the optical output, and when the output from 0 mA to 20 mA is proportional to the current, the output from 20 mA to 100 mA and the current is the ratio of the actual output at 100 mA to the output at 100 mA assuming the relationship maintains a proportional relationship up to 20 mA, given by dividing the output value at 100 mA by five times the output value at 20 mA. shown. Specifically, it is as shown in the following formula.
(Po maintenance rate) = (Po [luminescence output at 100 mA energization]) / (Po [luminescence output at 20 mA energization]) × 5

Table 1 below shows a list of X, Y ₁ , Y ₂ , and W, which are the dimensions of the semiconductor light emitting devices fabricated in Examples 1 to 6, including Examples 3 to 6, which will be described later.

上記実験結果から、実施例１および２の半導体発光素子は、比較例と比べて発光出力の直線性が維持される傾向（Ｐｏ維持率の増加）が確認された。

From the above experimental results, it was confirmed that the semiconductor light emitting devices of Examples 1 and 2 tended to maintain the linearity of light emission output (increase in Po retention rate) compared to the comparative example.

Next, a study was conducted to confirm the influence of the minor axis length (line width) of the wiring portion. Examples 3 to 5 and Comparative Example 3 are described below.
(Examples 3-5)
In Examples 3 to 5, the first intermediate electrode and the second intermediate electrode as shown in FIG. Semiconductor light-emitting devices according to Examples 3 to 5 were produced by arranging the wiring portion and the pad portion. After that, the same evaluation as in Example 1 was performed to confirm the influence of the minor axis length W of the wiring portion. The results are shown in Table 3 below. Also, the dimensions of the semiconductor light emitting devices of _Examples 3 to ₅ are _, as _shown in FIG. , the diameter of the first intermediate electrode d ₁ =5 μm, the diameter of the second intermediate electrode d ₂ =5 μm, d ₃ =13.5 μm, and the distance d _ee =49 μm between the chip periphery and the first intermediate electrode. (See FIG. 7D).

(Comparative Example 3)
In Comparative Example 3, the same procedure as in Example 1 was performed except that the minor axis length W of the wiring portion was changed to the value shown in Table 3. In addition, a semiconductor light emitting device according to Comparative Example 3 was manufactured by arranging the pad portions. Therefore, the semiconductor light emitting device of Comparative Example 3 did not satisfy the condition that the minor axis length W was 5 to 12 μm. After that, the same evaluation as in Example 1 was performed to confirm the influence of the minor axis length W of the wiring portion. The results are shown in Table 3 below. Since Comparative Example 3 did not satisfy the short axis length condition, it was confirmed that the Po retention rate was not sufficient.

(Example 6)
By changing the interval (inter-electrode distance) X between the first intermediate electrodes from 35 _μm to 25 μm, the number of the first intermediate electrodes in each light extraction region is changed _. A semiconductor light emitting device according to Example 6 was fabricated in the same manner as in Example 2, except that the dimensions shown in . After that, the same evaluation as in Example 2 was performed to confirm the effect of the interval (inter-electrode distance) X. The results are shown in Table 4 below.

As shown in FIG. 11, the dimensions of the semiconductor light emitting device of this example are L ₁ =L ₂ =380 μm, X=25 μm, Y ₁ =20 μm, Y ₂ =23 μm, Y ₃ =23 μm, Y ₄ = 31 μm, Z=32 μm, d _x =22.5 μm, d _s =18 μm, W=8 μm, the diameter of the first intermediate electrode d ₁ =5 μm, and the distance d _ee =40 μm between the chip circumference and the first intermediate electrode. .

In the semiconductor light emitting device of Example 6, the proximity distance Y ₁ between the first intermediate electrode and the second intermediate electrode is 20 μm, and the first intermediate electrode and the second intermediate electrode that are second closest to the second intermediate electrode The proximity distance (Y ₂ ) between the intermediate electrodes was 23 μm, and the distance between the second intermediate electrodes was 32 μm. As compared with Example 2, the number of intermediate electrodes was increased, and the ratio of the reflective surface was decreased. Therefore, although the light emission output decreased, it was confirmed that the linearity of the light emission output was maintained remarkably.

According to the present invention, by appropriately arranging the intermediate electrodes and the positional relationship between the upper electrode and the intermediate electrode, it is possible to achieve excellent light output with a high light output maintenance rate (linearity of current-light output characteristics). It is possible to provide the semiconductor light emitting device shown in FIG. According to the method for manufacturing a semiconductor light-emitting device of the present invention, a semiconductor light-emitting device having a high emission output maintenance rate can be manufactured by appropriately arranging the positional relationship between the upper surface electrode and the intermediate electrode and by arranging the intermediate electrodes. .

REFERENCE SIGNS LIST 100 semiconductor light emitting device 10 growth substrate 20 etching stop layer 30 semiconductor laminate 31 first conductivity type semiconductor layer 35 semiconductor light emitting layer 35W well layer 35B barrier layer 37 second conductivity type semiconductor layer 39 cap layer 40a first contact portion 40b second 2 contact portion 53a first intermediate electrode 53b second intermediate electrode 50 junction layer 51 contact layer 51a contact layer portion 55 dielectric layer 60 metal reflection layer 70 metal junction layer 80 support substrate 91 rear surface electrode 93 upper surface electrode 93a wiring portion 93d pad portion E1 exposed area E2 exposed surface E3 exposed part

Claims (10)

A semiconductor light emitting device having a support substrate, a junction layer including an intermediate electrode, and a first conductivity type semiconductor layer, a semiconductor light emitting layer and a second conductivity type semiconductor layer made of a III-V group compound semiconductor in this order,
having an upper surface electrode comprising a pad portion and a wiring portion on the main surface of the second conductivity type semiconductor layer;
The wiring part has a long body with a short axis length of 5 to 12 μm,
a region on the main surface other than the top electrode forming region in which the top electrode is formed is partitioned into a plurality of light extraction regions by the wiring portion;
The intermediate electrodes each have a plurality of island-shaped first intermediate electrodes and second intermediate electrodes, and on a projection plane obtained by vertically projecting the intermediate electrodes onto the main surface,
(a) the intermediate electrode includes the first intermediate electrode arranged such that the projections of the first intermediate electrode closest to each other in the division of the light extraction region are equidistantly spaced apart X;
(b) the intermediate electrode includes the second intermediate electrode arranged so that the projection of the second intermediate electrode and the wiring portion overlap;
(c) the proximity distance Y1 between the second intermediate electrode and the first intermediate electrode closest to the second intermediate electrode among the first intermediate electrodes is _0.80X or more in relation to the distance X; .94X or less in magnitude ,
A semiconductor light emitting device characterized by: 2. The method according to claim 1, wherein said intermediate electrode further includes said first intermediate electrode and said second intermediate electrode arranged such that respective projections of said first intermediate electrode and said second intermediate electrode are out of said pad section. The semiconductor light emitting device described. 3. The semiconductor light emitting device according to claim 1, wherein said pad portion is provided in a central portion of said main surface. In the relationship between the first intermediate electrode and the second intermediate electrode in at least one of the light extraction regions, the first intermediate electrode and the second intermediate electrode that are second closest to the second intermediate electrode among the first intermediate electrodes. 4. The semiconductor according to any one of claims _{1 to 3, wherein said first intermediate electrode and said second intermediate electrode are arranged such that the proximity distance Y 2 to} the intermediate electrode and the proximity distance Y 1 are the same. light-emitting element. In the relationship between the first intermediate electrode and the second intermediate electrode at the boundary between all the light extraction regions and the wiring section, the second intermediate electrode that is second closest to the second intermediate electrode among the first intermediate electrodes 5. The first intermediate electrode and the second _intermediate electrode are arranged such that the proximity distance Y ₂ between the first intermediate electrode and the second intermediate electrode is the same as the proximity distance Y 1 . 1. The semiconductor light-emitting device according to claim 1. The semiconductor light-emitting device according to any one of claims 1 to 5, wherein said III-V group compound semiconductor is InGaAsP containing at least In and P, and said semiconductor light-emitting layer has an emission center wavelength of 1000 to 2200 nm. . A support substrate, a junction layer including a plurality of island-shaped first intermediate electrodes and second intermediate electrodes, and a first conductivity type semiconductor layer, a semiconductor light emitting layer and a second conductivity type semiconductor layer each made of a Group III-V compound semiconductor. A method for manufacturing a semiconductor light emitting device having in this order,
a semiconductor layer forming step of forming a semiconductor laminate including the second conductivity type semiconductor layer, the light emitting layer and the first conductivity type semiconductor layer on a substrate for growth;
a bonding layer forming step of bonding the support substrate and the semiconductor laminate via a bonding layer including the first intermediate electrode and the second intermediate electrode;
a growth substrate removing step of removing the growth substrate;
An upper electrode comprising a pad portion and a wiring portion is formed on the main surface of the semiconductor laminate from which the growth substrate has been removed, and a region on the main surface other than the upper electrode forming region in which the upper electrode is formed is: a step of forming an upper surface electrode partitioned into a plurality of light extraction regions by the wiring portion;
On a projection plane obtained by vertically projecting the first intermediate electrode and the second intermediate electrode with respect to the main surface,
(a) the first intermediate electrode is arranged such that the projections of the first intermediate electrode closest to each other in the division of the light extraction region are equidistantly spaced apart X;
(b) the second intermediate electrode is arranged such that the projection of the second intermediate electrode and the wiring portion overlap;
(c) The proximity distance Y1 between the second intermediate electrode and the first intermediate electrode closest to the second intermediate electrode among the first intermediate electrodes is 0.80X _or more in relation to the distance X and 0.80X or more. is 94X or less in size ,
A method for manufacturing a semiconductor light emitting device, characterized by: 8. The semiconductor light emitting device according to claim 7, wherein said first intermediate electrode and said second intermediate electrode are arranged such that projections of said first intermediate electrode and said second intermediate electrode are separated from said pad section. manufacturing method. In the relationship between the first intermediate electrode and the second intermediate electrode in at least one of the light extraction regions, the first intermediate electrode that is second closest to the second intermediate electrode among the first intermediate electrodes and the second intermediate electrode. 9. The manufacturing of the semiconductor light emitting device according to claim 7, wherein the first intermediate electrode and the second intermediate electrode are arranged such that the proximity distance _Y2 to the two intermediate electrodes and the proximity distance _Y1 are the same. Method. In the relationship between the first intermediate electrode and the second intermediate electrode at the boundary between all the light extraction regions and the wiring section, the second intermediate electrode that is second closest to the second intermediate electrode among the first intermediate electrodes 10. The first intermediate electrode and the second intermediate electrode are arranged such that the proximity distance _Y2 between the first intermediate electrode and the second intermediate electrode is the same as the proximity distance _Y1 . 2. A method for manufacturing a semiconductor light emitting device according to claim 1.

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