JP6875076B2 - Manufacturing method of semiconductor light emitting device and semiconductor light emitting device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor light emitting device and a semiconductor light emitting device.

Conventionally, an infrared light emitting semiconductor light emitting device having an infrared region having a wavelength of 750 nm or more as a light emitting wavelength is known. Infrared-emitting semiconductor light-emitting devices are widely used in applications such as sensors, gas analysis, and surveillance cameras.

When the emission wavelength of such a semiconductor light emitting device is in the near infrared region of 1000 nm to 2200 nm, it is common to use an InGaAsP-based III-V group semiconductor containing In and P in the active layer. Conventionally, when an InGaAsP-based III-V group semiconductor layer such as an InP layer is epitaxially grown, the InP substrate is used as a growth substrate in order to lattice-match the growth substrate and the InGaAsP-based III-V group semiconductor layer containing In and P. Has been used as.

For example, Patent Document 1 discloses a semiconductor laser having an oscillation wavelength of 1.3 μm. This semiconductor laser has a multiple strain quantum well active layer formed on an n-InP substrate, and the multiple strain quantum well active layer has a structure in which InGaAsP strain quantum wells and InGaAsP barrier layers are alternately laminated. doing.

Further, Patent Document 2 describes a strain quantum well layer composed of an InGaAsP barrier layer having the same lattice constant as the InP substrate, an In _0.3 Ga _0.7 As layer having a shorter lattice constant than the InP substrate, and an InP substrate. It is disclosed that a quantum well layer composed of a lattice strain compensating layer composed of InAs having a long lattice constant is provided on the InP substrate.

Japanese Unexamined Patent Publication No. 7-147454 Japanese Unexamined Patent Publication No. 6-237042

In the techniques described in Patent Document 1 and Patent Document 2, the InP substrate as a growth substrate is used as it is as a support substrate for a semiconductor light emitting device. This is because the InP substrate is transparent to light in the near infrared region, so that there is no problem in terms of light extraction.

However, in a group III-V compound semiconductor-based light emitting device containing In and P provided on an InP substrate, the current path is concentrated directly under the electrode, so that there is a limit to the increase in light emission output.

Therefore, a semiconductor laminate composed of a group III-V compound semiconductor-based layer is formed by epitaxially growing on an InP growth substrate, and a dielectric layer and a contact portion for controlling a current path are provided on the semiconductor laminate, and then The present inventor has conceived a junction-type semiconductor light emitting device in which a metal reflective layer and a conductive support substrate are further provided, and finally the substrate for InP growth is removed. However, it has been confirmed that even if an attempt is made to join the metal bonding layer and the metal reflective layer of the conductive support substrate, bonding failure may occur, and the present inventor has recognized this point as a new problem.

Therefore, the present invention is a bonding type in a group III-V compound semiconductor system containing In and P formed on an InP substrate, which can suppress bonding defects and increase the light emission output more than before. An object of the present invention is to provide a method for manufacturing a semiconductor light emitting device and a semiconductor light emitting device.

The present inventor has diligently studied ways to solve the above problems, and found that an appropriate gap is provided between the metal bonding layer on the support substrate side and the metal reflective layer on the semiconductor laminate side to prevent the occurrence of bonding defects. It has been found that it can be suppressed, and the present invention has been completed.

That is, the gist structure of the present invention is as follows.
(1) A first step of forming a semiconductor laminate in which a plurality of InGaAsP-based III-V compound semiconductor layers containing at least In and P are laminated on an InP growth substrate.
The second step of forming a contact layer made of a group III-V compound semiconductor on the semiconductor laminate, and
A third step of forming an ohmic metal portion on a part of the contact layer and leaving an exposed region on the surface of the contact layer.
The contact layer in the exposed region is removed until the surface of the semiconductor laminate is exposed to form a contact portion composed of the ohmic metal portion and the contact layer, and the exposed surface of the semiconductor laminate is formed. 4 steps and
A fifth step of forming a dielectric layer on a part of the exposed surface of the semiconductor laminate and making the periphery of the contact portion an exposed portion.
A sixth step of forming a metal reflective layer containing Au as a main component on the dielectric layer, the exposed portion, and the contact portion.
The seventh step of joining the conductive support substrate provided with the metal bonding layer on the surface to the metal reflecting layer via the metal bonding layer, and the seventh step.
It has an eighth step of removing the InP growth substrate.
In the fifth step, the thickness of the dielectric layer is formed to be larger than the thickness of the contact portion.
By the bonding in the seventh step, a gap is formed between the metal bonding layer and the metal reflecting layer, and the gap is located in a direction in which the contact portion and the exposed portion face the conductive support substrate. A method for manufacturing a semiconductor light emitting device.

(2) The method for manufacturing a semiconductor light emitting device according to (1) above, wherein the conductive support substrate is a conductive Si substrate.

(3) The method for manufacturing a semiconductor light emitting device according to (2) above, wherein the outer shape of the gap has a concave portion at the center and a convex portion at the peripheral edge.

(4) The semiconductor according to any one of (1) to (3) above, wherein the difference between the thickness of the dielectric layer formed in the fifth step and the thickness of the contact portion is 10 nm or more and 100 nm or less. A method for manufacturing a light emitting element.

(5) The method for manufacturing a semiconductor light emitting device according to any one of (1) to (4) above, wherein the contact area ratio of the dielectric layer in contact with the semiconductor laminate is 80% or more and 95% or less.

(6) The semiconductor laminate includes an n-type clad layer, an active layer, and a p-type clad layer in this order, and the n-type clad layer, the active layer, and the p-type clad layer contain In and P. The method for manufacturing a semiconductor light emitting device according to any one of (1) to (5) above, which is a layer made of at least an InGaAsP-based III-V compound semiconductor.

(7) The method for manufacturing a semiconductor light emitting device according to (6) above, wherein the semiconductor laminate has a double heterostructure or a multiple quantum well structure.

(8) The method for manufacturing a semiconductor light emitting device according to any one of (1) to (7) above, wherein the dielectric layer is made of SiO _2.

(9) Conductive support substrate and
A metal bonding layer provided on the surface of the conductive support substrate and
A metal reflective layer provided on the metal bonding layer, which partially contacts the metal bonding layer and covers the main surface of the metal bonding layer.
The voids provided between the metal bonding layer and the metal reflecting layer,
A semiconductor laminate provided on the metal reflective layer, which is formed by laminating a plurality of InGaAsP-based III-V compound semiconductor layers containing at least In and P.
It has a dielectric layer and a contact portion provided apart and in parallel between the metal reflective layer and the semiconductor laminate.
The main component of the metal reflective layer is Au.
In the gap where the dielectric layer and the contact portion are separated, the metal reflective layer and the semiconductor laminate come into contact with each other.
The semiconductor light emitting device is characterized in that the gap is located in a direction in which the contact portion and the gap are located in a direction facing the conductive support substrate.

(10) The semiconductor light emitting device according to (9) above, wherein the conductive support substrate is a conductive Si substrate.

(11) The semiconductor light emitting device according to (9) or (10), wherein the thickness of the dielectric layer is larger than the thickness of the contact portion.

(12) The semiconductor light emitting device according to any one of (9) to (11) above, wherein the outer shape of the gap has a concave portion at the center and a convex portion at the peripheral edge.

(13) The semiconductor light emitting device according to any one of (9) to (12) above, wherein the difference between the thickness of the dielectric layer and the thickness of the contact portion is 10 nm or more and 100 nm or less.

(14) The semiconductor light emitting device according to any one of (9) to (13) above, wherein the contact area ratio of the dielectric layer in contact with the semiconductor laminate is 80% or more and 95% or less.

(15) The semiconductor laminate includes an n-type clad layer, an active layer, and a p-type clad layer in this order, and the n-type clad layer, the active layer, and the p-type clad layer contain In and P. The semiconductor light emitting device according to any one of (9) to (14) above, which is a layer made of at least an InGaAsP-based III-V compound semiconductor.

(16) The semiconductor light emitting device according to (15) above, wherein the semiconductor laminate has a double heterostructure or a multiple quantum well structure.

(17) The semiconductor light emitting device according to any one of (9) to (16) above, wherein the dielectric layer is made of SiO _2.

According to the present invention, a bonding type in a group III-V compound semiconductor system containing In and P formed on an InP substrate, which can suppress bonding defects and increase the light emission output as compared with the conventional case. A method for manufacturing a semiconductor light emitting device and a semiconductor light emitting device can be provided.

(A) to (C) are schematic cross-sectional views in a manufacturing process of a semiconductor light emitting device according to an embodiment of the present invention. (A) to (C) are schematic cross-sectional views in a manufacturing process of a semiconductor light emitting device according to an embodiment of the present invention. (A) and (B) are schematic cross-sectional views in the manufacturing process of the semiconductor light emitting device according to one embodiment of the present invention. (A) and (B) are schematic cross-sectional views in the manufacturing process of the semiconductor light emitting device according to one embodiment of the present invention. It is a schematic diagram explaining the dielectric layer and the periphery of the contact part of the semiconductor light emitting device according to one Embodiment of this invention. (A) is a schematic top view which shows the pattern of the ohmic electrode part in an Example, and (B) is a schematic top view which shows the pattern of the top electrode part in an Example. (A) is a TEM cross-sectional view of the semiconductor light emitting device according to Invention Example 1, and (B) is a schematic view thereof.

Prior to the description of the embodiment according to the present invention, the following points will be described in advance. First, when the composition ratio is not specified in the present specification and is simply expressed as "InGaAsP", the chemical composition ratio of the group III element (total of In and Ga) and the group V element (As, P) is 1. It is assumed to mean an arbitrary compound which is 1 and the ratio of In and Ga which are Group III elements and the ratio of As and P which are Group V elements are indefinite, respectively. In this case, the case where either In or Ga is not contained in the group III element is included, and the case where either one of As or P is not contained in the group V element is included. However, when explicitly described as InGaAsP "containing at least In and P", the group III element contains more than 0% and 100% or less of In, and the group V element contains more than 0% and 100% or less of P. It shall be. Further, when it is described as "InGaP", it means that As is not contained in the above-mentioned "InGaAsP", and when it is described as "InGaAs", it means that P is not contained in the above-mentioned "InGaAsP". .. Similarly, when it is described as "InAsP", it means that Ga is not contained in the above "InGaAsP", and when it is described as "GaAsP", it means that In is not contained in the above "InGaAsP". To do. When it is expressed as "InP", it means that Ga and As are not included in the above "InGaAsP". The composition ratio of each component of InGaAsP can be measured by photoluminescence measurement, X-ray diffraction measurement, or the like.

Further, in the present specification, a layer that electrically functions as a p-type is referred to as a p-type layer, and a layer that electrically functions as an n-type is referred to as an n-type layer. On the other hand, when a specific impurity such as Zn, S, or Sn is not intentionally added and does not electrically function as a p-type or n-type, it is referred to as "i-type" or "undoped". The undoped InGaAsP layer may contain unavoidable impurities during the manufacturing process, and specifically, if the carrier density is small (for example, ^{less than 4 × 10 16} / cm ³ ), it is considered to be “undoped”. It shall be dealt with in this specification. Further, the values of the concentration of impurities such as Zn and Sn are based on SIMS analysis.

Further, the entire thickness of each layer to be formed can be measured by using an optical interference type film thickness measuring device. Further, each of the thicknesses of each layer can be calculated by observing the cross section of the growth layer with a light interference type film thickness measuring device and a transmission electron microscope. Further, when the thickness of each layer is small as in the superlattice structure, the thickness can be measured by using TEM-EDS. In the cross-sectional view, when a predetermined layer has an inclined surface, the thickness of the layer shall be the maximum height from the flat surface of the layer immediately below the layer.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. Here, the relationship between FIGS. 1 to 5 will be described prior to the description of the embodiment of the method for manufacturing a semiconductor light emitting device according to the present embodiment. 1 to 4 are schematic cross-sectional views for explaining each step in the method for manufacturing a semiconductor light emitting device according to an embodiment of the present invention, and the semiconductor light emitting devices are shown in FIGS. 1 (A) to 1 (C) and FIG. It can be manufactured in the order of (A) to (C), FIG. 3 (A), (B), FIG. 4 (A), (B). FIG. 5 is an enlarged view illustrating the periphery of the dielectric layer 50 and the contact portion 40 formed in FIG. 2C. In principle, the same components are given the same reference numbers, and duplicate explanations are omitted. Further, in each figure, for convenience of explanation, the aspect ratios of the substrate and each layer are exaggerated from the actual ratios.

(Manufacturing method of semiconductor light emitting device)
The method for manufacturing the semiconductor light emitting device 100 according to the embodiment of the present invention includes the first step, the second step, the third step, the fourth step, the fifth step, the sixth step, the seventh step, which will be described in detail below. It has an eighth step. In the first step, a semiconductor laminate 30 in which a plurality of InGaAsP-based III-V compound semiconductor layers containing at least In and P are laminated is formed on the InP growth substrate 10 (FIGS. 1A and 1B). ). In the second step, a contact layer 41 made of a group III-V compound semiconductor is formed on the semiconductor laminate 30 (FIG. 1 (C)). In the third step, the ohmic metal portion 43 is formed on a part of the contact layer 41, and the exposed region E1 is left on the surface of the contact layer 41 (FIG. 2A). In the fourth step, the contact layer 41 in the exposed region E1 is removed until the surface of the semiconductor laminate 30 is exposed to form the contact portion 40 composed of the ohmic metal portion 43 and the contact layer 41a, and the semiconductor laminate 30 is formed. The exposed surface E2 of the above is formed (FIG. 2 (B)). In the fifth step, the dielectric layer 50 is formed on a part of the exposed surface E2 of the semiconductor laminate 30, and the periphery of the contact portion 40 is designated as the exposed portion E3 (FIG. 2C). In the sixth step, a metal reflective layer 60 containing Au as a main component is formed on the dielectric layer 50, the exposed portion E3, and the contact portion 40 (FIG. 3 (A)). In the seventh step, the conductive support substrate 80 provided with the metal bonding layer 70 on the surface is bonded to the metal reflecting layer 60 via the metal bonding layer 70 (FIG. 3 (B)). Then, in the eighth step, the InP growth substrate 10 is removed (FIG. 4 (A)). Here, in the fifth step (FIG. 2C), the thickness of the dielectric layer 50 is formed to be larger than the thickness of the contact portion 40. Then, by joining in the seventh step (FIG. 3B), a gap V is formed between the metal bonding layer 70 and the metal reflecting layer 60, and the contact portion 40 and the exposed portion E3 are conductive in the gap V. It is located in the direction facing the support substrate 80. In this way, the semiconductor light emitting device 100 according to the embodiment of the present invention is manufactured. Hereinafter, details of each step will be described in sequence.

<First step>
As described above, the first step is a step of forming a semiconductor laminate 30 in which a plurality of InGaAsP-based III-V compound semiconductor layers containing at least In and P are laminated on the InP growth substrate 10 (FIG. 1). (A), (B)).

In the first step, as shown in FIG. 1A, first, the InP growth substrate 10 is prepared. As the InP growth substrate 10, any generally available n-type InP substrate, undoped InP substrate, or p-type InP substrate can be used. Hereinafter, for convenience of explanation, an embodiment in which an n-type InP substrate is used as the InP growth substrate 10 will be described.

In the first step, a semiconductor laminate 30 in which a plurality of InGaAsP-based III-V compound semiconductor layers containing at least In and P are laminated is formed on the InP growth substrate 10. The semiconductor laminate 30 includes an n-type clad layer 31, an active layer 35, and a p-type clad layer 37 in this order, and the n-type clad layer 31, the active layer 35, and the p-type clad layer 37 contain In and P. It is preferably a layer made of at least an InGaAsP-based III-V compound semiconductor. The semiconductor laminate 30 can have a double hetero (DH) structure or a multiple quantum well (MQW) structure in which the active layer 35 is sandwiched between the n-type clad layer 31 and the p-type clad layer 37. It is more preferable that the semiconductor laminate 30 has a multiple quantum well structure in order to improve the light output by suppressing crystal defects. The multiple quantum well structure can be formed by alternately repeating the well layer 35W and the barrier layer 35B, the well layer 35W can be InGaAsP, and the barrier layer 35B has a band gap larger than that of the well layer 35W. It is preferably a large InGaAsP. With such a semiconductor laminate 30, the emission wavelength of the semiconductor light emitting device 100 can be set to a wavelength in a desired near infrared region. For example, the emission peak wavelength can be set to 1000 to 1650 nm by changing the composition of the InGaAsP-based III-V group compound, and in the case of the MQW structure, in addition to changing the composition of the InGaAsP-based III-V group compound, the well layer and the barrier The emission peak wavelength can be set to 1000 to 1900 nm by adjusting the composition difference of the layers and applying strain to the well layer. In either case, the emission peak wavelength is preferably 1300 to 1500 nm. The n-type clad layer 31 is preferably an n-type InP clad layer, and the p-type clad layer 37 is preferably a p-type InP clad layer. Further, when the component composition of the well layer 35W _{is expressed as In xw} Ga _1-xw As _yw P _1-yw , 0.5 ≦ xw ≦ 1 and 0.3 ≦ yw ≦ 1 can be obtained. It is preferable that 6 ≦ xw ≦ 0.8 and 0.5 ≦ yw ≦ 1. Further, when the component composition of the barrier layer 35B _{is expressed as In xb} Ga _1-xb As _yb P _1-yb , 0.5 ≦ xb ≦ 1 and 0 ≦ yb ≦ 0.5 can be obtained. It is preferable that 8 ≦ xb ≦ 1 and 0 ≦ yb ≦ 0.2.

The overall thickness of the semiconductor laminate 30 is not limited, but can be, for example, 2 μm to 8 μm. Further, the thickness of the n-type clad layer 31 is not limited, but can be, for example, 1 μm to 5 μm. Further, the thickness of the active layer 35 is not limited, but can be, for example, 100 nm to 1000 nm. Further, the thickness of the p-type clad layer 37 is not limited, but can be, for example, 0.8 μm to 3 μm. When the active layer 35 has a quantum well structure, the thickness of the well layer 35W can be 3 nm to 15 nm, the thickness of the barrier layer 35B can be 5 to 15 nm, and the number of pairs of both can be 3 to 50. can do.

Further, it is also preferable that the semiconductor laminate 30 has a p-type cap layer 39 made of InGaAsP containing at least In and P on the p-type clad layer 37. By providing the p-type cap layer 39, the lattice mismatch can be alleviated. The thickness of the p-type cap layer 39 is not limited, but can be, for example, 50 to 200 nm. In the following embodiments, for convenience of explanation, the outermost layer of the semiconductor laminate 30 will be described as the p-type cap layer 39. However, since the p-type cap layer 39 has an arbitrary configuration, for example, the outermost layer of the semiconductor laminate 30 The surface layer may be the p-type clad layer 37.

Although not shown, it is also preferable that the semiconductor laminate 30 has an i-type InP spacer layer between the n-type clad layer 31 and the active layer 35 and between the active layer 35 and the p-type clad layer, respectively. By providing the i-type InP spacer layer, diffusion of the dopant can be prevented. The thickness of the i-type InP spacer layer is not limited, but can be, for example, 50 to 400 nm.

Here, each layer of the semiconductor laminate 30 can be formed by epitaxial growth, for example, an organic metal vapor deposition (MOCVD) method, a molecular beam epitaxy (MBE) method, or sputtering. It can be formed by a known thin film growth method such as a method. For example, trimethylindium (TMIn) as the In source, trimethylgallium (TMGa) as the Ga source, arsine (AsH ₃ ) as the As source, and phosphine (PH ₃ ) as the P source are used in a predetermined mixing ratio, and these raw material gases are used. By vapor phase growth using carrier gas, the InGaAsP layer can be formed to a desired thickness according to the growth time. Other InGaAsP layers to be epitaxially grown can also be formed by the same method. When each layer is p-type or n-type dopant, a dopant source gas may be further used if desired.

In the first step, it is also preferable to form the etching stop layer 20 on the InP growth substrate 10 prior to forming the semiconductor laminate 30. The etching stop layer 20 can be used when the InP growth substrate 10 is removed by etching in the eighth step. An n-type InGaAs layer can be used as the etching stop layer. In this case, the In composition ratio of the group III element is preferably 0.3 to 0.7 in order to lattice-match with the InP growth substrate 10. It is more preferably 0.5 to 0.6.

<Second step>
The second step is a step of forming a contact layer 41 made of a group III-V compound semiconductor on the semiconductor laminate 30 as described above (FIG. 1 (C)). For example, as shown in FIG. 1C, a p-type contact layer 41 can be formed on the p-type cap layer 39. The p-type contact layer 41 is a layer that is in contact with the ohmic metal portion 43 and is interposed between the ohmic metal portion 43 and the semiconductor laminate 30, and is between the ohmic metal portion 43 as compared with the semiconductor laminate 30. As long as the composition has a small contact resistance, for example, a p-type InGaAs layer can be used as the p-type contact layer 41. The thickness of the contact layer 41 is not limited, but can be, for example, 50 nm to 200 nm.

<Third step>
In the third step, as described above, the ohmic metal portion 43 is formed on a part of the contact layer 41, and the exposed region E1 is left on the surface of the contact layer 41 (FIG. 2A). The ohmic metal portion 43 can be formed by being dispersed in an island shape in a predetermined pattern. When a p-type InGaAs layer is used as the p-type contact layer 41, for example, Au, AuZn, AuBe, AuTi, etc. can be used as the ohmic metal portion 43, and it is also preferable to use a laminated structure thereof. For example, Au / AuZn / Au can be the ohmic metal portion 43. The thickness (or total thickness) of the ohmic metal portion 43 is not limited, but can be, for example, 300 to 1300 nm, more preferably 350 nm to 800 nm.

Here, for example, if a resist pattern is formed on the surface of the contact layer 41, the ohmic metal portion 43 is vapor-deposited, and the resist pattern is lifted off to form the resist pattern, the third step can be performed. The third step can also be performed by forming a predetermined metal layer on the entire surface of the contact layer 41, forming a mask on the metal layer, and etching to form the ohmic metal portion 43. it can. In either case, as shown in FIG. 2A, the ohmic metal portion 43 is formed on a part of the contact layer 41, and the surface of the contact layer 41 is a surface that the ohmic metal portion 43 does not contact, that is, The exposed region E1 is formed.

The shape of the ohmic metal portion 43 may be trapezoidal in the cross-sectional view as shown in FIG. 2 (A), but this is only a schematic example. The shape of the ohmic metal portion 43 may be formed in a rectangular shape in the cross-sectional view, or may have rounded corners.

<4th process>
In the fourth step, as described above, the contact layer 41 in the exposed region E1 is removed until the surface of the semiconductor laminate 30 is exposed to form the contact portion 40 composed of the ohmic metal portion 43 and the contact layer 41a. This is a step of forming the exposed surface E2 of the semiconductor laminate 30 (FIG. 2B). That is, the contact layer 41 formed in the third step above at a location other than the ohmic metal portion 43 is etched with the contact layer 41a until the surface of the p-type cap layer 39, which is the outermost layer of the semiconductor laminate 30, is exposed. To do. For example, a resist mask may be formed in the ohmic metal portion 43 and its vicinity (about 2 to 5 μm), and the exposed region E1 of the contact layer 41 may be wet-etched with a tartaric acid-hydrogen peroxide system or the like. In addition, wet etching is also possible with an inorganic acid-hydrogen peroxide system and an organic acid-hydrogen peroxide system. Further, when a mask is formed on the metal layer in the third step and the ohmic metal portion 43 is formed by etching, the etching in the fourth step may be continuously performed.

The thickness of the contact portion 40 corresponds to the total thickness of the contact layer 41 (41a) and the ohmic metal portion 43, and can be, for example, 350 nm to 1500 nm, more preferably 400 nm to 1000 nm.

<Fifth step>
As described above, the fifth step is a step of forming the dielectric layer 50 on a part of the exposed surface E2 of the semiconductor laminate 30 and forming the periphery of the contact portion 40 as the exposed portion E3 (FIG. 2 (C)). )). Such a dielectric layer 50 and the exposed portion E3 can be formed, for example, as follows.

First, a dielectric layer is formed on the entire surface of the semiconductor laminate 30 so as to cover the semiconductor laminate 30 and the contact portion 40. As the film forming method, known methods such as a plasma CVD method and a sputtering method can be applied. Then, a window pattern that completely surrounds the contact portion is formed by the resist above the contact portion 40 on the surface of the formed dielectric layer. In this case, it is preferable that the window pattern has an extension of about 1 to 5 μm with respect to the length in the width direction and the length in the longitudinal direction of the contact portion. By removing the dielectric material around the contact portion by etching using the resist pattern thus formed, the dielectric layer 50 is formed and the periphery of the contact portion 40 becomes the exposed portion E3. The etching may be wet etching with buffered hydrofluoric acid (BHF) or the like.

By providing the exposed portion E3, it is possible to suppress peeling between the dielectric layer 50 and the semiconductor laminate 30. In order to surely obtain this effect, the width W of the exposed portion E3 is preferably 0.5 μm or more and 5 μm or less, and more preferably 1 μm or more and 3.5 μm or less (see FIG. 5).

Further, the contact area ratio of the dielectric layer 50 in contact with the semiconductor laminate 30 is preferably 80% or more and 95% or less. By doing so, the path of the current flowing through the active layer 35 of the semiconductor laminate 30 can be appropriately controlled so as to be dispersed and flowed to other than directly under the electrode, and the light emitting output of the semiconductor light emitting element 100 can be further increased. be able to. The contact area ratio can be measured in the state of the wafer, and when the contact area ratio is calculated back from the state of the semiconductor light emitting device after the individualization, the semiconductor layer removed during the individualization (the contact area ratio) The width of the region where the dielectric layer was present) may be calculated assuming that the width of one side is 20 to 30 μm (both widths of 40 to 60 μm).

Here, in the present embodiment according to the manufacturing method, in order to form the void V in the subsequent seventh step, the thickness of the dielectric layer 50 is formed larger than the thickness of the contact portion 40 in the fifth step. And. That is, as shown in FIG. 5, if the thickness of the dielectric layer 50 was expressed _{H 1,} the thickness of the contact portion with _{H 2,} and _H 1> H _2. By doing so, the void V can be reliably formed. Under this condition, the thickness of the dielectric layer 50 can be, for example, 360 nm to 1600 nm, more preferably 410 nm to 1100 nm. Further, in order to more reliably form a void V, a thickness _{H 1} of the dielectric layer, the difference _H 1 -H ₂ between the thickness of _{H 2} contact portions 40 and more preferably to 10nm or 100nm or less.

Further, as the dielectric layer 50, SiO ₂ , SiN, ITO, AlN and the like can be used, and it is particularly preferable that the dielectric layer 50 is made of SiO ₂ . This is because SiO ₂ is easily etched by BHF or the like.

<Sixth step>
As described above, the sixth step is a step of forming a metal reflective layer 60 containing Au as a main component on the dielectric layer 50, the exposed portion E3, and the contact portion 40 (FIG. 3 (A)). The metal reflective layer 60 containing Au as a main component means that Au occupies more than 50% by mass in the composition of the metal reflective layer 60, and more preferably Au is 80% by mass or more. The metal reflective layer 60 can include a plurality of metal layers, but when the metal reflective layer 60 includes a metal layer made of Au (hereinafter, “Au metal layer”), the Au metal out of the total thickness of the metal reflective layer 60 The thickness of the layer is preferably more than 50%. As the metal constituting the metal reflective layer 60, Al, Pt, Ti, Ag and the like can be used in addition to Au. For example, the metal reflective layer 60 may be a single layer composed of only Au, or the metal reflective layer 60 may include two or more Au metal layers. In order to ensure the bonding in the subsequent seventh step, it is preferable that the outermost layer (the surface opposite to the semiconductor laminate 30) of the metal reflective layer 60 is an Au metal layer. For example, a metal layer can be formed in the order of Al, Au, Pt, and Au on the dielectric layer 50, the exposed portion E3, and the contact portion 40 to form the metal reflective layer 60. The thickness of one layer of the Au metal layer in the metal reflective layer 60 can be, for example, 400 nm to 2000 nm, and the thickness of the metal layer made of a metal other than Au can be, for example, 5 nm to 200 nm. The metal reflective layer 60 can be formed by forming a film on the dielectric layer 50, the exposed portion E3, and the contact portion 40 by a general method such as a vapor deposition method.

Here, as schematically shown in FIG. 3A, the upper surface of the metal reflective layer 60 does not become a flat surface, and the concave portion R is formed above the exposed portion E3 and the contact portion 40. This is because, in the fifth step, the thickness of the dielectric layer 50 was formed to be larger than the thickness of the contact portion 40, and the exposed portion E3 was formed on the surface of the semiconductor laminate 30. The recess R will be described later together with the void V in the following description of the seventh step.

<7th process>
As described above, the seventh step is a step of joining the conductive support substrate 80 provided with the metal bonding layer 70 on the surface to the metal reflective layer 60 via the metal bonding layer 70 (FIG. 3 (B)). .. A metal bonding layer 70 may be formed in advance on the surface of the conductive support substrate 80 by a sputtering method, a vapor deposition method, or the like. By arranging the metal bonding layer 70 and the metal reflecting layer 60 so as to face each other and bonding them together, and performing heat compression bonding at a temperature of about 250 ° C. to 500 ° C., both can be bonded.

For the metal bonding layer 70 to be bonded to the metal reflective layer 60, a metal such as Ti, Pt, Au or a metal (Sn or the like) forming a eutectic alloy with gold can be used, and these are laminated. Is preferable. For example, the metal bonding layer 70 can be formed by laminating Ti having a thickness of 400 nm to 800 nm, Pt having a thickness of 5 nm to 20 nm, and Au having a thickness of 700 to 1200 nm in order from the surface of the conductive support substrate 80. In order to facilitate the bonding between the metal reflective layer 60 and the metal bonding layer 70, the outermost layer on the metal bonding layer 70 side is an Au metal layer, and the metal layer on the metal bonding layer 70 side of the metal reflective layer 60 is also Au. As a result, it is preferable to join Au to each other by Au-Au diffusion.

As the conductive support substrate 80, it is preferable to use a substrate that is transparent to near-infrared wavelengths. For example, a conductive Si substrate can be used. In addition, a conductive GaAs substrate or a Ge substrate can be used. You may use it. In addition to the above-mentioned semiconductor substrate, a metal substrate can also be used. The thickness of the conductive support substrate 80 varies depending on the material used, but can be 100 μm or more and 500 μm or less, and if it is a Si substrate or a GaAs substrate, it can be handled even if the thickness is less than 200 μm. A Si substrate is particularly preferable in consideration of heat dissipation, brittleness, and cost.

Here, the gap V is formed between the metal bonding layer 70 and the metal reflecting layer 60 by the bonding in the seventh step. The gap V is located in the direction in which the contact portion 40 and the exposed portion E3 face the conductive support substrate 80. This is because the recess R formed in the sixth step is closed between the metal bonding layer 70 and the metal reflecting layer 60 to form a void V. When the void V is formed, the shape of the recess R may be slightly deformed by heat compression. In the present embodiment, since such a void V is intentionally formed, it has been experimentally confirmed that the metal reflective layer 60 and the metal bonding layer 70 can be satisfactorily bonded in a portion other than the void V. It was. Further, in this case, it was confirmed that the reliability of the forward voltage Vf (that is, the presence or absence of Vf increase or disconnection due to the change with time) can be improved. It is also presumed that the reason why such an effect is obtained is that the unique shape of the void V formed by the present embodiment has an effect of suppressing the diffusion of impurities from the conductive support substrate 80 side to the contact portion.

Here, it is preferable that the outer shape of the gap V has a concave portion at the center and a convex portion at the peripheral edge. Such a shape is sometimes called an outer ring mountain shape. When the outer shape of the gap V has an outer ring shape, the metal reflective layer 60 and the metal bonding layer 70 can be joined more reliably. The outer shape of the void V can be observed with an electron microscope. Further, it is preferable that the convex portion has a chevron shape or a trapezoidal shape and the convex portion has an inclined hem portion (inclined surface) in order to suppress stress concentration.

<8th step>
The eighth step is a step of removing the InP growth substrate 10 as described above (FIG. 4 (A)). The InP growth substrate 10 can be removed by wet etching using, for example, a hydrochloric acid diluent, and when the etching stop layer 20 is formed, the etching can be completed at the layer. When the etching stop layer is an n-type InGaAs layer, it may be removed by wet etching with, for example, a sulfuric acid-hydrogen peroxide system.

As described above, the semiconductor light emitting device 100 can be manufactured. Since the semiconductor light emitting device 100 has a gap V formed, it is possible to suppress a bonding defect. Further, since the dielectric layer 50, the contact portion 40, and the metal reflective layer 60 are formed on the surface of the semiconductor laminate 30 on the conductive support substrate 80 side, it is possible to control the current path so as not to concentrate directly under the electrodes. At the same time, the side opposite to the conductive support substrate 80 can be used as a light outlet. Therefore, the light emission output can be increased as compared with a semiconductor light emitting device using the conventional InP substrate as a growth substrate and a support substrate.

In the manufacturing method according to the present embodiment, as shown in FIG. 4B, after the semiconductor light emitting device 100 is manufactured, the back electrode 91 is formed on the back surface of the conductive support substrate 80, and the front surface of the semiconductor laminate 30 is formed. It may further have a step of forming the upper surface electrode 93. The top electrode 93 may include a wiring portion 93a and a pad portion 93b. By performing such a step, the semiconductor light emitting device 100'can be manufactured. A known method can be used for forming the back surface electrode 91 and the top surface electrode 93, and for example, a sputtering method, an electron beam vapor deposition method, a resistance heating method, or the like can be used.

Further, since this embodiment uses an n-type InP substrate as the InP growth substrate 10 for convenience of explanation, the n-type and p-type of each layer formed on the InP growth substrate 10 are described above. However, when a p-type InP substrate is used, it is naturally understood that the conductive n-type / p-type of each layer is reversed. When an undoped InP substrate is used as the InP growth substrate 10, the conductivity of each layer is determined according to the conductivity (p-type or n-type) of the semiconductor layer formed on the InP growth substrate 10. Just do it.

(Semiconductor light emitting device)
The semiconductor light emitting device 100 according to the embodiment of the present invention can be manufactured by the embodiment of the above-mentioned manufacturing method. That is, as shown in FIG. 4A, the semiconductor light emitting element 100 is placed on the conductive support substrate 80, the metal bonding layer 70 provided on the surface of the conductive support substrate 80, and the metal bonding layer 70. A metal reflective layer 60 that is provided and partially contacts the metal joint layer 70 and covers the main surface of the metal joint layer 70, a void V provided between the metal joint layer 70 and the metal reflective layer 60, and a metal. Between the semiconductor laminate 30 provided on the reflective layer 60 and having a plurality of InGaAsP-based III-V group compound semiconductor layers containing at least In and P laminated, and the metal reflective layer 60 and the semiconductor laminate 30. It has a dielectric layer 50 and a contact portion 40 provided separately and in parallel. The main component of the metal reflective layer 60 is Au, and the metal reflective layer 60 and the semiconductor laminate 30 come into contact with each other in the gap where the dielectric layer 50 and the contact portion 40 are separated. The gap is located in the direction facing the conductive support substrate 80.

As described above, since the gap V is formed in the semiconductor light emitting device 100, poor bonding is suppressed. Since the dielectric layer 50, the contact portion 40, and the metal reflective layer 60 are formed on the surface of the semiconductor laminate 30 on the conductive support substrate 80 side, the current path can be controlled and the conductive support can be controlled. The side opposite to the substrate 80 can be used as the light outlet. Therefore, the light emission output can be increased as compared with a semiconductor light emitting device using the conventional InP substrate as a growth substrate and a support substrate.

Here, the thickness of the dielectric layer 50 is preferably larger than the thickness of the contact portion 40. This is because the embodiment of the above-mentioned manufacturing method is suitable for forming the void V and does not require an extra step. However, in the present embodiment, the magnitude relationship between the thickness of the dielectric layer 50 and the thickness of the contact portion 40 is not limited. The void V can also be formed by a manufacturing method different from the above-described manufacturing method. For example, after forming the metal reflective layer 60, the void V can also be obtained by forming a recess on the metal reflective layer 60 at a position corresponding to the contact portion 40.

Further, as described above, the conductive support substrate 80 is preferably a conductive Si substrate. Further, the outer shape of the gap V preferably has a concave portion at the center and a convex portion at the peripheral edge. The contact area ratio of the dielectric layer 50 in contact with the semiconductor laminate 30 is preferably 80% or more and 95% or less.

Further, the semiconductor laminate 30 includes an n-type clad layer 31, an active layer 35, and a p-type clad layer 37 in this order, and the n-type clad layer 31, the active layer 35, and the p-type clad layer 37 are In and It is preferable that the layer is made of an InGaAsP-based III-V compound semiconductor containing at least P. Further, the semiconductor laminate 30 can have a double heterostructure or a multiple quantum well structure in which the active layer 35 is sandwiched between the n-type clad layer 31 and the p-type clad layer 37, and the active layer 35 has a multiple quantum well structure. As described above, it is preferable to have it. The dielectric layer is preferably _{made of SiO 2.}

Further, as described in the embodiment of the manufacturing method, the semiconductor light emitting device 100 may further have an arbitrary configuration. Further, as shown in FIG. 4B, the semiconductor light emitting device 100 may be provided with the back surface electrode 91 and the top surface electrode 93 to form the semiconductor light emitting device 100'.

(Invention Example 1)
Hereinafter, the present invention will be described in more detail with reference to Examples, but the present invention is not limited to the following Examples. The semiconductor light emitting device according to Invention Example 1 was manufactured according to the flowcharts shown in FIGS. 1 to 4. Specifically, it is as follows.

First, on the (100) surface of the n-type InP substrate, an n-type In _0.57 Ga _0.43 As etching stop layer, an n-type InP clad layer (thickness: 2 μm), and an i-type InP spacer layer (thickness: 300 nm). , Active layer of quantum well structure with emission wavelength 1300 nm (total 130 nm), i-type InP spacer layer (thickness: 300 nm), p-type InP clad layer (thickness: 1.2 μm), p-type In _0.80 Ga _0.20 As _0.50 P _0.50 cap layer (thickness: 50 nm) and p-type In _0.57 Ga _0.43 As contact layer (thickness: 130 nm) were sequentially formed by the MOCVD method. In forming the active layer of the quantum well structure, 10 layers of In _0.73 Ga _0.27 As _0.50 P _0.50 well layer (thickness: 5 nm) and 10 layers of In P barrier layer (thickness: 8 nm) were alternately formed. Laminated.

As shown in FIG. 6A, a p-type ohmic electrode portion (Au / AuZn / Au, total thickness: 530 nm) dispersed in an island shape is formed on the p-type In _0.57 Ga _{0.43 As contact layer.} did. The I-I cross-sectional view of FIG. 6 (A) corresponds to the schematic cross-sectional view of FIG. 2 (A). In forming this pattern, a resist pattern was formed, then an ohmic electrode was vapor-deposited, and the resist pattern was lifted off. When the semiconductor layer of the wafer was observed from above using an optical microscope in this state, the contact area ratio of the p-type ohmic electrode portion to the semiconductor layer was 4.5%. The outer size of FIG. 6A is 380 μm square.

Next, a resist mask was formed in and around the p-type ohmic electrode portion, and the p-type In _0.57 Ga _0.43 As contact layer other than the place where the ohmic electrode portion was formed was wetted with tartrate-hydrogen peroxide. Removed by etching. Then, a dielectric layer (thickness: 700 nm) made _{of SiO 2} was formed on the entire surface of the p-type In _0.80 Ga _0.20 As _0.50 P _{0.50 cap layer by the plasma CVD method.} Then, a window pattern having a shape in which a width of 3 μm is added in the width direction and the longitudinal direction is formed by a resist in the upper region of the p-type ohmic electrode portion, and the p-type ohmic electrode portion and the dielectric layer around it are wetted by BHF. It was removed by etching to expose the p-type In _0.80 Ga _0.20 As _0.50 P _0.50 cap layer. At this time, _{the height H 1} (700 nm) of the dielectric layer on the _{p-type In 0.80} Ga _0.20 As _0.50 P _0.50 cap layer is the p-type contact layer (thickness: 130 nm) and the p-type. The height of the contact portion including the ohmic electrode portion (thickness: 530) is _{40 nm higher than the height H 2} (660 nm). When the semiconductor layer of the wafer was observed from above using an optical microscope in this state, _{the contact area ratio of the dielectric layer (SiO 2} ) was 90%, and p-type In _0.80 Ga _0.20 As. The exposed width of the _0.50 P _{0.50 cap layer (the width of the gap between the SiO 2} dielectric layer and the p-type In _0.57 Ga _0.43 As contact layer) was about 3 μm.

Next, a metal reflective layer (Al / Au / Pt / Au) was formed by vapor deposition on the entire surface of _{the p-type In 0.80} Ga _0.20 As _0.50 P _{0.50 cap layer.} The thickness of each metal layer of the metal reflective layer is 10 nm, 650 nm, 100 nm, and 900 nm, respectively.

On the other hand, a metal bonding layer (Ti / Pt / Au) was formed on the conductive Si substrate to be the support substrate. The thickness of each metal layer of the metal bonding layer is 650 nm, 10 nm, and 900 nm, respectively.

These metal reflective layers and metal bonding layers were arranged so as to face each other, and heat compression bonding was performed at 300 ° C. Then, the InP substrate was removed by wet etching with a hydrochloric acid diluent, and the n-type In _0.57 Ga _0.43 As etching stop layer was removed by wet etching using a sulfuric acid-hydrogen peroxide system.

Next, on the n-type InP clad layer, as the wiring portion of the upper surface electrode, the n-type electrode (Au (thickness: 10 nm) / Ge (thickness: 33 nm) / Au (thickness: 57 nm) / Ni (thickness: 34 nm) / Au (thickness: 800 nm) / Ti (thickness: 100 nm) / Au (thickness: 1000 nm) was formed as shown in FIG. 6 (B) by forming a resist pattern, depositing an n-type electrode, and lifting off the resist pattern. .. Further, a pad portion (Ti (thickness: 150 nm) / Pt (thickness: 100 nm) / Au (thickness: 2500 nm)) was formed on the n-type electrode, and the pattern of the upper surface electrode was as shown in FIG. 6 (B). .. The cross-sectional view of II-II in FIG. 6 (B) corresponds to FIG. 4 (B). Similar to FIG. 6 (A), the outer size of FIG. 6 (B) is 380 μm square.

Finally, the semiconductor layer between each element (width 60 μm) was removed by mesa etching to form a dicing line. Then, a back electrode (Ti (thickness: 10 nm) / Pt (thickness: 50 nm) / Au (thickness 200 nm)) is formed on the back side of the Si substrate, and the chips are separated by dicing to obtain Invention Example 1. Such a semiconductor light emitting device was manufactured. The chip size is 350 μm × 350 μm.

(Comparative Example 1)
In Invention Example 1, except that aligned with the height of the contact portion of the height H ₁ of the dielectric layer as 660nm was manufactured semiconductor light-emitting element in Comparative Example 1 in the same manner as in Invention Example 1.

(Comparative Example 2)
In Invention Example 1, except that the dielectric layer height H ₁ reversed the height relationship between the height of the contact portion as 620nm was manufactured semiconductor light-emitting element in Comparative Example 2 in the same manner as in Invention Example 1.

(Conventional example 1)
The semiconductor light emitting device according to Comparative Example 1 was manufactured as follows. First, on the (100) surface of the n-type InP substrate, an n-type InP clad layer (thickness: 2 μm), an i-type InP spacer layer (thickness: 300 nm), and an active layer having a quantum well structure with an emission wavelength of 1300 nm (total 130 nm). , I-type InP spacer layer (thickness: 300 nm), p-type InP clad layer (thickness: 1.2 μm), p-type In _0.80 Ga _0.20 As _0.50 P _0.50 cap layer (thickness: 50 nm) , P-type In _0.57 Ga _0.43 As contact layer (thickness: 130 nm) was sequentially formed by the MOCVD method. Then, a back electrode (Ti (thickness: 10 nm) / Pt (thickness: 50 nm) / Au (thickness 200 nm)) is formed on the back surface of the n-type InP substrate to form a p-type In _0.57 Ga _0.43 As contact layer. A top electrode (AuGe / Ni / Au electrode) was formed on the central portion and individualized in the same manner as in Invention Example 1. In forming the active layer of the quantum well structure, 10 layers of In _0.73 Ga _0.27 As _0.50 P _0.50 well layer (thickness: 5 nm) and 10 layers of In P barrier layer (thickness: 8 nm) were alternately formed. Laminated.

<Evaluation 1: Joining evaluation>
In Invention Example 1 and Comparative Example 1, bonding could be performed satisfactorily. On the other hand, in Comparative Example 2, peeling may occur.

<Evaluation 2: Emission output evaluation>
The forward voltage Vf and the light emission output Po by the integrating sphere were measured when a current of 20 mA was passed through the semiconductor light emitting devices obtained from Invention Example 1, Comparative Example 1 and Conventional Example 1 using a constant current voltage power supply, and each of them was measured. The average value of the measurement results of the three samples was calculated. The results of Invention Example 1 and Conventional Example 1 are shown in Table 1. In Comparative Example 1, the initial characteristics (emission output and forward voltage) were similar to those in Invention Example 1, but unlike Invention Example 1, in the forward direction in the life measurement of 1000 hours (room temperature, applied current: 100 mA). Comparative Example 1 was inferior in reliability to Invention Example 1 because the number of chips in which the voltage increased was increased by about 10%. In addition, this evaluation has not been performed for Comparative Example 2 in which poor joining occurred. When the emission peak wavelengths of Invention Example 1, Comparative Example 1 and Conventional Example 1 were measured with an optical fiber spectroscope, they were all in the range of 1290 nm to 1310 nm.

From the above results, in Invention Example 1 satisfying the conditions of the present invention, the light emission output could be increased and the forward voltage could be improved as compared with the conventional example. In Comparative Example 1, bonding was possible as in Invention Example 1, but the reliability of the forward voltage was deteriorated. It is considered that this is because easily diffused elements such as Si diffused from the bonded metal to the contact portion.

<Reference evaluation: Observation of voids>
For Invention Example 1, a TEM cross-sectional view was obtained to confirm the formation of voids. FIG. 7A shows a cross-sectional view of the TEM. Here, in order to clarify the configuration, a part of the reference numerals used in FIGS. 1 to 5 is attached in FIG. 7 (A). In this reference evaluation, the reference numerals used in the embodiments will be used for explanation. The inside of the wavy line portion in the schematic of FIG. 7 (B) corresponds to the TEM cross-sectional view of FIG. 7 (A). However, in the TEM cross-sectional view shown in FIG. 7A, the boundary between the metal materials cannot be observed, so that the ohmic metal portion 43, the metal reflecting layer 60, and the metal bonding layer 70 appear to be continuous. As shown in FIG. 7B, the void V in FIG. 7A is one in which one convex portion in the shape of an outer ring and about half of the concave portion in the shape of a caldera are observed. The position indicated by the width W corresponds to the exposed portion E3 formed in the fifth step, and is a gap between the dielectric layer 50 and the contact portion 40 being separated from each other. It can be confirmed that the void V is formed and that the metal reflective layer 60 and the metal bonding layer 70 are satisfactorily bonded in a region other than the void V. It is also confirmed that the gap V is located in the direction in which the contact portion 40 and the gap are opposed to the conductive support substrate 80. Further, it is confirmed that the convex portion of the dielectric layer 50 and the void V is trapezoidal, and both have an inclined hem portion.

According to the present invention, it is possible to provide a method for manufacturing a junction-type semiconductor light-emitting device and a semiconductor light-emitting device capable of suppressing bonding defects and increasing the light emission output as compared with the conventional case. It is useful.

10 InP growth substrate 20 Etching stop layer 30 Semiconductor laminate 31 n-type clad layer 35 Active layer 35W Well layer 35B Barrier layer 37 p-type clad layer 39 p-type cap layer 40 Contact part 41 (41a) p-type contact layer 43 Ohmic Metal part 50 Dielectric layer 60 Metal reflective layer 70 Metal bonding layer 80 Conductive support substrate 100, 100'Semiconductor light emitting element 91 Back electrode 93 Top electrode E1 Exposed area E2 Exposed surface E3 Exposed part V Void

Claims (13)

The first step of forming a semiconductor laminate in which a plurality of InGaAsP-based III-V compound semiconductor layers containing at least In and P are laminated on an InP growth substrate, and
The second step of forming a contact layer made of a group III-V compound semiconductor on the semiconductor laminate, and
A third step of forming an ohmic metal portion on a part of the contact layer and leaving an exposed region on the surface of the contact layer.
The contact layer in the exposed region is removed until the surface of the semiconductor laminate is exposed to form a contact portion composed of the ohmic metal portion and the contact layer, and the exposed surface of the semiconductor laminate is formed. 4 steps and
A fifth step of forming a dielectric layer on a part of the exposed surface of the semiconductor laminate and making the periphery of the contact portion an exposed portion.
A sixth step of forming a metal reflective layer containing Au as a main component on the dielectric layer, the exposed portion, and the contact portion.
The seventh step of joining the conductive support substrate provided with the metal bonding layer on the surface to the metal reflecting layer via the metal bonding layer, and the seventh step.
It has an eighth step of removing the InP growth substrate.
In the fifth step, the thickness of the dielectric layer is formed to be larger than the thickness of the contact portion.
By the bonding in the seventh step, a gap is formed between the metal bonding layer and the metal reflecting layer, and the gap is located in a direction in which the contact portion and the exposed portion face the conductive support substrate. ,
The outer shape of the gap has a concave portion at the center and a convex portion at the peripheral portion.

A semiconductor having an emission wavelength in the near infrared region of 1000 to 2200 nm , characterized in that the difference between the thickness of the dielectric layer formed in the fifth step and the thickness of the contact portion is 10 nm or more and 100 nm or less. A method for manufacturing a light emitting element. The method for manufacturing a semiconductor light emitting device according to claim 1, wherein the conductive support substrate is a conductive Si substrate. The method for manufacturing a semiconductor light emitting device according to claim 1 or 2, wherein the contact area ratio of the dielectric layer in contact with the semiconductor laminate is 80% or more and 95% or less. The semiconductor laminate includes an n-type clad layer, an active layer, and a p-type clad layer in this order, and the n-type clad layer, the active layer, and the p-type clad layer contain at least In and P. The method for manufacturing a semiconductor light emitting device according to any one of claims 1 to 3, which is a layer made of a system III-V compound semiconductor. The method for manufacturing a semiconductor light emitting device according to claim 4, wherein the semiconductor laminate has a double heterostructure or a multiple quantum well structure. The method for manufacturing a semiconductor light emitting device according to any one of claims 1 to 5, wherein the dielectric layer is made of SiO _2. Conductive support substrate and
A metal bonding layer provided on the surface of the conductive support substrate and
A metal reflective layer provided on the metal bonding layer, which partially contacts the metal bonding layer and covers the main surface of the metal bonding layer.
The voids provided between the metal bonding layer and the metal reflecting layer,
A semiconductor laminate provided on the metal reflective layer, which is formed by laminating a plurality of InGaAsP-based III-V compound semiconductor layers containing at least In and P.
It has a dielectric layer and a contact portion provided apart and in parallel between the metal reflective layer and the semiconductor laminate.
The main component of the metal reflective layer is Au.
In the gap where the dielectric layer and the contact portion are separated, the metal reflective layer and the semiconductor laminate come into contact with each other.
The gap is located in a direction in which the contact portion and the gap face the conductive support substrate.
The outer shape of the gap has a concave portion at the center and a convex portion at the peripheral portion.
A semiconductor light emitting device having an emission wavelength in the near infrared region of 1000 to 2200 nm, wherein the difference between the thickness of the dielectric layer and the thickness of the contact portion is 10 nm or more and 100 nm or less. The semiconductor light emitting device according to claim 7, wherein the conductive support substrate is a conductive Si substrate. The semiconductor light emitting device according to claim 7 or 8, wherein the thickness of the dielectric layer is larger than the thickness of the contact portion. The semiconductor light emitting device according to any one of claims 7 to 9, wherein the contact area ratio of the dielectric layer in contact with the semiconductor laminate is 80% or more and 95% or less. The semiconductor laminate includes an n-type clad layer, an active layer, and a p-type clad layer in this order, and the n-type clad layer, the active layer, and the p-type clad layer contain at least In and P. The semiconductor light emitting device according to any one of claims 7 to 10, which is a layer made of a system III-V compound semiconductor. The semiconductor light emitting device according to claim 11, wherein the semiconductor laminate has a double heterostructure or a multiple quantum well structure. The semiconductor light emitting device according to any one of claims 7 to 12, wherein the dielectric layer is made of SiO _2.

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