JP6962945B2 - Power semiconductor module and power converter using it - Google Patents

Description

The present invention relates to a power semiconductor module and a power conversion device using the same.

The power conversion device has functions such as AC-DC conversion of electric power, DC-AC conversion, frequency conversion of AC power, and voltage conversion of DC power. In order to fulfill such a conversion function, the power conversion device includes a power conversion circuit that converts power by ON / OFF operation of a power semiconductor module having a switching function.

In a power semiconductor module used in a power conversion device, generally, an insulating substrate having a wiring pattern formed on a metal base for heat dissipation is joined with solder or the like, and a plurality of switches are switched on the wiring pattern of the insulating substrate. It is configured by connecting elements (semiconductor elements) in parallel.

There is a limit to the size of the insulating substrate because the problem of warpage due to heat occurs when the size is increased. Therefore, in the power semiconductor module for high power, the current rating is increased by further connecting the insulating substrates on which a plurality of switching elements (semiconductor elements) are mounted in parallel.

As a background technology in this technical field, for example, there is a technology such as Patent Document 1. Patent Document 1 proposes "a method of electrically connecting the main electrodes of a switching element with a conductor member as a countermeasure against LC resonance between the capacitance of a switching element connected in parallel in a 1in1 module and the wiring inductance". Here, the 1in1 module is a module in which one switching element or one switching element connected in antiparallel and one diode are mounted in one power main conductor module.

On the other hand, in order to further reduce the size of the power conversion circuit, for example, there is an increasing demand for a 2in1 module as disclosed in Patent Document 2. The 2in1 module constitutes a half-bridge circuit with one module, in which two insulating substrates are connected in series inside the module, one of which is an upper arm and the other of which is a lower arm.

Japanese Patent No. 5637944 Japanese Unexamined Patent Publication No. 2009-278772

A 2in1 module as in Patent Document 2 has advantages such as miniaturization and low inductance because the wiring distance between the upper and lower arms can be shortened as compared with the 1in1 module.

However, when the inductance between the upper and lower arms becomes smaller, a resonance current Ir due to LC resonance between the upper and lower arms is likely to be generated, and when the resonance current Ir flows through the gate wiring, gate voltage vibration is generated. This gate voltage vibration can be suppressed by strengthening the damping resistance by increasing the built-in gate resistance value of the switching element, but increasing the built-in gate resistance value slows down the switching speed, and as a result, there is a problem that the switching loss increases.

Therefore, an object of the present invention is a power semiconductor module capable of suppressing gate voltage vibration due to LC resonance between upper and lower arms and reducing loss in a 2in1 power semiconductor module constituting a half-bridge circuit, and a power using the power semiconductor module. The purpose is to provide a conversion device.

In order to solve the above problems, the present invention is mounted on a first insulating substrate, a first switching element including a first main electrode, a second main electrode and a gate electrode, and a second insulating substrate. A second switching element mounted on top and having a third main electrode, a fourth main electrode and a gate electrode, and a fifth main electrode and a sixth main electrode mounted on a third insulating substrate. A third switching element having a gate electrode, a fourth switching element mounted on a fourth insulating substrate and having a seventh main electrode, an eighth main electrode, and a gate electrode, and the first main electrode. A first main terminal electrically connected to the second main electrode, a second main terminal electrically connected to the second main electrode, and a third main terminal electrically connected to the third main electrode. The main terminal, the fourth main terminal electrically connected to the fourth main electrode, the fifth main terminal electrically connected to the fifth main electrode, and the seventh main electrode The sixth main terminal electrically connected to the first wiring pattern electrically connected to the gate electrode of the first switching element, and the gate electrode of the second switching element electrically connected to the first wiring pattern. The second wiring pattern connected, the third wiring pattern electrically connected to the gate electrode of the third switching element, and the third wiring pattern electrically connected to the gate electrode of the fourth switching element. The fourth wiring pattern, the first conductor that electrically connects the gate electrode of the first switching element and the first wiring pattern, the gate electrode of the second switching element, and the second wiring pattern. To the second conductor that electrically connects the third conductor, the gate electrode of the third switching element, the third conductor that electrically connects the third wiring pattern, and the gate electrode of the fourth switching element. A fourth conductor that electrically connects the fourth wiring pattern, a fifth wiring pattern that is electrically connected to the second main electrode, and an electrically connected fourth main electrode. A sixth wiring pattern, a seventh wiring pattern electrically connected to the sixth main electrode, an eighth wiring pattern electrically connected to the eighth main electrode, and the eighth wiring pattern. A fifth conductor that electrically connects the second main electrode and the fifth wiring pattern, a sixth conductor that electrically connects the fourth main electrode and the sixth wiring pattern, and the sixth conductor. A seventh conductor that electrically connects the sixth main electrode and the seventh wiring pattern,
An eighth conductor that electrically connects the eighth main electrode and the eighth wiring pattern, and a first auxiliary terminal that is electrically connected to the first wiring pattern and the second wiring pattern. And the second auxiliary terminal electrically connected to the third wiring pattern and the fourth wiring pattern, and the fifth wiring pattern and the sixth wiring pattern electrically connected to the fifth wiring pattern. The third auxiliary terminal, the fourth auxiliary terminal electrically connected to the seventh wiring pattern and the eighth wiring pattern, and the first main electrode and the sixth main electrode are electrically connected. In a power semiconductor module including a ninth conductor to be connected and a tenth conductor for electrically connecting the third main electrode and the eighth main electrode, the first main electrode and the ninth main electrode are provided. Between the impedance value between the three main electrodes, the impedance value between the fifth main electrode and the seventh main electrode, and the sixth main electrode and the eighth main electrode. Among the impedance values, the impedance value between the second main electrode and the fourth main electrode is larger than the minimum impedance value.

Further, the present invention is a power conversion device characterized in that the above power semiconductor module is mounted.

According to the present invention, in a 2in1 power semiconductor module constituting a half-bridge circuit, it is possible to suppress gate voltage vibration due to LC resonance between upper and lower arms and reduce loss at the same time.

This makes it possible to provide a highly efficient power conversion device.

Issues, configurations and effects other than those described above will be clarified by the description of the following embodiments.

Top view showing the structure of the first embodiment of the present invention Equivalent circuit diagram of the first embodiment of the present invention and connection example with an external circuit The figure which showed the LC resonance current Ir path Plan view showing the configuration of the prior art Equivalent circuit diagram of power semiconductor module by conventional technology The figure which compared the simulation result of the waveform at the time of the 2nd turn-on in the 1st Embodiment of this invention with a prior art Top view showing the structure of the 2nd Embodiment of this invention Top view showing the structure of the third embodiment of the present invention. The figure which showed the equivalent circuit diagram of the 3rd Embodiment of this invention and the LC resonance current Ir path. The figure which compared the simulation result of the waveform at the time of the 2nd turn-on in 3rd Embodiment of this invention with the prior art. Top view showing the structure of the 4th Embodiment of this invention Equivalent circuit diagram of the fourth embodiment of the present invention and connection example with an external circuit Top view showing the structure of the fifth embodiment of the present invention. Equivalent circuit diagram of the fifth embodiment of the present invention and connection example with an external circuit Top view showing the structure of the sixth embodiment of the present invention.

Hereinafter, examples of the present invention will be described with reference to the drawings. In each drawing, the same components are designated by the same reference numerals, and the detailed description of overlapping portions will be omitted. Further, the present invention is not limited to the following embodiments, and various modifications and applications are included in the technical concept of the present invention.

The first embodiment of the present invention will be described in detail with reference to FIGS. 1 to 6. First, the configuration of the first embodiment of the present invention will be described with reference to FIG. Next, FIG. 2 describes an equivalent circuit diagram of the first embodiment of the present invention and its operation (action). Then, FIG. 3 describes the effect of suppressing the gate voltage vibration according to the first embodiment of the present invention. Further, FIGS. 4 and 5 describe a configuration in which measures against gate voltage vibration are taken equally (evenly) with respect to the gate wiring of the upper and lower arms and an equivalent circuit thereof, and are shown in FIGS. 4 and 5 in FIG. The gate voltage waveforms of the configuration and the first embodiment of the present invention are compared.

FIG. 1 is a plan view showing the configuration of the first embodiment of the present invention. The configuration of the first embodiment of the present invention will be described with reference to FIG. In the first embodiment, four first to fourth insulating substrates (1, 2, 3, 4) and two first and second insulator substrates (98, 99) are placed on the heat-dissipating metal plate 100. ) Is placed. Then, the resin housing 101 surrounds the portion other than the heat-dissipating metal plate portion on the bottom surface. The inside of the power semiconductor module surrounded by the resin housing 101 and the heat-dissipating metal plate 100 is filled with an insulating material such as gel or hard resin to maintain the internal insulating property.

On the first to fourth insulating substrates (1, 2, 3, 4), the first to fourth switching elements (5, 6, 7, 8) and the first to fourth diodes (72, 73, 74, 75) are installed one by one. The switching element includes two main electrodes and one gate electrode. The diode has a cathode electrode and an anode electrode.

The first main electrode, the third main electrode, the fifth main electrode, and the seventh main electrode of the first to fourth switching elements (5, 6, 7, 8) are solder-bonded or metal-sinter-bonded. It is electrically connected to the first main electrode wiring pattern 9, the third main electrode wiring pattern 11, the fifth main electrode wiring pattern 13, and the seventh main electrode wiring pattern 15, respectively. ..

Including the wiring pattern described below, a conductive material such as copper or aluminum is used as the material of the wiring pattern. In addition, the "connection" described below means an electrical connection unless otherwise specified.

Similarly, the cathode electrodes of the first to fourth diodes (72, 73, 74, 75) are for the first main electrode wiring pattern 9, the third main electrode wiring pattern 11, and the fifth main electrode, respectively. It is connected to the wiring pattern 13 and the wiring pattern 15 for the seventh main electrode.

The second main electrode 10, the fourth main electrode 12, the sixth main electrode 14, and the eighth main electrode 16 of the first to fourth switching elements (5, 6, 7, 8) are from the first. It is connected to the anode electrode (76, 77, 78, 79) of the fourth diode by wiring (80, 81, 82, 83). That is, in each insulating substrate, the switching element and the diode are connected in parallel.

Including the wiring and conductor described below, aluminum wire, copper wire, copper lead and the like are used for the wiring and conductor. Further, as the switching element, Si-IGBT (Insulated Gate Bipolar Transistor), SiC-MOSFET (Metal Oxide Semiconductor Field Effect Transistor), or the like is used. As the diode, a Si-pn diode, a SiC-SBD (Schottky Barrier Diode) or the like is used.

The gate electrodes (17, 18, 19, 20) of the first to fourth switching elements are formed by the first to fourth conductors (43, 44, 45, 46) and the first to fourth wiring patterns (27). , 28, 29, 30).

The first wiring pattern 27 and the second wiring pattern 28 are connected to the first lower arm common wiring pattern 35 by the wiring 56 and the wiring 57. The first lower arm common wiring pattern 35 is connected to the first auxiliary terminal 39 by the wiring 64 and is pulled out to the outside of the resin housing 101.

Similarly, the third wiring pattern 29 and the fourth wiring pattern 30 are also connected to the first upper arm common wiring pattern 37 by the wiring 58 and the wiring 59. The first upper arm common wiring pattern 37 is also connected to the second auxiliary terminal 40 by the wiring 65 and is pulled out to the outside of the resin housing 101.

The second main electrode 10, the fourth main electrode 12, the sixth main electrode 14, and the eighth main electrode 16 of the first to fourth switching elements are the fifth to eighth conductors (47, 48, By 49,50), it is electrically connected to the fifth to eighth wiring patterns (31,32,33,34).

The fifth wiring pattern 31 and the sixth wiring pattern 32 are electrically connected to the second lower arm common wiring pattern 36 by the wiring 60 and the wiring 61. The second lower arm common wiring pattern 36 is connected to the third auxiliary terminal 41 by the wiring 66 and is pulled out to the outside of the resin housing 101.

Similarly, the seventh wiring pattern 33 and the eighth wiring pattern 34 are electrically connected to the second upper arm common wiring pattern 38 by the wiring 62 and the wiring 63. The second upper arm common wiring pattern 38 is also connected to the fourth auxiliary terminal 42 by the wiring 67 and is pulled out to the outside of the resin housing 101.

The fifth main electrode wiring pattern 13 and the seventh main electrode wiring pattern 15 are connected to the fifth main terminal 25 and the sixth main terminal 26 by the wiring 70 and the wiring 71, respectively, and the resin housing 101. It is pulled out to the outside of.

The wiring pattern 9 for the first main electrode and the wiring pattern 11 for the third main electrode are the joint surface 114 and the joint surface 115, respectively, and are connected to the first main terminal 21 and the third main terminal 23 by ultrasonic metal bonding. And is pulled out to the outside of the resin housing 101.

The second main electrode 10 and the fourth main electrode 12 are connected to the second main terminal 22 and the fourth main terminal 24 by the wiring 68 and the wiring 69, respectively, and are pulled out to the outside of the resin housing 101.

The principle will be described later with reference to FIG. 3, but in the first embodiment, in order to suppress the gate voltage vibration during switching, the sixth main electrode 14 and the eighth main electrode 16 are connected by the twelfth conductor 54. Connecting.

FIG. 2 shows an equivalent circuit diagram of the first embodiment of the present invention and an example of connection with an external circuit. First, the configuration of the circuit of FIG. 2 will be described, and then an operation example of the first embodiment of the present invention will be described with reference to FIG. Since the present invention is intended for a high frequency phenomenon during switching, wiring, conductors, and wiring patterns are all represented by inductance circuit symbols in the equivalent circuit diagram of FIG.

In the power semiconductor module according to the present invention, between the fifth main terminal 25 and the sixth main terminal 26, between the first main terminal 21 and the third main terminal 23, and between the second main terminal 22 and the fourth main terminal 22. It is assumed that the main terminals 24 are connected by external wiring (87,88,94,95,91,92) and used.

That is, the first switching element 5 and the first diode 72 mounted on the first insulating substrate 1 and the second switching element 6 and the second diode 73 mounted on the second insulating substrate 2 are in parallel. Be connected. Further, the third switching element 7 and the third diode 74 mounted on the third insulating substrate 3 and the fourth switching element 8 and the fourth diode 75 mounted on the fourth insulating substrate 4 are also in parallel. Be connected.

By connecting a plurality of switching elements and diodes in parallel, the rated current capacity of the power semiconductor module can be increased. However, as described above, since the size of the insulating substrate is limited due to the problem of warpage due to heat, in the present invention, the rated current capacity is increased by connecting the insulating substrate on which the switching element and the diode are mounted in parallel. There is.

A parallel circuit of switching elements and diodes mounted on the first insulating substrate 1 and the second insulating substrate 2, and a parallel circuit of switching elements and diodes mounted on the third insulating substrate 3 and the fourth insulating substrate 4. Is connected in series by a ninth conductor 51 and a tenth conductor 52.

As described above, in the present invention, two switching elements are connected in series inside the power semiconductor module, and the high potential terminal (fifth main terminal 25 and the sixth main terminal 26) and the intermediate potential terminal (first main terminal) are connected in series. It is a 2in1 module 144 in which a half-bridge circuit is formed by providing three potential terminals (21 and a third main terminal 23) and a low potential terminal (second main terminal 22 and a fourth main terminal 24).

As described above, the 2in1 module has advantages such as miniaturization and low inductance because the wiring connection between the upper and lower arms can be shortened as compared with the 1in1 module.

Further, although not shown, the high-potential terminals (fifth main terminal 25 and the sixth main terminal 26) and the low-potential terminals (second main terminal 22 and the fourth main terminal 22) in which the polarities of the flowing currents are opposite are reversed. By arranging the main terminals 24) of the above in parallel and close to each other, the mutual inductance between the two can be increased. As a result, the wiring inductance of the high potential terminal (fifth main terminal 25 and the sixth main terminal 26) and the low potential terminal (second main terminal 22 and the fourth main terminal 24) can be reduced, and the 2in1 module can be used. The wiring inductance can be further reduced.

A third switching element 7, a third switching element 7, connected between a high potential terminal (fifth main terminal 25 and a sixth main terminal 26) and an intermediate potential terminal (first main terminal 21 and third main terminal 23). The fourth switching element 8, the third diode 74 and the fourth diode 75 are attached to the upper arm, the intermediate potential terminal (first main terminal 21 and the third main terminal 23) and the low potential terminal (second main terminal 22). The first switching element 5, the second switching element 6, the first diode 72, and the second diode 73 connected between the and the fourth main terminal 24) are referred to as lower arms.

In FIG. 2, as an example, wiring (91, The configuration of the upper arm drive half-bridge circuit in which the inductance load 96 is connected via 92, 94, 95) is shown.

Wiring (87,88,89,91) between the high-potential terminal (fifth main terminal 25 and sixth main terminal 26) and the low-potential terminal (second main terminal 22 and fourth main terminal 24). , 92, 93), and the capacitor 85 is connected. Further, a DC power supply 84 is connected to the capacitor 85 via the wiring 86 and the wiring 90.

Subsequently, with reference to FIGS. 1 and 2, the operation (action) of the first embodiment of the present invention will be described by taking as an example a switching operation order that is repeated when mounted on a power conversion circuit. First, in the initial state, all the switching elements of the upper and lower arms are in the OFF state. The third switching element 7 and the fourth switching element 8 of the upper arm are connected to a common gate drive power supply 102 via the second auxiliary terminal 40 and the fourth auxiliary terminal 42 in order to operate in parallel. Similarly, in order to operate the first switching element 5 and the second switching element 6 in parallel with the lower arm, the common gate drive power supply 102 is connected to the common gate drive power supply 102 via the first auxiliary terminal 39 and the third auxiliary terminal 41. Be connected.

By applying a negative voltage from the gate drive power supply 102 to the auxiliary terminal, the switching element can be controlled to the OFF state. For example, when the switching element is an IGBT, about -15V is applied to the auxiliary terminal when the switching element is OFF. In the circuit of FIG. 2, when all the switching elements of the upper and lower arms are OFF, the DC power supply voltage Vcc is applied to the upper arm, and the DC power supply voltage Vcc is not applied to the inductance load 96, so that no current flows.

Next, the switching element of the upper arm is turned on (first turn-on) from the initial state. By applying a positive voltage from the gate drive power supply 102 to the auxiliary terminal, the switching element can be controlled to the ON state. For example, when the switching element is an IGBT, a gate voltage of about + 15V is applied to the auxiliary terminal when it is turned on.

When the switching element of the upper arm is turned on, the DC power supply voltage Vcc is applied to the inductance load 96 having an inductance value of Lload [H], and the current increasing with the inclination of Vcc / Lload is conducted through the switching element of the upper arm. It flows through the load 96.

When the switching element of the upper arm is changed from the ON state to the OFF state, the current Ic_H of the switching element of the upper arm is cut off, and the current is commutated to the path between the inductance load 96 and the diode of the lower arm. From there, when the switching element of the upper arm is changed from the OFF state to the ON state (second turn-on), the current is commutated to the path between the switching element of the upper arm and the inductance load 96.

The principle of generating gate voltage vibration will be described by taking this second turn-on time as an example. Ideally, the current flows evenly through the third switching element 7 and the fourth switching element 8 of the upper arm at the time of the second turn-on. However, if the currents of the third switching element 7 and the fourth switching element 8 become uneven due to variations in characteristics between switching elements, variations in gate wiring impedance, etc., a potential difference occurs between the insulating substrates connected in parallel, resulting in a potential difference. Current flows in the direction of reducing. At this time, LC resonance may occur between the switching element of the lower arm, the depletion layer capacitance of the diode, and the wiring inductance of the circuit. In particular, the LC resonance is likely to occur in a SiC (silicon carbide) device having a larger depletion layer capacity than a Si (silicon) device.

FIG. 3 shows the LC resonance current Ir path. As shown in FIG. 3, a resonance current Ir of opposite phase flows with the switching element of the lower arm and the diode as a boundary. At this time, the wiring between 3GL-4GL, which is the gate wiring of the upper arm on the drive side (3GL: wiring from the gate electrode 19 of the third switching element 7 to the connection point between the first upper arm common wiring pattern 37 and the wiring 65, 4GL: Wiring from the gate electrode 20 of the fourth switching element 8 to the connection point of the first upper arm common wiring pattern 37 and the wiring 65) and between 3EL-4EL (3EL: sixth main electrode 14 to second Resonant current Ir flows through the wiring to the connection point between the upper arm common wiring pattern 38 and the wiring 67, 4EL: wiring from the eighth main electrode 16 to the connection point between the second upper arm common wiring pattern 38 and the wiring 67). Then, the gate voltage Vge_H of the upper arm vibrates.

Since the upper arm switching element in the ON state operates as a current source controlled by the gate voltage, when the upper arm gate voltage Vge_H vibrates, the current of the upper arm switching element also vibrates in synchronization with it, and between the insulating substrates connected in parallel. This leads to self-excited vibration in which the potential difference at is further expanded. When self-excited vibration is reached, the upper arm gate voltage Vge_H vibration further increases, and the gate oxide film may cause dielectric breakdown.

In addition, the upper arm gate voltage whose reference potential is the midpoint potential, which tends to fluctuate depending on the operating state, is more likely to vibrate than the lower arm gate voltage. ..

Therefore, in the first embodiment of the present invention, the sixth main electrode 14 and the eighth main electrode 16 are connected by the twelfth conductor 54 in order to suppress the upper arm gate voltage vibration due to the self-excited vibration. do. The wiring inductance of the twelfth conductor 54 is smaller than the wiring inductance between 3GL-4GL, which is the gate wiring of the upper arm, and the wiring inductance between 3EL-4EL. This also applies to the wiring inductance of the thirteenth conductor 55, which will be described later. Since the twelfth conductor 54 is connected in parallel with the gate wiring of the upper arm, it has the effect of bypassing the resonance current Ir and reducing the resonance current Ir flowing through the gate wiring of the upper arm.

Therefore, by connecting the twelfth conductor 54, it is possible to suppress the upper arm gate voltage vibration due to self-excited vibration. Further, even if a conductor is connected between the fifth main electrode and the seventh main electrode or between the first main electrode and the third main electrode, which will be described in detail in Example 2, the same as in Example 1. A similar effect can be obtained.

On the other hand, as shown in the plan view of FIG. 4 and the equivalent circuit diagram of FIG. 5, in addition to connecting the sixth main electrode 14 and the eighth main electrode 16 with the twelfth conductor 54, the second It is also conceivable to connect the main electrode 10 and the fourth main electrode 12 with the fourteenth conductor 105 and take measures against the gate voltage vibration equally (evenly) with respect to the gate wiring of the upper and lower arms. However, in the 2in1 module having a low internal inductance, the total wiring inductance of the upper and lower arms is as small as about 10 nH, and the resonance current Ir between the upper and lower arms is likely to occur due to the above-mentioned LC resonance. Therefore, the configuration shown in FIGS. 4 and 5 was insufficient to suppress the gate voltage vibration.

Therefore, in the present invention, the configuration is such that the suppression of the upper arm gate voltage vibration, which is a problem, is prioritized and countermeasures are taken. Specifically, the twelfth conductor 54 is connected, but the fourteenth conductor 105 is not connected.

The reason will be explained below. As shown in FIG. 3, since the LC resonance current Ir flows in opposite phases with the switching element of the lower arm and the diode as the boundary, the second main electrode 10 and the fourth main electrode 12 are connected to the fourteenth conductor 105. The path of 3GL-4GL, which is the gate wiring of the upper arm, and the path of 3EL-4EL are not in parallel. Therefore, the fourteenth conductor 105 has no effect of bypassing the resonance current Ir with respect to the gate wiring of the upper arm.

On the other hand, the impedance of the resonance path is reduced by the fourteenth conductor 105, and the resonance current Ir flowing through the gate wiring of the upper arm is increased. Therefore, it is better not to connect the fourteenth conductor 105 in order to suppress the voltage vibration of the upper arm gate.

When the configuration of the present invention is described by the magnitude relationship of the impedance values between the main electrodes, the impedance values between the first main electrode and the third main electrode, and the fifth and seventh main electrodes Of the impedance value between the sixth main electrode 14 and the eighth main electrode 16, the second main electrode 10 and the fourth main electrode 12 are more than the minimum impedance value. It can be said that it is better to increase the impedance value between.

Further, the impedance values between the second main electrode 10 and the fourth main electrode 12 are the sixth main electrode 14 to the seventh conductor 49, the seventh wiring pattern 33, and the seventh wiring pattern 33. The impedance of the path that passes through the connection point between the wiring between the eighth wiring pattern 34 and the fourth auxiliary terminal 42, the eighth wiring pattern 34, and the eighth conductor 50, and reaches the eighth main electrode 16. It should be greater than or equal to the value.

At this time, each impedance value refers to the impedance value in a state where the external wiring (87,88,91,92,94,95) is not connected. Further, the impedance value refers to an absolute impedance value, that is, a value calculated from the square root of the sum of squares of the real part and the imaginary part. The impedance value refers to the impedance value at the LC resonance frequency.

The impedance values between the first main electrode and the third main electrode are the ninth conductor 51, the tenth conductor 52, the first conductor 43, the second conductor 44, the fifth conductor 47, and the fifth conductor. With the six conductors 48 cut, the impedance value between the first main electrode wiring pattern 9 and the third main electrode wiring pattern 11 is measured with a measuring instrument such as an impedance analyzer or LCR meter, or a calculation formula. It can be obtained by calculating with or a calculation tool.

The impedance values between the fifth and seventh main electrodes are the ninth conductor 51, the tenth conductor 52, the third conductor 45, the fourth conductor 46, the seventh conductor 49, and the seventh conductor. With the eighth conductor 50 cut, the impedance value between the fifth main electrode wiring pattern 13 and the seventh main electrode wiring pattern 15 is measured with a measuring instrument such as an impedance analyzer or LCR meter, or a calculation formula. It can be obtained by calculating with or a calculation tool.

The impedance value between the sixth main electrode 14 and the eighth main electrode 16 is the state in which the ninth conductor 51, the tenth conductor 52, the third conductor 45, and the fourth conductor 46 are cut. It can be obtained by measuring the impedance value between the sixth main electrode 14 and the eighth main electrode 16 with a measuring instrument such as an impedance analyzer or an LCR meter, or by calculating with a calculation formula or a calculation tool.

The impedance value between the second main electrode 10 and the fourth main electrode 12 is the state in which the ninth conductor 51, the tenth conductor 52, the first conductor 43, and the second conductor 44 are cut. It can be obtained by measuring the impedance value between the second main electrode 10 and the fourth main electrode 12 with a measuring instrument such as an impedance analyzer or an LCR meter, or by calculating with a calculation formula or a calculation tool.

A connection point between the sixth main electrode 14 to the seventh conductor 49, the seventh wiring pattern 33, the wiring between the seventh wiring pattern 33 and the eighth wiring pattern 34, and the fourth auxiliary terminal 42. In the measurement or calculation of the impedance value of the path through the eighth wiring pattern 34 and the eighth conductor 50 to the eighth main electrode 16, first, the ninth conductor 51, the tenth conductor 52, and the ninth conductor The third conductor 45 and the fourth conductor 46 are cut. Next, the wiring between the sixth main electrode 14 to the seventh conductor 49, the seventh wiring pattern 33, the seventh wiring pattern 33 and the eighth wiring pattern 34, and the fourth auxiliary terminal 42 The wiring connecting the sixth main electrode 14 and the eighth main electrode 16 other than the path leading to the eighth main electrode 16 through the connection point, the eighth wiring pattern 34, and the eighth conductor 50 is cut. .. After that, the impedance value between the sixth main electrode 14 and the eighth main electrode 16 can be obtained by measuring with a measuring instrument such as an impedance analyzer or an LCR meter, or by calculating with a calculation formula or a calculation tool.

FIG. 6 shows a diagram comparing the configuration shown in FIGS. 4 and 5 with the simulation result of the waveform at the time of the second turn-on in the first embodiment of the present invention shown in FIGS. 1 and 2. It can be seen that in the prior art (configurations shown in FIGS. 4 and 5), the upper arm gate voltage vibration Vge_H due to self-excited vibration is large, and the upper arm switching element current Ic_H and the upper arm switching element voltage Vce_H also vibrate significantly. ..

On the other hand, in the first embodiment of the present invention, it can be seen that the upper arm gate voltage vibration Vge_H due to self-excited vibration can be suppressed, and the vibration of the upper arm switching element current Ic_H and the upper arm switching element voltage Vce_H can also be suppressed.

Here, the suppression of the gate voltage vibration means that the gate voltage is suppressed within the range of + 20V to -20V even if the vibration is superimposed on the gate voltage in the case of the IGBT.

It should be noted that the twelfth conductor 54 is preferably realized by a plurality of short-distance conductors because the bypass effect of the resonance current Ir is higher when the impedance is lowered as much as possible. Further, the twelfth conductor 54 may be a conductor capable of electrically connecting electrodes such as an aluminum wire, a copper wire, and a copper lead.

The configuration of the second embodiment of the present invention will be described with reference to FIG. 7. FIG. 7 is a plan view showing the configuration of the second embodiment of the present invention. The only difference between FIGS. 1 and 7 is the presence or absence of the twelfth conductor 54 and the thirteenth conductor 55. In the second embodiment of the present invention, the wiring pattern 9 for the first main electrode and the wiring pattern 11 for the third main electrode are connected by the thirteenth conductor 55. The potentials of the first main electrode wiring pattern 9 and the third main electrode wiring pattern 11 are the midpoint potentials of the 2in1 module of the present invention, similarly to the sixth main electrode 14 and the eighth main electrode 16. .. Therefore, even with the configuration of FIG. 7, it is possible to obtain the same gate voltage vibration suppression effect as the configuration in which the sixth main electrode 14 and the eighth main electrode 16 of FIG. 1 are connected by the twelfth conductor 54.

Since the distance between the main electrodes to be connected is shorter in the second embodiment as compared with the first embodiment, the wiring inductance of the conductor connecting the main electrodes can be reduced. Further, since the area of the main electrode to be connected is also larger in the second embodiment than in the first embodiment, it is easy to increase the number of parallel conductors and the thickness of the conductors to further reduce the wiring inductance of the conductors. As described above, when the impedance of the conductor connecting the main electrodes is made as low as possible, the bypass effect of the resonance current Ir is higher.

The configuration of the third embodiment of the present invention will be described with reference to FIGS. 8 to 10. FIG. 8 is a plan view showing the configuration of the third embodiment of the present invention. The only difference between FIGS. 1 and 8 is the presence or absence of the twelfth conductor 54 and the resistor 106. In the third embodiment of the present invention, the wiring between the second main electrode 10 to the fifth conductor 47, the fifth wiring pattern 31, the fifth wiring pattern 31 and the sixth wiring pattern 32, and the third. The resistor 106 is connected between the connection point with the auxiliary terminal 41, the sixth wiring pattern 32, the sixth conductor 48, and the path to the fourth main electrode 12. The purpose of connecting the resistor 106 is to increase the impedance value between the second main electrode 10 and the fourth main electrode 12 and suppress the LC resonance current Ir.

FIG. 9 shows an equivalent circuit diagram of the third embodiment of the present invention and an LC resonance current Ir path. As shown in FIG. 6 above, when the upper arm is driven, the second main electrode 10 and the fourth main electrode 10 and the fourth main electrode are not parallel to the path between 3GL-4GL and the path between 3EL-4EL, which are the gate wirings of the upper arm. When the impedance value between the main electrodes 12 is reduced, the upper arm gate voltage vibration increases.

Therefore, in this embodiment, as shown in FIG. 8, a resistor 106 is connected between the second main electrode 10 and the fourth main electrode 12, and the impedance value is increased to increase the upper arm gate voltage. Suppress vibration. As shown in FIG. 9, since the resistor 106 is inserted into the LC resonance current Ir path, the LC resonance current Ir is reduced, and the resonance current Ir flowing through the gate wiring of the upper arm is reduced to reduce the upper arm gate voltage vibration. Can be suppressed.

FIG. 10 shows a diagram comparing the configurations shown in FIGS. 4 and 5 with the simulation results of the waveform at the time of the second turn-on in the third embodiment of the present invention. Also in the third embodiment of the present invention, as compared with the prior art (configuration shown in FIGS. 4 and 5), the upper arm gate voltage vibration Vge_H due to self-excited vibration is suppressed, and the upper arm switching element current Ic_H and It can be seen that the vibration of the upper arm switching element voltage Vce_H can also be suppressed.

The gate resistance value increased by the resistor 106 can be reduced by lowering the built-in gate resistance value of the switching element (not shown) or the external gate resistance value of the power semiconductor module without increasing the switching loss due to the insertion of the resistor 106. Gate voltage vibration can be suppressed.

Further, the second main electrode 10 and the fourth are made by inserting an inductor instead of the resistor 106 or intentionally increasing the wiring length between the fifth wiring pattern 31 and the sixth wiring pattern 32. The impedance value between the main electrodes 12 of the above may be increased.

In the third embodiment, since the conductor connecting the main electrodes is not required, it can be carried out without being affected by the mounting layout such as the switching element and the diode on the insulating substrate.

The configuration of the fourth embodiment of the present invention will be described with reference to FIGS. 11 and 12. FIG. 11 shows a plan view showing the configuration of the fourth embodiment of the present invention. The fourth embodiment of the present invention is a combination of the first embodiment and the second embodiment.

However, the number of parallel conductors 55 is increased to reduce the wiring inductance of the conductors. FIG. 11 shows an example in which three thirteenth conductors 55 are provided. Further, the twelfth conductor 54 is used to connect the sixth main electrode 14 and the eighth main electrode 16 directly, but via the wiring 107, the wiring pattern 109, the wiring pattern 110, and the wiring 108. Connected.

In terms of mounting, there is a structure between the sixth main electrode 14 and the eighth main electrode 16, and a twelfth conductor 54 is directly between the sixth main electrode 14 and the eighth main electrode 16. The configuration is based on the assumption that it cannot be connected.

FIG. 12 shows an equivalent circuit diagram of a fourth embodiment of the present invention and an example of connection with an external circuit. In the fourth embodiment of the present invention, there are two paths by the twelfth conductor 54 and the thirteenth conductor 55 in parallel with the path between 3GL-4GL and the path between 3EL-4EL, which are the gate wirings of the upper arm. Was added. As a result, the resonance current Ir flowing through the gate wiring of the arm can be further reduced and the effect of suppressing the upper arm gate voltage vibration can be enhanced as compared with the case where each conductor is connected independently.

In order to reduce the man-hours for manufacturing the power semiconductor module according to the present invention as much as possible, it is desirable to minimize the number of connecting conductors between the main electrodes. Under easy conditions, it is effective to take measures by increasing the number of connecting conductors between the main electrodes as in the fourth embodiment.

The configuration of the fifth embodiment of the present invention will be described with reference to FIGS. 13 and 14. FIG. 13 shows a plan view showing the configuration of the fifth embodiment of the present invention. The fifth embodiment of the present invention is a combination of the third embodiment and the fourth embodiment. FIG. 13 is a diagram in which a resistor 106 is added to FIG. As described above, by adding the resistor 106, the impedance value between the second main electrode 10 and the fourth main electrode 12 can be increased.

FIG. 14 shows an equivalent circuit diagram of a fifth embodiment of the present invention and an example of connection with an external circuit. By adding the resistor 106, the LC resonance current Ir is further reduced as compared with the fourth embodiment, and by reducing the resonance current Ir flowing through the gate wiring of the upper arm, the effect of suppressing the voltage vibration of the upper arm gate is suppressed. Can be enhanced.

Although the description of all combinations of the connection between the main electrodes by the conductor and the insertion of the resistor is omitted, one of the three embodiments from the first embodiment to the third embodiment will be omitted. Needless to say, the effect of suppressing the gate voltage vibration can be obtained in all the combinations in which the above is selected, the combination in which the two embodiments are selected, and the combination in which the three embodiments are selected.

FIG. 15 shows the configuration of the sixth embodiment of the present invention. A sixth embodiment of the present invention is a power conversion system (power conversion device) 152 equipped with the power semiconductor module 144 according to the present invention. In FIG. 15, a three-phase inverter is composed of three power semiconductor modules 144 according to the present invention, using the DC power supply 84 as a power source.

The midpoint potential terminal of the power semiconductor module 144 according to the present invention is connected to the motor 146, which is a load, respectively. The control device 145 is based on the information of the three-phase current (Iu, Iv, Iw) of the motor 146 detected by the current sensor (147, 148, 149) and the rotation speed (ω) of the motor 146 detected by the speed detector 150. The gate voltage value applied to the three power semiconductor modules 144 is calculated and output to the auxiliary terminals of each power semiconductor module 144.

Since the power semiconductor module 144 according to the present invention can suppress the gate voltage vibration without increasing the gate resistance value, the switching loss of the power semiconductor module can be reduced as compared with the prior art. Therefore, by mounting the power semiconductor module 144 according to the present invention on the power conversion circuit 151 of the power conversion system (power conversion device) 152, a more efficient power conversion system (power conversion device) can be configured as compared with the conventional one. be able to.

The present invention is not limited to the above-described examples, and includes various modifications. For example, the above examples have been described in detail to aid in understanding of the present invention, and are not necessarily limited to those having all the configurations described. Further, it is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. Further, it is possible to add / delete / replace a part of the configuration of each embodiment with another configuration.

1 ... 1st insulating substrate 2 ... 2nd insulating substrate 3 ... 3rd insulating substrate 4 ... 4th insulating substrate 5 ... 1st switching element 6 ... 2nd switching element 7 ... 3rd switching element 8 ... Fourth switching element 9 ... Wiring pattern for the first main conductor 10 ... Wiring pattern for the second main conductor 11 ... Wiring pattern for the third main electrode 12 ... Wiring pattern for the fourth main electrode 13 ... Wiring pattern for the fifth main electrode 14 ... 6th main conductor 15 ... Wiring pattern for 7th main conductor 16 ... 8th main conductor 17 ... Gate electrode of 1st switching element 18 ... Gate electrode of 2nd switching element 19 ... 3rd switching Element gate electrode 20 ... Fourth switching element gate electrode 21 ... First main terminal 22 ... Second main terminal 23 ... Third main terminal 24 ... Fourth main terminal 25 ... Fifth main terminal 26 ... 6th main terminal 27 ... 1st wiring pattern 28 ... 2nd wiring pattern 29 ... 3rd wiring pattern 30 ... 4th wiring pattern 31 ... 5th wiring pattern 32 ... 6th wiring pattern 33 ... Seventh wiring pattern 34 ... Eighth wiring pattern 35 ... First lower arm common wiring pattern 36 ... Second lower arm common wiring pattern 37 ... First upper arm common wiring pattern 38 ... Second upper arm common Wiring pattern 39 ... 1st auxiliary terminal 40 ... 2nd auxiliary terminal 41 ... 3rd auxiliary terminal 42 ... 4th auxiliary terminal 43 ... 1st conductor 44 ... 2nd conductor 45 ... 3rd conductor 46 ... Fourth conductor 47 ... Fifth conductor 48 ... Sixth conductor 49 ... Seventh conductor 50 ... Eighth conductor 51 ... Ninth conductor 52 ... Tenth conductor 54 ... Twelfth conductor 55 ... Ninth Thirteen conductors 56 ... First wiring between the first wiring pattern 27 and the first lower arm common wiring pattern 35 57 ... The second wiring pattern 28 and the first lower arm common wiring pattern 35 Second wiring between 58 ... First wiring between the third wiring pattern 29 and the first upper arm common wiring pattern 59 ... First wiring between the third wiring pattern 29 and the first upper arm common wiring pattern 59 ... Fourth wiring pattern 30 and the first upper arm common wiring pattern 37 Second wiring between 60 ... Fifth wiring pattern 31 and second lower arm common wiring pattern 36 First wiring 61 ... Sixth wiring pattern 32 and second lower arm common wiring Second wiring between the pattern 36 62 ... First wiring between the seventh wiring pattern 33 and the second upper arm common wiring pattern 38 63 ... Eighth wiring pattern 34 and the second upper arm Common distribution Second wiring between the wire pattern 38 64 ... Wiring between the first lower arm common wiring pattern 35 and the first auxiliary terminal 39 65 ... First upper arm common wiring pattern 37 and the second auxiliary Wiring 66 ... Wiring between the second lower arm common wiring pattern 36 and the third auxiliary terminal 41 67 ... Wiring between the second upper arm common wiring pattern 38 and the fourth auxiliary terminal 42 Wiring between 68 ... Wiring between the second main electrode 10 and the second main terminal 22 69 ... Wiring between the fourth main electrode 12 and the fourth main terminal 24 70 ... Fifth main electrode Wiring between the wiring pattern 13 and the fifth main terminal 25 71 ... Wiring between the seventh main electrode wiring pattern 15 and the sixth main terminal 26 72 ... First diode 73 ... Second Diode 74 ... Third diode 75 ... Fourth diode 76 ... First diode anode electrode 77 ... Second diode anode electrode 78 ... Third diode anode electrode 79 ... Fourth diode anode electrode 80 ... Wiring between the second main electrode 10 and the anode electrode 76 of the first diode 81 ... Wiring between the fourth main electrode 12 and the anode electrode 77 of the second diode 82 ... Sixth main electrode Wiring between 14 and the anode electrode 78 of the third diode 83 ... Wiring between the eighth main electrode 16 and the anode electrode 79 of the fourth diode 84 ... DC power supply 85 ... Condenser 86 ... DC power supply 84 First wiring between the capacitors 85 87 ... First wiring between the fifth main terminal 25 and the sixth main terminal 26 88 ... The third wiring between the fifth main terminal 25 and the sixth main terminal 26 Second wiring 89 ... In the first wiring 87 between the fifth main terminal 25 and the sixth main terminal 26 and in the second wiring 88 between the fifth main terminal 25 and the sixth main terminal 26. Wiring between the point and the capacitor 85 90 ... Second wiring between the DC power supply 84 and the capacitor 85 91 ... First wiring between the second main terminal 22 and the fourth main terminal 24 92 ... Second Second wiring 93 between the main terminal 22 and the fourth main terminal 24 ... The first wiring 91 between the second main terminal 22 and the fourth main terminal 24, the second main terminal 22, and the second Wiring between the midpoint of the second wiring 92 between the four main terminals 24 and the capacitor 85 94 ... First wiring between the first main terminal 21 and the third main terminal 23 95 ... First Second wiring between the main terminal 21 and the third main terminal 23 ... Load inductance (inductivity load)
98 ... 1st insulator board 99 ... 2nd insulator board 100 ... Metal plate for heat dissipation 101 ... Resin housing 102 ... Gate drive power supply 103 ... Gate wiring inductance 105 ... 14th conductor 106 ... Resistor 107 ... Wiring 108 ... Wiring 109 ... Wiring pattern 110 ... Wiring pattern 111 ... Capacitance between the first main electrode and the second main electrode 10 112 ... Between the first main electrode and the gate electrode 17 of the first switching element Capacitance 113 ... Capacitance between the gate electrode 17 of the first switching element and the second main electrode 10 114 ... Joint surface 115 ... Joint surface 121 ... Between the third main electrode and the fourth main electrode 12. Capacitance 122 ... Capacitance between the third main electrode and the gate electrode 18 of the second switching element 123 ... Capacitance between the gate electrode 19 of the third switching element and the fourth main electrode 12 131 ... Capacitance between the fifth main electrode and the sixth main electrode 14 132 ... Capacitance between the fifth main electrode and the gate electrode 19 of the third switching element 133 ... The gate electrode 19 of the third switching element Capacitance between the seventh main electrode 14 and the sixth main electrode 141 ... Capacitance between the seventh main electrode and the eighth main electrode 16 142 ... Between the seventh main electrode and the gate electrode 20 of the fourth switching element Capacitance 143 ... Capacitance between the gate electrode 20 of the fourth switching element and the eighth main electrode 16 144 ... Power semiconductor module (2in1 module) according to the present invention
145 ... Control device 146 ... Motor 147 ... Current sensor 148 ... Current sensor 149 ... Current sensor 150 ... Speed detector 151 ... Power conversion circuit 152 ... Power conversion system (power conversion device)

Claims (15)

A first switching element mounted on a first insulating substrate and having a first main electrode, a second main electrode, and a gate electrode.
A second switching element mounted on a second insulating substrate and having a third main electrode, a fourth main electrode, and a gate electrode.
A third switching element mounted on a third insulating substrate and provided with a fifth main electrode, a sixth main electrode, and a gate electrode.
A fourth switching element mounted on a fourth insulating substrate and provided with a seventh main electrode, an eighth main electrode, and a gate electrode.
The first main terminal electrically connected to the first main electrode,
A second main terminal electrically connected to the second main electrode,
A third main terminal electrically connected to the third main electrode,
A fourth main terminal electrically connected to the fourth main electrode,
The fifth main terminal, which is electrically connected to the fifth main electrode,
The sixth main terminal, which is electrically connected to the seventh main electrode,
The first wiring pattern electrically connected to the gate electrode of the first switching element,
A second wiring pattern electrically connected to the gate electrode of the second switching element,
A third wiring pattern electrically connected to the gate electrode of the third switching element,
A fourth wiring pattern electrically connected to the gate electrode of the fourth switching element,
A first conductor that electrically connects the gate electrode of the first switching element and the first wiring pattern,
A second conductor that electrically connects the gate electrode of the second switching element and the second wiring pattern,
A third conductor that electrically connects the gate electrode of the third switching element and the third wiring pattern,
A fourth conductor that electrically connects the fourth wiring pattern to the gate electrode of the fourth switching element, and
A fifth wiring pattern electrically connected to the second main electrode and
A sixth wiring pattern electrically connected to the fourth main electrode and
A seventh wiring pattern electrically connected to the sixth main electrode and
The eighth wiring pattern electrically connected to the eighth main electrode and
A fifth conductor that electrically connects the second main electrode and the fifth wiring pattern,
A sixth conductor that electrically connects the fourth main electrode and the sixth wiring pattern,
A seventh conductor that electrically connects the sixth main electrode and the seventh wiring pattern,
An eighth conductor that electrically connects the eighth main electrode and the eighth wiring pattern,
The first wiring pattern and the first auxiliary terminal electrically connected to the second wiring pattern,
The third wiring pattern and the second auxiliary terminal electrically connected to the fourth wiring pattern,
The fifth wiring pattern and the third auxiliary terminal electrically connected to the sixth wiring pattern,
The seventh wiring pattern and the fourth auxiliary terminal electrically connected to the eighth wiring pattern,
A ninth conductor that electrically connects the first main electrode and the sixth main electrode,
A tenth conductor that electrically connects the third main electrode and the eighth main electrode,
In the power semiconductor module equipped with
The impedance value between the first main electrode and the third main electrode, the impedance value between the fifth main electrode and the seventh main electrode, and the sixth main electrode and the above. A power semiconductor module characterized in that the impedance value between the second main electrode and the fourth main electrode is larger than the minimum impedance value among the impedance values between the eighth main electrode. In the power semiconductor module according to claim 1,
The impedance value between the second main electrode and the fourth main electrode is from the sixth main electrode to the seventh conductor, the seventh wiring pattern, the seventh wiring pattern and the seventh. At the impedance value or higher of the connection point between the wiring between the eight wiring patterns and the fourth auxiliary terminal, the eighth wiring pattern, the eighth conductor, and the path to the eighth main electrode. A power semiconductor module characterized by being present. In the power semiconductor module according to claim 1,
A power semiconductor module characterized in that the fifth main electrode and the seventh main electrode are electrically connected by a conductor inside the power semiconductor module. In the power semiconductor module according to claim 1,
A power semiconductor module characterized in that the sixth main electrode and the eighth main electrode are electrically connected by a conductor inside the power semiconductor module. In the power semiconductor module according to claim 1,
A power semiconductor module characterized in that the first main electrode and the third main electrode are electrically connected by a conductor inside the power semiconductor module. In the power semiconductor module according to claim 1,
The connection point between the second main electrode and the fifth conductor, the fifth wiring pattern, the wiring between the fifth wiring pattern and the sixth wiring pattern, and the third auxiliary terminal, the said. A power semiconductor module characterized in that a resistor is connected between a sixth wiring pattern, a path through the sixth conductor and a path to the fourth main electrode. In the power semiconductor module according to claim 1,
The connection point between the second main electrode, the fifth conductor, the fifth wiring pattern, the wiring between the fifth wiring pattern and the sixth wiring pattern, and the third auxiliary terminal, the said. A power semiconductor module characterized in that an inductor is connected between a sixth wiring pattern, a path through the sixth conductor and a path to the fourth main electrode. In the power semiconductor module according to claim 1,
From the second main electrode to the fifth conductor, the fifth wiring pattern, the connection point between the wiring between the fifth wiring pattern and the sixth wiring pattern and the third auxiliary terminal, the said. The sixth wiring pattern, the wiring length of the path passing through the sixth conductor and reaching the fourth main electrode, is the wiring length from the sixth main electrode to the seventh conductor, the seventh wiring pattern, the seventh. It passes through the connection point between the wiring between the seventh wiring pattern and the eighth wiring pattern and the fourth auxiliary terminal, the eighth wiring pattern, the eighth conductor, and reaches the eighth main electrode. A power semiconductor module characterized by being longer than the wiring length of the path. In the power semiconductor module according to claim 4,
A power semiconductor module characterized in that the fifth main electrode and the seventh main electrode are electrically connected by a conductor inside the power semiconductor module. In the power semiconductor module according to claim 5,
A power semiconductor module characterized in that the sixth main electrode and the eighth main electrode are electrically connected by a conductor inside the power semiconductor module. In the power semiconductor module according to claim 6,
A power semiconductor module characterized in that the first main electrode and the third main electrode are electrically connected by a conductor inside the power semiconductor module. In the power semiconductor module according to claim 10,
A power semiconductor module characterized in that the fifth main electrode and the seventh main electrode are electrically connected by a conductor inside the power semiconductor module. In the power semiconductor module according to claim 11,
A power semiconductor module characterized in that the sixth main electrode and the eighth main electrode are electrically connected by a conductor inside the power semiconductor module. In the power semiconductor module according to claim 13,
A power semiconductor module characterized in that the fifth main electrode and the seventh main electrode are electrically connected by a conductor inside the power semiconductor module. A power conversion device including the power semiconductor module according to any one of claims 1 to 14.

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