JP6748407B2 - OLED display - Google Patents

Description

The present invention relates to an organic light emitting display device, and more particularly to an organic light emitting display device with improved display quality.

Recently, weight reduction and thickness reduction of monitors, televisions, portable display devices, etc. have been demanded. In response to such a demand, the existing cathode ray tube display device has been replaced by a flat panel display device such as a liquid crystal display device or an organic light emitting diode display device. Among such flat panel display devices, an organic light emitting display device has a high response speed, low power consumption, and wide viewing angle characteristics, and thus has attracted attention as a next-generation flat panel display device.

An organic light emitting diode display is known to control the magnitude of a current supplied to an organic light emitting diode to control the brightness or gray level of one pixel. At this time, the magnitude of the current provided to the organic light emitting device may be determined by the voltage difference between the gate and the source of the driving transistor and the coefficient of the current driving characteristic of the driving transistor. Ideally, the driving transistors of all pixels of the organic light emitting diode display should have the same characteristics, and for the same data voltage, the pixels should express the same gray level, but , Different process characteristics, different degrees of deterioration, etc. may have different characteristic coefficients, which causes a gray scale imbalance depending on the position of the OLED display.

Therefore, the problem to be solved by the present invention is to provide an organic light emitting display device with improved display quality.

The problems to be solved by the present invention are not limited to the technical problems mentioned above, and other problems not mentioned above will be apparent to those having ordinary skill in the technical field of the present invention from the following description. You will understand.

In order to solve the above problems, an organic light emitting display device according to an embodiment of the present invention, a display panel including a plurality of pixels respectively connected to a plurality of scanning lines and a plurality of data lines, a plurality of. A scan driver that sequentially applies scan signals to the plurality of scan lines, a data driver that receives a video signal and outputs a plurality of data output signals, an analog sense signal, and a digital sense signal. The voltage ADC, a data switching unit that connects a plurality of data lines to the data driving unit or connects a plurality of data lines to the voltage ADC in response to a switching signal, and the original video data and the digital sense signal. A controller for receiving and processing original image data into an image signal based on the digital sense signal, providing the image signal to the data driver, and providing a switching signal to the data switching unit; The data switching unit connects the plurality of data lines to the data driving unit, the data driving unit applies an initialization voltage to the connected data lines, and b) at least in the first sensing period. One pixel charges at least one data line with a first voltage, the data switching unit connects the voltage ADC to the plurality of data lines, and the voltage ADC outputs a second analog sense signal from the connected data line. Receiving one voltage, converting an analog sense signal corresponding to the first voltage into a digital sense signal and outputting the digital sense signal to the controller, and c) in the second initialization period, the data switching unit connects the plurality of data lines. The data driver is connected to the data driver, and the data driver applies an initialization voltage to the connected data line. d) In the second sensing period, the voltage applied to the data line is from the initialization voltage to the second voltage. The data switching unit connects the voltage ADC to the plurality of data lines, the voltage ADC receives the second voltage from the connected data lines, and digitally outputs an analog sense signal corresponding to the second voltage. It is converted into a sense signal and output to the control unit.

Meanwhile, the first initialization section, the first sensing section, the second initialization section, and the second sensing section are located within a period in which an image of one frame is displayed.

Meanwhile, the lengths of the first sensing section and the second sensing section are the same.

Meanwhile, the controller determines a voltage obtained by subtracting the second voltage from the first voltage based on the digital sense signal corresponding to the first voltage and the digital sense signal corresponding to the second voltage.

Meanwhile, at least one pixel of the plurality of pixels includes first to fifth transistors, the first to fifth transistors are PMOS transistors, and a node connected to a source terminal of the first transistor is a fourth transistor. The drain terminal of the transistor is connected, the source terminal of the first transistor is connected to the first power supply voltage source through the fourth transistor, and the node connected to the drain terminal of the first transistor is connected to the anode of the organic light emitting device. The cathode of the organic light emitting device is connected to the second power supply voltage source, the drain terminal of the second transistor is connected to the node connected to the gate terminal of the first transistor, and the source terminal of the second transistor is at least one data line. , The gate terminal of the second transistor is connected to at least one scan line, the source terminal of the third transistor is connected to the node connected to the drain terminal of the first transistor, and the drain terminal of the third transistor is at least The third transistor is connected to one data line, the sensing terminal is connected to the gate terminal of the third transistor, the drain terminal of the fourth transistor is connected to the node connected to the source terminal of the first transistor, and the source terminal of the fourth transistor. Is connected to the first power supply voltage source, the gate terminal of the fourth transistor is connected to the emission voltage, the source terminal of the fifth transistor is connected to the sustain voltage, and the drain terminal of the fifth transistor is connected to the source terminal of the first transistor. The gate terminal of the fifth transistor is connected to the connected node and is connected to at least one scan line.

Meanwhile, at least one pixel of the plurality of pixels further includes a sixth transistor, a source terminal of the sixth transistor is connected to a node connected to a source terminal of the first transistor, and a drain terminal of the sixth transistor. Is connected to the node connected to the gate terminal of the first transistor, and the gate terminal of the sixth transistor is connected to the bias voltage.

Meanwhile, at least one of the plurality of pixels further includes a sustain electrode having both ends connected between a node connected to the source terminal of the first transistor and a node connected to the gate terminal of the first transistor. Including an organic light emitting display device.

Meanwhile, e) in the third initialization period, the data switching unit connects the plurality of data lines to the data driving unit, the data driving unit applies an initialization voltage to the connected data lines, and f ) In the third sensing period, at least one pixel charges at least one data line with a third voltage, the data switching unit connects the voltage ADC to the plurality of data lines, and the voltage ADC is connected. Receiving a third voltage as an analog sense signal from the data line, converting the analog sense signal corresponding to the third voltage into a digital sense signal and outputting the digital sense signal to the controller, and g) switching the data in the fourth initialization period. A part connects the plurality of data lines to the data driver, the data driver applies an initialization voltage to the connected data lines, and h) a voltage applied to the data lines in the fourth sensing section. Changes from the initialization voltage to the fourth voltage, the data switching unit connects the voltage ADC to the plurality of data lines, and the voltage ADC receives the fourth voltage from the connected data lines and the fourth voltage The analog sense signal corresponding to is converted into a digital sense signal and output to the controller.

Meanwhile, the first initialization section, the first sensing section, the second initialization section, the second sensing section, the third initialization section, the third sensing section, the fourth initialization section and the fourth sensing section are one frame. It is located within the period when the image of is displayed.

Meanwhile, the first sensing section and the second sensing section have the same length, and the third sensing section and the fourth sensing section have the same length.

Other specific details of the invention are included in the detailed description and drawings.

According to the embodiment of the present invention, there are at least the following effects.

It is possible to improve the display quality by compensating the characteristic deviation of each pixel, especially the driving transistor of the pixel, by an external driving IC.

Further, when the drive IC performs external compensation, it is possible to eliminate erroneous detection due to leakage current.

The effects according to the present invention are not limited by the contents illustrated above, and various effects are included in the present specification.

It is a block diagram which shows the structure of the organic light emitting diode display concerning the Example of this invention roughly. FIG. 4 is a block diagram schematically showing a part of a display panel and other components connected to the display panel of the organic light emitting diode display according to an exemplary embodiment of the present invention. FIG. 6 is a timing diagram illustrating a data voltage sensing operation of the organic light emitting diode display according to an exemplary embodiment of the present invention. FIG. 3 is a circuit diagram showing one pixel of a display panel of an organic light emitting diode display according to an exemplary embodiment of the present invention, and a data line, a scan line, and a data switch unit connected to the pixel. The circuit diagram shown in FIG. 4 is a timing diagram showing the sensing operation of the data voltage in the low gradation driving region. The circuit diagram shown in FIG. 4 is a timing diagram showing the sensing operation of the data voltage in the high gradation driving region. FIG. 6 is a timing diagram illustrating a display operation of the organic light emitting diode display according to an exemplary embodiment of the present invention. 6 is a circuit diagram illustrating one pixel of an organic light emitting display panel according to another exemplary embodiment of the present invention, and a data line, a scan line, and a data switching unit connected to the pixel. 6 is a timing diagram illustrating a display operation of an organic light emitting diode display according to another exemplary embodiment of the present invention.

Advantages and features of the present invention, as well as methods of achieving the same, will become apparent in the embodiments described in detail below in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but is realized in various forms different from each other, and the present embodiments merely complete the disclosure of the present invention. The present invention is provided to fully inform a person having ordinary knowledge in the technical field to which the invention belongs, and the present invention is defined only by the claims. In the present specification, the same reference numeral indicates substantially the same configuration.

The first, second, etc. are used to describe various elements and components, but it goes without saying that these elements and components are not limited by these terms. These terms are only used to distinguish one element from another. Therefore, it goes without saying that the first component referred to below may be the second component within the technical idea of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram schematically showing a configuration of an organic light emitting display device according to an embodiment of the present invention.

Referring to FIG. 1, the OLED display includes a display panel 100, a controller 200, a scan driver 300, a data driver 400, a voltage ADC 500 (Analog to Digital Converter), a power supply unit 600, and a gradation voltage generator 700. And a data switching unit 800.

In FIG. 1, each component is shown as a block different from each other. However, each component shown in FIG. 1 is a component that performs different functions on the basis of its function in a separated manner, and each component physically represents one component, for example, one component. It can be a complex of algorithms implemented on an IC chip.

The display panel 100 includes a plurality of scan lines (SL1 to SLn) extending in the first direction X1, a plurality of data lines (DL1 to DLm) extending in the second direction X2, and a plurality of scan lines (SL1 to SLn). It may include a plurality of pixels respectively connected to the plurality of data lines (DL1 to DLm). The configuration and operation of each of the plurality of pixels will be described in detail with reference to FIGS.

The controller 200 receives the original image data and the digital sense signal provided from the outside, processes the original image data into the image signal RGB based on the digital sense signal, and provides the image signal RGB to the data driver 400. In particular, in the exemplary embodiment of the present invention, the controller 200 provides the data switching unit 800 with a switching signal SS, and the data switching unit 800 responds to the switching signal SS to transfer data through a plurality of data lines (DL1 to DLm). It connects to the driving unit 400 or connects a plurality of data lines (DL1 to DLm) to the voltage ADC 500.

In order to perform the functions described above, the controller 200 according to the exemplary embodiment of the present invention may include a video data corrector 220, a timing controller 210, and a memory 230.

The timing controller 210 receives the corrected image data IMAGE′ from the image data corrector 220, processes the corrected image data IMAGE′ into an image signal RGB, and transmits the image signal RGB to the data driver 400. Also, the timing controller 210 outputs a data control signal DCS and a scan control signal SCS for driving the data driver 400 and the scan driver 300 in synchronization with the video signal RGB. The image signal RGB may be a signal obtained by processing the image data IMAGE′ corrected so as to correspond to the tone value or tone voltage of each pixel of the display panel 100. In addition, the timing control unit 210 additionally modulates or compensates the corrected video signal according to the user's preference or the unique device characteristics of the organic light emitting display device to process the video signal RGB.

In addition, the timing controller 210 provides a pixel control signal PCS for controlling the driving of the pixels of the display panel 100 to the pixels of the display panel 100.

In addition, the timing controller 210 provides a switching signal SS to the data switching unit 800, and the data switching unit 800 connects a plurality of data lines (DL1 to DLm) to the data driver 400 in response to the switching signal SS. The data lines (DL1 to DLm) are connected to the voltage ADC 500.

The image data correction unit 220 may read the corrected reference value from the memory 230 and receive the original image data IMAGE from an external image source, for example, an external graphic processing unit. The video data correction unit 220 corrects the original video data IMAGE based on the correction reference value and generates the corrected video data IMAGE'.

At this time, the correction reference value may be an offset value indicating a difference in driving characteristics for each pixel, and the offset value is a value obtained by cumulatively updating the digital sense signal recorded in the memory 230 via the voltage ADC 500. possible.

In addition, the video data correction unit 220 stores the received video data or the corrected video data IMAGE′ in the memory 230.

The memory 230 may be a non-volatile memory 230 capable of storing information specific to the display device, such as specifications, characteristics, look-up tables for gamma curves, etc., at least when the display device is powered off. It may include a flash memory 230, an EEPROM (Electrically Erasable Programmable Read-Only MEMORY), and the like. In addition, the memory 230 may include a volatile memory 230, such as a DRAM or an SRAM, which can store information regarding the same correction reference value as the offset value that is cumulatively updated when the display device is powered on.

In FIG. 1, the timing control unit 210 and the video data correction unit 220 are shown as separate functional blocks, but the present invention is not limited to this. The image data correction unit 220 may be an algorithm that performs an image correction function according to an exemplary embodiment of the present invention as a part of the image processing algorithm of the timing control unit 210, and the timing control unit 210 and the image data correction unit 220 may be a single unit. It can be a single module built into an IC chip.

The scan driver 300 receives the scan control signal SCS from the timing controller 210 and sequentially drives the plurality of scan lines (SL1 to SLn) in response to the received scan control signal SCS.

The data driver 400 receives the video signal RGB and the data control signal DCS from the timing controller 210, and drives the plurality of data lines (DL1 to DLm) in response to the received video signal RGB and the data control signal DCS. To output a plurality of data output signals (DO1 to DOm). For example, the data output signals (DO1 to DOm) are provided to the plurality of data lines (DL1 to DLm) via the data switching unit 800.

More specifically, the data driver 400 receives a plurality of grayscale voltages (V0 to V255) from the grayscale voltage generator 700 and selects one or more of the received grayscale voltages (V0 to V255). , And the selected grayscale voltage can be transmitted to the data switching unit 800 as data output signals (DO1 to DOm). In addition, the data driver 400 may change the data output signal output in response to the data control signal DCS, and outputs another voltage signal other than the received video signal RGB, for example, an initialization signal. Output as signals (DO1 to DOm).

The data switching unit 800 selectively connects the plurality of data lines (DL1 to DLm) to the data driving unit 400 in response to the switching signal SS provided from the timing control unit 210, or the plurality of data lines (DL1 to DLm). DLm) is connected to the voltage ADC 500. That is, when the plurality of data voltages output from the data driver 400 are transmitted to the plurality of data lines DL1 to DLm, the data switching unit 800 connects the plurality of data lines DL1 to DLm to the data driver 400. However, when the voltage of the data line is to be sensed by the voltage ADC 500, the data switching unit 800 may connect the plurality of data lines (DL1 to DLm) to the voltage ADC 500. Specifically, the data switching unit 800 is connected to the voltage ADC 500 via a sense line (Sense_L), is connected to the data driving unit 400 via a data transmission line (DATA_L), and is connected to the display panel 100 as a data line. (DL1 to DLm).

In this specification, the plurality of data signals refer to voltage levels applied to the respective data lines (DL1 to DLm) and are distinguished from the data output signals output from the data driver 400. For example, when the data switching unit 800 connects the data transmission lines (DATA_L) connected to the data driving unit 400 to the data lines (DL1 to DLm), the data output signals (DO1 to DOm) may be the same as the data signals. However, when the data switching unit 800 connects the sense lines (Sense_L) connected to the voltage ADC 500 to the data lines (DL1 to DLm), the data output signals (DO1 to DOm) may be different from the data signals.

The voltage ADC 500 is connected to the plurality of data lines (DL1 to DLm) of the display panel 100 via the data switching unit 800. For example, when the data signal corresponding to the voltage level applied to the data lines DL1 to DLm is to be sensed, the data switching unit 800 may connect the sense lines Sense_L connected to the voltage ADC 500 to the data lines DL1 to DLm. ), the voltage ADC 500 receives a data signal corresponding to the voltage level of the data lines (DL1 to DLm) as an analog signal, and outputs the analog signal as a digital sense signal. The output digital sense signal is written in the memory 230 of the control unit 200.

In FIG. 1, the data switching unit 800, the voltage ADC 500, and the data driving unit 400 are shown as separate functional blocks, but the present invention is not limited thereto. The data switching unit 800, the data driving unit 400, and the voltage ADC 500 are integrally formed on the same IC chip and connected to at least a part of the display panel 100. Further, the data switching unit 800, the data driving unit 400, and the voltage ADC 500 are It may be an integrated circuit integrally formed with the controller 200 or the scan driver 300 as one driving IC, or formed in at least a partial region of the display panel 100.

The power supply unit 600 is a voltage source that transmits an appropriate voltage to each component in the display panel 100. In particular, in one embodiment of the present invention, the power supply unit 600 provides the first power supply voltage source ELVDD and the second power supply voltage source ELVSS to the plurality of pixels of the display panel 100, and provides the grayscale voltage generation unit 700 with the first power supply voltage source ELVDD. A reference power supply REF1 and a second reference power supply REF2 are provided.

The gradation voltage generation unit 700 receives at least the first reference power supply REF1 and the second reference power supply REF2 from the power supply unit 600, distributes the voltage of the first reference power supply REF1 and the second reference power supply REF2, and outputs a plurality of gradation voltages. (V0 to V255) is generated.

Although FIG. 1 shows the case where the grayscale voltage generation unit 700 generates 256 grayscale voltages (V0 to V255), the present invention is not limited to this. The type of grayscale voltage generated by the grayscale voltage generator 700 may be increased or decreased depending on the display quality required for the display panel 100, the panel size, and the driving method of the display panel 100 and the data driver 400. Although not shown in the drawing, the grayscale voltage generator 700 receives a grayscale voltage selection signal (not shown) from the timing controller 210 and outputs a plurality of grayscale voltage selection signals according to the received grayscale voltage selection signal. The voltage level of the gradation voltage (V0 to V255) can be adjusted.

Hereinafter, a process of sensing a data signal of the organic light emitting diode display according to an exemplary embodiment of the present invention and a process of correcting image data according to the process will be described in detail with reference to FIGS. 2 and 3.

FIG. 2 is a block diagram schematically showing a part of the display panel 100 and other components connected to the display panel 100 of the organic light emitting diode display according to an exemplary embodiment of the present invention.

FIG. 3 is a timing diagram illustrating a data voltage sensing operation of the OLED display according to an exemplary embodiment.

2 and 3, pixels (Pi1 to Pim) connected to one scanning line SLi and a plurality of data lines (DL1 to DLm) are illustrated.

Referring to FIGS. 2 and 3, in the OLED display according to the exemplary embodiment of the present invention, a plurality of pixels are connected to the scan lines (SL1 to SLn) and the data lines (DL1 to DLm), respectively. A data signal applied from the data lines (DL1 to DLm) is provided to each pixel in response to a scan signal applied from SL1 to SLn). Each pixel provided with the data signal provides a driving current having a magnitude corresponding to the voltage level of the data signal to the organic light emitting device, and the organic light emitting device emits light having a brightness corresponding to the magnitude of the driving current provided. To do.

The magnitude of the driving current flowing through each pixel is controlled by adjusting the voltage level of the data signal applied to the gate of the driving transistor.

In saturation, the current flowing in the drive transistor is generally approximated by the following "equation 1".

Here, μ, Cox, W, and L are the charge mobility of the driving transistor, the gate capacitance per unit area, the channel width, and the channel length, respectively, which are characteristic characteristics unique to each transistor, and Vth is the driving transistor. Is a critical voltage that means a minimum source-gate voltage difference for turning on, and this is also an inherent characteristic coefficient of each transistor.

Ideally, in an organic light emitting diode display, the driving transistors included in a plurality of pixels all have the same characteristic coefficient, but the plurality of pixels in an actual organic light emitting diode display may be different in process conditions and panel sustainability. A minute difference in the characteristic coefficient may be indicated by a difference in deterioration of each pixel due to specific use. The difference in the characteristic coefficient for each pixel may cause light of another gradation to be emitted for each pixel with respect to the same image data, that is, the same data signal, which is a factor that hinders the display quality of the OLED display device. Become.

In an exemplary embodiment of the present invention, the voltage ADC 500 senses a value related to a driving current with respect to a driving threshold voltage of a driving transistor and a driving reference voltage from the data lines (DL1 to DLm), and transmits the value to the control unit 200. The data correction unit 220 corrects the original image data based on the values associated with the characteristic coefficients of the plurality of pixels sensed for each pixel to generate corrected image data.

Specifically, the data switching unit 800 selectively connects the data driving unit 400 to the plurality of data lines (DL1 to DLm) or the voltage ADC 500 to the plurality of data lines (DL1 to DLm) in response to the switching signal SS. To connect with. When the data driver 400 is connected to a plurality of data, the data output signal is provided as a data signal on the data line, and the plurality of pixels display an image corresponding to the applied data signal.

A data signal according to an exemplary embodiment of the present invention is provided while a video of one frame is displayed on the display panel 100 or during a waiting time for displaying a video of one frame and displaying a video of the next frame. Sensing operation is performed.

First, during the first initialization period, the data switch SW_D is turned on and the sensing switch SW_S is turned off. That is, in the first initialization period, the data switching unit 800 connects the plurality of data lines (DL1 to DLm) to the data driving unit 400 and disconnects the plurality of data lines (DL1 to DLm) from the voltage ADC 500.

During the first initialization period, the data driver 400 outputs the initialization voltage signal Vint as a data output signal in response to the data control signal DCS from the timing controller 210, and outputs it to all the data lines (DL1 to DLm). Is applied with a data signal corresponding to the initialization voltage signal.

Then, the data switch SW_D is turned off and the sensing switch SW_S is turned on during the first voltage sensing period. That is, in the first voltage sensing period, the data switching unit 800 disconnects the plurality of data lines (DL1 to DLm) from the data driving unit 400 and connects the plurality of data lines (DL1 to DLm) to the voltage ADC 500.

During the first voltage sensing period, the pixels connected to the i-th scan line (Pi1 to Pim) may receive the first voltage (V1_D1 to V1_Dm) on the connected data lines (DL1 to DLm) in response to the pixel control signal PCS. ) Is charged. The charging of the data lines (DL1 to DLm) with the first voltage (V1_D1 to V1_Dm) is continued during the first voltage sensing period, and the voltage ADC500 is the voltage level of the data line, that is, the data signal is an analog sense signal. The signal is received, converted into a digital sense signal, and the digital sense signal is transmitted to the memory 230 of the control unit 200.

During the first voltage sensing period, the first voltages (V1_D1 to V1_Dm) charged in the data lines (DL1 to DLm) are driving currents of the pixels (Pi1 to Pim) connected to the respective data lines (DL1 to DLm). The control unit 200 senses the first voltages (V1_D1 to V1_Dm) to adjust the respective pixels (Pi1 to Pim) to the correction reference value for compensating the characteristic coefficient deviation. To update.

However, as shown in FIG. 2, while performing the first voltage sensing of the pixels (Pi1 to Pim) connected to the i-th scan line, a leakage current (I_l) may occur through the transistors of other pixels that do not perform sensing. May occur, which affects the first voltage (V1_D1 to V1_Dm) charged in the data line.

A switching transistor that connects other pixels that do not perform sensing to the data lines (DL1 to DLm) in a switchable manner maintains a turn-off state. However, in the case of a non-ideal transistor, a minute current may flow in the turn-off state. The non-sensing scan lines other than the pixels (Pi1 to Pim) connected to the scan line and the number of pixels connected to the scan line are the i-th scan line to detect and the pixel connected to the scan line (Pi1). ~Pim), such a leakage current (I_l) has a large effect on the sensed data signal.

In particular, the smaller the sensed first voltage (V1_D1 to V1_Dm), the deeper this effect becomes.

Then, during the second initialization period, the data switch SW_D is turned on and the sensing switch SW_S is turned off. That is, in the second initialization period, the data switching unit 800 connects the plurality of data lines (DL1 to DLm) to the data driving unit 400 and disconnects the plurality of data lines (DL1 to DLm) from the voltage ADC 500.

During the second initialization period, the data driver 400 responds to the data control signal DCS from the timing controller 210, outputs the initialization voltage signal Vint as a data output signal, and outputs it to all the data lines (DL1 to DLm). Is applied with a data signal corresponding to the initialization voltage signal.

Then, during the second voltage sensing period, the data switch SW_D is turned off and the sensing switch SW_S is turned on. That is, in the second voltage sensing period, the data switching unit 800 blocks the plurality of data lines (DL1 to DLm) from the data driving unit 400 and connects the plurality of data lines (DL1 to DLm) to the voltage ADC 500.

During the second voltage sensing period, the switching transistors of the pixels (Pi1 to Pim) connected to the i th scan line may be turned off, and the pixels connected to the i th scan line (Pi1 to Pim) may be turned off. The connection can be cut off from the data lines (DL1 to DLm).

During the second voltage sensing period, a leakage current I_l may be generated between the plurality of data lines DL1 to DLm and the plurality of pixels connected to the plurality of data lines DL1 to DLm. The voltage of (DLm) can be changed from the initialization voltage Vint to the second voltage (V2_D1 to V2_Dm).

During the second voltage sensing period, the voltage ADC 500 may receive a voltage level of the data lines (DL1 to DLm), that is, a data signal as an analog sense signal and convert it into a digital sense signal, and the digital sense signal of the controller 200 may be received. It may be transmitted to the memory 230.

Next, in the data rewriting period, the data switch (SW_D) is turned on and the sensing switch (SW_S) is turned off. That is, in the data rewriting section, the data switching unit 800 connects the plurality of data lines (DL1 to DLm) to the data driving unit 400 and disconnects the plurality of data lines (DL1 to DLm) from the voltage ADC 500.

The data driver 400 may output the data output signal applied to the pixels (Pi1 to Pim) connected to the i-th scan line before the sensing operation is performed, and the pixels (Pi1 to Pim) may be output as they are. It emits light corresponding to the data signal. However, in some embodiments, when the sensing operation is performed during the waiting time from the end of one frame to the next frame, such a data rewriting period may be omitted.

A series of sensing operations for the pixels (Pi1 to Pim) connected to at least one scan line SLi are performed in one frame. This is because the amount of current leaked to other unsensed pixels depends on the level of the data voltage pre-applied to the other unsensed pixels and the amount of driving current flowing accordingly, so that it may be different for different frames. When the first sensing section and the second sensing section are located, the amount of current leaked in the first sensing section and the second sensing section and the voltage fluctuation of the data lines (DL1 to DLm) due to the leakage current may be different. is there.

Also, the length or time of the first sensing section and the second sensing section may be the same. The current leaked in the first sensing section and the second sensing section and the voltage variation of the data lines (DL1 to DLm) due to the leakage current are maintained during the leaking time. If the length or time is the same, the leakage current in the first sensing section and the second sensing section and the voltage fluctuations of the data lines (DL1 to DLm) due to the leakage current may be the same.

The image data correction unit 220 includes a digital sense signal corresponding to the first voltage (V1_D1 to V1_Dm) received from the memory 230 during the first sensing period and the second voltage (V2_D1 to V1_D1) received during the second sensing period. The digital sense signal corresponding to V2_Dm) is read, and the voltage in which the voltage variation due to the leakage current is removed is determined by the first voltage (V1_D1 to V1_Dm) based on the digital sense signal corresponding to the second voltage (V2_D1 to V2_Dm). ..

For example, the initialization voltage Vint is a predetermined voltage, and is applied to each of the pixels (Pi1 to Pim) connected to the i-th scan line in the same manner, and the initialization voltage Vint and the sensed second voltage ( The difference from V2_D1 to V2_Dm corresponds to the leakage voltage (ΔVleakage_D1 to ΔVleakage_Dm) due to the current leaked in each data line (DL1 to DLm). Therefore, when the second voltage (V2_D1 to V2_Dm) is subtracted from the first voltage (V1_D1 to V1_Dm) sensed from each of the data lines (DL1 to DLm), and a predetermined initialization voltage Vint is added, The first voltage (V1_D1 to V1_Dm) sensed by each of the data lines (DL1 to DLm) determines the voltage from which the leakage voltage (ΔVleakage_D1 to ΔVleakage_Dm) components due to the leakage current are removed.

The first voltages (V1_D1 to V1_Dm) provided to the data lines (DL1 to DLm) by the plurality of panels may be voltage signals in which characteristic deviations of respective pixels are reflected. The control unit 200 determines the voltage obtained by removing the leakage voltage component from the sensed first voltage (V1_D1 to V1_Dm) and the second voltage (V2_D1 to V2_Dm) by the first voltage (V1_D1 to V1_Dm), and the determined voltage. To output the corrected image data IMAGE′, which is obtained by compensating the image data IMAGE for the characteristic deviation of each pixel.

For example, in the first sensing period, the pixels (Pi1 to Pim) connected to the i-th scan line apply a voltage including the threshold voltage Vth component of the driving transistor to each of the data lines (DL1 to DLm), The voltage level of (DL1 to DLm), that is, the data signal is charged with the first voltage (V1_D1 to V1_Dm). When the pixel operates in a low gray level region, that is, when the voltage level of the data signal applied to the driving transistor is low, the influence of the threshold voltage Vth of the driving transistor on the gray level or characteristic of each pixel is relatively large. Would be big.

In addition, in the first sensing period, the pixels (Pi1 to Pim) connected to the i-th scan line have a specific gray level, for example, a data signal corresponding to a gray level when the organic light emitting device emits light at the maximum gray level. The current is provided to the data lines (DL1 to DLm), so that the data lines (DL1 to DLm) are charged with the first voltage (V1_D1 to V1_Dm). When the pixel operates in a high gradation region, that is, when the voltage level of the data signal applied to the driving transistor is high, the threshold voltage Vth of the driving transistor has a relatively small influence on the gradation or characteristics of each pixel. , Other characteristics of the driving transistor, such as charge mobility, gate capacitance, channel width and channel length, will have a relatively large effect on the gray level or characteristics of each pixel.

In some embodiments of the present invention, the control unit 200 determines all the characteristic deviations of a plurality of pixels in a low gradation area and the characteristic deviations of a plurality of pixels in a high gradation area, and combines them to obtain a correction reference value. To generate.

That is, in order to determine the characteristic deviation of the pixel in the low gradation region, one of the first initialization section, the first voltage sensing section, the second initialization section, and the second voltage sensing section, which have been described above, is used. After being performed in the frame, a third initialization period, a third voltage sensing period, a fourth initialization period, and a fourth voltage sensing period are performed to determine the characteristic deviation of the pixel in the high gradation region.

Hereinafter, an implementation example of the above-mentioned pixel and a data voltage sensing method will be described in detail with reference to FIGS. 4 to 6.

FIG. 4 is a circuit diagram showing one pixel of the display panel 100 of the OLED display device according to an exemplary embodiment of the present invention, and a data line, a scan line, and a data switching unit 800 connected to the pixel.

FIG. 5 is a timing diagram showing a case where the circuit diagram of FIG. 4 performs a data voltage sensing operation in a low gradation driving region.

FIG. 6 is a timing diagram showing a case where the circuit diagram shown in FIG. 4 performs a data voltage sensing operation in a high gradation driving region.

Referring to FIG. 4, FIG. 4 illustrates one pixel Pij of the plurality of pixels of the display panel 100, the scan line SLi and the data line DLj connected to the pixel Pij, and other signal lines.

In FIG. 4, one pixel Pij of the display panel 100 according to the exemplary embodiment of the present invention may include first to sixth transistors T6, and the first to sixth transistors T6 are PMOS transistors.

The first transistor T1 is a transistor that adjusts the amount of current supplied to the organic light emitting device, and corresponds to the driving transistor described above with reference to FIGS. 1 to 3. The node S connected to the source terminal of the first transistor T1 is connected to the drain terminal of the fourth transistor T4, and the source terminal of the first transistor T1 is connected to the first power supply voltage source ELVDD via the fourth transistor T4. .. The node D connected to the drain terminal of the first transistor T1 is connected to the anode of the organic light emitting element, and the drain terminal of the first transistor T1 is connected to the second power supply voltage source ELVSS via the organic light emitting element.

When the organic light emitting device emits light, the second power supply voltage source ELVSS may have a lower voltage level than the first power supply voltage source ELVDD, and the first transistor may have a voltage difference between the first power supply voltage source ELVDD and the second power supply voltage source ELVSS. A drive current flowing through T1 is generated, and the first transistor T1 operates in the saturation region.

The second transistor T2 is a transistor that switches in order to control connection/disconnection of the node G connected to the gate terminal of the first transistor T1 and one data line DLj, and refer to FIGS. 1 to 3 in advance. It corresponds to the switching transistor described above. The drain terminal of the second transistor T2 is connected to the node G connected to the gate terminal of the first transistor T1, and the source terminal of the second transistor T2 is connected to one data line DLj. The gate terminal of the second transistor T2 is connected to one scan line SLi, and the scan signal SCAN is applied from the scan line SLi.

The third transistor T3 is a transistor that switches in order to control connection/disconnection of the node D connected to the drain terminal of the first transistor T1 and the anode of the organic light emitting device and one data line DLj. The source terminal of the third transistor T3 is connected to the node D connected to the drain terminal of the first transistor T1, and the drain terminal of the third transistor T3 is connected to one data line DLj. The sensing voltage SENSE is applied to the gate terminal of the third transistor T3, and the third transistor T3 connects the node D connected to the drain terminal of the first transistor T1 and one data line DLj in response to the sensing voltage SENSE. Switching to control availability.

The fourth transistor T4 is a transistor that switches in order to control connection/disconnection of the node S connected to the source terminal of the first transistor T1 and the first power supply voltage source ELVDD. That is, the fourth transistor T4 plays a role of opening or blocking the voltage or current supplied to the first transistor T1, and also plays a role of a switch for quickly turning on or off the organic light emitting device.

The drain terminal of the fourth transistor T4 is connected to the node S connected to the source terminal of the first transistor T1, and the source terminal of the fourth transistor T4 is connected to the first power supply voltage source ELVDD. The gate terminal of the fourth transistor T4 is connected to the emission voltage EM, and the fourth transistor T4 is connected to the first power supply voltage source ELVDD and the node S connected to the source terminal of the first transistor T1 in response to the emission voltage EM. Switching to control the availability.

The fifth transistor T5 is a transistor that controls whether the sustain voltage Vsus is applied to the node S connected to the source terminal of the first transistor T1. The sustain voltage Vsus is applied to the source terminal of the fifth transistor T5, and the drain terminal of the fifth transistor T5 is connected to the node S connected to the source terminal of the first transistor T1. The gate terminal of the fifth transistor T5 is connected to one scan line SLi, receives the scan signal SCAN from the scan line SLi, and switches to control turn-on or turn-off of the fifth transistor T5.

The sixth transistor T6 is a transistor that switches in order to control connection/disconnection of the node G connected to the gate terminal of the first transistor T1 and the node S connected to the source terminal of the first transistor T1. The source terminal of the sixth transistor T6 is connected to the node S connected to the source terminal of the first transistor T1, and the drain terminal of the sixth transistor T6 is connected to the node G connected to the gate terminal of the first transistor T1. .. The bias voltage BIAS is applied to the gate terminal of the sixth transistor T6, and the sixth transistor T6 responds to the bias voltage BIAS to the node S connected to the source terminal of the first transistor T1 and the gate terminal of the first transistor T1. Connects or disconnects the connected node G.

The sustain electrode CSTG is in parallel with the sixth transistor T6, and both ends thereof are connected to the node S connected to the source terminal of the first transistor T1 and the node G connected to the gate terminal of the first transistor T1.

Next, referring to FIG. 5, when the pixel Pij operates in the low gradation region, that is, when the voltage level of the data signal Dj applied to the gate terminal of the first transistor T1 is low, the threshold voltage of the first transistor T1 is reduced. A low gray level sensing operation of sensing a voltage related to Vth will be described.

Referring to FIG. 5, the low gray level sensing operation includes a first initialization section, a Vth sensing section, a second initialization section, a leakage current sensing section, and a data rewriting section. In some embodiments, the data rewriting section can be omitted.

First, since the second power supply voltage source ELVSS and the bias voltage BIAS can maintain a high voltage (turn-off voltage) during the entire low gradation sensing operation, the current flowing through the organic light emitting device during the entire low gradation sensing operation. And the sixth transistor T6 can be turned off.

The data switch SW_D is turned on and the sensing switch SW_S is turned off during the first initialization period. That is, in the first initialization period, the data switching unit 800 connects the plurality of data lines (DL1 to DLm) to the data driving unit 400 and disconnects the plurality of data lines (DL1 to DLm) from the voltage ADC 500.

During the first initialization period, the data driver 400 outputs the initialization voltage signal Vint as a data output signal in response to the data control signal DCS from the timing controller 210, and outputs it to all the data lines (DL1 to DLm). Is applied with a data signal corresponding to the initialization voltage signal.

During the first initialization period, the scan voltage SCAN maintains a low voltage (turn-on voltage), the emission voltage EM maintains a high voltage (turn-off voltage), and the sensing voltage SENSE maintains a high voltage (turn-off voltage).

As a result, the second transistor T2 and the fifth transistor T5 are turned on, the fourth transistor T4 is turned off, and the third transistor T3 is turned off.

Therefore, during the first initialization period, the initialization voltage is applied to the node G connected to the data line DLj and the gate terminal of the first transistor T1 and to the node S connected to the source terminal of the first transistor T1. Is applied with the sustain voltage Vsus.

Then, during the Vth voltage sensing period, the data switch (SW_D) is turned off and the sensing switch (SW_S) is turned on. That is, in the Vth voltage sensing period, the data switching unit 800 disconnects the plurality of data lines (DL1 to DLm) from the data driving unit 400 and connects the plurality of data lines (DL1 to DLm) to the voltage ADC 500.

During the Vth voltage sensing period, the scan voltage SCAN maintains a low voltage (turn-on voltage), the emission voltage EM maintains a high voltage (turn-off voltage), and the sensing voltage SENSE maintains a low voltage (turn-on voltage).

As a result, the second transistor T2 and the fifth transistor T5 are turned on, the fourth transistor T4 is turned off, and the third transistor T3 is turned on.

That is, the node G connected to the gate terminal of the first transistor T1 and the node D connected to the drain terminal of the first transistor T1 may be conducted through the third transistor T3, the data line DLj, and the second transistor T2. Therefore, a diode connection in which the drain terminal and the gate terminal of the first transistor T1 are connected is formed in the first transistor T1. Since the first transistor T1 forms a diode connection and the sustain voltage Vsus is applied to the source terminal of the first transistor T1, the voltage applied to the gate terminal or the drain terminal of the first transistor T1 is Vsus-|Vth| Corresponds to. Therefore, the voltage level of data line DLj rises to Vsus-|Vth|. Here, |Vth| means the absolute value of the threshold voltage Vth of the first transistor T1, and Vsus means the sustain voltage Vsus provided from the fifth transistor T5.

The sustain voltage Vsus is provided as a predetermined value to a plurality of pixels in the same manner. The voltage ADC 500 senses the voltage level (Vsus−|Vth|) charged in the data line DLj in the Vth voltage sensing section to determine the threshold voltage Vth of the first transistor T1. However, as described above with reference to FIGS. 1 to 3, the data line DLj is charged by the current leaked to the other pixels (P1j to Pnj) that are connected to the data line DLj and are not sensed. The leakage voltage difference (ΔVleakage_Dj) component corresponding to the error due to the leakage current should be taken into consideration, and the voltage level of the data line DLj sensed by the voltage ADC 500 is Vsus−|Vth|+ΔVleakage_Dj. possible.

The voltage ADC 500 may receive the voltage level (Vsus−|Vth|+ΔVleakage_Dj) of the data line DLj as an analog signal, convert it into a digital sense signal, and transmit the converted digital sense signal to the memory 230 of the controller 200.

Then, during the second initialization period, the data switch SW_D is turned on and the sensing switch SW_S is turned off. That is, in the second initialization period, the data switching unit 800 connects the plurality of data lines (DL1 to DLm) to the data driving unit 400 and disconnects the plurality of data lines (DL1 to DLm) from the voltage ADC 500.

During the second initialization period, the data driver 400 outputs the initialization voltage signal Vint as a data output signal in response to the data control signal DCS from the timing controller 210, and outputs the initialization voltage signal Vint to all the data lines. Corresponding data signal is applied.

During the second initialization period, the scan voltage SCAN maintains a high voltage (turn-off voltage), the emission voltage EM maintains a low voltage (turn-on voltage), and the sensing voltage SENSE maintains a high voltage (turn-off voltage).

As a result, the second transistor T2, the third transistor T3, and the fifth transistor T5 are turned off, and the fourth transistor T4 is turned on.

Therefore, during the second initialization period, the initialization voltage is applied to the data line DLj, and the data line DLj is disconnected from the pixel Pij.

Then, during the leakage current sensing period, the data switch (SW_D) is turned off and the sensing switch (SW_S) is turned on. That is, in the leakage current sensing section, the data switching unit 800 disconnects the plurality of data lines (DL1 to DLm) from the data driving unit 400 and connects the plurality of data lines (DL1 to DLm) to the voltage ADC 500.

During the leakage current sensing period, the scan voltage SCAN maintains a high voltage (turn-off voltage), the emission voltage EM maintains a low voltage (turn-on voltage), and the sensing voltage SENSE maintains a high voltage (turn-off voltage).

As a result, the second transistor T2, the third transistor T3, and the fifth transistor T5 are turned off, and the fourth transistor T4 is turned on.

That is, the connection between the data line DLj and the pixel Pij is cut off, and the initialization voltage charged in the data line DLj during the second initialization period is connected to the pixel (connected to the data line DLj during the leakage current sensing period). The voltage level leaked to P1j to Pnj) and thereby charged in the data line DLj may be Vint-ΔVleakage_Dj obtained by subtracting the leakage voltage difference (ΔVleakage_Dj) due to the leakage current at the initialization voltage Vint.

The voltage ADC 500 may perform analog sensing of the voltage level (Vint-ΔVleackage_Dj) of the data line DLj in the leakage current sensing section and convert it into a digital sense signal, and the converted digital sense signal voltage ADC500 may be the voltage level (Vint of the data line DLj. -ΔVleakage_Dj) may be received as an analog signal, converted into a digital sense signal, and the converted digital sense signal may be transmitted to the memory 230 of the control unit 200.

The initialization voltage Vint is provided to a plurality of pixels as a predetermined value. In addition, the control unit 200 may accurately sense the leakage voltage difference (ΔVleakage_Dj) due to the leakage current from the sensed voltage level (Vint-ΔVleakage_Dj) of the data line DLj in the leakage current sensing section.

Specifically, the controller 200 changes the voltage level of the data line DLj sensed during the Vth sensing period from the sensed voltage level of the data line DLj (Vsus−|Vth|+ΔVleakage_Dj) to the leak current sensing period. By adding a predetermined Vint value to the subtracted value ((Vsus-|Vth|+[Delta]Vleakage_Dj)-Vint-[Delta]Vleakage_Dj), the voltage including the threshold voltage Vth component of the first transistor T1 can be determined.

That is, the control unit 200 derives an expression of (Vsus-|Vth|+[Delta]Vleakage_Dj)-Vint-[Delta]Vleakage_Dj+Vint=(Vsus-|Vth|). Since the sustain voltage Vsus also has a predetermined value, the control unit 200 can determine the threshold voltage Vth of the first transistor T1 in which the leakage current is taken into consideration.

The control unit 200 determines the (Vsus-|Vth|) value corresponding to each pixel, and the control unit 200 stores the determined (Vsus-|Vth|) value in the memory 230. Hereinafter, the (Vsus−|Vth|) value for each pixel stored in the memory 230 will be referred to as a stored voltage V _MEM .

As described above, the series of sensing operations of the low gradation region for at least one pixel Pij is performed in one frame. This is because the amount of current leaking to other pixels that are not sensed varies depending on the level of the data voltage that is previously applied to the other pixels that are not sensed and the amount of driving current that flows accordingly, so that Vth sensing is performed on different frames. This is because when the section and the leakage current sensing section are located, the amount of current leaking in the Vth sensing section and the leakage current sensing section and the voltage fluctuation of the data lines (DL1 to DLm) due to the leakage current may be different.

In addition, the Vth sensing section and the leakage current sensing section may have the same section length or time. In the Vth sensing section and the leakage current sensing section, the leakage current and the voltage fluctuation of the data lines (DL1 to DLm) due to the leakage current are maintained for the leakage time, and thus the length of the Vth sensing section and the leakage current sensing section is long. If the same or the same time, the leakage current in the Vth sensing section and the leakage current sensing section and the voltage fluctuations of the data lines (DL1 to DLm) due to the same may be the same.

Next, in the data rewriting period, the data switch (SW_D) is turned on and the sensing switch (SW_S) is turned off. That is, in the data rewriting section, the data switching unit 800 connects the plurality of data lines (DL1 to DLm) to the data driving unit 400 and disconnects the plurality of data lines (DL1 to DLm) from the voltage ADC 500.

The data driver 400 may output the data output signal applied to the pixels (Pi1 to Pim) connected to the i th scan line before the sensing operation is performed, and the pixels (Pi1 to Pim) may output the original data. It can emit light corresponding to the signal. However, in some embodiments, when the sensing operation is performed during the waiting time from the end of one frame to the next frame, such a data rewriting period may be omitted.

Next, referring to FIG. 6, when the pixel Pij operates in a high gradation region, that is, when the current flowing through the first transistor T1 is relatively large, the characteristic deviation of the first transistor T1 is determined. The high gradation sensing operation will be described.

Referring to FIG. 6, the high gray level sensing operation includes a Vref write period, a first initialization period, a ΔVIref voltage sensing period, a second initialization period, a leakage current sensing period, and a data rewriting period. In some embodiments, the data rewriting section may be omitted.

First, the second power supply voltage source ELVSS and the bias voltage BIAS may maintain a high voltage (turn-off voltage) during the entire period of the high gradation sensing operation, and the current flowing through the organic light emitting device may be applied to the entire area of the high gradation sensing operation. It may turn off and turn off the sixth transistor T6.

During the Vref writing period, the data switch (SW_D) is turned on and the sensing switch (SW_S) is turned off. That is, in the Vref write period, the data switching unit 800 connects the plurality of data lines (DL1 to DLm) to the data driving unit 400 and disconnects the plurality of data lines (DL1 to DLm) from the voltage ADC 500.

During the Vref writing period, the data driver 400 may _{generate the} reference voltage Vref from the stored voltage V _MEM stored in the memory 230 in the low gray level sensing operation in response to the data control signal DCS from the timing controller 210. the voltage signal obtained by subtracting output as the data output signal, the data signal corresponding to the data lines (DL1 to DLm) separately voltage obtained by subtracting the reference voltage Vref from the stored voltage V _MEM is applied.

The scan voltage SCAN maintains a low voltage (turn-on voltage), the emission voltage EM maintains a high voltage (turn-off voltage), and the sensing voltage SENSE maintains a high voltage (turn-off voltage) during the Vref write period.

As a result, the second transistor T2 and the fifth transistor T5 are turned on, the fourth transistor T4 is turned off, and the third transistor T3 is turned off.

Thus, during the Vref write section, the data line DLj and the voltage on the connection node G to the gate terminal of the first transistor T1 minus the reference voltage Vref from the stored voltage _{V MEM} voltage, _i.e., (V MEM -Vref ) Is applied, and the sustain voltage Vsus is applied to the node S connected to the source terminal of the first transistor T1.

Then, during the first initialization period, the data switch SW_D is turned on and the sensing switch SW_S is turned off. That is, in the first initialization period, the data switching unit 800 connects the plurality of data lines (DL1 to DLm) to the data driving unit 400 and disconnects the plurality of data lines (DL1 to DLm) from the voltage ADC 500.

During the first initialization period, the data driver 400 outputs the initialization voltage signal Vint as a data output signal in response to the data control signal DCS from the timing controller 210, and initializes the initialization voltage signal to all the data lines. Corresponding data signal is applied.

During the first initialization period, the scan voltage SCAN maintains a high voltage (turn-off voltage), the emission voltage EM maintains a low voltage (turn-on voltage), and the sensing voltage SENSE maintains a high voltage (turn-off voltage).

As a result, the second transistor T2, the third transistor T3, and the fifth transistor T5 are turned on, and the fourth transistor T4 is turned off.

Therefore, during the first initialization period, the data line DLj is electrically disconnected from the pixel Pij by the turned off second transistor T2 and the third transistor T3, and the data line DLj maintains the initialization voltage Vint level. .. The node S connected to the source terminal of the first transistor T1 is connected to the first power supply voltage source ELVDD via the fourth transistor T4, and the voltage level of the node S connected to the source terminal of the first transistor T1 is It may be the same as the voltage level of the first power supply voltage source ELVDD. Further, the Vref write section, because both ends of the sustain electrodes CSTG is charged with a voltage difference _(V MEM -Vref) -Vsus, node S connected to a source terminal of the first transistor T1 in the first initialization period _{(V MEM -Vref) -Vsus + ELVDD} = (Vsus- | Vth | -Vref) -Vsus + ELVDD = ELVDD-Vref- | may have a voltage level of | Vth.

Then, the data switch (SW_D) is turned off and the sensing switch (SW_S) is turned on during the ΔVIref voltage sensing period. That is, in the ΔVIref voltage sensing period, the data switching unit 800 blocks the plurality of data lines (DL1 to DLm) from the data driving unit 400 and connects the plurality of data lines (DL1 to DLm) to the voltage ADC 500.

During the ΔVIref voltage sensing period, the scan voltage SCAN maintains a high voltage (turn-off voltage), the emission voltage EM maintains a low voltage (turn-on voltage), and the sensing voltage SENSE maintains a low voltage (turn-on voltage).

As a result, the second transistor T2 and the fifth transistor T5 are turned off, and the third transistor T3 and the fourth transistor T4 are turned on.

That is, the node D connected to the drain terminal of the first transistor T1 and the data line DLj are conducted through the third transistor T3, and the drive current (IT1) flowing through the first transistor T1 charges the data line DLj, and ΔVIref. The degree to which the voltage level of the data line DLj changes during the voltage sensing period may be indicated by the reference charging voltage difference (ΔVIref).

At this time, the value of the reference charging voltage difference (ΔVIref) can be shown in “Equation 2” below.

Here, ts is the time of the ΔVIref voltage sensing section, and CDATA is the capacitance of the data line DLj. In an embodiment of the present invention, the time or length of the voltage sensing period and the time or length of the leakage current sensing period may be the same, and ts may be the time of the leakage current sensing period. The initialization voltage Vint is a value that is provided to a plurality of pixels as a predetermined value. The voltage ADC 500 senses the voltage level (Vint+ΔVIref) charged in the data line DLj in the ΔVIref voltage sensing period to determine the reference charging voltage difference (ΔVIref). However, as described above with reference to FIGS. 1 to 3, the voltage level charged in the data line DLj due to a current leaking to other pixels (P1j to Pnj) connected to the data line DLj and not sensing. The leakage voltage difference (ΔVleakage_Dj) component corresponding to the error due to the leakage current should be taken into consideration, and the voltage level of the data line DLj sensed by the voltage ADC 500 may be Vint+ΔVIref − ΔVleakage_Dj.

The voltage ADC 500 receives the voltage level (Vint+ΔVIref − ΔVleakage_Dj) of the data line DLj as an analog signal, converts it into a digital sense signal, and transmits the converted digital sense signal to the memory 230 of the control unit 200.

Then, during the second initialization period, the data switch SW_D is turned on and the sensing switch SW_S is turned off. That is, in the second initialization period, the data switching unit 800 connects the plurality of data lines (DL1 to DLm) to the data driving unit 400 and disconnects the plurality of data lines (DL1 to DLm) from the voltage ADC 500.

During the second initialization period, the data driver 400 responds to the data control signal DCS from the timing controller 210, outputs the initialization voltage signal Vint as a data output signal, and outputs the initialization voltage to all the data lines DLj. A data signal corresponding to the signal is applied.

During the second initialization period, the scan voltage SCAN maintains a high voltage (turn-off voltage), the emission voltage EM maintains a low voltage (turn-on voltage), and the sensing voltage SENSE maintains a high voltage (turn-off voltage).

As a result, the second transistor T2, the third transistor T3, and the fifth transistor T5 are kept turned off, and the fourth transistor T4 is kept on-on.

Therefore, during the second initialization period, the initialization voltage Vint is applied to the data line DLj, and the data line DLj is disconnected from the pixel Pij.

Then, during the leakage current sensing period, the data switch (SW_D) is turned off and the sensing switch (SW_S) is turned on. That is, in the leakage current sensing section, the data switching unit 800 disconnects the plurality of data lines (DL1 to DLm) from the data driving unit 400 and connects the plurality of data lines (DL1 to DLm) to the voltage ADC 500.

During the leakage current sensing period, the scan voltage SCAN maintains a high voltage (turn-off voltage), the emission voltage EM maintains a low voltage (turn-on voltage), and the sensing voltage SENSE maintains a high voltage (turn-off voltage).

As a result, the second transistor T2, the third transistor T3, and the fifth transistor T5 are kept turned off, and the fourth transistor T4 is kept on-on.

That is, the connection between the data line DLj and the pixel Pij is cut off, and the initialization voltage charged in the data line DLj during the second initialization period is connected to the pixel (P1j) connected to the data line DLj during the leakage current sensing period. ~Pnj), and thereby the voltage level charged in the data line DLj may be Vint-ΔVleakage_Dj, which is the initialization voltage Vint minus the leakage voltage difference (ΔVleakage_Dj) due to the leakage current.

The voltage ADC 500 performs analog sensing of the voltage level (Vint-ΔVleackage_Dj) of the data line DLj in the leakage current sensing section and converts the voltage level into a digital sense signal. The converted digital sense signal voltage ADC500 has a voltage level (Vint- of the data line DLj. [Delta]Vleakage_Dj) is received as an analog signal, converted into a digital sense signal, and the converted digital sense signal is transmitted to the memory 230 of the control unit 200.

The initialization voltage Vint is provided to a plurality of pixels as a predetermined value. In addition, in the leakage current sensing section, the control unit 200 accurately senses the leakage voltage difference (ΔVleakage_Dj) due to the leakage current from the sensed voltage level (Vint-ΔVleakage_Dj) of the data line DLj.

Specifically, the controller 200 may change the voltage level (Vint+ΔVIref − ΔVleakage_Dj) of the data line DLj sensed during the ΔVIref voltage sensing period from the voltage level (Vint) of the data line DLj sensed during the leakage current sensing period. - ΔVleackage_Dj) by subtracting, to determine the reference charging voltage difference leakage current component is removed (ΔVIref).

The controller 200 determines the reference charging voltage difference (ΔVIref) for each pixel, and the controller 200 stores the determined reference charging voltage difference (ΔVIref) for each pixel in the memory 230.

However, in an embodiment of the present invention, the sensed reference charging voltage difference (ΔVIref) is not recorded in the memory 230 but the sensed reference charging voltage difference (ΔVIref) is stored in the memory 230. The reference voltage Vref for each pixel is increased or decreased according to the comparison result, and the increased or decreased reference voltage Vref for each pixel is stored in the memory 230. Also, in another embodiment of the present invention, the reference voltage Vref for each pixel may have a fixed value, and the memory 230 compares the sensed reference charging voltage difference (ΔVIref) with the target charging voltage difference (ΔVI_target). An offset value for the reference voltage Vref may be stored according to the result.

Specifically, the target charging voltage difference (ΔVI_target) can be shown in “Equation 3” below.

Here, ts corresponds to the time of the ΔVIref voltage sensing section and the time of the leakage current sensing section, and CDATA is the capacitance of the data line DLj. Iref may be a current value for a reference data signal when a plurality of pixels of the display panel 100 perform an ideal operation without a characteristic deviation as a reference current value. For example, a driving current for a data signal corresponding to a maximum grayscale value. Can be a value.

The controller 200 compares the sensed reference charging voltage difference (ΔVIref) with the target charging voltage difference (ΔVI_target), and determines the reference charging voltage smaller than the target charging voltage difference (ΔVI_target) among the reference charging voltage differences (ΔVIref) for each pixel. For a pixel having a difference (ΔVIref), the reference voltage Vref value is reduced to reduce the driving current (IT1) flowing through the pixel, and the target charging voltage difference (ΔVI_target) among the reference charging voltage difference (ΔVIref) for each pixel is reduced. ) For a pixel having a larger reference charging voltage difference (ΔVIref), the reference voltage Vref value is increased to increase the driving current (IT1) flowing through the first transistor T1 of the corresponding pixel. The increased or decreased reference voltage Vref for each pixel is recorded and updated in the memory 230.

Such high gray level sensing is repeatedly performed, the reference voltage Vref for each pixel is cumulatively updated, and the reference charging voltage difference (ΔVIref) for each pixel is repeatedly updated to gradually reach the target charging voltage difference (ΔVI_target). Match close to.

That is, by repeatedly updating the reference voltage Vref for each pixel, the reference current Iref and the sensed drive current (IT1) flowing through the first transistor T1 become the same.

In addition, the current flowing through the first transistor T1 of the pixel Pij can be shown in “Equation 4” below.

Here, μ, Cox, W, and L are the charge mobility of the first transistor T1, the gate capacitance per unit area, the channel width, and the channel length, respectively, which are peculiar characteristic coefficients for each transistor. It can be confirmed that the above equation has removed the threshold voltage Vth component, as compared with “Equation 1” that expresses the driving current of the driving transistor of the pixel described above.

Assuming that the threshold voltage Vth of the first transistor T1 of each pixel has no deviation or a large deviation, the threshold voltage Vth of the first transistor T1 of all pixels in a high gray level sensing operation may be a specific voltage, for example. , 0.3 V, and the reference current Iref shown in the above “equation 4” is determined in the high gradation sensing operation.

Alternatively, considering the deviation of the threshold voltage Vth of the first transistor T1 of each pixel, the threshold voltage Vth of the first driving transistor of each pixel is sensed by the low gray level sensing operation as described above. The threshold voltage Vth component is removed by the reference current determined by the high gradation sensing operation.

When the drive current IT1 flowing through the first transistor T1 sensed by the repeated update of the reference voltage Vref for each pixel and the reference drive current Iref are the same, the updated reference voltage Vref has “Equation 5” such as

Finally, the values stored in the memory 230 are the voltage (V _MEM =Vsus−|Vth|) stored for each pixel and the reference voltage Vref, and these values are continuously updated and the first driving of the pixel is performed. It compensates for changes in the characteristic deviation of the transistor over time.

Hereinafter, a display operation method of the organic light emitting display device that performs the low gradation sensing operation and the high gradation sensing operation will be described with reference to FIG. 7.

FIG. 7 is a timing diagram illustrating a display operation of an organic light emitting diode display according to an exemplary embodiment of the present invention. FIG. 7 illustrates the display operation for the pixels (Pi1 to Pim) connected to the i-th scan line SLi as an example.

Referring to FIGS. 4 and 7, during a display operation of the OLED display device according to an exemplary embodiment of the present invention, the data switch SW_D is turned on, the sensing switch SW_S is turned off, and the sensing voltage SENSE is changed. A high voltage (turn-off voltage) is applied, the third transistor T3 is turned off, and the voltage of the second power supply voltage source ELVSS is sufficiently lower than the voltage of the first power supply voltage source ELVDD.

As shown in FIG. 7, the display operation of the i-th scan line SLi includes an off-bias period, a data writing period, and a light emitting period.

During the off-bias period, the bias voltage maintains the turn-on voltage, the scan voltage SCAN of the i-th scan line maintains the turn-off voltage, and the emission voltage EM maintains the turn-on voltage.

That is, the sixth transistor T6 and the fourth transistor T4 are turned on and the second transistor T2 and the fifth transistor T5 are turned off during the off bias period.

The sensing voltage SENSE maintains a high voltage (turn-off voltage) state during all display operations, and the third transistor T3 maintains a turn-off state during all display operations.

Since the sixth transistor T6 is turned on in the off bias period, the first transistor T1 is in an off bias state, that is, the node S connected to the source terminal of the first transistor T1 and the gate terminal of the first transistor T1 are connected. Since the source-gate voltage Vgs of the first transistor T1 is 0, the first transistor T1 can maintain the turn-off state. In addition, since the fourth transistor T4 is turned on in the off-bias period, all the voltages of the node S connected to the source terminal of the first transistor T1 and the node G connected to the gate terminal of the first transistor T1 are the same. It may be at the same level as the voltage of one power supply voltage source ELVDD.

Next, during the data write period, the bias voltage BIAS is a high voltage (turn-off voltage), the scan voltage SCAN of the i-th scan line SLi is a low voltage (turn-on voltage), and the emission voltage EM is a high voltage (turn-off voltage). ).

That is, the second transistor T2 and the fifth transistor T5 are turned on and the sixth transistor T6 and the fourth transistor T4 are turned off during the data writing period. The third transistor T3 may remain turned off during the entire display operation as previously described.

During the data write period, the data driver 400 may include data output signals DO1 to DOm corresponding to the data signals of the pixels Pi1 to Pim connected to the i-th scan line SLi in the data lines DL1 to DLm. ) Is output, and the data voltage VDATA is applied to the node G connected to the gate terminal of the first transistor T1 of the pixel (Pi1 to Pim) connected to the i-th scanning line SLi.

In addition, since the fifth transistor T5 is turned on during the data writing period, the sustain voltage Vsus is applied to the node S connected to the source terminal of the first transistor T1.

In addition, since the sixth transistor T6 maintains the turn-off state, the storage capacitor CSTG is charged with a voltage equal to the difference between the data voltage VDATA and the sustain voltage Vsus.

At this time, the data voltage VDATA which is applied to each pixel (Pi1~Pim) is determined by using the respective stored voltages _{V MEM} and the reference voltage Vref which is stored in the memory 230, the data voltage VDATA following This can be shown in “Equation 6”.

Here, n is the number of bits that determine the number of gradation levels that can be represented by the pixel, D_data is the gradation level represented by each pixel in the video data, and gamma (γ) is the gamma value. Calibration constant, which can be, for example, 2.2. Also, when a pixel has 256 gray levels, n=8 (8-bit) and D_data may have a value between 0 and 255 depending on the gray level represented by the pixel.

Next, during the light emission period, the bias voltage BIAS is a high voltage (turn-off voltage), the scan voltage SCAN of the i-th scan line SLi is a high voltage (turn-off voltage), and the emission voltage EM is a low voltage (turn-on voltage). Can be

That is, during the data writing period, the second transistor T2 and the second transistor T2, the sixth transistor T6 and the fifth transistor T5 are turned off, and the fourth transistor T4 is turned on. The third transistor T3 remains turned off during the entire display operation, as previously described. The first transistor T1 is turned on according to the applied data voltage Vdata level to provide a driving current to the organic light emitting device.

Since the fourth transistor T4 is turned on during the data writing period, the node S connected to the source terminal of the first transistor T1 is connected to the first power supply voltage source ELVDD and connected to the source terminal of the first transistor T1. The voltage of the node S may be the same as the voltage of the first power supply voltage source ELVDD. The node G connected to the gate terminal of the first transistor T1 is connected to the source terminal of the first transistor T1 at the voltage (VDATA-Vsus) charged across the storage capacitor CSTG in the data write period. The voltage ELVDD applied to S may have an applied voltage level.

That is, the voltage of the node G connected to the gate terminal of the first transistor T1 can be represented by the following “equation 7”.

In the light emission section, the organic light emitting device emits light by the drive current flowing through the first transistor T1, and the drive current flowing through the first transistor T1 at the time of light emission is shown in “Equation 8” below.

At this time, as described above, the reference current Iref corresponds to the drive current at the maximum grayscale light emission when the first transistor T1 of each pixel performs an ideal operation without characteristic deviation. It can be confirmed that the driving current Iemission of the first transistor T1 at that time generates a current that is not related to other characteristic coefficients such as the threshold voltage Vth and the charge mobility. Accordingly, the organic light emitting display panel improves the brightness uniformity of the plurality of pixels of the panel.

Hereinafter, an OLED display device according to another exemplary embodiment of the present invention will be described with reference to FIGS. 8 to 9.

FIG. 8 is a circuit diagram illustrating one pixel of the organic light emitting display panel 100 according to another embodiment of the present invention and a data line, a scan line, and a data switching unit 800 connected to the pixel.

FIG. 9 is a timing diagram illustrating a display operation of an organic light emitting diode display according to another exemplary embodiment of the present invention.

Referring to FIG. 8, a circuit diagram of one pixel Pij of the organic light emitting display panel 100 according to another embodiment of the present invention is shown in FIG. 4 in one pixel of the organic light emitting display panel 100 according to one embodiment of the present invention. It is similar to the circuit diagram of FIG. 4, except that the sixth transistor T6 and the terminal connected to the sixth transistor T6 for providing the bias voltage BIAS are removed.

In the organic light emitting diode display according to an exemplary embodiment of the present invention shown in FIGS. 4 to 6, the bias voltage BIAS maintains a high level (turn-off voltage) in the entire period of the low gradation sensing operation and the high gradation sensing operation. The sixth transistor T6 remains turned off. Therefore, the low gray level sensing operation and the high gray level sensing operation of the organic light emitting diode display according to another embodiment of the present invention shown in FIG. 8 are the same as the low gray level sensing operation and the high gray level sensing operation shown in FIGS. 4 to 6. Therefore, overlapping drawings and description will be omitted.

However, since the display panel 100 of the organic light emitting diode display according to another embodiment of the present invention does not include the sixth transistor T6 that is switched by the bias voltage BIAS, the display operation method of the organic light emitting diode display is shown in FIG. The display operation method of the organic light emitting diode display according to an exemplary embodiment may be different.

Referring to FIG. 9, during a display operation of an organic light emitting display device according to another embodiment of the present invention, the data switch SW_D is turned on, the sensing switch SW_S is turned off, and the sensing voltage SENSE is high. Turn-off voltage), the third transistor T3 is turned off, and the voltage of the second power supply voltage source ELVSS is sufficiently lower than the voltage of the first power supply voltage source ELVDD.

The display operation of the i-th scan line SLi illustrated in FIG. 9 includes an off-bias period, a data writing period, and a light emitting period.

During the off-bias period, the scan voltage SCAN of the i-th scan line SLi maintains a turn-on voltage, and the emission voltage EM maintains a turn-off voltage. In addition, the data driver 400 outputs an off voltage Voff that can turn off the first transistor T1 as a data output signal (DO1 to DOm).

That is, during the off bias period, the second transistor T2 and the fifth transistor T5 are turned on, the fourth transistor T4 is turned off, and the first transistor T1 is turned off.

The sustain voltage Vsus is applied to the node S connected to the source terminal of the first transistor T1.

Then, during the data write period, the scan voltage SCAN of the i-th scan line SLi may be a low voltage (turn-on voltage) and the emission voltage EM may be a high voltage (turn-off voltage).

That is, the second transistor T2 and the fifth transistor T5 are turned on and the fourth transistor T4 is turned off during the data writing period. The third transistor T3 remains turned off during the entire display operation, as previously described.

During the data write period, the data driver 400 may include data output signals DO1 to DOm corresponding to the data signals of the pixels Pi1 to Pim connected to the i-th scan line SLi in the data lines DL1 to DLm. ) Is output, and the data voltage VDATA is applied to the node G connected to the gate terminal of the first transistor T1 of the pixel (Pi1 to Pim) connected to the i-th scanning line SLi.

In addition, since the fifth transistor T5 is turned on and the fourth transistor T4 is turned off during the data writing period, the sustain voltage Vsus is applied to the node S connected to the source terminal of the first transistor T1.

Further, the storage capacitor CSTG is charged at both ends with a voltage corresponding to the difference between the data voltage VDATA and the sustain voltage Vsus.

At this time, the data voltage VDATA which is applied to each pixel (Pi1~Pim) is determined by using the respective stored reference voltage Vref to the voltage _{V MEM} was stored in the memory 230, the data voltage VDATA is below This can be shown in "Equation 6" described earlier.

At this time, n is the number of bits that determine the number of gradation levels that can be represented by the pixel, D_data is the gradation level represented by each pixel in the video data, and gamma (γ) is the gamma value. Calibration constant, which can be, for example, 2.2. Also, when a pixel has 256 gradation levels, n=8 (8-bit), and D_data may have a value between 0 and 255 depending on the gradation represented by the pixel.

Then, during the light emitting period, the scan voltage SCAN of the i-th scan line SLi may be a high voltage (turn-off voltage) and the emission voltage EM may be a low voltage (turn-on voltage).

That is, the second transistor T2 and the second transistor T2, the sixth transistor T6 and the fifth transistor T5 are turned off and the fourth transistor T4 is turned on during the data writing period. The third transistor T3 remains turned off during the entire display operation, as previously described. The first transistor T1 is turned on according to the applied data voltage Vdata level to provide a driving current to the organic light emitting device.

Since the fourth transistor T4 is turned on during the data writing period, the node S connected to the source terminal of the first transistor T1 is connected to the first power supply voltage source ELVDD and connected to the source terminal of the first transistor T1. The voltage of the node S may be the same as the voltage of the first power supply voltage source ELVDD. The node G connected to the gate terminal of the first transistor T1 is connected to the node S connected to the source terminal of the first transistor T1 at the voltage (VDATA-Vsus) charged across the storage capacitor CSTG in the data write period. It may have a voltage level plus the applied voltage ELVDD.

That is, the voltage of the node G connected to the gate terminal of the first transistor T1 can be shown in “Equation 7” described above.

In the light emission period, the organic light emitting device emits light by the drive current flowing through the first transistor T1, and the drive current flowing through the first transistor T1 during light emission can be represented by the above-described “equation 8”.

At this time, as described above, the reference current Iref corresponds to the drive current at the maximum grayscale light emission when the first transistor T1 of each pixel performs an ideal operation without characteristic deviation. It can be confirmed that the driving current Iemission of the first transistor T1 generates a current that is not related to the threshold voltage Vth and other characteristic coefficients such as charge mobility. Accordingly, the organic light emitting display panel 100 may improve the brightness uniformity of a plurality of pixels of the panel.

100 display panel,
200 control unit,
300 scan driver,
400 data driver,
500 voltage ADC,
600 power supply,
700 gradation voltage generation unit,
800 data switch section.

Claims (9)

A display panel including a plurality of pixels respectively connected to a plurality of scan lines and a plurality of data lines,
A scan driver that sequentially applies a plurality of scan signals to the plurality of scan lines;
A data driver that receives a video signal and outputs a plurality of data output signals;
A voltage ADC for receiving an analog sense signal and outputting a digital sense signal,
A data switching unit that connects a plurality of data lines to the data driving unit or connects a plurality of data lines to the voltage ADC in response to a switching signal;
A control unit for receiving the original video data and the digital sense signal, processing the original video data into a video signal based on the digital sense signal, providing the processed data to the data driving unit, and providing a switching signal to the data switching unit; Including,
a) In the first initialization period, the data switching unit connects the plurality of data lines to the data driving unit, the data driving unit applies an initialization voltage to the connected data lines,
b) a first sensing period, the plurality of at least one pixel connected to the i th scan line of the scan lines are connected to at least one data line among the plurality of data lines, and the plurality of among the data lines to charge the first voltage to at least one of the data lines, the data switching unit connects said voltage ADC to the plurality of data lines, said voltage ADC as analog sense signals from the connected data lines Receiving a first voltage, converting an analog sense signal corresponding to the first voltage into a digital sense signal and outputting the digital sense signal to the controller,
c) In the second initialization section, the data switching unit connects the plurality of data lines to the data driving unit, and the data driving unit applies an initialization voltage to the connected data lines,
d) In the second sensing period, the at least one pixel connected to the i-th scan line is cut off from the at least one data line, and the voltage applied to the data line is a reset voltage to a second voltage. The data switching unit disconnects the plurality of data lines from the data driving unit and connects the voltage ADC to the plurality of data lines, and the voltage ADC is connected to the second data line from the connected data lines. Receiving a voltage, converting an analog sense signal corresponding to the second voltage into a digital sense signal and outputting the digital sense signal to the controller,
The controller is configured to add the initialization voltage to a voltage obtained by subtracting the second voltage from the first voltage based on the digital sense signal corresponding to the first voltage and the digital sense signal corresponding to the second voltage. To determine,
Organic light emitting display device. The OLED display of claim 1, wherein the first initialization section, the first sensing section, the second initialization section, and the second sensing section are located within a period in which an image of one frame is displayed. .. The OLED display of claim 1, wherein the first sensing section and the second sensing section have the same length. At least one pixel of the plurality of pixels includes first to fifth transistors, and the first to fifth transistors are PMOS transistors.
The node connected to the source terminal of the first transistor is connected to the drain terminal of the fourth transistor, the source terminal of the first transistor is connected to the first power supply voltage source via the fourth transistor, and the drain terminal of the first transistor The node connected to is connected to the anode of the organic light emitting element, the cathode of the organic light emitting element is connected to the second power supply voltage source,
The drain terminal of the second transistor is connected to the node connected to the gate terminal of the first transistor, the source terminal of the second transistor is connected to at least one data line, and the gate terminal of the second transistor is connected to one scan line. Connected,
The source terminal of the third transistor is connected to the node connected to the drain terminal of the first transistor, the drain terminal of the third transistor is connected to at least one data line, and the sensing voltage is connected to the gate terminal of the third transistor. Was
The drain terminal of the fourth transistor is connected to the node connected to the source terminal of the first transistor, the source terminal of the fourth transistor is connected to the first power supply voltage source, and the gate terminal of the fourth transistor is connected to the emission voltage. ,
The source terminal of the fifth transistor is connected to the sustain voltage, the drain terminal of the fifth transistor is connected to the node connected to the source terminal of the first transistor, and the gate terminal of the fifth transistor is connected to the one scan line. The organic light emitting display device according to claim 1. At least one pixel of the plurality of pixels further includes a sixth transistor,
The source terminal of the sixth transistor is connected to the node connected to the source terminal of the first transistor, the drain terminal of the sixth transistor is connected to the node connected to the gate terminal of the first transistor, and the gate of the sixth transistor is connected. The OLED display of claim 4, wherein the terminal is connected to a bias voltage. At least one pixel of the plurality of pixels further includes a storage capacitor having both ends connected between a node connected to a source terminal of the first transistor and a node connected to a gate terminal of the first transistor. Item 5. The organic light-emitting display device according to item 4. e) In the third initialization period, the data switching unit connects the plurality of data lines to the data driving unit, the data driving unit applies an initialization voltage to the connected data lines,
f) In the third sensing period, at least one pixel charges at least one data line with a third voltage, the data switching unit connects the voltage ADC to the plurality of data lines, and the voltage ADC is connected. Receiving a third voltage as an analog sense signal from the data line, converting the analog sense signal corresponding to the third voltage into a digital sense signal, and outputting the digital sense signal to the controller.
g) In the fourth initialization period, the data switching unit connects the plurality of data lines to the data driving unit, disconnects the plurality of data lines from the voltage ADC, and the data driving unit connects the connected data. Applying an initializing voltage to the line, the connected data line is disconnected from the at least one pixel,
h) In the fourth sensing period, the connected data line remains disconnected from the at least one pixel, and the initialization voltage charged in the data line in the fourth initialization period is: The voltage leaked to the at least one pixel connected to the data line and applied to the data line changes from an initialization voltage to a fourth voltage, and the data switching unit drives the data lines to drive the data. And disconnecting the voltage ADC and connecting the voltage ADC to the plurality of data lines, the voltage ADC receiving a fourth voltage from the connected data lines, and outputting an analog sense signal corresponding to the fourth voltage to the digital sense signal. And output to the control unit,
(I) In the reference voltage write section preceding the third initialization section, the control unit generates a voltage signal obtained by subtracting a reference voltage from the predetermined voltage corresponding to each of the plurality of data lines, and A voltage signal obtained by subtracting a reference voltage from the predetermined voltage corresponding to each of the plurality of data lines is output as a data output signal, and a data signal corresponding to the data output signal corresponding to each of the plurality of data lines is output. Each of the plurality of data lines and a gate terminal of a first transistor of a pixel connected to each of the plurality of data lines, and a sustain voltage is applied to a source terminal of the first transistor,
According to the reference voltage writing period, the third initialization period, the third sensing period, the fourth initialization period, and the fourth sensing period, the controller controls the digital sense signal corresponding to the third voltage. The OLED display of claim 1, wherein a correction reference value is generated based on a digital sense signal corresponding to the fourth voltage and a data signal corresponding to the data output signal. The first initialization section, the first sensing section, the second initialization section, the second sensing section, the reference voltage writing section, the third initialization section, the third sensing section, the fourth initialization. The OLED display of claim 7, wherein the section and the fourth sensing section are located within a period in which an image of one frame is displayed. The OLED display of claim 7, wherein the first sensing section and the second sensing section have the same length, and the third sensing section and the fourth sensing section have the same length.