JP6628837B2 - Electronics - Google Patents

Description

The present invention relates to a driving circuit of a display device. Further, the invention includes an electronic device manufactured using the driving circuit of the display device. Note that in this specification, a display device includes a liquid crystal display device including a liquid crystal element in a pixel and a light-emitting display device including self-luminous elements such as an organic electroluminescence (EL) element. A driving circuit refers to a circuit which performs processing for inputting a video signal to a pixel arranged in a display device and performing video display, and includes a pulse circuit including a shift register, an amplifier, and the like. It shall include an amplifier circuit.

2. Description of the Related Art In recent years, a display device in which a semiconductor thin film is formed over an insulator, particularly a glass substrate, particularly an active matrix display device using a thin film transistor (hereinafter, referred to as a TFT) has become remarkable. An active matrix type display device using TFTs has hundreds of thousands to millions of pixels arranged in a matrix, and displays images by controlling the charge of each pixel by the TFT arranged in each pixel. It is carried out.

As a more recent technology, in addition to a pixel TFT constituting a pixel, a TF is provided around a pixel portion.
Technology related to polysilicon TFTs in which drive circuits are simultaneously formed using T has been developed, and has greatly contributed to miniaturization and low power consumption of devices. Display devices have become indispensable devices for display units and the like.

As a driving circuit of a display device, a CMOS circuit combining an N-type TFT and a P-type TFT is generally used. As a feature of the CMOS circuit, the logic changes (from Hi potential to Lo).
The current flows only at the moment (from the Lo potential to the Hi potential), and does not flow while a certain logic is held (actually, there is a small leak current). Can be reduced, and there is an advantage in high-speed driving.

Demand for display devices using liquid crystals and self-luminous elements is rapidly increasing with the miniaturization and weight reduction of mobile electronic devices.However, from the viewpoint of yield, etc., the manufacturing cost is sufficiently low. Difficult to control. It is easily anticipated that demand in the future will increase even more rapidly, and it is therefore desirable to be able to supply display devices at lower cost.

As a method for manufacturing a driver circuit over an insulator, using a plurality of photomasks, an active layer,
It is common to create patterns by exposing and etching wiring and other patterns, but since the number of steps at this time directly affects the manufacturing cost, manufacturing is performed with as few steps as possible. Ideally. In view of this, a driving circuit conventionally constituted by a CMOS circuit is constituted by using only N-type or P-type TFTs of only one conductivity type. With this method, part of the ion doping step can be omitted, and the number of photomasks can be reduced.

(Problems of the technology before the present invention)
FIG. 9A shows an example of a CMOS inverter (I) conventionally used generally and inverters (II) and (III) configured using TFTs of only one polarity. (II) is TFT
A load type inverter, (III) is a resistance load type inverter. Hereinafter, each operation will be described.

FIG. 9B shows a waveform of a signal input to the inverter. Here, the input signal amplitude is between VDD and GND (GND <VDD). Specifically, it is assumed that GND = 0 [V].

The circuit operation will be described. In addition, in order to make the description clear and simple, N
The threshold voltage of the TFT is uniform (VthN) assuming that there is no variation. The same applies to the P-type TFT (VthP).

When a signal as shown in FIG. 9B is input to the CMOS inverter, the potential of the input signal becomes Hi.
At (VDD), the P-type TFT 901 is turned off and the N-type TFT 902 is turned on, so that the potential of the output node becomes Lo (GND). Conversely, when the potential of the input signal is Lo, P
When the type TFT 901 is turned on and the N-type TFT 902 is turned off, the potential of the output node becomes Hi (FIG. 9C).

Next, the operation of the TFT load type inverter (II) will be described. Similarly, consider a case where a signal as shown in FIG. 9B is input. First, when the input signal is Lo, the N-type TFT 9
04 is turned off. On the other hand, since the load TFT 903 is always performing a saturation operation, the potential of the output node is raised in the Hi direction. On the other hand, when the input signal is Hi, the N-type TFT 904
Turns ON. Here, by setting the current capability of the N-type TFT 904 sufficiently higher than the current capability of the load TFT 903, the potential of the output node is lowered in the Lo direction.

Similarly, for the resistance load type inverter (III), the ON resistance value of the N-type TFT 906 is calculated as follows.
By setting the resistance sufficiently lower than the resistance value of the load resistor 905, when the input signal is Hi, the N-type TFT 906 is turned ON, so that the output node is pulled down in the Lo direction. When the input signal is Lo, the N-type TFT 906 is turned off, and the output node is pulled up in the Hi direction.

However, there are the following problems when using a TFT load type inverter or a resistance load type inverter. FIG. 9D shows an output waveform of the TFT load type inverter.
When the output is Hi, the potential is lower than VDD by the amount indicated by 907. Load TFT90
In 3, if the terminal on the output node side is the source and the terminal on the power supply VDD side is the drain, the gate electrode and the drain region are connected, and the potential of the gate electrode at this time is VDD. Also, the condition for this load TFT to be ON is (the voltage between the gate and the source of the TFT 903> VthN), so that the potential of the output node is (VDD−VthN) at the maximum.
) Only to rise. That is, 907 is equal to VthN. Further, the load TFT 903
Depending on the ratio of the current capability of the N-type TFT 904 to the current capability, when the output potential is Lo potential, the potential becomes higher than GND by the amount indicated by 908. To make this sufficiently close to GND, the load T
The current capability of the N-type TFT 904 needs to be sufficiently larger than that of the FT 903. Similarly, FIG. 9E shows the output waveform of the resistive load type inverter.
909 and the ON resistance of the N-type TFT 906, the potential is increased by the amount indicated by 909. That is, when an inverter constituted by using a TFT having only one polarity shown here is used, the amplitude of the output signal is attenuated with respect to the amplitude of the input signal. In order to constitute a drive circuit, an output must be obtained without attenuating the amplitude.

The present invention has been made in view of the above problems, and can be manufactured at low cost by reducing the number of manufacturing steps using TFTs of only one polarity, and can produce an output without amplitude attenuation. It is an object of the present invention to provide a driving circuit of a display device which can be obtained.

In the TFT load type inverter shown in (II) of FIG. 9A, a condition for the amplitude of the output signal to be normally VDD-GND is considered. First, in the circuit shown in FIG. 1A, when the potential of the output signal is Lo, in order to sufficiently bring the potential close to GND, the resistance between the power supply VDD and the output node needs to be increased. It is sufficient that the resistance value between the GND and the output node is sufficiently low. That is, while the N-type TFT 102 is ON, the N-type TFT
It is sufficient that 101 is turned off. Second, when the potential of the output signal becomes Hi, the absolute value of the gate-source voltage of the N-type TFT 101 becomes Vth so that the potential becomes equal to VDD.
It is only necessary to always exceed N. That is, in order to satisfy the condition that the Hi potential of the output node becomes VDD, the potential of the gate electrode of the N-type TFT 101 needs to be higher than (VDD + VthN). Since only two types of power are supplied to the circuit, VDD and GND, the condition cannot be satisfied unless there is a third power having a higher potential than VDD.

Therefore, the present invention takes the following measures. As shown in FIG.
A capacitor 103 is provided between the gate and the source of 101. When the potential of the output node is increased when the gate electrode of the N-type TFT 101 is in a floating state at a certain potential, the capacitance 103
, The potential of the gate electrode of the N-type TFT 101 is also raised with the potential rise of the output node. By utilizing this effect, the potential of the gate electrode of the N-type TFT 101 can be made higher than VDD (more precisely, higher than VDD + VthN). Therefore, the potential of the output node can be sufficiently raised to VDD.

Note that the capacitor 103 shown in FIG. 1B may be actually manufactured as a capacitor portion,
A parasitic capacitance between the gate and the source of the TFT 101 may be used.

  The configuration of the present invention is described below.

According to the first aspect of the present invention, there is provided a drive circuit of a display device according to the present invention, wherein the first transistor has the first impurity region electrically connected to the first power supply, and the first impurity region has the second impurity region. A second transistor electrically connected to the first power supply; a third transistor electrically connected to the first impurity region with the first power supply; and a second power supply electrically connected to the first impurity region. A drive circuit for a display device having a fourth transistor and a capacitor electrically connected to the first transistor, wherein
The fourth to fourth transistors are of the same conductivity type, and the second transistor of the first transistor
And the second impurity region of the second transistor are both electrically connected to one terminal of the capacitor, and the second impurity region of the third transistor is connected to the fourth impurity region of the fourth transistor. The second impurity region of the transistor and the gate electrode of the first transistor are both electrically connected to another terminal of the capacitor, and the gate electrode of the second transistor is connected to the fourth electrode of the fourth transistor. The gate electrode of the transistor is electrically connected to the input signal line,
The gate electrode of the third transistor is electrically connected to the first power supply.

According to a second aspect of the present invention, in the drive circuit of the display device according to the present invention, the first transistor has the first impurity region electrically connected to the first power supply, and the first impurity region has the second impurity region. A second transistor electrically connected to the first power supply; a third transistor electrically connected to the first impurity region with the first power supply; and a second power supply electrically connected to the first impurity region. A driving circuit of a display device having a fourth transistor and a capacitor electrically connected to the first transistor, wherein the first to fourth transistors are all of the same conductivity type; The second impurity region and the second impurity region of the second transistor are both electrically connected to one terminal of the capacitor, and the second impurity region of the third transistor is connected to the second impurity region. Second impurity region of transistor 4 A gate electrode of the first transistor,
Both are electrically connected to the other terminal of the capacitor, the gate electrode of the second transistor and the gate electrode of the fourth transistor are electrically connected to a first input signal line, A gate electrode of the third transistor is electrically connected to a second input signal line.

According to a third aspect of the present invention, in the driving circuit of the display device according to the second aspect of the present invention, in the second aspect, the second input signal line receives an inverted signal of a signal input to the first input signal line. Signal lines.

According to a fourth aspect of the present invention, in the driving circuit of the display device according to the first aspect of the present invention, in the first or the second aspect, the capacitor is connected to any one of the gate electrode of the first transistor and the impurity region. It is characterized by using a capacity between the two.

According to a fifth aspect of the present invention, in the driving circuit of the display device according to the first aspect of the present invention, the capacitance is any one of an active layer material, a material forming a gate electrode, and a wiring material. It is characterized in that the capacitor is formed using two materials.

According to a sixth aspect of the present invention, in the driving circuit for a display device according to the present invention, in any one of the first to fifth aspects, the one conductivity type is an N-channel type.

According to a seventh aspect of the present invention, in the driving circuit for a display device according to the present invention, in any one of the first to fifth aspects, the one conductivity type is a P-channel type.

According to claim 8, in the drive circuit of the display device according to the present invention, in claim 6, the potential when the input signal is Hi potential is equal to the third power supply potential, and the potential when the input signal is Lo potential is the third power supply potential. When the power supply potential is equal to the fourth power supply potential, the second power supply potential ≦ the fourth power supply potential <the third power supply potential ≦ the first power supply potential
Is satisfied.

According to a ninth aspect of the present invention, in the driving circuit of the display device according to the seventh aspect, the potential when the input signal is the Hi potential is equal to the third power supply potential, and the potential when the input signal is the Lo potential is the third potential. When the first power supply potential ≦ the fourth power supply potential <the third power supply potential ≦ the second power supply potential
Is satisfied.

According to the tenth aspect, the driving circuit of the display device of the present invention includes the first to ninth aspects.
Wherein the driving circuit of the display device is an inverter, a buffer, or a level shifter, or is a component of the inverter, the buffer, or the level shifter.

With the display device driving circuit of the present invention, the driving circuit and the pixel portion of the display device can be formed using only one-conductivity type TFTs. By reducing the number of manufacturing steps of the display device, cost reduction and yield can be achieved. And it is possible to supply the display device at lower cost.

FIG. 4 illustrates an operation principle of a driving circuit of a display device of the present invention. FIG. 3 is a diagram showing an inverter which is a basic form of a drive circuit of a display device of the present invention and waveforms of input / output signals thereof. FIG. 4 is a diagram illustrating a connection example in the case where a plurality of stages of inverters, which are basic forms of a drive circuit of a display device of the present invention, are connected and used. FIG. 3 is a diagram showing a level shifter shown as an example of a drive circuit of a display device of the present invention and waveforms of input / output signals thereof. 3A and 3B are diagrams illustrating an operation of a level shifter and a configuration example of the level shifter. FIG. 4 is a diagram showing a configuration example of a two-input type level shifter having an inversion signal. 1 is a schematic view of a display device manufactured by applying the present invention. FIG. 9 illustrates an example in which a drive circuit of a display device of the present invention is applied to an electronic device. The figure which shows the structure of a conventional type CMOS inverter and a load type inverter, and the waveform of each input / output signal. FIG. 4 illustrates input signals and circuit operations in a 4-TFT inverter and a 3-TFT inverter.

FIG. 2A illustrates one embodiment of a driving circuit of a display device of the present invention, which is a circuit functioning as an inverter. The circuit includes N-type TFTs 201 to 204 and a capacitor 205, and a portion surrounded by a dotted frame 206 corresponds to the circuit illustrated in FIG. A portion surrounded by a dotted frame 210 constitutes an output amplitude compensation circuit. The output amplitude compensating circuit 210 is intended to create a floating state in the gate electrode of the N-type TFT 203, and has the same function as shown in FIG.
The configuration is not limited to this.

In the circuit in FIG. 2A, an input signal is input to the gate electrodes of the N-type TFT 202 and the N-type TFT 204. The N-type TFT 201 functions as a load, and the N-type TFT 201, 20
2 (this node is denoted by α in FIG. 2A) is input to the gate electrode of the N-type TFT 203.

The details of the operation of the circuit will be described step by step. The power supply potentials are VDD and GND,
The amplitude of the input signal is also set to VDD (Hi) -GND (Lo). First, the potential of the input signal is Hi.
At this time, the N-type TFTs 202 and 204 are turned on. Here, the N-type TFT 201 operates in saturation because the gate electrode and the drain region are connected to each other. However, by making the current capability of the N-type TFT 202 sufficiently higher than the current capability of the N-type TFT 201, the node α Is pulled down to the GND side. As a result, the N-type TFT 203 is turned off, and the Lo potential is output to the output node.

Subsequently, when the potential of the input signal is Lo, the N-type TFTs 202 and 204 are turned off. As a result, the potential of the node α is raised to the VDD side, and the potential becomes (VDD−VthN).
When it becomes, it temporarily floats. On the other hand, when the potential of the node α starts to rise, the N-type TFT 203 is turned on soon, and the potential of the output node is raised to the VDD side. When the node α is in a floating state, the potential of the output node is still rising, so that the N-type TFT 20
The presence of the gate-source capacitor 205 of No. 3 causes the potential of the node α in a floating state to rise with the rise of the potential of the output node. As a result, the potential of the node α becomes (VDD + Vth
The potential can be higher than N). Therefore, the Hi potential is output to the output node,
The potential at this time becomes equal to VDD.

With the above operation, the amplitude of the output signal can be obtained without attenuating the amplitude of the input signal. Such a method of raising the potential by utilizing the capacitive coupling between two points is called a bootstrap method. FIG. 2B shows a waveform of an input signal of the circuit shown in FIG. 2A, and FIG. 2C shows a waveform of a potential at the node α. (D) shows the waveform of the output signal. In FIG. 2C, the potential indicated by 208 is higher than VDD by VDD.
The potential at the node α is increased by the amount indicated by 207 by the bootstrap. As a result, as shown in FIG. 2D, when the output node is at the Hi potential, the potential rises to VDD, and an output signal having an amplitude between VDD and GND can be obtained.

By the way, in the drive circuit of the display device of the present invention, amplitude compensation of an output signal by a bootstrap method is basically performed, and at this time, a gate electrode of a TFT utilizing capacitive coupling is in a floating state. Is assumed. FIG. 10 illustrates a configuration example of a circuit using the bootstrap method. FIG. 10A illustrates a basic configuration of a driving circuit of a display device of the present invention. Thus, the potential of the node α is raised by using the gate-source capacitance 1005 of the TFT 1003, thereby compensating the amplitude of the output signal. FIG. 10B shows a circuit including three TFTs. Similarly, since the node β is in a floating state, a node using the gate-source capacitance 1009 of the TFT 1007 is used. The potential of β is raised, thereby compensating for the amplitude of the output signal.

Next, the amplitude of the input signal and the power supply potential will be considered. Now, the power supply potential on the high potential side is VDD.
, The power supply potential on the low potential side is GND, the amplitude of the input signal (in) is VDD-GND, and inb is an inverted signal of the input signal. Here, the amplitudes of in and inb are VDD3
Consider the state of the nodes α and β when −GND (however, GND <VthN <VDD3 <VDD−VthN). In FIG. 10A, when inb is Hi, N
The gate electrode potential of the type TFT 1001 becomes VDD3. Since VthN <VDD3,
The N-type TFT 1001 is turned on, the potential of the node α is pulled up to the VDD side, and the potential becomes (
(VDD3-VthN), it becomes a floating state. That is, the Hi potential of inb is V
If it exceeds thN, the node α can surely be in a floating state, and an operation of raising the gate electrode potential of the N-type TFT 1003 by bootstrap becomes possible. on the other hand,
In FIG. 10B, since the gate electrode potential of the N-type TFT 1006 is always VDD, when inb is Hi, the potential of the node β is raised to VDD3. But now VD
Since D3 <VDD−VthN, the N-type TFT 1006 is always on regardless of the potential of the input signal. Therefore, the node β does not enter a floating state. Therefore, the potential of node β cannot be raised by bootstrap. That is, FIG.
In the case of the circuit shown in (1), in order for the node β to be in a floating state, when the Lo potential of inb is GND, there is a minimum condition that at least the Hi potential is equal to or higher than (VDD−VthN). It is disadvantageous in view of variations in TFT characteristics.

Thus, under certain conditions when the amplitude of the input signal is smaller than the power supply voltage,
In the configuration shown in FIG. 10B, it is possible that a floating state cannot be given to the node β. On the other hand, in the configuration shown in FIG. There is a merit that can be in the state.

  Hereinafter, examples of the present invention will be described.

FIG. 3A illustrates a circuit in which a plurality of inverters, which are one mode of a driver circuit of a display device of the present invention, are connected. Such a circuit is often used as a buffer in a drive circuit or the like of a display device. Here, when a circuit as shown in FIG. 3A is used, the following disadvantages can be given.

In FIG. 3A, when the input signal is Hi, the N-type TFT 302 is turned on.
Here, the N-type TFT 301 functions as a load with a short circuit between the gate and the drain,
Since the saturation operation is always performed, when the N-type TFT 302 is turned on, VDD-GND
A through current flows between them. The same applies to the TFTs 303, 304 and 305, 306 in each stage, and the current consumption increases.

As an example for avoiding such a problem, there is a method using a two-input inverter as shown in FIG. In the case of such a circuit, since the TFTs arranged between VDD and GND perform an exclusive operation because the polarities of the input signals are always reversed, no through current flows.

However, in the case of using the circuit in FIG. 3B, it is necessary to prepare inverted and non-inverted two-phase signals as input signals.

Therefore, as a combined form, as shown in FIG. 3C, the one-input type inverter of the present invention is used in the first stage, and the two-input type inverter is used in the second and subsequent stages. As for the input of the second stage, the output signal of the previous stage may be input to one side, and the input signal of the previous stage may be input to the other side. Thus, it can be used as a buffer of a one-input type and in which a through current is minimized.

The drive circuit of the display device of the present invention can easily function as a level shifter by giving a potential different from the amplitude potential of an input signal as a power supply potential supplied to the circuit. An example is shown below.

First, three potentials of GND, VDD1, and VDD2 are considered as power supply potentials, and the magnitude relation between them is set to GND <VDD1 <VDD2. At this time, a case where a signal having an amplitude between GND and VDD1 is input, converted into an amplitude between GND and VDD2, and extracted is considered as an example.

FIG. 4A shows an example. The configuration of the circuit may be the same as that of the embodiment and the first embodiment.
The amplitude of the input signal is between GND and VDD1, and the potential of the power supply connected to one end of the impurity region of the N-type TFTs 401 and 403 is VDD2.

The operation of the circuit will be described. FIG. 4B shows the waveform of the input signal. GND-VDD1
A signal having an amplitude between them is input to the gate electrodes of the N-type TFTs 402 and 404. When the input signal is at the Hi potential, the N-type TFTs 402 and 404 are turned on, the potential at the node α is pulled down to the GND side, and the N-type TFT 403 is turned off. Therefore, the potential at the output node becomes Lo potential.

When the input signal is at the Lo potential, the N-type TFTs 402 and 404 are turned off, and the potential at the node α is raised to the VDD2 side. Therefore, the N-type TFT 403 is turned on, and the potential of the output node rises. On the other hand, at the node α, the potential becomes (VDD2-N type TFT).
(Absolute value of the threshold voltage of 403), it becomes a floating state. Thereafter, as the potential of the output node rises, the potential of the node α is further raised by the capacitive coupling 405 existing between the gate and the source of the N-type TFT 403, and takes a potential higher than VDD2 (FIG. 4C).
). Therefore, the potential of the output node becomes Hi potential, and a signal having an amplitude between GND and VDD2 is output (the solid line in FIG. 4D).

The reason that the circuit shown in this embodiment can be easily handled as a level shifter is that the gate electrodes of the TFTs 401 and 403 connected to the high-potential-side power supply (VDD2) do not have a signal input with a low voltage amplitude. Can be In the two-input circuit shown in FIG. 5A, even when a low-voltage amplitude signal is input to the TFT 501 connected to the high-potential-side power supply (VDD2), the node β
Can only rise to near VDD1. Therefore, the TFT 503 cannot be sufficiently turned on, and the gate electrode potential of the TFT 503 cannot be raised using capacitive coupling, so that normal operation cannot be expected.

Therefore, when the load imposed immediately after the level shifter shown in this embodiment is large and a configuration such as a buffer is required, two stages of one-input type circuits are used as shown in FIG. All subsequent input signal amplitudes must be high voltage amplitudes. In FIG. 5B, a TFT to which a signal with a low voltage amplitude is input is limited to a portion of the TFT surrounded by a dotted frame 506. Both inputs (inputs to the gate electrodes of the TFTs 507 and 508) can operate normally because a signal with a high voltage amplitude is input.

When a signal to be subjected to amplitude conversion has an inverted signal, a configuration may be used in which the mutual output signal is used as the inverted input of the next stage. FIG. 6 shows an example. Input signals are in and inb, and are input to the gate electrodes of the TFTs 602 and 614, respectively.
The output of the first stage 650 of the level shifter is input to the TFTs 606 and 617 of the second stage,
Is input to the second-stage TFTs 605 and 618. Since the input signals to the second stage are all signals with a high voltage amplitude, they thereafter normally function as buffers, and output signals Out and outb are obtained from the final stage.

In this embodiment, an example in which a display device is manufactured using a driver circuit of the display device of the present invention will be described.

FIG. 7 is a schematic diagram of a display device. A source signal line driver circuit 701, a gate signal line driver circuit 702, and a pixel portion 703 are formed over a substrate 700 by integral formation. In the pixel portion, a portion surrounded by a dotted frame 710 is one pixel. In the example of the figure, a pixel of a liquid crystal display device is shown, and electric charge applied to one electrode of a liquid crystal element is controlled by one TFT (hereinafter, referred to as a pixel TFT). Signal input to the source signal line driver circuit 701 and the gate signal line driver circuit 702 is performed by a flexible print circuit (Flexible Print Circuit: FPC).
) 704 from outside.

The display device described in this embodiment is configured using the drive circuit of the display device of the present invention so that the drive circuit forming the entire display device including the pixel portion has one polarity having the same polarity as the pixel TFT. (For example, an N-type TFT). This makes it possible to omit the ion doping step of giving a P-type to the semiconductor layer, thereby contributing to a reduction in manufacturing cost and an improvement in yield.

Although the polarity of the TFT constituting the display device of this embodiment is N-type, it is of course possible by the present invention to configure the drive circuit and the pixel TFT using only the P-type TFT. In this case, note that the omitted ion doping step is a step of giving an N-type to the semiconductor layer. Further, the present invention can be applied not only to a liquid crystal display device but also to any device which is manufactured by integrally forming a drive circuit on an insulator.

The drive circuit of the display device of the present invention can be applied to manufacture of display devices used in various electronic devices. Such electronic devices include a portable information terminal (electronic notebook, mobile computer, mobile phone, etc.), a video camera, a digital camera, a personal computer, a television, a mobile phone, and the like. FIG. 8 shows an example of them.

FIG. 8A illustrates a liquid crystal display (LCD), which includes a housing 3001, a support 3002, a display portion 3003, and the like. The driving circuit of the display device of the present invention includes the display portion 3003
It can be applied to the production of

FIG. 8B illustrates a video camera, which includes a main body 3011, a display portion 3012, and a sound input portion 301.
3, an operation switch 3014, a battery 3015, an image receiving unit 3016, and the like. The driver circuit of the display device of the present invention can be applied to manufacturing the display portion 3012.

FIG. 8C illustrates a laptop personal computer, which includes a main body 3021 and a housing 3022.
, A display unit 3023, a keyboard 3024, and the like. The driver circuit of the display device of the present invention can be applied to manufacturing the display portion 3023.

FIG. 8D illustrates a portable information terminal, which includes a main body 3031, a stylus 3032, and a display portion 303.
3, an operation button 3034, an external interface 3035, and the like. The driver circuit of the display device of the invention can be applied to the manufacturing of the display portion 3033.

FIG. 8E illustrates a sound reproducing device, specifically, an audio device for a vehicle.
, A display unit 3042, operation switches 3043, 3044, and the like. The driver circuit of the display device of the present invention can be used for manufacturing the display portion 3042. In this embodiment, the in-vehicle audio device is described as an example, but the present invention may be applied to a portable or home audio device.

FIG. 8F illustrates a digital camera, which includes a main body 3051, a display unit (A) 3052, and an eyepiece unit 3.
053, an operation switch 3054, a display portion (B) 3055, a battery 3056, and the like. The drive circuit of the display device of the present invention includes a display unit (A)
3052 and the display portion (B) 3055 can be applied.

FIG. 8G illustrates a mobile phone, which includes a main body 3061, an audio output unit 3062, and an audio input unit 306.
3, a display unit 3064, operation switches 3065, an antenna 3066, and the like. The driver circuit of the display device of the present invention can be applied to the manufacture of the display portion 3064.

It should be noted that the example shown in this embodiment is merely an example, and the present invention is not limited to these applications.

Claims (2)

A pixel and a driving circuit,
The driving circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. A transistor and a capacitor ,
The pixel has a ninth transistor,
A conductivity type of the first transistor, a conductivity type of the second transistor, a conductivity type of the third transistor, a conductivity type of the fourth transistor, and a conductivity type of the fifth transistor; The conductivity type of the sixth transistor, the conductivity type of the seventh transistor, the conductivity type of the eighth transistor, and the conductivity type of the ninth transistor are the same,
One of a source and a drain of the first transistor is electrically connected to a gate of the third transistor,
One of a source and a drain of the second transistor is electrically connected to a gate of the third transistor,
One of a source and a drain of the third transistor is electrically connected to a gate of the eighth transistor,
One of a source and a drain of the fourth transistor is electrically connected to a gate of the eighth transistor,
One of a source and a drain of the fifth transistor is electrically connected to a gate of the seventh transistor,
One of a source and a drain of the sixth transistor is electrically connected to a gate of the seventh transistor,
One of a source and a drain of the seventh transistor is electrically connected to one of a source and a drain of the eighth transistor,
A first electrode of the capacitor is electrically connected to a gate of the seventh transistor;
A second electrode of the capacitor is electrically connected to one of a source and a drain of the seventh transistor;
A gate of the first transistor is electrically connected to a first wiring;
A gate of the second transistor is electrically connected to a second wiring;
The first wiring has a function of supplying a first signal to a gate of the first transistor,
The second wiring has a function of supplying a second signal to a gate of the second transistor,
A gate of the second transistor is electrically connected to a gate of the fourth transistor;
A gate of the second transistor is electrically connected to a gate of the fifth transistor;
An electronic device in which a gate of the sixth transistor is electrically connected to a gate of the eighth transistor,
An electronic device having a period in which the polarity of the first signal is opposite to the polarity of the second signal. A pixel and a driving circuit,
The driving circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. A transistor and a capacitor ,
The pixel has a liquid crystal element and a ninth transistor,
A conductivity type of the first transistor, a conductivity type of the second transistor, a conductivity type of the third transistor, a conductivity type of the fourth transistor, and a conductivity type of the fifth transistor; The conductivity type of the sixth transistor, the conductivity type of the seventh transistor, the conductivity type of the eighth transistor, and the conductivity type of the ninth transistor are the same,
One of a source and a drain of the first transistor is electrically connected to a gate of the third transistor,
One of a source and a drain of the second transistor is electrically connected to a gate of the third transistor,
One of a source and a drain of the third transistor is electrically connected to a gate of the eighth transistor,
One of a source and a drain of the fourth transistor is electrically connected to a gate of the eighth transistor,
One of a source and a drain of the fifth transistor is electrically connected to a gate of the seventh transistor,
One of a source and a drain of the sixth transistor is electrically connected to a gate of the seventh transistor,
One of a source and a drain of the seventh transistor is electrically connected to one of a source and a drain of the eighth transistor,
A first electrode of the capacitor is electrically connected to a gate of the seventh transistor;
A second electrode of the capacitor is electrically connected to one of a source and a drain of the seventh transistor;
A gate of the first transistor is electrically connected to a first wiring;
A gate of the second transistor is electrically connected to a second wiring;
The first wiring has a function of supplying a first signal to a gate of the first transistor,
The second wiring has a function of supplying a second signal to a gate of the second transistor,
A gate of the second transistor is electrically connected to a gate of the fourth transistor;
A gate of the second transistor is electrically connected to a gate of the fifth transistor;
An electronic device in which a gate of the sixth transistor is electrically connected to a gate of the eighth transistor,
An electronic device having a period in which the polarity of the first signal is opposite to the polarity of the second signal.

Images