JP6318061B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device including a power conversion switching element used in a power conversion device.

  Conventionally, as a technique for reducing the switching loss of a power conversion switching element, there has been a technique in which a trench gate is divided into a set of two gates and each is driven by a different control signal (see, for example, Patent Document 1).

International Publication No. 2014/038064

  In recent years, switching elements for power conversion, such as IGBTs (Insulated Gate Bipolar Transistors), have come to be widely applied from low-power devices such as home air conditioners and microwave ovens to high-power devices in railways and steelworks. It was. In order to promote the use of renewable energy and energy conservation, power conversion from direct current to alternating current or from alternating current to direct current is indispensable. It is an important key component to realize.

  By the way, when a switching element for power conversion such as IGBT is applied to a power conversion inverter device or the like, a conduction loss associated with an on-resistance occurs during conduction, and a switching loss associated with a switching operation occurs during switching. Therefore, in order to increase the efficiency and size of the inverter, it is necessary to reduce conduction loss and switching loss.

  Patent Document 1 discloses an example of an IGBT that can reduce a switching loss by dividing a trench gate into a pair of two gates and driving them with different control signals. When energized, an off signal is supplied to one set of gates prior to the other set, so that a part of the accumulated carriers is discharged prior to turn-off of the entire device. When the entire device is turned off, only the remaining gate has to be turned off, and the switching loss can be reduced because the number of stored carriers is small.

  However, according to the examination of the inventors of the present application, the IGBT having the structure disclosed in Patent Document 1 is not sufficient in reducing the switching loss, and an IGBT having a structure that can further reduce the switching loss is desired.

  Therefore, it becomes a problem to provide a switching element for power conversion that can reduce the switching loss at the time of turn-off.

In order to solve the above problems, the semiconductor device of the present invention is, for example, along the xy plane with respect to the xy plane defined by the x and y directions orthogonal to each other and the z direction orthogonal to the xy plane. A first conductivity type drift layer formed on the first surface of the drift layer, a second conductivity type collector layer formed on the first surface of the drift layer, and a second conductivity type channel formed on the second surface of the drift layer. A plurality of trenches that extend from the surface of the channel layer to the drift layer through the channel layer in the z direction and extend in the y direction, and a gate insulating film formed on a wall surface of the trench The first gate electrode formed on the gate insulating film and independently driven and the second gate electrode, and on the surface of the channel layer, on the side of the first gate electrode Through the gate insulating film A first source region of the first conductivity type selectively formed, and a second source of the first conductivity type selectively formed on the side of the second gate electrode via the gate insulating film The first gate electrode and the second gate electrode are alternately arranged in the x direction, and the carrier injection efficiency of the first source region is The carrier injection efficiency of the second source region is small.

  ADVANTAGE OF THE INVENTION According to this invention, the switching element for power conversion which can reduce the switching loss at the time of turn-off can be provided.

It is a figure which shows typically the example of the structure of the switching element for power conversion which concerns on the 1st Example of this invention. It is a figure which shows the example of the drive sequence of the drive signal which drives a 1st gate electrode and a 2nd gate electrode, respectively, when turning off the switching element for power conversion. It is a figure which shows the example of the output characteristic of the switching element for power conversion. It is a figure which shows typically the example of the structure of the switching element for power conversion which concerns on the 2nd Example of this invention. It is a figure which shows typically the example of the structure of the switching element for power conversion which concerns on the 3rd Example of this invention.

  Hereinafter, embodiments of the present invention will be described as examples with reference to the drawings. In all the drawings for explaining the embodiments, the same reference numerals are given to the same components, and the repeated explanation thereof is omitted.

  FIG. 1 is a diagram schematically showing an example of the structure of a power conversion switching device 100 according to a first embodiment of the present invention.

  As shown in FIG. 1, the switching element 100 for power conversion can be called an IGBT having two independent control gates, and is a trench type disposed adjacent to each other on the surface side of an n − type drift layer 101 such as silicon. The set of the first gate electrode 106 and the second gate electrode 107 has a structure in which they are repeatedly arranged.

  Here, in the first gate electrode 106 and the second gate electrode 107, for example, a p-type channel layer 104 is formed on the surface side of the n − type drift layer 101, and the p-type channel layer 104 has its p A trench deeper than the channel layer 104 is formed, a gate insulating film 105 is formed on the inner wall of the trench, and conductive polysilicon or the like is embedded in the trench in which the gate insulating film 105 is formed. The

  In addition, n-type source regions 108 and 109 are formed at portions of the surface of the p-type channel layer 104 that are in contact with the first gate electrode 106 and the second gate electrode 107 through the gate insulating film 105, respectively. Has been. The length of the first n-type source region 108 in contact with the first gate electrode 106 via the gate insulating film 105 in the y direction is a1, and the y-type of the p-type channel layer 104 including the first n-type source region 108 Let b1 be the repeat unit length in the direction. The length of the second n-type source region 109 in contact with the second gate electrode 107 via the gate insulating film 105 in the y direction is a2, and the p-type channel layer 104 including the second n-type source region 109 is included. Let b2 be the repeating unit length in the y direction.

  At this time, the ratio a1 / b1 occupied by the first n-type source region 108 in the y direction is smaller than the ratio a2 / b2 occupied by the second n-type source region 109 in the y direction. As a result, the amount of electrons injected from the first n-type source region 108 is smaller than the amount of electrons injected from the second n-type source region 109. As a result, the carrier injection efficiency of the first n-type source region 108 is smaller than the carrier injection efficiency of the second n-type source region 109.

  On the p-type channel layer 104, the gate insulating film 105, and the n-type source regions 108 and 109, an emitter electrode made of a conductive metal or the like (not shown) is formed. In addition, a p-type collector layer 102 is formed on the back side of the n− type semiconductor layer 101, and a collector electrode 103 made of a conductive metal or the like is formed so as to be in contact with the p-type collector layer 102. Has been.

  As described above, the switching element 100 for power conversion according to the first embodiment of the present invention includes the first gate electrode 106 and the second gate electrode 107 that can be driven independently from the outside, The carrier injection efficiency of the n-type source region 108 is smaller than the carrier injection efficiency of the second n-type source region 109.

  FIG. 2 is a diagram showing an example of a drive sequence of drive signals for driving the first gate electrode 106 and the second gate electrode 107 when the power conversion switching element 100 is turned off. Here, a voltage higher than the threshold voltage Vth is already applied to both the first gate electrode 106 and the second gate electrode 107, and the switching state of the power conversion switching element 100 is in the “on” state. And

  Note that the threshold voltage Vth here refers to the n-type source regions 108 and 109 in the p-type channel layer 104 and n − when the voltage is applied to the first gate electrode 106 and the second gate electrode 107. This is the lowest voltage at which a conduction path (channel) that connects the type drift layer 101 is formed.

  In this embodiment, as shown in FIG. 2, when the power conversion switching element 100 is turned off, first, the drive signal for the second gate electrode 107 is changed from a state higher than the threshold voltage Vth to a lower state ( Turn off). In addition, the drive signal of the first gate electrode 106 is changed from a state higher than the threshold voltage Vth to a state lower than the threshold voltage Vth (turned off) with a predetermined time delay from the turn-off timing.

  As described above, in the drive signals for driving the first gate electrode 106 and the second gate electrode 107, the turn-off loss of the power conversion switching device 100 is reduced by shifting the turn-off timing by a predetermined time. The effect is obtained. The reason why this effect can be obtained can be explained as follows.

  While the voltage of the drive signal of the first gate electrode 106 is higher than the threshold voltage Vth, the voltage of the drive signal of the second gate electrode 107 is changed from a state higher than the threshold voltage Vth to a lower state. The channel connecting the n-type source region 109 and the n − -type drift layer 101 generated in the p-type channel layer 104 by the second gate electrode 107 disappears. For this reason, electrons are no longer injected into the n − type drift layer 101 through the channel formed on the second gate electrode 107 side, and accordingly the p type collector layer 102 is injected into the n − drift layer 101 accordingly. The amount of holes played is reduced.

  In such a state, if the voltage of the drive signal of the first gate electrode 106 is changed from a state higher than the threshold voltage Vth to a lower state (turned off), the first gate electrode 106 side Then, the channel formed in the n-type drift layer disappears, and electrons are not injected into the n − -type drift layer 101 through the channel. As a result, the switching state of the power conversion switching element 100 is in the “off” state. That is, the power conversion switching element 100 is turned off.

  In this case, when the voltage of the drive signal for the first gate electrode 106 is changed (turned off) from a state higher than the threshold voltage Vth to a state lower than the threshold voltage Vth, the holes accumulated in the n − type drift layer Since the amount is decreasing, the hole discharge time is shortened accordingly. As a result, the turn-off time of the power conversion switching element 100 is shortened, and the turn-off loss is reduced.

  FIG. 3 shows an example of output characteristics of the power conversion switching element 100. First, it is assumed that the carrier injection efficiency of the first n-type source region 108 is equal to the carrier injection efficiency of the second n-type source region 109 (different from the present embodiment). That is, the repeating unit length b1 in the y direction of the p-type channel layer 104 including the first n-type source region 108 and the repeating unit length in the y-direction of the p-type channel layer 104 including the second n-type source region 109 It is assumed that the length b2 is equal and the length a1 of the first n-type source region 108 in the y direction is equal to the length a2 of the first n-type source region 108 in the y direction.

  In this case, the voltage of the drive signal of each of the first gate electrode 106 and the second gate electrode 107 is compared with the collector voltage Vce in a state where both are higher than the threshold voltage Vth (on state). A state in which the voltage of the drive signal for one gate electrode 106 is higher than the threshold voltage Vth (ON state), and a state in which the voltage of the drive signal for the second gate electrode 107 is lower than the threshold voltage Vth ( The collector voltage Vce in the off state increases. As described above, since the electron injection into the n− type drift layer 101 via the channel formed on the second gate electrode 107 side is eliminated, the n-type drift layer 101 is accordingly n-typed accordingly. This is because the amount of holes injected into the drift layer 101 is reduced.

  Next, it is assumed that the carrier injection efficiency of the first n-type source region 108 is smaller than the carrier injection efficiency of the second n-type source region 109 as in the present embodiment. That is, the repeating unit length b1 in the y direction of the p-type channel layer 104 including the first n-type source region 108 and the repeating unit length in the y-direction of the p-type channel layer 104 including the second n-type source region 109 It is assumed that the lengths b2 are equal and the length a1 of the first n-type source region 108 in the y direction is smaller than the length a2 of the first n-type source region 108 in the y direction. However, the sum (a1 + a2) of the length a1 of the first n-type source region 108 in the y direction and the length a2 of the first n-type source region 108 in the y direction is the same as the previous case.

  In this case, the collector voltage Vce when the drive signal voltages of the first gate electrode 106 and the second gate electrode 107 are both higher than the threshold voltage Vth (on state) is the same as in the previous case. does not change. This is because the sum (a1 + a2) of the length a1 in the y direction of the first n-type source region 108 and the length a2 in the y direction of the first n-type source region 108 is the same as in the previous case. The amount of electrons injected into the n − -type drift layer 101 through the channel formed by the gate electrode 106 and the second gate electrode 107 does not change, and the n-type drift layer 101 changes from the p-type collector layer 102 to n according to the electron injection. This is because the amount of holes injected into the drift layer 101 does not change.

  However, the voltage of the drive signal for the first gate electrode 106 is higher (on state) than the threshold voltage Vth, and the voltage of the drive signal for the second gate electrode 107 is higher than the threshold voltage Vth. The collector voltage Vce in the low state (off state) is larger than in the previous case. This is because the amount of reduction in electron injection into the n − -type drift layer 101 due to the disappearance of the channel formed on the second gate electrode 107 side is larger than in the previous case. As a result, as the electron injection decreases, the amount of holes injected from the p-type collector layer 102 to the n− drift layer 101 decreases more than before, and the collector voltage Vce increases.

  As described above, the carrier injection efficiency of the first n-type source region 108 is reduced by making the carrier injection efficiency of the first n-type source region 108 smaller than the carrier injection efficiency of the second n-type source region 109. Compared with the case where the carrier injection efficiency of the second n-type source region 109 is equal, the amount of hole reduction can be increased. As a result, the turn-off time of the power conversion switching device 100 is shortened, and the effect of reducing the turn-off loss can be obtained.

  FIG. 4 is a diagram schematically showing an example of the structure of the power conversion switching device 100 according to the second embodiment of the present invention.

  In the present invention, the method of making the carrier injection efficiency of the first n-type source region 108 smaller than the carrier injection efficiency of the second n-type source region 109 is in contact with the first gate electrode 106 through the gate insulating film 105. The method is not limited to the method in which the length a1 of the first n-type source region 108 in the y direction is shorter than the length a2 of the second n-type source region 109 in the y direction.

  In the second embodiment of the present invention shown in FIG. 4, for example, the first gate electrode 106 has a depth in the z direction that is shallower than the depth of the second gate electrode 107 in the z direction. The carrier injection efficiency of the n-type source region 108 is made smaller than the carrier injection efficiency of the second n-type source region 109.

  When the trench is shallow, the channel is formed only shallowly, and the hole discharge resistance is reduced. As a result, the carrier injection efficiency is reduced and the turn-off loss is reduced.

  FIG. 5 is a diagram schematically showing an example of the structure of the power conversion switching device 100 according to the third embodiment of the present invention.

  The effects of the present invention are not limited to trench type IGBTs. In the third embodiment of the present invention shown in FIG. 5, an example applied to a planar type IGBT is shown. In this embodiment, the p-channel region 104 is selectively formed on the surface of the n-drift layer 101, and the first gate electrode 106 and the second gate electrode 107 are so covered as to cover the region where the n-drift layer 101 is exposed. Are arranged with the gate insulating film 105 interposed therebetween.

  Also in the present embodiment, the length a1 of the first n-type source region 108 adjacent to the first gate electrode 106 in the y direction is equal to the length of the second n-type source region 109 adjacent to the second gate electrode 107. By making it shorter than the length a2 in the y direction, the injection efficiency of the first n-type source region 108 is made smaller than the injection efficiency of the second n-type source region 109. As a result, turn-off loss is reduced.

100 switching element for power conversion 101 n-type drift layer 102 p-type collector layer 103 collector electrode 104 p-type channel layer 105 gate insulating film 106 first gate electrode 107 second gate electrode 108 first n-type source region 109 Second n-type source region

Claims (8)

For the xy plane defined by the x and y directions orthogonal to each other, and the z direction orthogonal to the xy plane,
A first conductivity type drift layer formed along the xy plane;
A collector layer of a second conductivity type formed on the first surface of the drift layer;
A channel layer of a second conductivity type formed on the second surface of the drift layer;
A plurality of trenches extending in the y direction, extending from the surface of the channel layer to the drift layer through the channel layer in the z direction;
A gate insulating film formed on the wall of the trench;
A first gate electrode formed on the gate insulating film and capable of being independently driven; and a second gate electrode;
A first source region of a first conductivity type selectively formed on the side of the first gate electrode via the gate insulating film on the surface of the channel layer, and the second gate electrode A semiconductor device comprising a second source region of a first conductivity type selectively formed on a side portion through the gate insulating film,
The first gate electrode and the second gate electrode are alternately and repeatedly arranged in the x direction,
A semiconductor device, wherein the carrier injection efficiency of the first source region is smaller than the carrier injection efficiency of the second source region. The semiconductor device according to claim 1,
The ratio a1 / b1 of the length a1 in the y direction of the first source region to the length b1 of the repeating unit in the y direction of the channel layer including the first source region is:
A semiconductor device, wherein the length a2 of the second source region in the y direction is smaller than the ratio a2 / b2 to the length b2 of the repeating unit in the y direction of the channel layer including the second source region . The semiconductor device according to claim 1,
The timing at which the voltage of the drive signal applied to the second gate electrode switches from a state higher than a threshold voltage to a lower state,
The semiconductor device according to claim 1, wherein the voltage of the drive signal applied to the first gate electrode is earlier than the timing of switching from a higher state to a lower state than a threshold voltage. The semiconductor device according to claim 3.
The ratio a1 / b1 of the length a1 in the y direction of the first source region to the length b1 of the repeating unit in the y direction of the channel layer including the first source region is:
The semiconductor device, wherein the length a2 of the second source region in the y direction is smaller than the ratio a2 / b2 to the length b2 of the repeating unit in the y direction of the channel layer including the second source region . With respect to the xy plane defined by the x and y directions orthogonal to each other, and the z direction orthogonal to the xy plane,
A first conductivity type drift layer formed along the xy plane;
A collector layer of a second conductivity type formed on the first surface of the drift layer;
A channel region of a second conductivity type selectively formed on the second surface of the drift layer;
A first source region of a first conductivity type selectively formed on the surface of the channel region;
A second source region of the first conductivity type selectively formed on the surface of the channel region;
A first gate electrode formed on the first source region, the channel region and the drift layer via a gate insulating film;
A semiconductor device comprising: a second gate electrode formed on the second source region, the channel region and the drift layer via a gate insulating film;
The first gate electrode and the second gate electrode are alternately and repeatedly arranged in the x direction,
A semiconductor device, wherein the carrier injection efficiency of the first source region is smaller than the carrier injection efficiency of the second source region. The semiconductor device according to claim 5,
The ratio a1 / b1 of the length a1 in the y direction of the first source region to the length b1 of the repeating unit in the y direction of the channel region including the first source region is:
The semiconductor device, wherein the length a2 of the second source region in the y direction is smaller than the ratio a2 / b2 to the length b2 of the repeating unit in the y direction of the channel region including the second source region . The semiconductor device according to claim 5,
The timing at which the voltage of the drive signal applied to the second gate electrode switches from a state higher than a threshold voltage to a lower state,
The semiconductor device according to claim 1, wherein the voltage of the drive signal applied to the first gate electrode is earlier than the timing of switching from a higher state to a lower state than a threshold voltage. The semiconductor device according to claim 7,
The ratio a1 / b1 of the length a1 in the y direction of the first source region to the length b1 of the repeating unit in the y direction of the channel region including the first source region is:
The semiconductor device, wherein the length a2 of the second source region in the y direction is smaller than the ratio a2 / b2 to the length b2 of the repeating unit in the y direction of the channel region including the second source region .