JPH11345969A - Power semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the fall time of a power semiconductor device, lower the turning-on voltage of the device, and improve the load short-circuiting resistance of the device by specifying the sizes of an emitter layer of a first conductivity and a contact layer of a second conductivity in the channel widthwise direction. SOLUTION: When the sizes W1 and W2 of an n-type emitter layer 8 and a p-type contact layer 9 in the channel widthwise direction meets a relation, W1/(W1+W2)<=0.4, sizes in an IGBT, the fall time of a power semiconductor device when the device is turned off can be shortened while the increase of the turning-on voltage of the device is suppressed. When the size of the emitter layer 8 in the channel widthwise direction is adjusted to <=3 μm, the latch-up resistance and load short-circuiting resistance of the device can be improved by scarcely raising the turning-on voltage. In addition, since the emitter layer 8 is not brought into contact with an emitter electrode even partially, carriers can be stored in an element and the turning-on voltage of the device can be lowered.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to an IGBT (Insula
The present invention relates to a power semiconductor device including an insulated gate semiconductor element such as a ted Gate Bipolar Transistor).

[0002]

2. Description of the Related Art In response to recent demands for miniaturization and high performance of power supply equipment in the field of power electronics, power semiconductor devices have been required to have high withstand voltage, high current, low loss and high speed. Improvement is focused.

Conventionally, an IGBT has been used as a power semiconductor element having a breakdown voltage of about 2000 V or less.
IGBTs are roughly classified into those having a planar structure in which a gate electrode is provided in a plate shape on a substrate, and those having a trench structure in which a gate electrode is buried in a trench on the surface of the substrate.

Generally, an IGB having a trench structure
T is more advantageous than an IGBT having a planar structure in that the channel resistance is easily reduced and the carrier injection amount in one chip is easily increased.

FIG. 33 shows an I-type semiconductor device having a conventional trench structure.
1 shows a cross-sectional view of a GBT.

In the drawing, reference numeral 81 denotes an n-type base layer having a high resistance. One surface of the n-type base layer 81 has a p-type buffer layer 82 having a high impurity concentration via an n-type buffer layer 82 having a high impurity concentration. A collector layer 83 is formed, and a plurality of trenches 84 are formed on the other surface.

A gate electrode 86 is buried inside these trenches 84 via a gate insulating film 85. A p-type base layer 87 is formed on the surface of n-type base layer 81 in a region sandwiched between trenches 84, and n-type emitter layer 88 is formed on the surface of p-type base layer 87 so as to be in contact with the side surface of trench 84. Are selectively formed. Thus, the n-type base layer 81, the p-type base layer 87, the n-type emitter layer 88, the gate insulating film 85, and the gate electrode 8
6 constitutes an electron injection MOSFET having a region indicated by CH1 in the drawing as a channel.

Further, a collector electrode 89 is provided on the p-type collector layer 83, and the n-type emitter layer 88 and the p-type base layer 8
7, an emitter electrode 90 is provided.

The emitter electrode 90 is in contact with the p-type base layer 87 via the p-type contact layer 91 having a high impurity concentration, and is in direct contact with the n-type emitter layer 88. The p-type base layer 87 and the n-type emitter layer 88 are short-circuited by the emitter electrode 90, and have the same structure in the depth direction.

This IGBT operates as follows.

That is, when a positive voltage larger than that of the emitter electrode 90 is applied to the gate electrode 86 while a positive voltage is applied to the collector electrode 89 and a negative voltage is applied to the emitter electrode 90, the gate electrode 86 of the p-type base layer 87 is applied to the gate electrode 86. The contacted surface is inverted to the n-type, and electrons are injected from the n-type emitter layer 88 to the n-type base layer 81 via the inversion layer, so that the p-type collector layer 8 is formed.
Reach 3. Accordingly, holes are injected from the p-type collector layer 83 into the n-type base layer 81. As described above, when both electrons and holes are injected into the n-type base layer 81 and conduction modulation occurs, the on-voltage is reduced and the element is brought into a conductive state.

On the other hand, to turn off the gate electrode 8
6, a negative voltage is applied to the emitter electrode 90. Thus, the inversion layer formed on the surface of the p-type base layer 87 in contact with the gate electrode 86 disappears, and the electron injection stops. On the other hand, a part of the holes accumulated in the n-type base layer 81 is discharged to the emitter electrode 90 through the p-type base layer 87, and the remaining holes recombine with the electrons and disappear. Eventually, the device turns off.

However, the conventional IGBT having the trench structure has several problems as described below.

[0014] In other words, when you try to shorten the fall time t _f, there was a turn-on voltage (Vce (sat)) problem that is raised (the first problem).

Further, since the IGBT is an element having a built-in parasitic thyristor structure, it is designed so that it does not latch up. For this reason, there is a problem (second problem) that the on-voltage is higher than that of various thyristors such as GTO.

Further, even if the on-voltage can be reduced, there are two problems (third and fourth problems) as described below.

That is, when a load is short-circuited in a circuit such as an inverter circuit composed of IGBTs, the collector current flowing when the load is short-circuited increases due to a low ON voltage, and as a result, heat generated by the product of the collector voltage and the collector current is generated. When the amount increases, a problem that the element is destroyed occurs. That is, there is a problem (third problem) that the load short-circuit withstand capability is reduced and the element is destroyed.

FIG. 34 shows an IGBT 101, a voltage power supply 102, and a gate circuit 10 for testing such a problem.
3 shows a load short-circuit test circuit, and FIG. 35 shows a waveform of the load short-circuit test.

Further, when the on-voltage is reduced, the collector current in the on-state is increased, so that the parasitic thyristor structure is easily latched up (fourth problem).
was there.

In order to miniaturize the element, FIG.
As shown in (1), it is necessary to diffuse the high impurity concentration p-type contact layer 91 on the surface of the p-type base layer 87 to suppress an increase in the contact resistance of the emitter electrode 90.

However, when forming the p-type contact layer,
The type impurity diffuses into the n-type emitter layer 88, and the n-type emitter layer 88 in the region where the channel is to be formed is reduced to such a degree as to cause deterioration of the device characteristics. In the worst case, the channel should be formed. A problem (fifth problem) occurs that the n-type emitter layer 88 in the region disappears.

[0022]

As described above, the conventional IGBT having the trench structure has various problems (first to first problems).
Fifth problem).

[0023] That is, without increasing the on-voltage, a problem that it is difficult to shorten the fall time t _f (first problem) had.

Also, since the IGBT is designed so that the parasitic thyristor structure does not latch up, the GTO
There is a problem (second problem) that the on-state voltage is higher than various thyristors.

Further, when the ON voltage is reduced, the collector current flowing when the load is short-circuited becomes large, so that the load short-circuit withstand capability is reduced (third problem).

When the on-voltage is reduced, the collector current in the on-state is increased, so that the parasitic thyristor structure is easily latched up (fourth problem).
was there.

In order to prevent an increase in the contact resistance of the emitter electrode caused by miniaturization of the element, a p-type contact layer having a high impurity concentration is formed by diffusion on the surface of the p-type base layer. The n-type emitter layer in the region where the channel is formed (channel region) is reduced to such an extent that the device characteristics are degraded, or the n-type emitter layer in the channel region disappears due to the diffusion into the type emitter layer. There was a problem (fifth problem).

The present invention has been made in view of the above circumstances, and has as its object to provide a power semiconductor device having an IGBT that can solve the above first to fifth problems. .

[0029]

[Means for Solving the Problems] [Structure] To achieve the above object, a first power semiconductor device according to the present invention comprises:
A power semiconductor device including an insulated gate power semiconductor element, wherein the insulated gate power semiconductor element is formed on a high resistance first conductivity type base layer and a surface of the first conductivity type base layer. A second conductivity type base layer, a first conductivity type emitter layer selectively formed on the surface of the second conductivity type base layer, and penetrating the first conductivity type emitter layer and the second conductivity type base layer. A gate electrode buried through a gate insulating film in a groove reaching a middle depth of the first conductive type base layer; and a groove and the first conductive layer on a surface of the second conductive type base layer. A second conductivity type contact layer selectively formed to be in contact with the conductivity type emitter layer; and a second conductivity type contact layer formed on a surface of the first conductivity type base layer opposite to a surface on which the first conductivity type emitter layer is formed. The second conductivity type collector layer, An emitter electrode provided on the one conductivity type emitter layer, provided on the second conductivity type base layer via the second conductivity type contact layer, and a collector electrode provided on the second conductivity type collector layer. And satisfying the condition of W1 / (W1 + W2) ≦ 0.4 when the dimensions of the first conductivity type emitter layer and the second conductivity type contact layer in the channel width direction are W1 and W2, respectively. I do.

Here, W1 is preferably 3 μm or less.

It is preferable that the first conductivity type emitter layer and the second conductivity type contact layer are alternately formed in a stripe shape on the surface of the second conductivity type base layer.

A second power semiconductor device according to the present invention is a power semiconductor device including an insulated gate power semiconductor device, wherein the insulated gate power semiconductor device is a high-resistance first conductive semiconductor device. A mold base layer, a second conductivity type base layer formed on the surface of the first conductivity type base layer, a first conductivity type emitter layer selectively formed on the surface of the second conductivity type base layer, The first conductive type emitter layer and the second conductive type
A gate electrode penetrating through the conductive type base layer and reaching a depth in the middle of the first conductive type base layer via a gate insulating film, and a gate electrode buried through the surface of the second conductive type base layer. A second conductivity type contact layer selectively formed so as to be in contact with the groove and the first conductivity type emitter layer; and a first conductivity type opposite to a surface on which the first conductivity type emitter layer is formed. The second formed on the surface of the mold base layer
A conductivity type collector layer, an emitter electrode provided on the first conductivity type emitter layer, and provided on the second conductivity type base layer via the second conductivity type contact layer;
A collector electrode provided on the second conductivity type collector layer, wherein a dimension of the first conductivity type emitter layer in a channel width direction is 3 μm or less.

A third power semiconductor device according to the present invention is a power semiconductor device including an insulated gate power semiconductor device, wherein the insulated gate power semiconductor device is a high-resistance first conductive semiconductor device. A base layer, a second conductive type base layer formed on the surface of the first conductive type base layer, a first conductive type emitter layer selectively formed on the surface of the second conductive type base layer, and a second conductive type base layer. A second conductivity type collector layer, a first conductivity type emitter layer and the second conductivity type base layer,
A gate electrode buried through a gate insulating film in a groove reaching a depth in the middle of the first conductivity type base layer, and a gate electrode on a side opposite to a surface on which the first conductivity type emitter layer is formed. The second conductive layer formed on the surface of the first conductive type base layer
A conductivity type collector layer, an emitter electrode provided on the first conductivity type emitter layer, and provided on the second conductivity type base layer via the second conductivity type contact layer;
A collector electrode provided on the second conductivity type collector layer, wherein a plurality of the grooves are formed, and a part of the first conductivity type emitter layer divided into a plurality by the grooves, The first conductive type emitter layer which is not electrically connected to the emitter electrode and is electrically connected to the emitter electrode among the plurality of divided first conductive type emitter layers. When the dimensions of the second type contact layer in the channel width direction are W1 and W2, respectively, the condition of W1 / (W1 + W2) ≦ 0.4 is satisfied.

A fourth power semiconductor device according to the present invention is a power semiconductor device including an insulated gate power semiconductor device, wherein the insulated gate power semiconductor device is a high-resistance first conductive semiconductor device. A mold base layer, a second conductivity type base layer formed on the surface of the first conductivity type base layer, a first conductivity type emitter layer selectively formed on the surface of the second conductivity type base layer, The first conductive type emitter layer and the second conductive type
A gate electrode pierced through a conductive type base layer and buried through a gate insulating film in a groove reaching a depth in the middle of the first conductive type base layer. Means for discharging carriers to the outside of the device without passing through the second conductivity type base layer on which the one conductivity type emitter layer is formed, and the first conductive type emitter layer on the side opposite to the surface on which the first conductivity type emitter layer is formed. A second conductivity type collector layer formed on the surface of the conductivity type base layer; an emitter electrode provided on the first conductivity type emitter layer and the second conductivity type base layer; and a second conductivity type collector layer provided on the second conductivity type collector layer And a collector electrode provided.

More specific configurations are as described below in the fifth and sixth power semiconductor devices according to the present invention.

That is, a fifth power semiconductor device according to the present invention is a power semiconductor device including an insulated gate power semiconductor device, wherein the insulated gate power semiconductor device is a high-resistance first conductive semiconductor device. A mold base layer, a second conductivity type base layer formed on the surface of the first conductivity type base layer, a first conductivity type emitter layer selectively formed on the surface of the second conductivity type base layer, A gate electrode buried through a gate insulating film in a groove penetrating the first conductivity type emitter layer and the second conductivity type base layer and reaching a middle depth of the first conductivity type base layer; A second conductive type drain layer having a high impurity concentration formed on a surface of the second conductive type base layer and in a region between the trenches where the first conductive type emitter layer is not formed; Is the surface on which the emitter layer is formed A second conductive type collector layer formed on the surface of the first conductive type base layer on the opposite side; an emitter electrode provided on the first conductive type emitter layer and the second conductive type base layer; A drain electrode provided on the conductive type drain layer and electrically connected to the emitter electrode; and a collector electrode provided on the second conductive type collector layer.

A sixth power semiconductor device according to the present invention is a power semiconductor device including an insulated gate power semiconductor device, wherein the insulated gate power semiconductor device is a high-resistance first conductive semiconductor device. A mold base layer, a second conductivity type base layer formed on the surface of the first conductivity type base layer, a first conductivity type emitter layer selectively formed on the surface of the second conductivity type base layer, The first conductive type emitter layer and the second conductive type
A gate electrode penetrating through the conductive type base layer and buried through a gate insulating film in a groove reaching a depth in the middle of the first conductive type base layer; and a surface of the first conductive type base layer. A second conductivity type drain layer selectively formed and for discharging carriers having the same polarity as the majority carrier of the second conductivity type base layer, and discharged to the outside of the element through the second conductivity type drain layer. Carrier control means for controlling the amount of the carrier, a second conductivity type collector layer formed on the surface of the first conductivity type base layer opposite to the surface on which the first conductivity type emitter layer is formed, An emitter electrode provided on the first conductivity type emitter layer and the second conductivity type base layer; a drain electrode provided on the second conductivity type drain layer and electrically connected to the emitter electrode; 2-conductivity type Characterized in that it comprises a collector electrode provided on the data layer.

Here, it is preferable that the carrier control means reduces the discharge amount of the carrier at the time of turn-on and increases the discharge amount of the carrier at the time of turn-off or overcurrent application.

A seventh power semiconductor device according to the present invention is a power semiconductor device including an insulated gate power semiconductor device, wherein the insulated gate power semiconductor device is a high-resistance first conductive semiconductor device. A mold base layer, a second conductivity type base layer formed on the surface of the first conductivity type base layer, a first conductivity type emitter layer selectively formed on the surface of the second conductivity type base layer, The second conductive type base layer and the first conductive type base layer;
A gate electrode buried through a gate insulating film and the first conductivity type emitter layer are formed in a trench penetrating the conductivity type emitter layer and reaching a depth in the middle of the first conductivity type base layer. A second conductivity type collector layer formed on the surface of the first conductivity type base layer opposite to the surface, and an emitter electrode connected to the first conductivity type emitter layer and the second conductivity type base layer. A collector electrode provided on the second conductivity type collector layer, and a region where the emitter electrode is connected to the first conductivity type emitter layer is formed at a predetermined interval, so that the first conductivity type base layer Wherein the carrier concentration on the side of the second conductivity type base layer is increased in the ON state.

An eighth power semiconductor device according to the present invention is a power semiconductor device including an insulated gate power semiconductor element, wherein the insulated gate power semiconductor element is a high-resistance first conductive semiconductor element. A base layer, a second conductivity type base layer formed on the surface of the first conductivity type base layer, and a first conductivity type emitter layer selectively formed on the surface of the second conductivity type base layer. A conductive type contact layer, and a trench penetrating through the first conductive type emitter layer and the second conductive type base layer and reaching a depth halfway through the first conductive type base layer, is buried via a gate insulating film. A gate electrode formed, a second conductivity type collector layer formed on the surface of the first conductivity type base layer opposite to the surface on which the first conductivity type emitter layer is formed, and the first conductivity type. An emitter layer; An emitter electrode provided on the second conductive type base layer via a conductive type contact layer, and a collector electrode provided on the second conductive type collector layer, wherein the second conductive type contact layer is It is characterized in that it is not in contact with an edge portion of the one conductivity type emitter layer which is in contact with the groove where a channel is formed.

[Action] According to the study of the present inventors, IG
In the BT, the dimensions of the n-type emitter layer and the p-type contact layer in the channel width direction are W1 and W2, respectively.
When W1 / (W1 + W2) ≦ 0.4, it was found that the fall time at the time of turn-off can be shortened while suppressing the increase of the on-voltage. Therefore, according to the present invention (claims 1 and 2), the fall time can be shortened without increasing the on-voltage. That is, the first problem can be solved.

According to the study of the present inventors, IGB
At T, it was found that when the dimension of the n-type emitter layer in the channel width direction was 3 μm or less, the latch-up resistance and the load short-circuit resistance could be improved with almost no increase in on-voltage. Therefore, according to the present invention (claim 3), the third and fourth problems can be solved.

According to the present invention (claim 4), the first
Since a part of the conductive type emitter layer is not connected to the emitter electrode, carriers can be effectively accumulated in the device in the ON state, and the ON voltage can be reduced. Moreover, in the present invention, W1 / (W
Since 1 + W2) ≦ 0.4, the fall time at turn-off can be shortened. That is, the first and second problems can be solved.

Further, according to the present invention (claim 5), when a load is short-circuited, carriers can be discharged out of the element without passing through the second conductivity type base layer on which the first conductivity type emitter layer is formed. Therefore, even if an overcurrent flows into the element due to a load short circuit, the carriers are effectively discharged out of the element, so that element destruction due to the overcurrent can be effectively prevented.

Therefore, according to the present invention, even if the collector current flowing when the load is short-circuited becomes large as a result of introducing the structure in which the ON voltage is reduced, it is possible to prevent the load short-circuit withstand capability from being lowered. That is, the third problem can be solved.

According to the present invention, at the time of turn-off,
Since carriers can be discharged out of the device without passing through the second conductivity type base layer on which the first conductivity type emitter layer is formed, a region between the first conductivity type emitter layer and the second conductivity type collector layer is formed. Carriers can be effectively discharged, thereby preventing a large current that would latch up the parasitic thyristor structure from flowing into the region.

Therefore, according to the present invention, as a result of introducing a structure in which holes flow to a place other than the channel region, even if the collector current in the ON state becomes large,
Latch-up of the parasitic thyristor structure can be prevented. That is, the fourth problem can be solved.

According to the present invention (claim 6), even if an overcurrent flows in the element due to a load short circuit,
Since the current in the device is discharged out of the device through a p-type layer having a high impurity concentration in addition to a normal discharge path, the device can be effectively prevented from being destroyed due to an overcurrent.

Therefore, according to the present invention, as a result of introducing a structure in which holes flow to a place other than the channel region, even if the collector current flowing when the load is short-circuited becomes large, the element can be prevented from being destroyed. Become. That is,
The third problem can be solved.

Further, according to the present invention, the current in the device is discharged out of the device through the p-type layer having a high impurity concentration in addition to the normal discharge path. Second
The carrier density in the region between the conductive type collector layer and the conductive type collector layer can be effectively reduced, so that a large current that would cause the parasitic thyristor structure to latch up can be prevented from flowing into the region.

Therefore, according to the present invention, as a result of introducing a structure in which holes flow to a place other than the channel region, even if the collector current in the ON state becomes large,
Latch-up of the parasitic thyristor structure can be prevented. That is, the fourth problem can be solved.

According to the present invention (claims 7 and 8),
By increasing the amount of the carrier discharged from the second conductivity type drain layer when the overcurrent is applied by the carrier density control means, the load short-circuit withstand capability can be increased. That is, the third problem can be solved.

Further, according to the present invention, the amount of carriers discharged from the second conductivity type drain layer to the outside of the device at the time of turn-off by the carrier density control means is increased, so that the first conductivity type emitter layer and the first conductivity type emitter layer are separated. Carriers in the region between the two-conductivity-type collector layer can be effectively discharged, so that a large current such as a latch-up of the parasitic thyristor structure can be prevented from flowing into the device.

Therefore, according to the present invention, as a result of introducing a structure for increasing the carrier discharge amount at the time of turn-off,
Even if the collector current in the ON state increases, latch-up of the parasitic thyristor structure can be prevented. That is, the fourth problem can be solved.

Further, according to the present invention, the amount of carriers discharged from the drain layer of the second conductivity type in the turn-on state is reduced by the carrier density control means, whereby the emitter layer of the first conductivity type and the collector of the second conductivity type are reduced. Since the carrier density in the region between the layers can be effectively increased, the on-voltage can be reduced.

Further, according to the present invention (claim 9), since the first conductivity type emitter layers are formed apart from each other in the channel width direction, if the distance between these first conductivity type emitter layers is widened, The width of the second conductivity type base layer in the region sandwiched between the first conductivity type emitter layers is increased.

Thus, the resistance of the second conductive type base layer having a wide region between the first conductive type emitter layers can be made higher than the resistance of the first conductive type emitter layer.

By increasing the resistance of the second conductivity type base layer in this manner, most of the carriers (holes or electrons) do not pass under the high resistance second conductivity type base layer at the time of turn-on. It passes under the lower first conductivity type emitter layer.

As a result, carriers (holes or electrons) on the side of the emitter electrode are increased, and carriers (electrons or holes) having a polarity opposite to that of the carriers from the first conductivity type emitter layer.
Implantation is promoted, and the on-resistance decreases.

On the other hand, when the current density in the device becomes high, such as at the time of turn-off or load short-circuit, carriers (holes or electrons) do not concentrate only under the first conductivity type emitter layer, but once the second region of the wide region Since there is also a bypass path that enters the conductive base layer and then escapes to the emitter electrode, it is possible to prevent the latch-up of the parasitic thyristor structure and to improve the load short-circuit tolerance.

Therefore, according to the present invention, the ON voltage can be reduced, and even if the current density in the element is increased due to a load short circuit or the like, the latch-up of the parasitic thyristor structure can be prevented and the load short-circuit tolerance can be improved. Become. That is, the third and fourth problems can be solved.

According to the present invention (claim 10), the second conductivity type contact layer is a pattern that does not contact the edge portion of the first conductivity type emitter layer that is in contact with the groove where the channel is formed. Therefore, in the diffusion step when forming the second conductivity type contact layer, the second conductivity type impurity can be prevented from diffusing into the channel region.

Therefore, according to the present invention, even if the channel region is reduced due to miniaturization of the element, the diffusion of the second conductivity type impurity in the formation of the second conductivity type contact layer can reduce the channel region. It is possible to solve the problem that the first conductivity type emitter layer is reduced to such an extent that the element characteristics are deteriorated, or the first conductivity type emitter layer in the channel region disappears, that is, the fifth problem.

[0064]

Embodiments of the present invention (hereinafter, referred to as embodiments) will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a plan view of an IGBT having a trench structure according to a first embodiment of the present invention, and FIG. 2 is a sectional view taken along the line AA ′ of the plan view. FIG. 3 shows a cross-sectional perspective view of the IGBT. In this figure, electrodes and the like are omitted for easy understanding of the inside.

Referring to FIG. 1, reference numeral 1 denotes a high-resistance n-type base layer. One surface of the n-type base layer 1 has a high-impurity-concentration p-type buffer layer 2 interposed therebetween. A collector layer 3 is formed.

On the other surface, a plurality of stripe-shaped trenches 4 are formed in parallel with the channel width direction.
The reason why the shape of the trench 4 is formed in a stripe shape is to reduce the channel density and increase the load short-circuit tolerance.
Moreover, in the case of the trench 4 having the trench shape, the positioning accuracy between the mask pattern used for forming the trench and the channel region does not need to be increased.

A gate electrode 6 is buried inside these trenches 4 with a gate insulating film 5 interposed therebetween.
A p-type base layer 7 is formed on the surface of the n-type base layer 1 in a region sandwiched between the trenches 4.

On the surface of the p-type base layer 7, a high impurity concentration n-type emitter layer 8 and a p-type contact layer 9 are formed.
It is formed alternately along the longitudinal direction (channel width direction) of the trench 4 in contact with the side surface of the trench 4.

The n-type base layer 1, the p-type base layer 7, the n-type emitter layer 8, the gate insulating film 5, and the gate electrode 6
An electron injection MOSFET is formed between the n-type base layer 1 and the n-type base layer 1 and has a channel formed on the surface of the p-type base layer 7 in contact with the trench 4.

The collector electrode 10 is formed on the p-type collector layer 3.
Is provided. An emitter electrode 12 is provided on the n-type emitter layer 8 and the p-type base layer 7 via an interlayer insulating film 11. This emitter electrode 12 is in contact with the p-type base layer 7 via the p-type contact layer 9.

Here, as described above, the n-type emitter layer 8 and the p-type contact layer 9 are alternately formed along the longitudinal direction of the trench 4 in contact with the side surfaces of the trench 4, so that the p-type base layer The layer 7 and the n-type emitter layer 8 are separated by the emitter electrode 12 in the channel width direction (in the depth direction).
A short circuit will occur.

This short-circuit structure prevents the latch-up of the npnp thyristor composed of the n-type base layer 1, the p-type collector layer 3, the p-type base layer 7, and the n-type emitter layer 8.

On the other hand, in the conventional IGBT, as shown in FIG. 33, the p-type base layer 7 and the n-type emitter layer 8 are short-circuited by the emitter electrode 12 in the channel length direction (lateral direction).

Here, as shown in FIG. 1, when the width of the n-type emitter layer 8 is Wn and the width of the p-type contact layer is Wp, the n-type emitter layer 8 is defined as D = Wn / (Wn + Wp). The value of the short-circuit rate in the depth direction of the emitter layer 8 is set to 0.4 or less in the present embodiment.

For the reason, according to the study of the present inventors, as shown in Table 1, when D = 1 and the channel is formed along the longitudinal direction of the trench 4 without interruption, the electron injection increases. As a result, the ON voltage (Vce (sat)) decreases,
Although contrary to the turn-off time t _f becomes longer, D ≦
When 0.4 ON voltage (Vce (sat)) is because rises slightly found that turn-off time t _f is significantly shortened.

[0077] That is, by the short circuit ratio D to 0.4 or less, can be sufficiently short turn-off time t _f, yet such a small value to be ON voltage by a short-circuit ratio D (Vce (sat)) It turns out that it can be kept low.

[0078]

[Table 1]

Further, the on-voltage is reduced and the turn-off time t
_{Since f} can be shortened, the loss of the entire device can be sufficiently achieved. Conventionally, in order to reduce the ON voltage, the channel region in the depth direction is omitted, that is, D
Was not reduced. The results in Table 1 show that the short-circuit rate D is 0.4, the power supply voltage is 300 V, and the current is 1
5A, obtained by an experiment under the conditions of a gate voltage of ± 15 V.

Further, according to the study by the present inventors, as shown in Table 2, in order to lower the on-voltage effectively, regardless of the condition of the short-circuit rate D ≦ 0.4, Wn is reduced. It has been found that the thickness should be set to 3 μm or less. Note that the results in Table 2 were obtained by experiments under the conditions of a power supply voltage of 300 V, a current of 15 A, and a gate voltage of ± 15 V.

[0081]

[Table 2]

[0082] According to the present embodiment as described above, without increasing the on-voltage by setting the short circuit ratio D ≦ 0.4, it is possible to shorten the turn-off time t _f. In addition, the short-circuit rate D is set to 0.4 or less,
And by setting Wn ≦ 3 [mu] m, it is possible to shorten the ON voltage low and turn-off time t _f.

(Second Embodiment) FIG. 4 shows a second embodiment of the present invention.
It is a top view of IGBT which has a trench structure concerning an embodiment. 1 to 3 correspond to FIGS.
The same reference numerals as those in FIG. 3 denote the same parts, and a detailed description thereof will be omitted (the same applies to other embodiments).

This embodiment differs from the first embodiment in that the center of the n-type emitter layer 8 is replaced with a p-type contact layer 9 along the longitudinal direction of the trench 4.
As a result, the dimension of the n-type emitter layer 8 in the channel width direction is reduced, so that latch-up of the parasitic thyristor structure can be more effectively prevented.

In order to effectively prevent the latch-up of the parasitic thyristor structure, the dimension of the n-type emitter layer 8 in the channel length direction is preferably 2 μm or less.

(Third Embodiment) FIG. 5 shows a third embodiment of the present invention.
FIG. 4 is a cross-sectional view of an IGBT having a trench structure according to the embodiment.

The present embodiment is different from the first embodiment in that the emitter electrode 12 is contacted not with all the n-type emitter layers 8 but only with some of the n-type emitter layers 8.

Specifically, the emitter electrode 1 between the two n-type emitter layers 8 contacting the emitter electrode 12
The number of n-type emitter layers 8 not in contact with 2 was two. That is, the emitter electrode 12 is connected to the n-type emitter layer 8 at a ratio of one to three continuous n-type emitter layers 8.
Was contacted.

With such a configuration, the same effect as that of the first embodiment can be obtained, and the electron injection can be performed by contacting the emitter electrode 12 only with a part of the n-type emitter layer 8. As a result, the on-state voltage can be further reduced.

In this embodiment, the emitter electrode 1
2 are not in contact, the short-circuit rate D ≦ 0.
Condition 4 may not be satisfied.

In this embodiment, the emitter electrode 12 is in contact with the n-type emitter layer 8 at a ratio of one to three n-type emitter layers 8, but the number is one, two or four. It may be above. Basically, the larger the number, the lower the on-voltage.

(Fourth Embodiment) FIG. 6 is a plan view of an IGBT having a trench structure according to a fourth embodiment of the present invention, and FIG. 7 is a cross-sectional view taken along the line AA ′ of the plan view. FIG. 8 is a sectional perspective view of the IGBT. In this figure, electrodes and the like are omitted for easy understanding of the inside.

This embodiment is different from the first embodiment in that IGBT cells in which a channel is formed and dummy cells in which a channel is not formed are alternately arranged in a direction perpendicular to the longitudinal direction of the trench 4 (channel length direction). It was formed in.

That is, in the IGBT cell, the n-type emitter layer 8 and the p-type contact layer 9 are formed on the surface of the p-type base layer 7, and in the dummy cell, the p-type contact layer 9 is formed on the surface of the p-type base layer 7. Only have been formed.

The emitter electrode 12 is an IGBT cell.
Contact is made with the n-type emitter layer 8 and the p-type contact layer 9, and in the dummy cell, only with the p-type contact layer 9.

A load short-circuit experiment was performed using the IGBT having such a configuration as the IGBT of the load short-circuit test circuit shown in FIG. 34, and it was found that the short-circuit period (the period indicated by tsc in FIG. 35) was sufficient. It was found that the load short-circuit withstand capability became sufficiently large. For example, in a conventional IGBT, 1
μsec, but in the IGBT of the present embodiment, 1
0 μsec or more.

The reason why such an experimental result was obtained is that, at the time of short circuit, holes accumulated in the device are effectively discharged from the emitter electrode 12 in contact with the p-type contact layer 9 of the dummy cell to the outside of the device. This is because that.

As is well known, if there is a time margin of about 10 μsec at the time of a short circuit, an overcurrent can be detected by an external circuit and the gate voltage can be reduced, so that the IGBT can be protected. Therefore, the IGBT of the present embodiment can protect against a short circuit accident.

At the time of turn-off, the dummy cell p
As a result, the n-type emitter layer 8 is effectively discharged out of the device from the emitter electrode 12 in contact with the n-type emitter layer 8.
Since the density of the hole current of the lower p-type base layer 7 becomes lower,
Latch-up of the parasitic thyristor structure can be prevented.

The conventional IGBT and the IGBT of the present embodiment used in the above experiment have a blocking voltage of 4.5 kV, and the only parameter that differs between the conventional IGBT and the IGBT of the present embodiment is the surface pattern. The power supply voltage (Vcc) was 2 kV.

In this embodiment, the emitter electrode 12
Is provided on the n-type emitter layer 8 via the p-type contact layer 9, but may be provided directly.

(Fifth Embodiment) FIG. 9 shows a fifth embodiment of the present invention.
FIG. 4 is a cross-sectional view showing an IGBT having a trench structure according to the embodiment.

This embodiment is different from the fourth embodiment in that the ratio of the number of cells in which no channel is formed is increased. According to the present embodiment, at the time of turn-off, holes accumulated in the device can be more effectively discharged to the outside of the device, so that the load short-circuit withstand capability can be further increased.

(Sixth Embodiment) FIG. 10 is a sectional view showing an IGBT having a trench structure according to a sixth embodiment of the present invention.

The present embodiment differs from the fourth embodiment in that the dummy cell contacting the emitter electrode 12
The mold contact layer 9 is insulated from the emitter electrode 12 by the interlayer insulating film 11.

Also in this embodiment, the load short-circuit withstand capability is large as compared with the related art. Further, at the time of turn-on, holes discharged to the outside of the element via the p-type contact layer 9 of the dummy cell are eliminated, and holes are easily accumulated in the element, so that the ON voltage can be reduced.

(Seventh Embodiment) FIG. 11 is a sectional view showing an IGBT having a trench structure according to a seventh embodiment of the present invention.

The present embodiment is the same as the fourth embodiment in that an IGBT cell and a dummy cell are present, but the configuration of these cells is different from the fourth embodiment.

That is, in the case of the present embodiment, in the IGBT cell, the n-type emitter layer 8 and the p-type contact layer 9
Are short-circuited in the lateral direction as in the prior art, and in the dummy cell, a p-type drain layer 21 having a high impurity concentration is formed instead of the p-type contact layer 9, and a drain electrode 22 is provided on the p-type drain layer 21. Have been. This drain electrode 22 is connected to the emitter electrode 12.

Also in this embodiment, since the IGBT cell and the dummy cell are present, the load short-circuit withstand capability is larger than that of the related art.

In the IGBT according to the present embodiment, the amount of holes (h
When the ratio between 1) and the amount of holes (h2) discharged from the dummy cell was examined, it was found that h1: h2 = 59: 41.

(Eighth Embodiment) FIG. 12 is a sectional view showing an IGBT having a trench structure according to an eighth embodiment of the present invention.

The present embodiment differs from the seventh embodiment in that the number of dummy cells in contact with the drain electrode 22 is reduced. The p-type drain layer 21 is not formed in the dummy cell not in contact with the drain electrode 22.

Also in the present embodiment, the load short-circuit withstand capability is larger than in the prior art. In addition, since the number of dummy cells in contact with the drain electrode 22 is reduced, in the on state, the amount of holes discharged to the outside of the device through the dummy cell is reduced, and holes are easily accumulated in the device. . Therefore, the ON voltage can be reduced.

The IGBT according to the present embodiment has the following characteristics.
When the ratio of the hole amount (h1) discharged from the GBT cell to the hole amount (h2) discharged from the dummy cell was examined, it was found that h1: h2 = 67: 33. IGBT
The form of the combination of the cell and the dummy cell is not limited to that of the present embodiment, and various forms are conceivable.

(Ninth Embodiment) FIG. 13 is a sectional view and an equivalent circuit of an IGBT having a trench structure according to a ninth embodiment of the present invention.

In this embodiment, an IGBT cell in which a channel whose width between two trenches 4 is W1 is formed,
Dummy cells in which a channel having a width W2 (<W1) between two trenches 4 is not formed are alternately formed.

In the IGBT cell, a p-type base layer 7 and an n-type emitter layer 8 are formed as usual, and these 7, 8 are short-circuited in the lateral direction by an emitter electrode 12.

On the other hand, in the dummy cell, a p-type drain layer 21 is formed instead of the p-type base layer 7. A drain electrode 22 is provided on the p-type drain layer 21, and the drain electrode 22 is connected to the emitter electrode 12.

Here, since W1> W2, the IGBT
A point (A1, A2) at the same depth as the trench bottom of the n-type base layer 1 of the cell. The resistance R1 between the collector electrode 10 and the emitter electrode 12 is lower than the resistance R2 between the dummy cell and the drain electrode 22. Become.

Note that W1 = W2 and p-type drain layer 2
1 can be made lower than that of the p-type base layer 7 to obtain a similar resistance magnitude relationship (R1 <<).
R2) can be realized. Alternatively, as shown in FIG.
By making the type drain layer 9 shallow, the magnitude relationship (R1 <R2) of the resistance can also be realized.

The operation of the IGBT thus configured is as follows.
The driving method is the same as that of the conventional IGBT.
That is, to turn on the device, a positive voltage is applied to the collector electrode 10 and the emitter electrode 12 and the drain electrode 2
With a negative voltage applied to the gate electrode 2, a positive voltage with respect to the emitter electrode 12 is applied to the gate electrode 6.

As a result, an n-type channel is formed on the surface of p-type base layer 7 in contact with the side surface of trench 4, and
As shown in (a), electrons e are transferred from n-type emitter layer 8 to n-type emitter layer 8.
The n-type base layer 1 is injected through the type channel to reach the p-type collector layer 3, and accordingly, holes h are injected from the p-type collector layer 3 into the n-type base layer 1. In this way, both the electron e and the hole h are injected into the n-type base layer 1, and n
Conduction modulation occurs in the mold base layer 1, and the device becomes conductive.

Here, the difference from the prior art is that the holes h injected from the p-type collector layer 3 into the n-type base layer 1 are formed by a path in which electrons exist at a high concentration to satisfy the charge neutral condition, that is, a resistance. Flow through the inter-trench region of the IGBT cell having a low drain voltage, so that the drain electrode 22
(That is, the ratio of the hole current discharged to the emitter electrode 12) can be suppressed to a small value.

In other words, since R1 <R2 in the on state, the amount of holes discharged to the outside of the device through the p-type drain layer 21 is reduced. As a result, the carrier (electron concentration) is higher than that of the conventional IGBT. e, holes h) are accumulated in the n-type base layer 1. As a result, the ON voltage decreases.

On the other hand, to turn off the device, a negative voltage is applied to the gate electrode 6 with respect to the emitter electrode 12.

As a result, the n-type channel formed on the surface of the p-type base layer 7 in contact with the side surface of the trench 4 disappears, stopping the electron injection and accumulating in the n-type base layer 1. Some of the holes h are discharged to the emitter electrode 12 (drain electrode 22) via the p-type base layer 7 and the p-type drain layer 21, and the remaining holes h recombine with the electrons e and disappear. . As the carriers (electrons e and holes h) in the device disappear in this way, the device is turned off.

Here, the difference from the prior art is that FIG.
As shown in FIG. 5, since the p-type accumulation layer is formed on the surface of the n-type base layer 1 in contact with the side wall of the trench 4, the resistance of the hole h discharge path passing through the p-type drain layer 21 is in the ON state. The resistance is lower than the resistance (R ₂ ′ << R ₂ ), while the resistance of the hole h exhaust path through the p-type base layer 7 is higher than the resistance in the ON state (R ₁ ′> R _1). ). It should be noted that those marked with 'indicate resistance at turn-off.

Since the n-type emitter layer 8 is not formed on the p-type drain layer 21, the p-type drain layer 21
Is smaller than the resistance of the hole h discharge path through the p-type base layer 7 (R ₁ ′>
R ₂ ').

As a result, at the time of turn-off, the resistance of the hole h discharge path passing through the p-type drain layer 21 becomes slightly smaller than the resistance of the hole h discharge path passing through the p-type base layer 7 (R1 ≧ R2). The hole current is effectively discharged.

In other words, at the time of turn-off, R ₁ ′ ≧
Since R ₂ ′, the amount of holes discharged out of the device via the p-type drain layer 21 increases, and the holes are discharged out of the device via the p-type base layer 7 immediately below the n-type emitter layer 8. Reduce the amount of holes.

As a result, the potential of the p-type base layer 7 immediately below the n-type emitter layer 8, which has been a problem in the conventional IGBT, is reduced by the pn composed of the n-type emitter layer 8 and the p-type base layer 7.
The latch-up of the parasitic thyristor structure caused by exceeding the built-in voltage of the junction can be prevented.

As described above, according to the present embodiment, R1 << R2 in the on state, and R ₁ ′ ≧ R in the off state.
_By designing the element to be ₂ ', that is, by reducing the amount of holes discharged out of the element via the p-type drain layer 21 in the on state and increasing it in the turn-off state, , And the latch-up of the parasitic thyristor structure can be prevented.

If the amount of holes discharged out of the device through the p-type drain layer 21 is increased by controlling R ₁ ′ ≧ R ₂ ′ when the load is short-circuited, the overcurrent Can be protected, and the load short-circuit tolerance can be increased.

(Tenth Embodiment) FIG. 16 shows an IGBT having a trench structure according to a tenth embodiment of the present invention.
2 is a sectional view and an equivalent circuit of FIG.

The present embodiment differs from the ninth embodiment in that the amount of holes discharged out of the device via the p-type drain layer 21 is controlled by the depletion layer.

In this embodiment, as shown in FIG. 16, the impurity concentration of the p-type drain layer 21 is set lower than that of the p-type base layer 7 so that the depletion layer can be used. Also, p
On the surface of the type drain layer 21, a p-type contact layer 23 is formed in order to reduce the contact resistance of the drain electrode 22.

With such a configuration, in the turn-on state, a positive voltage is applied to the gate electrode 6 and the structure shown in FIG.
(A), as shown in FIG. 18 (b), the p-type drain layer 2
1, a depletion layer is formed, pinch-off occurs, and a potential barrier against holes is generated.

As a result, the resistance of the hole h discharge path passing through the p-type drain layer 21 becomes larger than the resistance of the hole h discharge path passing through the p-type base layer 7, that is, the p-type drain layer 21 , The amount of holes (electrons e, holes h) having a higher concentration than in the conventional IGBT is accumulated in the n-type base layer 1, and the on-voltage is reduced.

On the other hand, when the transistor is turned off, a negative voltage is applied to the gate electrode 6, the depletion layer disappears, and the potential barrier for holes disappears, so that holes are also discharged from the p-type drain layer 21. Therefore, occurrence of latch-up of the parasitic thyristor structure can be prevented.

As shown in FIGS. 17 (b) and 18 (c), the potential barrier against holes is reduced, and as a result, the p-type drain layer 21 in contact with the side wall of trench 4 is formed.
A p-type accumulation layer is also formed on the surface of the n-type base layer 1 in contact with the side wall of the trench 4 as in the tenth embodiment.
Since the p-type storage layer is formed on the surface of the semiconductor device, the occurrence of latch-up of the parasitic thyristor structure can be more effectively prevented.
Further, similarly to the ninth embodiment, the load short-circuit capacity can be increased.

(Eleventh Embodiment) FIG. 19 shows an IGBT having a trench structure according to an eleventh embodiment of the present invention.
2 is a sectional view and an equivalent circuit of FIG.

The present embodiment differs from the ninth embodiment in that the amount of holes discharged from the p-type drain layer 21 to the outside of the device is controlled by a Schottky diode.

In order to use a Schottky diode, in this embodiment, as shown in FIG. 19, the impurity concentration of the p-type drain layer 23 is reduced, and A
A Schottky electrode 24 made of a metal such as l or W is used.

To turn on the device, a positive voltage is applied to the gate electrode 6 as usual. At this time, since the rise in the potential of the p-type base layer 7 is small, the shot diode remains off. Therefore, the p-type drain layer 24
No holes are discharged to the outside of the element via the. As a result, carriers are effectively accumulated in the n-type base layer 1, and
The ON voltage decreases. For reference, FIG.
The band diagram of the p-type base layer 7 when the voltage V _pb of the p-type base layer 7 is 0 V is shown.

When an overcurrent flows through the element, p
The voltage V _pb of the mold base layer 7 increases, and the shot diode is turned on. As a result, holes in the device are discharged out of the device via the p-type drain layer 21, so that the occurrence of latch-up of the parasitic thyristor structure can be prevented and the device can be protected from overcurrent.

FIG. 21 shows the present embodiment and a conventional IGB.
4 shows a characteristic diagram of a collector current-collector voltage of T. FIG. From the figure, it can be seen that the collector current-collector voltage characteristics of the IGBT of the present embodiment exhibit saturation characteristics, unlike those of the conventional IGBT. That is, the IGBT of the present embodiment
Can be more easily protected from overcurrent than conventional ones.

(Twelfth Embodiment) FIG. 22 shows an IGBT having a trench structure according to a twelfth embodiment of the present invention.
FIG.

This embodiment is different from the ninth embodiment in that the p-type drain layer 21 and the p-type drain electrode 22 are formed in the depth direction.

Here, the dimension in the depth direction of the p-type drain layer 21 (the dimension in the direction parallel to the longitudinal direction of the trench 4).
Is smaller than that of the p-type base layer 7. To make the same, the impurity concentration of the p-type drain layer 21 is made lower than that of the p-type base layer 7, or the p-type drain layer 9 is formed shallower.

Also in this embodiment, at the time of turn-on, the resistance of the hole discharge path passing through the p-type drain layer 21 is higher than that of the p-type drain layer 21 by p-type.
The height is higher than that of the hole discharge path through the mold base layer 7, that is, the amount of holes discharged from the p-type drain layer 21 to the outside of the device is reduced, and carriers are effectively contained in the n-type base layer 1. , The ON voltage can be reduced.

On the other hand, at the time of turn-off, a p-type accumulation layer is formed on the surface of n-type base layer 1 in contact with the side wall of trench 4, and n-type emitter layer 8 is not formed on p-type drain layer 21. In addition, since the resistance of the discharge path of the holes h passing through the p-type drain layer 21 is smaller than the resistance of the discharge path of the holes h passing through the p-type base layer 7, that is, Since the amount of holes to be discharged increases, the latch-up of the parasitic thyristor structure can be prevented. Further, similarly to the ninth embodiment, the load short-circuit tolerance can be increased. FIGS. 23 and 24 are cross-sectional views taken along the line AA ′ of the IGBT of FIG. 22 at the time of turn-off.
The sectional view taken along the line BB 'is shown.

(Thirteenth Embodiment) FIG. 25 shows an IGBT having a trench structure according to a thirteenth embodiment of the present invention.
FIG. FIG. 26 shows the IGB of FIG.
A sectional view taken along the line AA ′ of T is shown.

The present embodiment is different from the first embodiment in that the longitudinal direction of the trench 4 (channel width direction) is different from that of the first embodiment.
This is because the interval between two adjacent p-type contact layers 9 and the interval between the n-type emitter layers 8 in contact with them are increased.

An interlayer insulating film 11 is provided on the p-type base layer 7 in a region sandwiched by these p-type contact layers 9 so that the emitter electrode 12 does not contact the p-type base layer 7. I have.

According to the present embodiment, since the interval between two adjacent p-type contact layers 9 is increased in the longitudinal direction of trench 4, the p-type base in the region sandwiched by these p-type contact layers 9 is formed. The layer 7 has a higher resistance than the p-type contact layer 9 and the n-type emitter layer 8 in contact therewith.

Therefore, in the ON state, as shown in FIG. 26, most of the holes h do not pass under the p-type base layer 7 in the wide area, but the p-type contact layer 9 and the n-type emitter layer in the narrow area. 8 will pass below. As a result, the hole concentration on the side of the emitter electrode 12 is increased, the injection of electrons from the n-type emitter layer 8 is promoted, and the on-resistance is reduced.

On the other hand, when the current density becomes high such as at the time of turn-off or load short-circuit, holes do not concentrate only under the n-type emitter layer 8 but once enter the p-type base layer 7 and Since there is also a bypass path to escape, it is possible to prevent the latch-up of the parasitic thyristor structure and improve the load short-circuit tolerance.

(Fourteenth Embodiment) FIG. 27 shows an IGBT having a trench structure according to a fourteenth embodiment of the present invention.
FIG. The sectional view of FIG. 27 corresponds to the sectional view of FIG. 26 of the thirteenth embodiment.

This embodiment is different from the thirteenth embodiment in that the p-type contact layer 9 is formed in the longitudinal direction of the trench 4.
And the other p-type base layer 7 is omitted except for the p-type base layer 7 near the periphery of the n-type emitter layer 8.

As a result, regarding the longitudinal direction of the trench 4,
Most of the region sandwiched between two adjacent p-type contact layers 9 is the n-type base layer 1 having a higher resistance than the p-type base layer 7.
Will occupy.

Therefore, if the size of the region sandwiched between two adjacent p-type contact layers 9 in the longitudinal direction of trench 4 is the same as that of the thirteenth embodiment, more holes are formed in the narrow region. Since the current passes under the p-type contact layer 9 and the type emitter layer 8, the on-voltage can be further reduced.

On the other hand, when the ON voltage is the same as that of the thirteenth embodiment, the size of the region sandwiched between two adjacent p-type contact layers 9 in the longitudinal direction of the trench 4 is reduced to the thirteenth embodiment. Since it can be smaller than that of the embodiment, the area efficiency can be made higher than that of the thirteenth embodiment.

(Fifteenth Embodiment) FIG. 28 shows an IGBT having a trench structure according to a fifteenth embodiment of the present invention.
FIG. The sectional view of FIG. 28 corresponds to the sectional view of FIG. 26 of the thirteenth embodiment.

The present embodiment is different from the fourteenth embodiment in that the p-type floating layer is in contact with the trench (gate insulating film 5) on the surface of the n-type base layer 1 in the region where the p-type base layer 7 is omitted. 25.

Since the IGBT of the fourteenth embodiment partially omits the p-type base layer 7 where it should be, it is difficult to design the IGBT in terms of withstand voltage.

However, according to the present embodiment, at the time of turn-off, a p-type inversion layer is formed on the surface of n-type base layer 1 in contact with trench (gate insulating film 5), and p-type floating layer is formed via this p-type inversion layer. Layer 25 is electrically connected to p-type base layer 7.

As a result, since the potential of the n-type base layer 1 in the region excluding the p-type base layer 7 is fixed, the breakdown voltage is increased. In the on state, the p-type floating layer 25 is electrically separated from the p-type base layer 7, and the on-voltage drops.

(Sixteenth Embodiment) FIG. 29 shows an IGBT having a trench structure according to a sixteenth embodiment of the present invention.
FIG. The sectional view of FIG. 29 corresponds to the sectional view of FIG. 26 of the thirteenth embodiment.

The first point of the present embodiment that differs from the fourteenth embodiment is that the interlayer insulating film 11 is eliminated and the emitter electrode 12 is removed.
Is in contact with the p-type ballast layer 26. As a result, the holes for discharging holes at the time of turn-off or load short-circuiting are widened, so that the latch-up of the parasitic thyristor structure can be more effectively prevented, and the load short-circuit capacity can be further increased.

Further, the present embodiment is different from the fourteenth embodiment in that the surface of the n-type base layer 1 where the p-type base layer 7 is omitted is designed to have a low impurity concentration and a high resistance. That is, the P-type ballast layer 26 is provided. Thereby, the discharge of holes in the ON state is restricted, so that an increase in ON voltage can be suppressed.

(Seventeenth Embodiment) FIG. 30 shows an IGBT having a trench structure according to a seventeenth embodiment of the present invention.
FIG.

This embodiment is different from the thirteenth embodiment in that no contact is made with the emitter electrode 12 along the direction perpendicular to the longitudinal direction of the trench 4 (channel length direction).
That is, the presence of the mold emitter layer 8. This emitter electrode 12 is insulated from the n-type emitter layer 8 by the interlayer insulating film 11.

According to such a structure, concentration of hole current also occurs in the direction perpendicular to the longitudinal direction of trench 4, that is, the density of hole current under n-type emitter layer 8 in contact with emitter electrode 12. And the injection of electrons from the n-type emitter layer 8 is promoted, and the on-voltage is reduced.

Therefore, according to the present embodiment, n is set in the direction parallel to the longitudinal direction of the trench 4 (Y-axis direction) and the direction perpendicular to the longitudinal direction of the trench 4 (X-axis direction).
Since the injection of electrons from the mold emitter layer 8 is promoted, the on-voltage can be further reduced.

(Eighteenth Embodiment) FIG. 31 is a plan view of an IGBT having a trench structure according to an eighteenth embodiment of the present invention, FIG. 32 is a sectional view of the IGBT taken along the line AA ′, and FIG.
It shows a B ′ sectional view, a CC ′ sectional view, and a DD ′ sectional view.

The present embodiment is different from the first embodiment in that the p-type contact layer 9 has a pattern advantageous for miniaturization of the device.

That is, the p-type contact layer 9 of the present embodiment has a pattern that does not contact the edge of the n-type emitter layer 8 that contacts the trench 4 where the channel is formed.

The p-type contact layer 9 having such a pattern
Then, it is possible to prevent the p-type impurity from diffusing into the channel region in the diffusion step of forming the same.

Therefore, according to the present embodiment, even if the channel region is reduced by miniaturizing the device, the n-type emitter layer 8 in the channel region is reduced to such an extent that the device characteristics are deteriorated, or Region n-type emitter layer 8
The problem of disappearing does not occur.

The present invention is not limited to the above embodiment. For example, in the above embodiment, the case of the IGBT was described. However, the present invention relates to an IEGT (Injection Enha
ncement Gate Transistor). Further, the above embodiments may be appropriately combined and implemented. In addition, various modifications can be made without departing from the scope of the present invention.

[0182]

As described in detail above, according to the present invention, a power semiconductor device which can solve the above-described first to fifth problems can be realized.

[Brief description of the drawings]

FIG. 1 is a plan view of an IGBT having a trench structure according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the line A-A ′ in the plan view.

FIG. 3 is a sectional perspective view of the IGBT.

FIG. 4 is a plan view of an IGBT having a trench structure according to a second embodiment of the present invention.

FIG. 5 is a sectional view of an IGBT having a trench structure according to a third embodiment of the present invention.

FIG. 6 is a plan view of an IGBT having a trench structure according to a fourth embodiment of the present invention.

FIG. 7 is a cross-sectional view taken along the line A-A ′ in the plan view.

FIG. 8 is a sectional perspective view of the IGBT.

FIG. 9 is a sectional view showing an IGBT having a trench structure according to a fifth embodiment of the present invention.

FIG. 10 is a sectional view showing an IGBT having a trench structure according to a sixth embodiment of the present invention.

FIG. 11 is a sectional view showing an IGBT having a trench structure according to a seventh embodiment of the present invention.

FIG. 12 is a sectional view showing an IGBT having a trench structure according to an eighth embodiment of the present invention.

FIG. 13 is a sectional view and an equivalent circuit of an IGBT having a trench structure according to a ninth embodiment of the present invention.

FIG. 14 is a diagram showing a carrier flow in the device for explaining the operation of the IGBT.

FIG. 15 is a sectional view showing another structure for realizing R1 <R2.

FIG. 16 is a sectional view and an equivalent circuit of an IGBT having a trench structure according to a tenth embodiment of the present invention.

FIG. 17 is a diagram showing a carrier flow in the device for explaining the operation of the IGBT.

FIG. 18 is a band diagram for explaining the operation of the IGBT.

FIG. 19 is a sectional view and an equivalent circuit of an IGBT having a trench structure according to an eleventh embodiment of the present invention.

FIG. 20 is a band diagram of the p-type base layer when the voltage of the p-type base layer is 0 V;

FIG. 21 is a diagram showing a characteristic diagram of collector current-collector voltage of FIG. 18 and a conventional IGBT.

FIG. 22 is a sectional view of an IGBT having a trench structure according to a twelfth embodiment of the present invention.

FIG. 23 is a sectional view taken along the line AA ′ of the IGBT when it is turned off.

FIG. 24 is a sectional view taken along the line BB ′ of the IGBT when it is turned off.

FIG. 25 is a sectional perspective view of an IGBT having a trench structure according to a thirteenth embodiment of the present invention.

FIG. 26 is a sectional view taken along the line A-A ′ of the IGBT.

FIG. 27 is a sectional view of an IGBT having a trench structure according to a fourteenth embodiment of the present invention.

FIG. 28 is a sectional view of an IGBT having a trench structure according to a fifteenth embodiment of the present invention.

FIG. 29 is a sectional view of an IGBT having a trench structure according to a sixteenth embodiment of the present invention.

FIG. 30 is a sectional perspective view of an IGBT having a trench structure according to a seventeenth embodiment of the present invention.

FIG. 31 is a plan view of an IGBT having a trench structure according to an eighteenth embodiment of the present invention.

FIG. 32 is a cross-sectional view of the IGBT taken along the lines AA ′, BB ′, CC ′, and DD ′;

FIG. 33 is a cross-sectional view showing an IGBT having a conventional trench structure.

FIG. 34 is a circuit diagram showing a load short-circuit test circuit of the IGBT.

FIG. 35 is a waveform chart showing a load short-circuit test waveform of the IGBT.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... n-type base layer (1st conductivity type base layer) 2 ... n-type buffer layer 3 ... p-type collector layer (2nd conductivity type collector layer) 4 ... Trench (groove) 5 ... Gate insulating film 6 ... Gate electrode 7 ... p-type base layer (second conductivity type base layer) 8 ... n-type emitter layer (first conductivity type emitter layer) 9 ... p-type contact layer (second conductivity type contact layer) 10 ... collector electrode 11 ... interlayer insulating film DESCRIPTION OF SYMBOLS 12 ... Emitter electrode 21 ... P-type drain layer (2nd conductivity type drain layer) 22 ... Drain electrode 23 ... P-type contact layer (2nd conductivity type contact layer) 24 ... Schottky electrode 25 ... P-type floating layer 26 ... P Mold ballast layer

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Masahiro Tanaka 1 Tokoba, Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa

Claims (11)

[Claims] 1. A power semiconductor device including an insulated gate power semiconductor element, wherein the insulated gate power semiconductor element includes a high-resistance first conductivity type base layer and a first conductivity type base layer. A second conductivity type base layer formed on the surface; a first conductivity type emitter layer selectively formed on the surface of the second conductivity type base layer; a first conductivity type emitter layer and the second conductivity type A gate electrode that penetrates the base layer and is buried via a gate insulating film in a groove reaching a depth in the middle of the first conductivity type base layer; A second conductivity type contact layer selectively formed to be in contact with the trench and the first conductivity type emitter layer; and a first conductivity type base opposite to a surface on which the first conductivity type emitter layer is formed. The second conductive type core formed on the surface of the layer A collector layer provided on the second conductivity type base layer via the second conductivity type contact layer; and an emitter electrode provided on the second conductivity type base layer via the second conductivity type contact layer. The first conductive type emitter layer and the second conductive type contact layer have dimensions in the channel width direction of W1 and W, respectively.
2. A power semiconductor device, satisfying a condition of W1 / (W1 + W2) ≦ 0.4 when 2. 2. The power semiconductor device according to claim 1, wherein said W1 is 3 μm or less. 3. A power semiconductor device including an insulated gate power semiconductor element, wherein the insulated gate power semiconductor element includes a high resistance first conductivity type base layer, and a first conductivity type base layer. A second conductivity type base layer formed on the surface; a first conductivity type emitter layer selectively formed on the surface of the second conductivity type base layer; a first conductivity type emitter layer and the second conductivity type A gate electrode that penetrates the base layer and is buried via a gate insulating film in a groove reaching a depth in the middle of the first conductivity type base layer; A second conductivity type contact layer selectively formed to be in contact with the trench and the first conductivity type emitter layer; and a first conductivity type base opposite to a surface on which the first conductivity type emitter layer is formed. The second conductive type core formed on the surface of the layer A collector layer provided on the second conductivity type base layer via the second conductivity type contact layer; and an emitter electrode provided on the second conductivity type base layer via the second conductivity type contact layer. And a dimension in the channel width direction of the first conductivity type emitter layer is 3
A power semiconductor device, which is not more than μm. 4. A power semiconductor device including an insulated gate power semiconductor element, wherein the insulated gate power semiconductor element includes a high-resistance first conductivity type base layer and a first conductivity type base layer. A second conductivity type base layer formed on the surface; a first conductivity type emitter layer and a second conductivity type collector layer selectively formed on the surface of the second conductivity type base layer; A gate electrode buried through a gate insulating film in a groove that penetrates the base layer and the second conductivity type base layer and reaches a middle depth of the first conductivity type base layer; A second conductivity type collector layer formed on a surface of the first conductivity type base layer opposite to a surface on which the emitter layer is formed; and a second conductivity type provided on the first conductivity type emitter layer. The second through a contact layer An emitter electrode provided on a conductive type base layer, and a collector electrode provided on the second conductive type collector layer, wherein the plurality of grooves are formed, and the plurality of grooves are divided by the plurality of grooves. A part of the first conductive type emitter layer is not electrically connected to the emitter electrode, and is electrically connected to the emitter electrode among the plurality of divided first conductive type emitter layers. When the dimensions in the channel width direction of the first conductivity type emitter layer and the type 2 contact layer are W1 and W2, respectively, the condition of W1 / (W1 + W2) ≦ 0.4 is satisfied. Characteristic power semiconductor device. 5. A power semiconductor device including an insulated gate power semiconductor element, wherein the insulated gate power semiconductor element includes a high resistance first conductivity type base layer, and a first conductivity type base layer. A second conductivity type base layer formed on the surface; a first conductivity type emitter layer selectively formed on the surface of the second conductivity type base layer; a first conductivity type emitter layer and the second conductivity type A gate electrode embedded through a gate insulating film in a groove penetrating the base layer and reaching a middle depth of the first conductivity type base layer; Means for discharging carriers out of the device without passing through the second conductivity type base layer on which the first conductivity type emitter layer is formed; and the first conductivity type on the opposite side to the surface on which the first conductivity type emitter layer is formed. Formed on the surface of the base layer A second conductivity type collector layer; an emitter electrode provided on the first conductivity type emitter layer and the second conductivity type base layer; and a collector electrode provided on the second conductivity type collector layer. A power semiconductor device characterized by the above-mentioned. 6. A power semiconductor device including an insulated gate power semiconductor element, wherein the insulated gate power semiconductor element includes a high-resistance first conductivity type base layer and a first conductivity type base layer. A second conductivity type base layer formed on the surface; a first conductivity type emitter layer selectively formed on the surface of the second conductivity type base layer; a first conductivity type emitter layer and the second conductivity type A gate electrode that penetrates the base layer and is buried through a gate insulating film in a groove reaching a depth in the middle of the first conductivity type base layer; and a gate electrode formed on the surface of the second conductivity type base layer. A high impurity concentration second conductivity type drain layer formed in a region where the first conductivity type emitter layer is not formed between the trenches; Formed on the surface of the first conductivity type base layer A second conductivity type collector layer, an emitter electrode provided on the first conductivity type emitter layer and the second conductivity type base layer, and an emitter electrode provided on the second conductivity type drain layer. A power semiconductor device comprising: a drain electrode connected to the collector electrode; and a collector electrode provided on the second conductivity type collector layer. 7. A power semiconductor device including an insulated gate type power semiconductor element, wherein the insulated gate type power semiconductor element includes a high resistance first conductivity type base layer and a first conductivity type base layer. A second conductivity type base layer formed on the surface; a first conductivity type emitter layer selectively formed on the surface of the second conductivity type base layer; a first conductivity type emitter layer and the second conductivity type A gate electrode buried via a gate insulating film in a groove penetrating through the base layer and reaching a middle depth of the first conductivity type base layer; and selectively covering a surface of the first conductivity type base layer. A second conductivity type drain layer for discharging carriers having the same polarity as the majority carrier of the second conductivity type base layer; and the carriers discharged out of the device via the second conductivity type drain layer. Control to control the amount of Means, a second conductivity type collector layer formed on a surface of the first conductivity type base layer opposite to a surface on which the first conductivity type emitter layer is formed, the first conductivity type emitter layer and the second conductivity type collector layer. An emitter electrode provided on the second conductivity type base layer; a drain electrode provided on the second conductivity type drain layer and electrically connected to the emitter electrode; and a drain electrode provided on the second conductivity type collector layer. A power semiconductor device comprising a collector electrode. 8. The carrier control device according to claim 7, wherein said carrier control means reduces the discharge amount of said carrier in an on state, and increases the discharge amount of said carrier at the time of turn-off or overcurrent application. 3. The power semiconductor device according to claim 1. 9. A power semiconductor device including an insulated gate power semiconductor element, wherein the insulated gate power semiconductor element includes a high-resistance first conductivity type base layer, and a first conductivity type base layer. A second conductivity type base layer formed on the surface; a first conductivity type emitter layer selectively formed on the surface of the second conductivity type base layer; the second conductivity type base layer; and the first conductivity type A gate electrode buried via a gate insulating film in a trench that penetrates the emitter layer and reaches a middle depth of the first conductivity type base layer; and a surface on which the first conductivity type emitter layer is formed. A second conductivity type collector layer formed on the surface of the first conductivity type base layer opposite to the first conductivity type, an emitter electrode connected to the first conductivity type emitter layer and the second conductivity type base layer, Provided on the second conductivity type collector layer ; And a collector electrode, by forming a region where the emitter electrode is connected to the first conductive type emitter layer at a predetermined interval,
A power semiconductor device, wherein a carrier concentration of the first conductivity type base layer on the side of the second conductivity type base layer is increased in an ON state. 10. A power semiconductor device including an insulated gate power semiconductor element, wherein the insulated gate power semiconductor element includes a high-resistance first conductivity type base layer and a first conductivity type base layer. A second conductivity type base layer formed on the surface; a first conductivity type emitter layer and a second conductivity type contact layer selectively formed on the surface of the second conductivity type base layer; and a first conductivity type emitter layer And a gate electrode buried through a gate insulating film in a groove penetrating the second conductive type base layer and reaching a middle depth of the first conductive type base layer; and the first conductive type emitter. A second conductivity type collector layer formed on the surface of the first conductivity type base layer opposite to a surface on which the layer is formed; and a second conductivity type contact provided on the first conductivity type emitter layer. The second conduction through a layer An emitter electrode provided on an electric base layer; and a collector electrode provided on the second conductive collector layer, wherein the second conductive contact layer is a channel of the first conductive emitter layer. A power semiconductor device, which is not in contact with an edge portion in contact with the groove where the groove is formed. 11. The first conductivity type emitter layer and the second conductivity type contact layer are alternately and selectively formed in a stripe shape on the surface of the second conductivity type base layer. The power semiconductor device according to claim 1.