JP6154383B2 - Insulating substrate, multilayer ceramic insulating substrate, joined structure of power semiconductor device and insulating substrate, and power semiconductor module - Google Patents

Description

  The present invention relates to an insulating substrate, a multilayer ceramic insulating substrate, a power semiconductor device / insulating substrate bonding structure, and a power semiconductor module that have high resistance to thermal cycle stress with a large temperature difference.

  A power semiconductor device using a wide bandgap semiconductor such as silicon carbide (SiC), gallium nitride (GaN), diamond (C), etc., even at a high semiconductor junction temperature (Tj), silicon (Si) or gallium arsenide ( Compared with a power semiconductor device using GaAs), the on-resistance is low, and there is an advantage that high-speed switching is possible. For this reason, it is possible to reduce the size of the semiconductor device. At the same time as miniaturization, the passive components and coolers that make up the system can be miniaturized, and it is expected that a compact, lightweight, and low-priced power electronics system can be realized.

  In order to actualize such a power electronics system, it is high at a high semiconductor junction temperature Tj (for example, Tj> 200 ° C.) and a wide temperature range ΔTj (for example, Tj = −40 ° C. to 300 ° C.). A power semiconductor module that operates reliably must be realized.

  In order to solve such a problem, a power semiconductor module disclosed in Japanese Patent Laid-Open No. 2008-270353 (Patent Document 1) has been proposed. In the power semiconductor module, a combination of a semiconductor element, an insulating portion, and a heat sink is used.

  The power semiconductor module disclosed in Patent Document 1 has a reliability that can withstand about 2000 cycles in a thermal cycle test in which the maximum semiconductor junction temperature (Tj) is 200 ° C. and the temperature range (ΔTj = 240 ° C.). It is disclosed to have.

JP 2008-270353 A

  However, the power semiconductor module disclosed in Patent Document 1 tries to operate in an environment having a higher maximum temperature Tj and a larger temperature range (for example, Tj = −40 ° C. to 250 ° C., ΔTj = 290 ° C.). In this case, there are the following problems. The joint between the power semiconductor device constituting the power semiconductor module and the insulating substrate joining structure fails with an extremely small number of cycles, and practically cannot be put to practical use in this temperature region.

  The present invention has been made in order to solve such a conventional problem, and the object of the present invention is to be used in an environment of a thermal cycle where the semiconductor junction temperature (Tj) is high and the temperature range (ΔTj) is wide. It is another object of the present invention to provide an insulating substrate, a multilayer ceramic insulating substrate, a power semiconductor device / insulating substrate bonding structure, and a power semiconductor module that operate with high reliability.

A multilayer ceramic insulating substrate according to one embodiment of the present invention is formed by bonding a plurality of insulating substrates, and includes a ceramic substrate and a low heat stretchable metal plate attached to the upper surface and the lower surface of the ceramic substrate. The low thermal stretchable metal plate includes a pair of Cu plates having substantially the same thickness and a low thermal expansion metal plate provided between the pair of Cu plates and having a thermal expansion coefficient lower than that of the Cu plate. The lower surface of the low heat stretchable metal plate attached to the lower surface of the ceramic substrate constituting one insulating substrate is joined to the upper surface of the low heat stretchable metal plate attached to the upper surface of the ceramic substrate constituting the other insulating substrate. The thickness of each of the pair of Cu plates is 1/5 or less of the thickness of the low thermal expansion metal plate.

FIG. 1 is a cross-sectional view showing a main part of an insulating substrate according to first to third embodiments of the present invention. FIG. 2 is a cross-sectional view showing a main part of a multilayer ceramic insulating substrate according to the fourth embodiment of the present invention. FIG. 3 is a cross-sectional view showing a main part of a multilayer ceramic insulating substrate according to the fifth embodiment of the present invention. FIG. 4 is a cross-sectional view showing a main part of a joined structure of a power semiconductor device and an insulating substrate according to the sixth embodiment of the present invention. FIG. 5: is a characteristic view which shows the thermal test result of the joining structure body of the power semiconductor device which concerns on 6th Embodiment of this invention, and an insulated substrate, and the joining structure body concerning a comparative example. 6A and 6B show a power semiconductor module according to a seventh embodiment of the present invention, in which FIG. 6A is a plan view and FIG. FIG. 7 is a cross-sectional view showing a main part of a power semiconductor module according to the eighth embodiment of the present invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following, the configuration of the insulating substrate, the multilayer ceramic insulating substrate, the power semiconductor device / insulating substrate bonding structure, and the power semiconductor module will be described with reference to various schematic views (cross-sectional views, plan views, etc.). In order to facilitate understanding, these schematic diagrams exaggerate the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like.

[Description of Insulating Substrate According to First Embodiment]
Hereinafter, the insulating substrate according to the first embodiment will be described. The insulating substrate according to the first embodiment solves the problem of “Cu plate peeling”. This problem may occur in a conventional power semiconductor module in which Cu plates are attached to both sides of a SiN insulating substrate.

  FIG. 1 is a cross-sectional view showing an insulating substrate according to the first embodiment of the present invention. As shown in FIG. 1, the insulating substrate 100 according to the first embodiment is provided with a ceramic substrate 21 made of SiN (silicon nitride) at substantially the center in the thickness direction. The thickness of the ceramic substrate 21 is desirably 0.1 mm or more and 2 mm or less, and preferably 0.31 mm.

  Further, low thermal stretchable metal plates 12-1 and 12-2 are joined to both surfaces (lower surface and upper surface) of the ceramic substrate 21, respectively. The low heat stretchable metal plate is made of, for example, a CIC clad metal plate. Hereinafter, the low thermal stretchable metal plates 12-1 and 12-2 are referred to as CIC clad metal plates 12-1 and 12-2. Each of the CIC clad metal plates 12-1 and 12-2 has the same configuration. The thickness of each CIC clad metal plate 12-1 (12-2) is desirably 0.1 mm or more and 2 mm or less, and preferably 0.37 mm. Here, the CIC clad metal plates 12-1 and 12-2 are a pair of oxygen-free copper plates (Cu plates 14, 14) on both sides of an Inver (registered trademark) alloy plate 13 (containing main components Fe and 36.5 vol% Ni). 15) is a three-layer metal plate joined using a metallurgical method. Further, since the linear expansion coefficient of the Invar alloy plate 13 is as small as about 1.2 ppm / ° C., the Cu plates 14 and 15 having approximately the same thickness (an error of about −1% to + 1%) on both sides of the Invar alloy plate 13. The CIC clad metal plates 12-1 and 12-2 sandwiched between the layers have lower stretchability (or lower synthetic thermal expansion) than the Cu plate alone.

  The thicknesses of the Cu plate 14 and the Cu plate 15 provided on the CIC clad metal plates 12-1 and 12-2 are preferably at least 5 μm or more and 10 μm or more in order to maintain good heat conduction and electrical conduction. It is more desirable. In addition, in the cooling cycle described later, each of the Cu plates 14 and 15 with respect to the Invar alloy plate 13 from the viewpoint of reducing the thermal stress applied to the interface between the ceramic substrate 21 and the CIC clad metal plates 12-1 and 12-2. The thickness ratio (C / I ratio) is preferably made as small as possible to suppress the difference from the linear expansion coefficient of SiN (ceramic substrate 21). Specifically, the thickness of each of the pair of Cu plates 14 and 15 is desirably 1/2 or less, more desirably 1/5 or less of the thickness of the Invar alloy plate 13.

  The ceramic substrate 21 and the CIC clad metal plates 12-1 and 12-2 are joined by an active metal joining method using a brazing agent (not shown) such as Ti—Cu—Ag or Ti—Cu—Ag—Ni. Can be done with. After the CIC clad metal plates 12-1 and 12-2 are bonded to the ceramic substrate 21, the Ni plating film 16 for mounting is formed on the outermost Cu surface of the CIC clad metal plates 12-1 and 12-2. Cover. The Ni plating film 16 is not an essential component in the insulating substrate 100 according to the first embodiment.

  Next, the operation of the insulating substrate 100 according to the first embodiment will be described. In order to verify the effect of the insulating substrate 100 according to the present embodiment, the inventors manufactured an insulating substrate (sample of the first embodiment) and conducted a thermal cycle test. The sample of the first embodiment has a length of 17 mm, a width of 8.5 mm, a thickness of 0.37 mm, and a C / I ratio = 1/8 on each side of the SiN ceramic substrate 21 having a length of 20 mm, a width of 18 mm, and a thickness of 0.31 mm. This is an insulating substrate (sample of this embodiment) to which CIC clad metal plates 12-1 and 12-2 are attached.

  The inventors also produced an insulating substrate (a sample of a comparative example) according to a comparative example. The sample of the comparative example is an insulating substrate using an oxygen-free Cu plate having a length of 17 mm, a width of 8.5 mm, a thickness of 0.3 mm, and a surface plated with Ni instead of the CIC clad metal plates 12-1 and 12-2. It is. A similar thermal cycle test was performed on the sample of the comparative example.

  As a result of the test, in the thermal cycle test of Tj = −40 ° C. to 250 ° C. (ΔTj = 290 ° C.), all the samples in the comparative example failed due to Cu plate peeling in less than 150 cycles. On the other hand, in the sample of the first embodiment, no peeling occurred even after exceeding 10,000 cycles, and the thermal cycle test was completed. In the thermal cycle test of Tj = −40 ° C. to 300 ° C. (ΔTj = 340 ° C.), the insulating substrate according to the comparative example caused a failure due to Cu peeling in less than 60 cycles. On the other hand, it was found that no failure occurred in the insulating substrate 100 according to the first embodiment even when it reached 7300 cycles.

  From the results of the above thermal cycle test, according to the insulating substrate 100 according to the first embodiment of the present invention, the Cu (conductor) plate in the thermal cycle of a high semiconductor junction temperature (Tj) and a wide temperature range (ΔTj). It has been found that can solve the problem of peeling from the SiN ceramic substrate. Specifically, high reliability was obtained in the maximum semiconductor junction temperature Tjmax = 300 ° C. or lower and the temperature range Tj = −40 ° C. to 300 ° C. (ΔTj = 340 ° C.).

  Thus, in the first embodiment of the present invention, the low thermal stretchable metal plates (CIC clad metal plates) 12-1 and 12 formed by sandwiching the Invar alloy plate 13 between the two Cu plates 14 and 15 are used. -2 is attached to both surfaces of a ceramic substrate 21 such as SiN to constitute the insulating substrate 100. For this reason, compared with the insulating substrate according to the comparative example, it is possible to avoid the occurrence of trouble that the Cu (conductor) plate is peeled off from the SiN ceramic substrate due to repeated temperature changes.

  In this embodiment, since the thickness of the ceramic substrate 21 is 0.1 mm or more and 2 mm or less, durability against repeated temperature changes can be further improved.

  The CIC clad metal plates 12-1 and 12-2 are three-layer metal plates in which a pair of Cu plates 14 and 15 are bonded to both sides of an Invar alloy plate (low thermal expansion metal plate) 13 using a metallurgical method. is there. Thereby, it is possible to prevent the Cu plates 14 and 15 from being separated from the Invar alloy plate 13.

  Since the thicknesses of the Cu plate 14 and the Cu plate 15 included in the CIC clad metal plates 12-1 and 12-2 are 5 μm or more, good heat conduction and electric conduction can be maintained.

  The thickness ratio (C / I ratio) of each of the Cu plates 14 and 15 to the Invar alloy plate 13 is set to 1/2 or less. As a result, the thermal stress applied to the interface between the ceramic substrate 21 and the CIC clad metal plates 12-1 and 12-2 in the thermal cycle can be reduced, and the CIC clad metal plates 12-1 and 12 from the ceramic substrate 21 can be reduced. -2 can be prevented from peeling off.

  In the first embodiment, the low thermal stretchable metal plates 12-1 and 12-2 are attached to both surfaces of the ceramic substrate 21. However, the present invention is not limited to any one of the ceramic substrates 21. It is also possible to adopt a configuration in which only one surface is attached.

[Description of Insulating Substrate According to Second Embodiment]
In the first embodiment, an example in which SiN (silicon nitride) excellent in mechanical strength including fracture toughness and bending strength is used as the base material of the ceramic substrate 21 has been described. In the second embodiment, an example in which a ceramic material other than SiN is used as the base material of the ceramic substrate 21 will be described.

Specifically, the ceramic substrate 21 in the second embodiment is made of a ceramic material selected from the group consisting of alumina (Al ₂ O ₃ ), aluminum nitride (AlN), and beryllia (BeO). The thickness of the ceramic substrate 21 is desirably 0.1 mm to 2 mm. Since the insulating substrate according to the second embodiment is the same as the configuration shown in FIG. 1 except that the ceramic substrate is a ceramic material other than SiN, a detailed description of the configuration is omitted.

  Beryllia (BeO) has the advantage of having the highest thermal conductivity among the three ceramic materials described above, but has the disadvantage of being toxic.

Alumina (Al ₂ O ₃ ) has an advantage that the material cost is low compared with SiN or AlN. The mechanical strength is lower than SiN and higher than AlN.

  Aluminum nitride (AlN) has a very high thermal conductivity as compared with alumina and SiN, and is suitable as a material used for the insulating substrate of this embodiment from the viewpoint of heat removal design of a semiconductor chip that generates heat. On the other hand, mechanical strength is weak compared with SiN and alumina. For this reason, there is a drawback that the Cu plate is more easily peeled off in a shorter time than SiN against a thermal cycle stress where the maximum semiconductor junction temperature Tjmax is 200 ° C. or higher and the temperature range (ΔTj) is 250 ° C. or higher.

  Considering the above points, it is considered that aluminum nitride (AlN) is the most practical of the above three ceramic materials. The inventors configured an insulating substrate 100 using aluminum nitride (AlN) as the ceramic substrate 21 shown in FIG. 1, and performed the following thermal cycle test using the insulating substrate 100.

  A CIC clad metal plate 12-1 having a length of 17 mm, a width of 8.5 mm, a thickness of 0.37 mm, and a C / I ratio of 1/8 on both surfaces of an AlN ceramic substrate 21 having a length of 20 mm, a width of 18 mm, and a thickness of 0.64 mm. , 12-2 is manufactured, and a thermal cycle test is performed. The test results are as follows.

  A thermal cycle test of Tj = −40 ° C. to 250 ° C. (ΔTj = 290 ° C.) was performed. As a result, as in the case of using the SiN ceramic substrate shown in the first embodiment, no peeling occurred even after 10,000 cycles. Moreover, the thermal cycle test of Tj = -40 degreeC-300 degreeC ((DELTA) Tj = 340 degreeC) was implemented. As a result, it was found that no failure occurred even after 7300 cycles.

  From the results of the above thermal cycle test, according to the insulating substrate 100 according to the second embodiment of the present invention, the Cu (conductor) plate in the thermal cycle of a high semiconductor junction temperature (Tj) and a wide temperature range (ΔTj). It has been found that can solve the problem of peeling from the AlN ceramic substrate. Specifically, high reliability was obtained in the maximum semiconductor junction temperature Tjmax = 300 ° C. or lower and the temperature range Tj = −40 ° C. to 300 ° C. (ΔTj = 340 ° C.).

  In this manner, in the second embodiment of the present invention, the insulating substrate 100 is configured by attaching the low thermal stretchable metal plates (CIC clad metal plates) 12-1 and 12-2 to both surfaces of the AlN ceramic substrate 21. doing. Thereby, compared with the insulating substrate according to the comparative example, it is possible to avoid the occurrence of trouble that the Cu (conductor) plate is peeled off from the AlN ceramic substrate due to repeated temperature changes.

  Note that a direct Cu bonding method (DCB method) can also be used as a method for bonding the CIC clad metal plates 12-1 and 12-2 according to the second embodiment.

[Description of Insulating Substrate According to Third Embodiment]
Next, an insulating substrate according to the third embodiment will be described. In the first and second embodiments described above, the low heat stretchable metal plates 12-1 and 12-2 are CIC clad metal plates. The low heat stretchable metal plates 12-1 and 12-2 are not limited to CIC clad metal plates. If it is a metal plate having low thermal stretchability, a CMC clad metal plate in which a metal plate other than the Invar alloy plate 13 is sandwiched between Cu plates 14 and 15 can be used as the low thermal stretch metal plates 12-1 and 12-2. . The material of the metal plate other than the Invar alloy plate is “M”. The total thickness of the CMC clad metal plate is desirably 0.1 mm or more and 2 mm or less, and the thickness of the Cu plates 14 and 15 is desirably at least 5 μm or more, preferably 10 μm or more. The ratio (C / M ratio) of each of the Cu plates 14 and 15 to the metal plate other than the Invar alloy plate is desirably 1/2 or less, preferably 1/5 or less, like the CIC clad metal plate. desirable.

  An example of the metal plate material (M) constituting the CMC clad metal plate is molybdenum (Mo). In addition, super invar (containing main components Fe, Ni 32 vol% and Co 5 vol%) and stainless steel invar (containing main components Fe and Co 54 vol%) can be used as the material “M” of the metal plate.

  The inventors manufactured a sample of an insulating substrate including a CMC clad metal plate (low thermal stretchable metal plates 12-1 and 12-2) having a laminated structure of Cu—Mo—Cu and a SiN ceramic substrate 21. And the thermal cycle test of Tj = -40 degreeC-300 degreeC ((DELTA) Tj = 340 degreeC) was implemented. As a result, even if 2000 cycles or more passed, the result that there was no peeling defect of the low thermal stretchable metal plates 12-1 and 12-2 was obtained.

  From the results of the above thermal cycle test, according to the insulating substrate according to the third embodiment of the present invention, the Cu (conductor) plate is used in the thermal cycle of a high semiconductor junction temperature (Tj) and a wide temperature range (ΔTj). It has been found that the problem of peeling from the SiN ceramic substrate can be solved. Specifically, high reliability was obtained in the maximum semiconductor junction temperature Tjmax = 300 ° C. or lower and the temperature range Tj = −40 ° C. to 300 ° C. (ΔTj = 340 ° C.).

  In this way, in the third embodiment of the present invention, the insulating substrate is formed by pasting the CMC clad metal plate as the low thermal stretchable conductor plate on both surfaces of the ceramic substrate such as SiN. This makes it possible to avoid the occurrence of trouble that the Cu (conductor) plate is peeled off from the ceramic substrate due to repeated temperature changes as compared with the insulating substrate according to the comparative example.

In the present embodiment, any one of silicon nitride (SiN), alumina (Al ₂ O ₃ ), aluminum nitride (AlN), and beryllia (BeO) can be used as the ceramic substrate 21. Therefore, the mechanical strength can be increased and the strength of the entire insulating substrate can be improved.

  As a low thermal expansion metal plate, Invar (containing main component Fe, Ni 36.5 vol%), molybdenum (Mo), Super Invar (containing main components Fe, Ni 32 vol% and Co 5 vol%), stainless steel invar (containing main components Fe, Co 54 vol%) Use one of these. Thereby, thermal expansion caused by temperature change can be suppressed, stress applied to the low heat stretchable metal plate can be reduced, and peeling can be prevented from occurring.

[Description of Multilayer Ceramic Insulating Substrate According to Fourth Embodiment]
Next, a multilayer ceramic insulating substrate according to the fourth embodiment of the present invention is described. In the above-described first to third embodiments, the single-layer ceramic insulating substrate in which the low thermal stretchable metal plates 12-1 and 12-2 are attached to both surfaces of the various ceramic substrates 21 has been described. In the fourth embodiment, a multilayer ceramic insulating substrate in which two or more single-layer ceramic insulating substrates are stacked will be described.

  FIG. 2 is a cross-sectional view showing a configuration of a multilayer (for example, two layers) ceramic insulating substrate 200 according to the fourth embodiment. As shown in FIG. 2, the multilayer ceramic insulating substrate 200 includes two insulating substrates that are stacked one above the other, that is, a first insulating substrate member 31 a and a second insulating substrate member 31 b. The basic configuration of each of the insulating substrate members 31a and 31b is substantially the same as that of the insulating substrate 100 shown in FIG. In FIG. 2, the Invar alloy plate 13 and the Cu plates 14 and 15 are the same as those in the first to third embodiments described above, and the description of the configuration is omitted.

  The first insulating substrate member 31a includes a ceramic substrate 21a, a low heat stretchable metal plate 12a-1 attached to the upper surface of the ceramic substrate 21a, and a low heat stretchable metal plate 12a- attached to the lower surface of the ceramic substrate 21a. And 2. Similarly, the second insulating substrate member 31b includes a ceramic substrate 21b, a low heat stretchable metal plate 12b-1 attached to the upper surface of the ceramic substrate 21b, and a low heat stretchable metal attached to the lower surface of the ceramic substrate 21b. Plate 12b-2.

  The wax material Ti—Cu—Ag or Ti—Cu—Ag—Ni (not shown) is composed of the low heat stretchable metal plate 12a-2 of the first insulating substrate member 31a and the low heat stretchable metal of the second insulating substrate member 31b. The plate 12b-1 is joined.

  The advantage of applying the multilayer ceramic insulating substrate 200 is that an intermediate-layer conductor plate (low thermal stretchable metal plates 12a-2 and 12b-1 in the example shown in FIG. 2) can be used as wiring. Thereby, the floating inductance of the multilayer ceramic insulating substrate 200 can be reduced, and the mounting area of the multilayer ceramic insulating substrate 200 can be reduced. In order to make this advantage even more effective, a via window 17 is opened at a predetermined position of the ceramic substrate 21a, and a via window metal plate 18 (for example, Cu) embedded in the via window 17 is used to form an upper portion. The low heat stretchable metal plate 12a-1 may be electrically connected to the lower low heat stretchable metal plate 12a-2. The joining of the low heat stretchable metal plate 12a-1 and the via window metal plate 18 and the joining of the via window metal plate 18 and the low heat stretchable metal plate 12a-2 are performed using an active metal brazing material Ti—Cu— (not shown). Bonding can be performed using Ag, Ti-Cu-Ag-Ni, or the like.

  Next, a method for manufacturing the multilayer ceramic insulating substrate 200 shown in FIG. 2 will be described. First, the first insulating substrate member 31a and the second insulating substrate member 31b are separately manufactured by the same method as the insulating substrate 100 shown in the first to third embodiments. At this time, the Ni plating 16 shown in FIG. 2 is not provided.

  Next, using the active metal brazing material Ti—Cu—Ag, Ti—Cu—Ag—Ni or the like, the low heat stretchable metal plate 12a-2 of the first insulating substrate member 31a and the low heat stretch of the second insulating substrate member 31b are used. The conductive metal plate 12b-1 is bonded together.

  Thereafter, Ni plating 16 is coated on the surfaces (upper surface and lower surface) of the low heat stretchable metal plates 12a-1 and 12b-2. As a result, the multilayer ceramic insulating substrate 200 shown in FIG. 2 is completed. In order to improve the wettability of the high-temperature solder, an Au plating layer, an Ag plating layer, or a Cu plating layer may be coated on the Ni plating 16.

  The inventors manufactured a sample of the multilayer ceramic insulating substrate 200 shown in FIG. 2 and conducted a thermal cycle test. In the sample of the multilayer ceramic insulating substrate 200, each of the first insulating substrate member 31a and the second insulating substrate member 31b is the insulating substrate 100 of the first embodiment in which a SiN ceramic substrate and a CIC clad metal plate are combined. As a result, in the thermal cycle test of Tj = −40 ° C. to 300 ° C. (ΔTj = 340 ° C.), the low thermal stretchable metal plates 12a-1, 12a-2, 12b-1, 12b− It has been found that the defect that 2 peels from the ceramic substrates 21a and 21b does not occur.

  From the results of the above thermal cycle test, according to the multilayer ceramic insulating substrate 200 according to the fourth embodiment of the present invention, Cu (conductor) in the thermal cycle of a high semiconductor junction temperature (Tj) and a wide temperature range (ΔTj). It has been found that the problem of peeling of the plate from the SiN ceramic substrate can be solved. Specifically, high reliability was obtained in the maximum semiconductor junction temperature Tjmax = 300 ° C. or lower and the temperature range Tj = −40 ° C. to 300 ° C. (ΔTj = 340 ° C.).

  Thus, in the fourth embodiment of the present invention, the first insulating substrate member 31a, and the CIC clad metal plate as the low thermal stretchable metal plate are attached to both surfaces of the ceramic substrates 21a and 21b such as SiN. The second insulating substrate member 31b is manufactured. Then, the multilayer ceramic insulating substrate 200 is configured by laminating the first insulating substrate member 31a and the second insulating substrate member 31b. Thereby, in contrast to the insulating substrate according to the comparative example, it is possible to avoid the occurrence of trouble that the Cu (conductor) plate peels off from the SiN insulating substrate due to repeated temperature changes.

  In the fourth embodiment, the multilayer (two-layer) ceramic insulating substrate 200 in which the two insulating substrate members 31a and 31b are stacked is illustrated. However, the number of layers is not limited to two, and three or more layers are also possible. Although SiN is shown as an example of the ceramic substrates 21a and 21b, all the materials exemplified in the second embodiment can be used. Although the CIC clad metal plate is shown as an example of the low heat stretchable metal plates 12a-1 and 12b-2, the CMC clad metal plate exemplified in the third embodiment can also be used.

[Description of Multilayer Ceramic Insulating Substrate According to Fifth Embodiment]
Next, a multilayer ceramic insulating substrate according to the fifth embodiment will be described. FIG. 3 is a cross-sectional view showing the configuration of the multilayer ceramic insulating substrate 300 according to the fifth embodiment, which is an improved configuration of the structure of the multilayer ceramic insulating substrate 200 shown in FIG.

  As shown in FIG. 3, the multilayer ceramic insulating substrate 300 according to the fifth embodiment includes a first ceramic substrate 21a and a second ceramic substrate 21b. A low heat stretchable metal plate 12a-1 is attached to the upper surface of the first ceramic substrate 21a, and a low heat stretchable metal plate 12b-2 is attached to the lower surface of the second ceramic substrate 21b.

  An intermediate metal plate 19 is provided between the first ceramic substrate 21a and the second ceramic substrate 21b. The thickness of the intermediate metal plate 19 is not less than 0.1 mm and not more than 2 mm, preferably not less than 0.2 mm and not more than 1 mm.

  The low heat stretchable metal plates 12a-1 and 12b-2 are the same as the CIC clad metal plate or the CMC clad metal plate described in the first to third embodiments. A description of the configuration of the Invar alloy plate 13 and the Cu plates 14 and 15 in FIG. 3 is omitted. Here, a CMC clad metal plate will be described as an example.

  A via window 17 is opened in the ceramic substrate 21 a, and a via window metal plate 18 is embedded in the via window 17. The low heat stretchable metal plate 12 a-1 and the intermediate metal plate 19 are connected to each other through a via window metal plate 18.

  Between the ceramic substrates 21a, 21b and the intermediate metal plate 19, between the via window metal plate 18 and the intermediate metal plate 19, between the ceramic substrates 21a, 21b and the low heat stretchable metal plates 12a-1, 12b-2, The via window metal plate 18 and the low heat stretchable metal plate 12a-1 are joined by an active metal brazing material Ti—Cu—Ag, Ti—Cu—Ag—Ni (not shown) or the like. In order to improve the wettability of the high-temperature solder, an Au plating layer, an Ag plating layer, or a Cu plating layer may be coated on the Ni plating 16.

  Next, a method for manufacturing the multilayer ceramic insulating substrate 300 shown in FIG. 3 will be described. First, the active metal brazing material is placed on the low heat stretchable metal plate 12b-2 placed on the susceptor of the firing furnace, and the ceramic substrate 21b is placed thereon. Further thereon, an active metal wax material, an intermediate metal plate 19, an active metal wax material, a ceramic substrate 21a, an active metal wax material, and a low heat stretchable metal plate 12a-1 are laminated in this order. However, when the ceramic substrate 21a is placed, the via window metal plate 18 is simultaneously installed in the via window 17.

  When the above laminated body is completed, a weight serving as a load is placed on the top. Thereafter, the inside of the furnace is made a reducing atmosphere or an inert atmosphere, heated to a temperature equal to or higher than the melting point (or liquidus) of the active metal wax material, and then gradually cooled to room temperature. As a result, the multilayer ceramic insulating substrate 300 shown in FIG. 3 is completed.

  The inventors manufactured a sample of the multilayer ceramic insulating substrate 300 according to the fifth embodiment and conducted a thermal cycle test. A sample of the multilayer ceramic insulating substrate 300 includes SiN ceramic substrates 21a and 21b and low thermal stretchable metal plates (CMC clad metal plates) 12a-1 and 12b-2. A Cu plate (thickness: about 0.31 mm) is used as the via window metal plate 18 and the intermediate metal plate 19. As a result, in the thermal cycle test of Tj = −40 ° C. to 300 ° C. (ΔTj = 340 ° C.), the low thermal stretchable metal plates 12a-1 and 12b-2 and the intermediate metal plate 19 are not damaged even after 1000 cycles. Defects that peeled off from the ceramic substrates 21a and 21b were not observed.

  From the results of the thermal cycle test described above, according to the multilayer ceramic insulating substrate 300 according to the fifth embodiment, the Cu (conductor) plate is used in the thermal cycle with a high semiconductor junction temperature (Tj) and a wide temperature range (ΔTj). It has been found that the problem of peeling from the ceramic substrate can be solved. Specifically, high reliability was obtained in the maximum semiconductor junction temperature Tjmax = 300 ° C. or lower and the temperature range Tj = −40 ° C. to 300 ° C. (ΔTj = 340 ° C.).

  Note that the intermediate metal plate (Cu) 19 that is not the low heat stretchable metal plate does not peel from the ceramic substrates 21a and 21b. The reason is that the thermal stress generated at the interface between the ceramic and Cu due to the difference in thermal expansion is divided into the interface between the upper ceramic substrate 21a and the lower ceramic substrate 21b, and the thermal stress generated at each interface is This is because it has been halved.

  Thus, in the fifth embodiment of the present invention, a CMC clad metal plate as a low heat stretchable metal plate is attached to one surface of ceramic substrates 21a, 21b such as SiN, and further, between the ceramic substrates 21a, 21b. An intermediate metal plate 19 is provided. Thus, the multilayer ceramic insulating substrate 300 was configured. In contrast to the insulating substrate according to the comparative example, it is possible to avoid the occurrence of trouble that the Cu (conductor) plate is peeled off from the ceramic substrate due to repeated temperature changes.

  When the structure of the multilayer ceramic insulating substrate 300 according to the fifth embodiment is compared with the structure of the multilayer ceramic insulating substrate 200 according to the fourth embodiment, in the fifth embodiment, the intermediate metal plate 19 is a Cu single plate, and the multilayer ceramic substrate The insulating substrate 300 has a thin thickness and a good conductive Cu thickness. Therefore, the multilayer ceramic insulating substrate 300 according to the fifth embodiment is advantageous in that it can be made cheaper than the multilayer ceramic insulating substrate 200 and the heat conduction in the thickness direction can be improved.

  A via window 17 is opened in the ceramic substrate 21 a, and a via window metal plate 18 such as Cu is embedded in the via window 17. As a result, the low heat stretchable metal plate 12 a-1 and the intermediate metal plate 19 can be electrically connected via the via window metal plate 18. Although SiN is shown as an example of the ceramic substrates 21a and 21b, all the materials exemplified in the second embodiment can be used.

[Description of Bonded Structure of Power Semiconductor Device and Insulating Substrate According to Sixth Embodiment]
Next, with reference to FIG. 4, a power semiconductor device / insulating substrate bonded structure 400 (hereinafter, abbreviated as “bonded structure 400”) according to a sixth embodiment will be described. An example in which a SiC (silicon carbide) power element is used as the power semiconductor device 41 described in the sixth to eighth embodiments will be described. However, the power semiconductor device 41 includes other wide band gap semiconductor elements such as GaN (gallium nitride) elements, diamond elements, ZnO (zinc oxide) elements, and Si semiconductor elements (SOI elements and sensor elements) for high-temperature applications. Etc. Further, ceramic elements having mechanical and thermal properties similar to those of the power semiconductor device, specifically, passive elements and functional elements such as ceramic chip capacitors and ceramic thermistors can be applied.

  As shown in FIG. 4, the joint structure 400 according to the sixth embodiment includes an insulating substrate 101 and a power semiconductor device 41 joined by a heat-resistant solder layer 42. Since the insulating substrate 101 has the same structure as that of the insulating substrate 100 shown in FIG. 1, the same reference numerals are given and detailed description of the structure is omitted.

  FIG. 4 shows an example in which the insulating substrate 101 includes the SiN ceramic substrate 21 and the CIC clad metal plates 12-1 and 12-2 shown in the first embodiment. The insulating substrate 101 may include the other ceramic substrate described in the second embodiment and the other low thermal stretchable CMC clad metal plate described in the third embodiment.

  The power semiconductor device 41 is, for example, a transistor using SiC or a diode. An ohmic contact 23 such as Ni silicide is provided on the back surface of the power semiconductor device 41. On the lower surface of the ohmic contact 23, a mounting electrode 22 made of a laminated film of Ti (titanium) / Ni (nickel) / Ag (silver) or the like is formed.

  The heat-resistant solder layer 42 mechanically and electrically joins the low heat stretchable metal plate 12-1 and the power semiconductor device 41. The heat-resistant solder layer 42 has a solidus temperature that is at least 30 ° C. higher than the maximum semiconductor junction temperature Tjmax of the power semiconductor device 41 and a liquidus temperature that is at least 30 higher than the instantaneous heat-resistant temperature 450 ° C. of the SiC power semiconductor device 41. It is made of a metal material that is lower than ℃ Specifically, the heat-resistant solder layer 42 includes eutectic Au—Ge solder, eutectic Au—Si solder, eutectic Au—Sn solder, eutectic Zn—Al solder, eutectic Bi—Ag solder, Bi solder, etc. Consists of. The heat-resistant solder layer 42 is not limited to this, and the solder material having a hypoeutectic composition or a hypereutectic composition can be used without departing from the eutectic composition.

  Next, a method for manufacturing the joint structure 400 according to the sixth embodiment will be described using a case where eutectic Au—Ge solder is used as the heat-resistant solder layer 42 as an example.

  First, the power semiconductor device 41 (chip) and the insulating substrate 101 are ultrasonically cleaned with an organic solvent such as acetone or isopropyl alcohol to remove contaminants attached to the surfaces of these components. When the eutectic Au—Ge solder is not a paste but a plate, the eutectic Au—Ge solder is cleaned in the same manner.

  Subsequently, the insulating substrate 101 is installed on the reflow stand of the reduced pressure reflow apparatus, and the eutectic Au—Ge solder is placed on a predetermined position of the low thermal stretchable metal plate, that is, the CIC clad metal plate 12-1. If the eutectic Au—Ge solder is paste-like, the eutectic Au—Ge solder paste is dropped onto a predetermined position of the CIC clad metal plate 12-1 using a syringe or the like. Then, the power semiconductor device 41 is placed on the eutectic Au—Ge solder and is stationary.

  Here, in order to accurately place the eutectic Au—Ge solder and the semiconductor element at the position to be bonded to the insulating substrate 101 and prevent the position of the power semiconductor device 41 during the reflow process, a template-type carbon jig is used. It is desirable to use

  When the preparation is completed, a reflow process is performed. First, the door of the vacuum reflow device is closed and the sample chamber is evacuated. When the pressure in the sample chamber becomes 5 mbar or less, an inert gas is introduced. This operation is performed several times to replace the air in the sample chamber with an inert gas. As a result, the sample chamber is filled with the inert gas.

  Then, the reflow table or the entire sample chamber is heated to raise the temperature of the material to approximately 200 ° C., and this temperature is maintained for about 2 minutes. At this time, an inert gas containing formic acid vapor may be introduced to promote removal of contaminating organic substances.

  Thereafter, the introduction of the inert gas is stopped, the exhaustion is restarted, and the sample chamber is decompressed to 5 mbar or less. The reflow table (or the entire sample chamber) is further heated to raise the temperature of the insulating substrate 101, the Au—Ge solder 42, and the power semiconductor device 41 to a reflow temperature of 410 ° C. and reflow. The holding time is about 1 minute.

  When the reflow is completed, an inert gas is introduced into the sample chamber and the temperature is lowered. When the temperature inside the chamber is lowered to a sufficiently low temperature, the finished product, that is, the joint structure 400 according to the present embodiment is taken out from the reflow apparatus.

  In addition, when using solder other than Au—Ge, the manufacturing process is almost the same. In most cases, only the reflow temperature and its holding time need be changed.

  The inventors produced a sample of the bonded structure 400 using the above method, and performed a thermal cycle test at Tj = −40 ° C. to 250 ° C. (ΔTj = 290 ° C.). The number of cycles was set to 3000 cycles applied to electronic parts that are used in relatively harsh environments such as automobiles. The chip size of the power semiconductor device 41 was 2 mm in length, 2 mm in width, and 0.3 mm in thickness. As a comparative example, a sample of a joined structure (solder layer is Au—Ge) including an insulating substrate using oxygen-free Cu alone instead of a CIC clad metal plate was produced, and the same thermal cycle test as described above was performed.

  FIG. 5 is a diagram showing the results of a thermal cycle test at Tj = −40 ° C. to 250 ° C. (ΔTj = 290 ° C.). In FIG. 5, the bond strength (shear strength) is plotted as a function of cycle number. As described above, in the sample of the bonded structure according to the comparative example, it is understood that the shear strength rapidly deteriorates as the number of cycles increases. This was the problem of the comparative example. Note that the bonding strength in the comparative example indicates the bonding strength between the oxygen-free Cu simple substance and the power semiconductor device.

  On the other hand, in the sample of the bonded structure 400 according to the present embodiment, the deterioration rate of the shear strength is moderate even if the number of cycles is increased. By approximating the decreasing tendency of the plot to a straight line by the method of least squares, the number of cycles decreasing to the IEC60749-19 standard regarding the shear strength of the electronic component was predicted. As a result, a result of about 9000 cycles was obtained. The standard of the cycle life required empirically for an electronic component used in a relatively harsh environment is 3000 cycles. Therefore, the joint structure 400 according to the present embodiment has a life that is about three times as long as this guideline. The bonding strength in the present embodiment indicates the bonding strength between the Cu plate of the CIC clad metal plate and the power semiconductor device.

  As is apparent from the above test results, in the sixth embodiment, the power semiconductor device chip is bonded onto the low thermal stretchable metal plate 12-1 of the insulating substrate 101 shown in the first to fifth embodiments. The bonded structure 400 is configured. As a result, rapid deterioration of the bonding strength between the power semiconductor device 41 and the insulating substrate 101 can be suppressed, and the cycle life can be greatly extended.

  The insulating substrate 101 and the power semiconductor device 41 are joined using the heat-resistant solder layer 42. Thereby, even when a temperature change is repeated, the problem that the heat-resistant solder layer 42 deteriorates and peels can be solved.

  The power semiconductor device 41 uses one semiconductor material selected from the group consisting of silicon carbide (SiC), gallium nitride (GaN), diamond (C), and zinc oxide (ZnO). As a result, the on-resistance can be lowered, and consequently the switching speed can be increased.

  In the bonding structure 400 according to the present embodiment, the example in which the insulating substrate 101 described in the first to third embodiments is applied has been described. However, the multilayer ceramic insulating substrate according to the fourth and fifth embodiments is employed. You may do it.

[Description of Power Semiconductor Module According to Seventh Embodiment]
Next, a power semiconductor module according to a seventh embodiment of the invention will be described. FIG. 6 shows a configuration of a power semiconductor module 500 according to the seventh embodiment, where FIG. 6A is a plan view and FIG. 6B is a cross-sectional view. As shown in FIGS. 6A and 6B, the power semiconductor module 500 according to this embodiment includes a bonded structure 400 of the power semiconductor device 41 and the insulating substrate 100 shown in FIG. The metal heat sink 50 joined to the lower surface with the heat-resistant solder 60, and the water cooling cooler 70 provided in the lower surface of the metal heat sink 50 are provided.

  A power semiconductor device 41 is provided on the upper surface of the insulating substrate 100 via a heat-resistant solder layer 42. A metal heat sink 50 and a water-cooled cooler 70 are provided on the lower surface of the insulating substrate 100. As shown in FIG. 6, the metal heat sink 50 (54) has a larger area than the insulating substrate 100 (21) when viewed in plan from the stacking direction.

  The metal heat sink 50 is configured by stacking Cu layers 54 and 56 on both sides of the Mo layer 52. The Mo layer 52 is disposed between the pair of Cu layers 54 and 56. The metal heat sink 50 is fixed to the water-cooled cooler 70 with screws 90. The low heat stretchable metal plate 12-1 and the power semiconductor device 41 are electrically connected by an aluminum wire 29.

  The cooling water 72 is supplied from the inlet 70a of the water-cooled cooler 70 and discharged from the outlet 70b. As a result, the metal heat sink 50 is cooled, and the heat generated in the power semiconductor device 41 can be released.

  Thus, in the power semiconductor module 500 according to the seventh embodiment, the joint structure 400 of the power semiconductor device 41 and the insulating substrate 100 shown in the sixth embodiment is used. As a result, it is possible to solve the problem that if the power semiconductor module 500 is operated in a cooling cycle with a high semiconductor junction temperature (Tj) and a wide temperature range (ΔTj), the power semiconductor module 500 fails in a very few cycles. Specifically, high reliability is obtained at a semiconductor junction temperature maximum value Tjmax = 300 ° C. or lower and a temperature range Tj = −40 ° C. to 300 ° C. (ΔTj = 340 ° C.).

[Description of Power Semiconductor Module According to Eighth Embodiment]
FIG. 7 is a cross-sectional view of a power semiconductor module 600 according to the eighth embodiment. The power semiconductor module 600 includes a power semiconductor device according to the fourth embodiment shown in FIG. 4, a bonded structure 400 of an insulating substrate, and cooling fins 71. The insulating substrate 100 shown in FIG. 7 includes a ceramic substrate 21 such as SiN, and low heat stretchable metal plates 12-1 and 12-2 attached to both surfaces of the ceramic substrate 21. The power semiconductor device 41 is, for example, a SiC power semiconductor device. The power semiconductor device 41 is connected to the low heat stretchable metal plate 12-1 by a heat resistant solder layer 42. The power semiconductor device 41 and the low heat stretchable metal plate 12-1 are electrically connected by an aluminum wire 29.

  Cooling fins 71 made of Cu or aluminum are provided on the lower surface of the low heat stretchable metal plate 12-2 via a heat-resistant solder layer 60. Ni plating (not shown) is applied to at least the upper surface of the cooling fin 71.

  As a material of the heat resistant solder layer 60, the solidus temperature is at least 30 ° C. higher than the maximum semiconductor junction temperature Tjmax of the SiC power semiconductor device 41, and the liquidus temperature is higher than the liquidus temperature of the heat resistant solder layer 60. A solder material that is at least 30 ° C. lower is selected. Examples of the solder material described above include eutectic Au—Ge solder, eutectic Au—Si solder, eutectic Au—Sn solder, eutectic Zn—Al solder, eutectic Bi—Ag solder, and Bi solder. . The material of the heat resistant solder layer 60 is not limited to these. If the heat-resistant solder layer 42 is eutectic Au—Ge solder, the eutectic Au—Sn solder, eutectic Bi—Ag solder, or Bi solder is suitable as the heat resistant solder layer 60.

  Therefore, it is possible to prevent the heat resistant solder layer 60 from being deteriorated due to repeated temperature changes, and it is possible to prevent the low heat stretchable metal plate 12-2 from peeling off. Note that a small air cooling fan (not shown) is connected to the cooling fin 71 to improve the heat radiation efficiency.

  As is clear from the configuration of FIG. 7, the power semiconductor module 600 according to the eighth embodiment uses the joint structure 400 of the power semiconductor device 41 and the insulating substrate 100 described in the fourth embodiment. As a result, it is possible to solve the problem that if the power semiconductor module 600 is operated in a cooling cycle with a high semiconductor junction temperature (Tj) and a wide temperature range (ΔTj), the power semiconductor module 600 will fail in very few cycles. Specifically, high reliability is obtained at the maximum semiconductor junction temperature Tjmax = 300 ° C. or lower and the temperature range Tj = −40 ° C. to 300 ° C. (ΔTj = 340 ° C.).

  Since the power semiconductor module 600 according to the eighth embodiment does not include the screwing mechanism on the heat radiating plate, the size of the power semiconductor module 600 viewed from the stacking direction can be greatly reduced. In this embodiment, since the joining structure 400 is directly connected to the cooling fin 71, the heat sink can be omitted. That is, in the eighth embodiment of the present invention, it is possible to reduce the size and weight of the device. As a result, it is possible to reduce the cost of the module.

  In the eighth embodiment, the example in which the insulating substrate 100 shown in the first to third embodiments is applied has been described. However, the multilayer ceramic insulating substrates 200 and 300 shown in the fourth and fifth embodiments are used. It is also possible to apply.

  As described above, the insulating substrate, the multilayer ceramic insulating substrate, the joined structure of the power semiconductor device and the insulating substrate, and the power semiconductor module according to the embodiment have been described, but the present invention is not limited to this, and the configuration of each part is , Can be replaced with any configuration having the same function.

  The entire contents of Japanese Patent Application No. 2012-184460 (application date: August 23, 2012) are incorporated herein by reference.

  Although the contents of the present invention have been described with reference to the embodiments, the present invention is not limited to these descriptions, and it is obvious to those skilled in the art that various modifications and improvements can be made.

  According to the embodiment of the present invention, an insulating substrate with high reliability can be realized in a cooling cycle with a high semiconductor junction temperature (Tj) and a wide temperature range (ΔTj). As a result, it is possible to avoid the occurrence of a failure in which one or both of the Cu plates are separated from the ceramic substrate. Embodiment of this invention can be utilized for the power semiconductor module which can endure a temperature cycle.

12 (12a, 12b) Low heat stretchable metal plate (CIC clad metal plate)
13 Invar alloy plate (low thermal expansion metal plate)
14, 15 Cu plate 17 Via window 18 Via window metal plate 19 Intermediate metal plate 21 (21a, 21b) Ceramic substrate 41 Power semiconductor device 50 Metal heat sink 70 Water-cooled cooler 71 Cooling fin 90 Screw 100 Insulating substrate 200, 300 Multi-layer Ceramic insulating substrate 400 Joining structure of power semiconductor device and insulating substrate 500,600 Power semiconductor module

Claims (17)

A multilayer ceramic insulating substrate formed by joining a plurality of insulating substrates,
The insulating substrate is
A ceramic substrate;
A low thermal stretchable metal plate affixed to the upper and lower surfaces of the ceramic substrate,
The low heat stretchable metal plate is
A pair of Cu plates having substantially the same thickness;
A low thermal expansion metal plate provided between the pair of Cu plates and having a thermal expansion coefficient lower than that of the Cu plate,
The lower surface of the low thermal expansion metal plate attached to the lower surface of the ceramic substrate constituting the one insulating substrate, the upper surface and the bonding of low thermal expansion and contraction of the metal plate affixed to the upper surface of the ceramic substrate constituting the other of the insulating substrate It is,
The multilayer ceramic insulating substrate according to claim 1, wherein a thickness of each of the pair of Cu plates is 1/5 or less of a thickness of the low thermal expansion metal plate . 2. The multilayer ceramic insulating substrate according to claim 1, wherein a thickness of each of the pair of Cu plates is 1/8 or less of a thickness of the low thermal expansion metal plate. The upper surface of the low thermal expansion metal plate affixed to the upper surface of the ceramic substrate constituting the lower surface of the low thermal expansion metal plate attached to the lower surface of the ceramic substrate constituting the one insulating substrate, the other insulating substrate the multilayer ceramic insulating substrate according to claim 1 or claim 2, characterized in that it is joined via a brazing material. The multilayer ceramic insulating substrate according to any one of claims 1 to 3, wherein a thickness of the ceramic substrate is 0.1 mm or more and 2 mm or less. The multilayer ceramic insulating substrate according to any one of claims 1 to 4 , wherein the ceramic substrate is made of one material selected from the group consisting of silicon nitride, alumina, aluminum nitride, and beryllia. The multilayer ceramic insulating substrate according to claim 1 , wherein the Cu plate has a thickness of 5 μm or more.   The multilayer ceramic insulation according to any one of claims 1 to 6, wherein the low thermal expansion metal plate is one material selected from the group consisting of invar, molybdenum, super invar, and stainless invar. substrate.   The multilayer ceramic insulating substrate according to any one of claims 1 to 7, wherein the pair of Cu plates and the low thermal expansion metal plate are joined together by a metallurgical method. A plurality of ceramic substrates having substantially the same thickness;
An intermediate metal plate whose upper surface is bonded to the lower surface of one ceramic substrate via a brazing material, and whose lower surface is bonded to the upper surface of the other ceramic substrate via a brazing material;
Low heat stretchable metal plates each affixed to the outer surface of the ceramic substrate located at the top and bottom,
The low heat stretchable metal plate is
A pair of Cu plates having substantially the same thickness;
A low thermal expansion metal plate provided between the pair of Cu plates and having a lower coefficient of thermal expansion than the Cu plate,
The multilayer ceramic insulating substrate according to claim 1, wherein a thickness of each of the pair of Cu plates is 1/5 or less of a thickness of the low thermal expansion metal plate . The multilayer ceramic insulating substrate according to claim 9, wherein the thickness of each of the pair of Cu plates is 1/8 or less of the thickness of the low thermal expansion metal plate. Via window in which a low heat stretchable metal plate and an intermediate metal plate or a pair of intermediate metal plates respectively disposed on both surfaces of at least one ceramic substrate are embedded in via windows penetrating both surfaces of the ceramic substrate The multilayer ceramic insulating substrate according to claim 9 or 10, wherein the multilayer ceramic insulating substrate is electrically connected through a metal plate. The multilayer ceramic insulating substrate according to any one of claims 1 to 8,
A power semiconductor device;
A heat-resistant solder layer for bonding between the multilayer ceramic insulating substrate and the power semiconductor device;
A bonded structure of a power semiconductor device and an insulating substrate, comprising: The power semiconductor device according to claim 12 , wherein the power semiconductor device is made of at least one wide band gap semiconductor selected from the group consisting of silicon carbide, gallium nitride, diamond, and zinc oxide. Structure. The solder of the heat resistant solder layer has a solidus temperature at least 30 ° C. higher than the maximum operating temperature Tjmax of the power semiconductor device, and a liquidus temperature of at least the instantaneous heat resistant temperature of the power semiconductor device. The power semiconductor device and the insulating substrate bonded structure according to any one of claims 12 and 13 , wherein the power semiconductor device and the insulating substrate are made of a metal material lower by 30 ° C or more. The solder of the heat-resistant solder layer is selected from the group consisting of eutectic Au-Ge solder, eutectic Au-Si solder, eutectic Au-Sn solder, eutectic Zn-Al solder, eutectic Bi-Ag solder, Bi solder. The joint structure of a power semiconductor device and an insulating substrate according to any one of claims 12 and 13 , wherein the solder structure is a solder. A joined structure of the power semiconductor device according to claim 12 and an insulating substrate,
A water-cooled cooler,
A metal heatsink disposed between the power semiconductor device and the insulating substrate and the water-cooled cooler and having a larger area in plan view than the power semiconductor device and the insulating substrate.
A joined structure of the power semiconductor device and the insulating substrate, and a heat-resistant solder that joins between the metal heat sink;
A screw for fixing between the metal radiator plate and the water-cooled cooler;
A power semiconductor module comprising: A joined structure of the power semiconductor device according to claim 12 and an insulating substrate,
Air cooling fins,
A joined structure of the power semiconductor device and the insulating substrate, and a heat-resistant solder layer that joins between the air-cooled cooling fins;
A power semiconductor module comprising:

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