JP5989156B2 - Flash memory module - Google Patents

Description

  The present invention relates to storage control for programming data in an electrically rewritable nonvolatile semiconductor memory.

  In the nonvolatile semiconductor memory, electrons are transmitted to the floating gate through the oxide insulating film in the process of data storage (programming) in the internal cell. Further, in the process of erasing the recorded data, electrons are extracted from the FG (Floating Gate) through the oxide insulating film.

  In a nonvolatile semiconductor memory having such a data storage mechanism, a load is applied to the oxide insulating film every time a program and erase process is performed. By repeating this load, a plurality of electron traps and hole traps are generated in the oxide insulating film.

  The nonvolatile semiconductor memory determines the recording data by measuring a threshold voltage that varies depending on the amount of charge (number of electrons) in the FG. For this reason, as described above, when an electron trap and a hole trap are generated in the oxide insulating film, electrons enter the electron trap and the hole trap to generate a voltage, and this voltage fluctuates the threshold voltage of the FG to record data. It is difficult to accurately discriminate.

  It is known that the fluctuation of the threshold voltage due to such electron trap and hole trap depends on the program, the cumulative number of erase executions, and the control interval. Also known is a change in time characteristics of data retention (hereinafter referred to as retention characteristics) due to fluctuations in threshold voltage.

  Since the amount of charge stored in the FG changes with time, the data retention period of the nonvolatile semiconductor memory is limited. In addition, since the threshold voltage due to the aforementioned electron trap and hole trap varies, the data retention period is further shortened.

  A semiconductor storage device using a nonvolatile semiconductor memory as a storage medium (hereinafter referred to as a storage device) needs to satisfy a data retention period standard defined as a device specification. The storage device predicts the deterioration degree of the oxide insulating film from the data program, the number of erases, and the like, and when the data retention period of the specific region of the mounted nonvolatile semiconductor memory is predicted not to meet the standard, this storage region Is disabled.

  In order for the storage device to continue to operate even if such an unusable area occurs, generally a spare storage area larger than the total storage data amount of the apparatus is mounted, and this spare storage area is determined to be unusable as described above. The storage area is assigned as a replacement for the designated area, and control is performed so that a constant storage area is always maintained. However, when the reserved spare area is depleted, the storage device stops because it loses the ability to newly record data.

  Therefore, in order to realize the long life of the storage device, it is necessary to suppress the fluctuation of the threshold voltage due to the electron trap and the hole trap and prevent the data retention period of the storage area from being shortened.

  As a document disclosing control for reducing the influence of such electron traps and hole traps, for example, there is Patent Document 1. Patent Document 1 discloses a storage device in which a region in which the retention characteristic is deteriorated is not used for a certain period, and electron traps and hole traps are reduced and reused (Patent Document 1).

US2010 / 0165689 A1

  For example, a nonvolatile semiconductor memory (typically a flash memory) is composed of a plurality of blocks, and this block is the minimum erase unit. As described above, since an electron trap and a hole trap are generated in the oxide insulating film by the repeated processing of erasing and programming, an upper limit of the number of erasing is provided for each block.

  In general, the semiconductor memory cannot be overwritten, and if the programmed area is not erased, the area cannot be reprogrammed. Therefore, when new data is programmed in a block in which data is programmed, erasure is always performed in combination with the program. Therefore, the storage device manages the number of times that the block has been erased (hereinafter referred to as the block erase number) for each block, and the data retention period (specifically, the data retention period for the block exceeding the upper limit of the block erase number). Is exceeded, the block is made unusable and a spare block is assigned as a substitute.

  When erase and program are concentrated on a specific block group, there is a possibility that many blocks that cannot be used because the number of block erases reaches the upper limit in a short period of time. Since it is necessary to allocate spare blocks to these blocks, the spare blocks are quickly depleted. That is, due to concentration of access to a specific block group, the spare block may be depleted earlier and the life of the storage device may be shortened.

  In order to prevent the program and access from being concentrated on such a specific group of blocks, the storage device distributes the program processing to the blocks and performs a process of leveling the number of erases for each block (hereinafter referred to as the block number). This process is referred to as wear leveling). In wear leveling, data is preferentially programmed to a block having a smaller number of erases than the average value of the number of erases of the blocks mounted on the storage device.

  For this reason, the average value of the number of block erases of the blocks mounted on the storage device is X (X is an integer equal to or greater than 1), and the number of block erases in the blocks mounted on the storage device is Y (Y is Y <X If there is a block (hereinafter referred to as a target block) that is an integer satisfying this, this target block is preferentially used. Therefore, there is a possibility that the program and erase are repeated in this target block in a short time.

  In general, the shorter the time from erasing a block to programming data in that block (hereinafter referred to as the EP interval), the longer the data retention period.

  For this reason, even if the number of block erases of a certain block is small, the time from the program to the erase (hereinafter referred to as the PE interval) for that block may be shortened by preferentially repeatedly using that block. is there. Therefore, even if the number of block erases of the block does not reach the upper limit value, a large number of blocks in which the data holding period has elapsed may occur in a short time. This increases the possibility of shortening the life of the storage device.

  That is, it may be difficult to maintain the reliability of the storage device only by counting the number of block erasures and wear leveling alone.

  Accordingly, an object of the present invention is to realize high reliability and long life of a semiconductor memory device using a nonvolatile semiconductor memory as a storage medium.

  The semiconductor memory device stores information representing at least one of the latest program time, which is the time when data is recently programmed in the block, and the latest erase time, which is the time when the erase process was recently performed on the block, in each nonvolatile semiconductor memory. Stores management information about the block. The semiconductor memory device controls (b1) the timing of programming data in the block based on at least one of the latest program time and the latest erase time of the block, and / or (b2) based on the latest program time of the block. In addition, the timing for performing the erase process on the block is controlled.

  For example, the semiconductor memory device may secure the minimum time by controlling the time interval between the program and erase processes, which are normal processes of the semiconductor memory device, while leveling the number of erases by wear leveling.

  Further, for example, the semiconductor memory device may control each block so that the time interval between each processing of the program and the erase is as long as possible in response to a request from the host device (for example, a host computer). .

  Further, for example, when a block with poor data retention characteristics is detected, the semiconductor memory device may be controlled to reduce the frequency of use of the block. As a result, a decrease in electron traps and hole traps is expected, and therefore recovery of retention characteristics is expected.

  According to the present invention, high reliability and long life of a semiconductor memory device can be achieved.

FIG. 1 shows a configuration example of a computer system 1 including an FM module 100 according to the first embodiment. FIG. 2 shows a configuration example of the memory chip 120. FIG. 3 shows an internal configuration example of the block 202. FIG. 4 shows an example of data stored in the page 301. FIG. 5 shows an example of the address conversion table 500. FIG. 6 shows an example of the block management table 600. FIG. 7 shows an example of the wear leveling management queue 700. FIG. 8 shows an example of a program stored in the RAM 114. FIG. 9 shows an outline of the control of the erase process. FIG. 10 shows an outline of control of program processing. FIG. 11 shows an example of a program processing flow. FIG. 12 shows an example of the flow of step S1102. FIG. 13 shows an example of the flow of read processing. FIG. 14 shows an example of the reclamation process flow. FIG. 15 shows an example of the PE interval management queue 1500. FIG. 16 is a schematic diagram showing a block use cycle in the second embodiment. FIG. 17 shows an example of the flow of invalid block generation processing. FIG. 18 shows an example of the erase process flow. FIG. 19 shows an example of a program stored in the RAM 114. FIG. 20 shows an example of a table representing the relationship between the elapsed days and the failure bit threshold. FIG. 21 shows an example of the management screen 2100. FIG. 22 shows an example of the flow of erase processing in the third embodiment. FIG. 23 shows an example of the flow of read processing in the third embodiment.

  Several embodiments of the present invention will be described below.

  In the following description, various types of information may be described using the expression “xxx table”, but the various types of information may be expressed using a data structure other than a table. In order to show that it does not depend on the data structure, the “xxx table” can be called “xxx information”.

  In the following description, a number is used as identification information for specifying an element, but other types of identification information (for example, English characters) may be used as the identification information instead of or in addition to the number. .

  In the following description, the process may be described using “program” as a subject. However, a program is executed by a processor (for example, a CPU (Central Processing Unit)), so that a predetermined process is appropriately performed. Since processing is performed using a storage resource (for example, a memory) and / or a communication interface device (for example, a communication port), the subject of processing may be a processor. The processing described with the program as the subject may be processing performed by a device (for example, a storage control device or a storage device) having the processor. The processor may include a hardware circuit that performs part or all of the processing instead of or in addition to a microprocessor such as a CPU. The computer program may be installed in each device from a program source. The program source may be, for example, a program distribution server or a computer-readable storage medium.

  The management computer may be composed of one or more computers. For example, when the management computer displays information or when the management computer transmits display information to a remote computer, one computer is the management computer. Further, for example, when a function equivalent to that of the management computer is realized by a plurality of computers, the plurality of computers (which may include a display computer when the display computer performs display) are management computers. .

  Further, in the following description, in the case of explaining without distinguishing the same type of elements, only the common code among the reference codes is used, and in the case of distinguishing and explaining the same kind of elements, the reference code (common code) is used. And a combination of individual codes).

  FIG. 1 shows a configuration example of a computer system 1 including a semiconductor memory device 100 according to the first embodiment of the present invention. Since the semiconductor memory is typically FM (Flash Memory), the semiconductor memory device is hereinafter referred to as “FM module”.

  The computer system 1 includes a host computer 10, a management computer 11, and a semiconductor storage device (hereinafter referred to as FM (Flash Memory) module) 100.

  The FM module 100 is connected to the host computer 10 via a built-in first FE-IF (Front End-Interface) 111 and connected to the management computer 11 via the built-in second FE-IF. Is done. The communication protocol between the FM module 100 and the host computer 10 and the communication protocol between the FM module 100 and the management computer 11 may be the same or different.

  The host computer 10 is, for example, a computer, a file server, or a storage device to which a large number of FM modules 100 are connected, which is the core of a business system.

  The host computer 10 includes hardware resources such as a processor, a memory, a network interface, and a local input / output device (not shown). The host computer 10 also includes software resources such as a device driver, an OS (Operating System), a management program, and an application program.

  The processor of the host computer 10 can execute various programs (software resources). For example, when the processor of the host computer 10 executes the application program, the host computer 10 can communicate with the FM module 100 and issue a data read / write command to the FM module 100. For example, when the processor of the host computer 10 executes the management program, the host computer 10 can acquire management information such as the usage status and processing status of the FM module 100. In addition, the host computer 10 can change the management unit, control method designation, and control method of the FM module 100.

  The management computer 11 can manage the entire computer system 1. The management computer 11 includes storage devices such as an input device such as a keyboard and a mouse, a display device such as a processor and a liquid crystal display device, and a memory (not shown). Various programs are stored in the storage resource, and the programs are executed by the processor to realize various functions.

  The FM module 100 includes an FM controller 110 and a plurality of (for example, 32) nonvolatile semiconductor memory chips (hereinafter simply referred to as memory chips) 120. A plurality of RAID groups may be configured based on the plurality of memory chips 120. A RAID group may be composed of two or more memory chips 120. A logical volume may be configured based on the RAID group. The logical volume may be provided to the host computer 10 or may be a type of logical volume that is not provided to the host computer 10 (for example, a pool volume that is a logical volume constituting a pool). The pool volume may be divided into two or more areas (hereinafter, real areas). The real area may be allocated to a virtual area constituting a virtual logical volume according to Thin Provisoning. At least one of the plurality of pool volumes constituting the pool may be a virtual logical volume to which a logical volume of an external storage device (not shown) connected to the FM module 100 is mapped. .

  In this embodiment, the FM controller 110 is a controller built in the FM module 100, but may be a computer that exists outside the FM module 100. The FM controller 110 includes an FE-IF (Front End-Interface) 111, a switch 112 that mutually transfers data, a storage resource (for example, a data buffer 113, a RAM (Random Access Memory) 114), a processor 115, FM-IF (Flash Memory-Interface) 116.

  The switch 112 connects the processor 115, the RAM 114, the data buffer 113, the FE-IF 111, and the FM-IF 116, and routes and transfers data according to an address or ID.

  The FE-IF 111 connects each component of the FM controller 110 to the host computer 10 and the management computer 11 via the switch 112. The FE-IF 111 receives from the host computer 10 a read / write command and an LBA (Logical Block Address) that specifies a target logical storage location. The FE-IF 111 that has received the write command from the host computer 10 also receives write data from the host computer 10. The FE-IF 111 receives a control command for the FM module 100 from the host computer 10 and the management computer 11 and controls the FM module 100 according to the command. Further, the FE-IF 111 notifies the processing status, usage status, current setting value, and the like of the FM module 100 to the host computer 10 and the management computer 11.

  The data buffer 113 stores temporary data during the data transfer process in the FM controller 110.

  Specifically, the RAM 114 is a volatile memory such as a DRAM (Dynamic Random Access Memory). The RAM 114 stores management information 1140 of the memory chip 120 used in the FM module 100, a transfer list including transfer control information used by each DMA (Direct Memory Access), and the like. The RAM 114 includes a part or all of the functions of the data buffer 113 for storing data, and can also be used as a temporary storage destination of data.

  The processor 115 is connected to each component of the FM controller 110 via the switch 112, and controls the entire FM controller 110 based on a program and management information stored in the RAM 114. In addition, the processor 115 monitors the entire FM controller 110 through periodic information acquisition, an interrupt reception function, and the like.

  The FM-IF 116 is connected to the memory chip 120 by a plurality of buses (for example, 16 buses). A plurality of (for example, two) memory chips 120 are connected to each bus. Each memory connected to each bus is controlled independently based on a CE (Chip Enable) signal.

  The FM-IF 116 performs processing according to a read / write command instructed from the processor 115. At this time, the FM-IF 116 indicates the command target by a physical address (hereinafter referred to as PBA (Physical Block Address)).

  Receiving the PBA, the FM-IF 116 calculates the necessary memory chip 120 (block, page) from the PBA, specifies the block and page for the memory chip 120, and processes the read / write command.

  The FM-IF 116 reads data from the memory chip 120 and transfers it to the data buffer 113 during the read process. Further, the FM-IF 116 calls the write data from the data buffer 113 and writes it to the memory chip 120 during the write process.

  Further, the FM-IF 116 has an ECC (Error Correcting Code) generation circuit, an ECC data loss detection circuit, and an ECC correction circuit. The FM-IF 116 writes data with ECC added during write processing. Further, the FM-IF 116 checks the call data from the memory chip 120 by a data loss detection circuit using ECC at the time of data call. When data loss is detected, the FM-IF 116 performs data correction by the ECC correction circuit and stores the number of correction bits in the RAM 114 in order to notify the processor 115 of the number of correction bits.

  The FE-IF 111, the switch 112, the data buffer 113, the RAM 114, the processor 115, and the FM-IF 116 described above are configured in one semiconductor element as an ASIC (Application Specific Integrated Circuit) or an FPGA (Field Programmable Gate Array). Alternatively, a configuration in which a plurality of individual dedicated ICs (Integrated Circuits) are connected to each other may be employed.

  FIG. 2 shows a configuration example of the memory chip 120.

  The memory chip 120 includes a plurality of (for example, 4096) blocks 202. Each block 202 is composed of a plurality of pages. The memory chip 120 is erased in units of blocks, and data read / program is performed in units of pages. The memory chip 120 is, for example, a NAND flash memory capable of erasing data in units of blocks. The flash memory may not be a NAND type (for example, a NOR type).

  The memory chip 120 includes a register 201. The register 201 is a register having a storage capacity equal to or larger than the page size (for example, 4 KB + additional ECC spare area).

  The memory chip 120 performs processing in accordance with a read / write command instruction from the FM-IF 116.

  In the write process, first, the memory chip 120 receives a write command and write destination information (for example, information indicating a target block of the write command, a page number, and a program start position in the page) from the FM-IF 116.

  Next, the memory chip 120 stores the write data transferred from the FM-IF 116 in the register 201 in the program start position (address) order in the page. After that, when receiving a data transfer completion command from the FM-IF 116, the register 201 writes (programs) the data stored in the register 201 to the designated memory chip 120 (page).

  In the read process, the memory chip 120 first receives a read command and read source information (for example, a target block and a page number of the read command) from the FM-IF 116. Next, the memory chip 120 reads the data stored in the page of the designated block 202 and stores it in the register 201. Thereafter, the register 201 transfers the data stored in the register 201 to the FM-IF 116.

  FIG. 3 shows an internal configuration example of the block 202.

  The block 202 is divided into a plurality of (for example, 128 pages) pages 301, and data reading and data writing can be processed only in units of pages. Further, the order in which the pages 301 in the block 202 are written is defined. In the figure, data is continuously written in order from the page 1.

  In the FM module 100, the LBA specified by the host computer 10 and the address PBA (Physical Block Address) specifying the physical storage location in the FM module 100 are managed by different address systems, and the LBA The correspondence with the PBA is managed as table information (see FIG. 5).

  Further, the FM module 100 cannot overwrite the written page, and cannot write to the page again unless the erase process is performed on the block to which the page belongs. Therefore, when updating the data, the page associated with the LBA before the update is changed to a new page, and the data is written to the new page. Thus, the host computer 10 does not know that a new page is associated with the LBA. Note that the page associated with the LBA before the update becomes an invalid page.

  The PBA can uniquely specify an arbitrary page of the FM module 100, and has an address system in which addresses are consecutive in the order of page numbers within a data size range of at least one block. For example, if the data size for one page is incremented with respect to the PBA specifying the third page of a block, the PBA specifying the fourth page is obtained.

  FIG. 4 shows an example of data stored in the page 301.

  The page 301 stores data of a certain number of bits (for example, 4 KB). The page 301 stores an ECC (Error Correcting Code) 402 added by the FM-IF 116 in addition to the data 401. The ECC is stored adjacent to data to be protected 401 (hereinafter referred to as protected data). Data 1 401 and ECC 402 added to data 1 401 are stored as one set to form an ECC CW (ECC CodeWord).

Although FIG. 4 shows a configuration in which four ECC CWs are stored in one page, any number can be used according to the page size and ECC performance (number of correctable bits).
In the above configuration, the data loss failure is a phenomenon that occurs when the number of failed bits per ECC CW exceeds the number of bits that can be corrected by the ECC constituting the ECC CW.

  The configuration of the FM module 100 and the data storage configuration of the FM module 100 have been described above.

  FIG. 5 shows an example of the address conversion table 500.

  The address conversion table 500 is one of management information 1140 stored in the RAM 114 of the FM module 100.

  The address conversion table 500 manages the LBA 501 and the PBA 502 in association with each page (4 KB in the example of FIG. 5).

  LBA 501 indicates the head address of data stored in one page. The PBA 502 indicates an address that uniquely specifies a page constituting the memory chip 120. When the PBA 502 is not associated, the LBA 501 stores information indicating that it is not allocated.

  In this embodiment, every time new data is written on a page corresponding to the LBA 501, the FM controller 110 associates a new PBA 502 with the LBA 501 instead of the PBA 502 associated with the LBA 501. The FM controller 110 associates the new PBA 502 with the LBA 501 designated by the host computer 10 and registers it in the address translation table 500. Although FIG. 5 shows an example in which LBA 501 and PBA are associated with 502 in page size units, the present invention is not limited to this unit. For example, the LBA 501 and the PBA 502 can be associated with each other in block size units.

  Next, management information for performing characteristic time control in the present embodiment will be described.

  FIG. 6 shows an example of the block management table 600.

  The block management table 600 is one of the management information stored in the RAM 114 of the FM module 100.

  The block management table 600 includes a PBA Group 601, a chip number 602, a block number 603, an erase count 604, a previous erase date and time 605, a First page program date and time 606, and a Last page program date and time 607 for each block (1 MB in the example of FIG. 6) 202. The final program page 608 and the invalid page number 609 are managed in association with each other.

  PBA Group 601 indicates the head address (head PBA) of block 202 (see FIG. 2).

  The chip number 602 indicates the number of the memory chip 120 having the block 202. In this embodiment, as shown in FIG. 6, the chip numbers 602 with earlier addresses are associated in order from the PBA Group 601 with earlier addresses.

  A block number 603 indicates a block number. In this embodiment, as shown in FIG. 6, block numbers 603 with earlier addresses are associated in order from PBA Group 601 with earlier addresses.

  The number of erases 604 indicates the number of erase processes performed on the block specified by the block number 603. Here, the erase process indicates that all data existing in the block 202 is erased, and that data in the block 202 is re-erased even if no data exists in the block 202. In the present embodiment, the erase count 604 is incremented by 1 each time the erase process is performed.

  The previous erase date and time 605 indicates the date and time when the erase process was recently performed on the block specified by the block number 603. In this embodiment, when the erase process is performed on the block, the date and time of the erase process is registered as the previous erase date and time 605.

  The First page program date and time 606 indicates the date and time when data was programmed for the first page of the block specified by the block number 603. Here, “program” indicates that data is written from the register 201 to the block 202 (page 301). In the present embodiment, when data is programmed in the first page, the date and time of the program is registered as the first page program date and time 606. It should be noted that a value indicating “all page erased” or “unwritten” is registered in the first page program date and time 606 for a block that has not been programmed for the first page. Hereinafter, writing data from the host computer 10 to the FM module 100 is referred to as “write”, and writing data in the FM module 100 is referred to as “program”.

  The Last page program date and time 607 indicates the date and time when data was programmed on the last page of the block 202 specified by the block number 603. In this embodiment, every time data is programmed in the last page, the date and time at the time of programming is registered as the Last page program date and time 607. For the block 202 in which the program for the last page is not executed, a value indicating that writing to all pages in the block is not completed is registered as the Last page program date and time 607.

  The last program page 608 indicates the number of the page where the program has been completed so far in the block specified by the block number 603. In the present embodiment, by incrementing the value of the final program page 608 by one, the next program destination page 301 is specified. When data is programmed in all pages 301 in the block 202, the last page number is registered in the last program page 608. The block 202 cannot be programmed with data until erase processing is performed.

  The number of invalid pages 609 indicates the number of invalid pages (pages not associated with the LBA 501) in the block 202 specified by the block number 603.

  Since the memory chip 120 cannot be overwritten, when the host computer 10 updates data to the LBA 501, a new PBA 502 is associated with the LBA 501 (see FIG. 5). Then, data is programmed into the page 301 corresponding to the newly associated PBA 502. For this reason, the page 301 in which the data before update is programmed becomes an invalid page that is not associated with the LBA 501 and is not referred to by the host computer 10. In this embodiment, the number of such invalid pages is managed for each block 202, and a block 202 to be a reclamation target to be described later is selected based on the number of invalid pages.

  This completes the description of the block management table 600. In the present embodiment, an example in which all information shown in FIG. 6 is used will be described. However, the block management table 600 does not necessarily have to be constructed with all types of information shown in FIG. As control objects in the control of the interval between instructions to the memory chip 120, “time between program and erase”, “time between erase and program”, “time between erase and next erase”, and “program and next program A plurality of times such as “interval time” are conceivable, but it may be constructed by only a part of each information column shown in FIG. 6 depending on the time to be controlled. For example, when the control target is “time between program and erase”, the block management table 600 may be constructed only by the Last page program date and time 607. Further, although the size of the table 600 increases, information indicating the program date and time may be registered in the table 600 for each page. As for the PE interval or EP interval, the program date / time is not necessarily the program date / time of the first or last page, but the program date / time other than the first or last page is adopted as the program date / time for the PE interval or EP interval. Also good.

  The various information (601 to 609) of the block management table 600 is not necessarily recorded in the RAM 113. For example, for PBA Group 601, chip number 602, block number 603, erase count 604, previous erase date and time 605, First page program date and time 606, and Last page program date and time 607, the block number included in this row It may be recorded on the last page of the block 202 specified by 603.

  For one block 202 (one page 301), a longer time (PE interval) from when data is programmed until it is erased is better. In this embodiment, when the FM controller 110 tries to erase data programmed in a certain block 202, the data is programmed in the last page 301 among the pages 301 constituting the block 202 to be erased. When the time from the “last page program date and time 607”, which is the recorded time, to the current time is detected and this time is greater than or equal to a certain threshold (hereinafter referred to as the PE threshold), it is programmed in the block 202 to be erased. Erase the data. In this way, it is possible to control so that the PE interval of all pages 301 constituting the block 202 is equal to or greater than the PE threshold. This is because the page 301 before the last page 301 is always longer than the last page 301 from the time the data is programmed until the current time. That is, the PE interval of the last page 301 for the block 202 is the shortest PE interval for the block 202, and the PE interval of the first page 301 for the block 202 is the longest PE interval for the block 202.

  Although it is desirable to manage the program date and time for each page 301 (or cell: a unit constituting the page 301), the management information becomes enormous. Instead of managing the program date and time of all the pages constituting the block 202, the program date and time is managed for the last page, and the PE interval is calculated based on this, thereby managing the size of the management information 1140. The PE interval can be controlled to be equal to or greater than the PE threshold value for all the pages constituting the block 202 while preventing the amount of data from becoming enormous.

  The page 301 should have a shorter time (EP interval) from when data is erased until it is programmed. In the present embodiment, the time from the “previous erase date / time 605” to the current time of the block 202 (program target block) that is about to be programmed with data is detected, and this time is less than a certain threshold (hereinafter referred to as EP threshold). If so, data is programmed into the block 202 to be programmed. Thereby, the EP interval can be controlled to be equal to or less than the EP threshold.

  When there is a block 202 in which the EP interval (the time from “previous erase date and time 605” to the current time) exceeds the EP threshold, the FM controller 110 does not block the block 202 even if data is programmed. Erase processing is executed for 202. As a result, “previous erase date and time 605” is updated to the current date and time, so the EP interval is reset to an initial value (for example, zero).

  FIG. 7 shows an example of the wear leveling management queue 700.

  The wear leveling management queue 700 is one piece of management information stored in the RAM 114. The wear leveling management queue 700 manages the number of erasures of the block 202 (PBA Group) by level division every predetermined number. The wear leveling management queue 700 manages the erase count range 701 and the PBA Group 702 in association with each other.

  The erase count range 701 indicates the range of the erase count (at least one of the upper limit and the lower limit of the erase count). FIG. 7 shows an example in which the level is divided into five levels based on statistics (for example, an average value) of the number of times of erasure of all the blocks 202 mounted on the FM module 100. That is, the erase frequency range varies depending on the average value of the erase frequency of all the blocks 202 mounted on the FM module 100. The erase frequency range may be updated regularly or irregularly.

  In FIG. 7, for example, the level with the smallest number of erases (erase number range) is a range where the number of erases is less than 201 times the average value, and thereafter, the erase range is divided every 200 times. In wear leveling that equalizes the number of erases of a block, the block is preferentially used from a block group with a small number of erases (by preferentially using blocks belonging to the smallest possible level), thereby equalizing the number of erases. Is realized.

  PBA Group 702 indicates the head address of the block 202 belonging to the erase count range 701.

  The PBA Group 702 is registered as a FIFO (first in first out) type queue, and a new PBA Group 702 is registered at the end of the queue (right end in the example of FIG. 7). When using a block, the block registered at the earliest in time series is used, and the block registered at the end of the queue is not selected until all previously registered blocks are used.

  In the present embodiment, the example in which the number of erases shown in FIG. 7 is divided into five levels every 200 times is shown, but the present invention is not limited to this level division. For example, any range can be classified according to the leveling accuracy of the required number of erases. Further, the erase frequency range is not necessarily uniform. For example, although a certain erase frequency range is 200 times, another erase frequency range may be 150 times.

  The above is the description of the management information used in this embodiment.

  FIG. 8 shows an example of a program stored in the RAM 114.

  The RAM 114 stores an input / output (I / O) program 1141, a reclamation program 1142, and an erase program 1143. These programs are executed by the processor 115 to realize various functions. Detailed descriptions of these programs will be described later using flowcharts.

  FIG. 9 shows an outline of the control of the erase process.

  The FM controller 110 checks the “invalid page count 609” of the block 202 constituting each memory chip 120 mounted on the FM module 100, and detects a block in which the invalid page count 609 is greater than the reference value (step S1). The reference value may be a predetermined threshold value, or may be an average value of the number of invalid pages of all blocks 202. That is, in S1, a block having an absolute and / or relatively large number of invalid pages is detected. Here, it is assumed that the block 202A is detected.

  Next, the FM controller 110 calculates the time from the “Last page program date and time 607” of the detected block 202A to the current time, and checks whether the calculated time (elapsed time) is equal to or greater than the PE threshold (S2). . According to the illustrated example, the PE threshold is 3h (h: time). In the block 202A, “Last page program date 607” is “2010 / 4.14 / 9: 00”. Since the current time is “2010 / 4.14 / 13: 00”, the time to the present is 4h. In this case, the FM controller 110 determines that the time since the block 202A was last programmed is equal to or greater than the PE threshold.

  Therefore, the FM controller 110 performs an erase process on the block 202A (S3).

  On the other hand, even if the FM controller 110 detects the block 202B (S5), the erase process is not performed on the block 202B. That is, since the “Last page program date and time 607” of the block 202B is “2010 / 4.14 / 11: 00” and the current time is “2010 / 4.14 / 13: 00”, the time until the present time Is 2h. The time (2h) is not longer than the PE threshold (3h). For this reason, the FM controller 110 does not perform erase processing on the block 202B (S6). When the time from “Last page program date and time 607” to the present time becomes equal to or greater than the PE threshold for the block 202B, the FM controller 110 executes an erase process on the block 202B.

  As described above, the erase process is not performed on the blocks whose time from the last page program date and time 607 to the current date and time is not equal to or greater than the PE threshold value. For this reason, it is guaranteed that the PE interval of the block becomes the PE threshold value.

  FIG. 10 shows an outline of control of program processing.

  The FM controller 110 detects a block (hereinafter, erased block) 202C in which no data is written after the erase process (S11). The FM controller 110 calculates the time from the “previous erase date and time 605” of the block 202C to the current time, and checks whether or not the calculated time is equal to or less than the EP threshold (S12).

  In the illustrated example, the EP threshold is 5h. The “previous erase date and time 605” of the block 202C is “2010 / 4.15 / 9: 00”. Since the current time is “2010 / 4.15 / 13: 00”, the time (elapsed time) up to the present time is 4h. In this case, the FM controller 110 determines that the time from the “previous erase date and time 605” of the block 202C is equal to or less than the EP threshold value. In this case, the FM controller 110 programs data on the first page of the block 202C (S13).

  On the other hand, even if the FM controller 110 detects the erased block 202D (S14), the FM controller 110 performs the erase process on the block 202D without programming the data in the first page of the block 202D. Specifically, the “last erase date and time 605” of the block 202D is “2010 / 4.15 / 5: 00”. Since the current time is “2010 / 4.15 / 13: 00”, the time to the present is 8h. In this case, the FM controller 110 determines that the time (8h) from the “previous erase date and time 605” of the block 202D exceeds the EP threshold (S15). In this case, the FM controller 110 does not program data on the first page of the block 202D, and performs an erase process on the block 202D (S16).

  As described above, data is not written to the first page of the erased block whose time from the “previous erase date and time 605” exceeds the EP threshold. For this reason, it is possible to avoid a block in which the EP interval exceeds the EP threshold.

  Details of the processing performed in this embodiment will be described below.

  FIG. 11 shows an example of a program processing flow. For example, the processor 115 can execute the processing described with reference to FIG. 11 by executing the I / O program 1141.

  The FM module 100 receives a write command including data to be written and an LBA for designating a write target area from the host computer 10 (S1101). More specifically, a write command is notified from the host computer 10 to the processor 115 via the FE-IF 111. Next, the processor 115 instructs the FE-IF 111 to write data to be written to the data buffer 113. The FE-IF 111 programs data to be written from the host computer 10 in the data buffer 113.

  Next, the processor 115 acquires the PBA associated with the LBA received in S1101 (S1102). Since this process is a characteristic process of this embodiment, the details will be described later.

  The processor 115 instructs the FM-IF 116 to generate an ECC (Error Correcting Code) (S1103). Next, the FM-IF 116 reads the data to be written from the data buffer 113 in units of ECC protection data length, and the ECC generation circuit in the FM-IF 116 calculates the ECC for each protection data length, and the data buffer Program 113.

  The processor 115 transfers the ECC generated in step S1103 and the write target data received in S1101 from the data buffer 113 to the memory chip 120, and executes the program (S1104). Specifically, the processor 115 transfers the data to be written to the FM-IF 116 and the ECC generated for it to the memory chip 120 and instructs the FM-IF 116 to execute the program. Next, the FM-IF 116 that has received the instruction reads the data to be written and the ECC from the data buffer 113, transfers them to the memory chip 120, and instructs the memory chip 120 to program. The memory chip 120 programs data according to the instruction. The data program destination is a page corresponding to the PBA specified in S1102.

  In order to associate the LBA received in S1101 with the PBA acquired in S1102, the processor 115 updates the address conversion table (see FIG. 5) (S1105). With this process, it is possible to obtain a PBA associated with the LBA from the host computer 10. Specifically, the processor 115 searches the address conversion table 500 for an LBA 501 that matches the LBA specified by the write command, and registers the PBA acquired in S1102 as the PBA 502 corresponding to the found LBA 501.

The processor 115 updates the block management table 600 (S1106). Specifically, the following is performed.
(S1106-1) The processor 115 searches the block management table 600 for a PBA Group that matches the PBA acquired in S1102.
(S1106-2) Next, the processor 115 acquires the page number 301 of the page that is the program destination in S1104 in the PBA block acquired in S1102 (the target block in the description of FIG. 11). The processor 115 registers the page number 301 as the final program page 608.
(S1106-3) When the page number 301 is the first page of the target block 202, the processor 115 registers information indicating the current date and time as the corresponding first page program date and time 606 of the block management table 600. Alternatively, when the page number 301 is the last page of the target block 202, the processor 115 registers information indicating the current date and time as the Last page program date and time 607.

  The above is the outline of the program processing.

  Next, step S1102 which is one feature of the present embodiment will be described with reference to FIG.

  If a long time elapses after the erase process is performed, or if a long time elapses after data is programmed in the page, the initial threshold voltage fluctuates in the page 301 and is appropriate for the floating gate during programming. It becomes difficult to apply a large amount of charge, and the reliability of stored data may be reduced.

  In this embodiment, for the characteristics of the memory chip 120, control is performed so that the elapsed time from the previous erase date and time and the elapsed time after programming the first page are within a certain time.

  FIG. 12 shows an example of the flow of step S1102.

  The processor 115 selects a candidate block from the midway program block group (S1201).

  Specifically, the processor 115 refers to the block management table 600 and arbitrarily selects one block from the plurality of blocks 202 whose final program page 608 does not indicate the final page. Here, the block 202 in which the final program page 608 does not indicate the final page is the “intermediate program block” in the description of FIG. 12, and one arbitrarily selected block is the “candidate” in the description of FIG. "Block".

  In step S1201, the processor 115 sets a block whose erase count 604 is equal to or greater than a reference value (a predetermined threshold or a value obtained based on the erase count of a plurality of blocks) as an intermediate writing block that can be a candidate block. good. Thus, since the block 202 with a small number of erases 604 can be preferentially programmed, it is possible to reduce the decrease in data retention reliability caused by the passage of time from the erase.

  The processor 115 determines whether a candidate block can be selected (S1202). If the candidate block can be acquired (S1202: Yes), the processor 115 identifies the First page program date and time 606 of the selected candidate block (S1203).

  The processor 115 calculates the elapsed time from the first page program date 606 to the present time (S1204).

  The processor 115 determines whether or not the elapsed time calculated in S1204 is equal to or less than a preset threshold (hereinafter referred to as PP threshold) (S1205). When the elapsed time is equal to or less than the PP threshold (S1205: Yes), the processor 115 specifies the PBA of the next page of the last program page of the candidate block (S1206). This is because the reliability is maintained when the elapsed time calculated in S1204 is equal to or less than the PP threshold.

  When the elapsed time calculated in S1204 exceeds the PP threshold (S1205: No), the processor 115 removes the block selected in S1201 from the midway program block group (S1207). This is because if the elapsed time calculated in S1204 exceeds the PP threshold, the reliability degradation may be outside the allowable range. In S1207, specifically, for example, the processor 115 registers the value of the last page as the last program page 608 and the information indicating the current date and time as the Last page program date and time 607 for the block selected in S1201. Good.

  On the other hand, when a candidate block cannot be selected (typically, when there is no program block in the middle) (S1202: No), the processor 115 refers to the wearing management queue 700 and has a block whose erase count is less than the reference value. Is selected (S1208). As described above, the memory chip 120 has a characteristic that reliability decreases when the EP time is long. For this reason, a control method of performing erase immediately before the program is effective for high reliability. However, in this embodiment, a block subjected to an erase process is prepared in advance for the purpose of improving the performance of the FM module 100 based on the characteristic that the time required for erasing the memory chip 120 is longer than the time for programming and reading. Is done. In this embodiment, a plurality of erased blocks are registered in the wear leveling management queue 700 by leveling according to the number of erases. In S1208, for example, a block with the smallest possible level in the erase count range is selected.

  The processor 115 identifies the “previous erase date and time 605” of the block selected in S1208 (S1209).

  The processor 115 calculates the elapsed time from the previous erase date and time 605 identified in S1209 to the current time (S1210).

  The processor 115 checks whether or not the elapsed time calculated in S1210 is equal to or less than the EP threshold (S1211). When the elapsed time calculated in S1210 is equal to or less than the EP threshold (S1212: Yes), the processor 115 identifies the PBA of the First page of the block acquired in S1208 (S1213).

  If the elapsed time calculated in S1210 is not less than or equal to the EP threshold (S1212: No), the processor 115 executes an erase process on the block selected in S1208 (S1212). By this process, the elapsed time from the previous erase date and time 605 to the present time is reset to an initial value (for example, zero). The processor 115 identifies the PBA of the First page of the block for which the erase process has been executed in S1212 (S1213).

  According to S <b> 1211 and S <b> 1212, it is guaranteed that the block having the page corresponding to the PBA specified in S <b> 1213 is a block whose elapsed time from the previous erase date / time 605 to the current time is equal to or less than the EP threshold.

  Data is programmed in S1104 of FIG. 11 to the page corresponding to the PBA specified in S1206 or S1213.

  Next, the read process will be described.

  FIG. 13 shows an example of the flow of read processing.

  The FM controller 110 receives from the host computer 10 a read command designating an LBA to be read (target LBA in the description of FIG. 13) (S1301).

  The processor 115 refers to the address conversion table 500 and identifies the PBA assigned to the target LBA (S1302).

  The processor 115 reads data from the page corresponding to the PBA specified in S1302 (S1303). Specifically, the processor 115 issues a read command to the FM-IF 116. Upon receiving the instruction, the FM-IF 116 reads data by designating the block 202 and the page 301 to the memory chip 120 having the page indicated by the PBA.

  The FM-IF 116 checks the consistency of the read data using the ECC attached to the data read in S1303. If an error is detected in this check, the FM-IF 116 corrects the read data using the ECC (S1304).

  The FM-IF 116 transfers the read data to the host computer 10. If the data has been corrected in S1304, the corrected data is transferred to the host computer 10 (S1305).

  The above is the description of the read processing in this embodiment.

  Next, the reclamation process in the present embodiment will be described. The reclamation process occurs secondary by a write process in addition to a request from the host computer 10.

  First, the trigger for starting the reclamation process will be described.

  As described above, the memory chip 120 has a characteristic that once data is programmed in a page, it cannot be overwritten. For this reason, when a write is performed on the same LBA, data is programmed in the page following the last program page, and the pre-update data is programmed in the address conversion table 500 as the PBA corresponding to the LBA. The PBA of the page in which data is newly programmed is registered from the PBA of the current page.

  By this control, the host computer 10 updates the data without making the host computer 10 aware that the PBA has been changed.

  When the update write described above is performed, a new page is used each time the update write is performed, and therefore the number of pages that can be programmed in the FM module 100 is reduced. For this reason, the FM module 100 according to the present embodiment performs a reclamation process when the number of pages that can be programmed in the FM module 100 becomes a predetermined amount or less.

The reclamation process is implemented, for example, by the processor 115 executing the reclamation program 1142. Specifically, in the reclamation process, the following is executed.
(X1) The processor 115 searches for a block having an invalid page equal to or greater than the reference value. The “reference value” referred to here may be a predetermined threshold value or a value (for example, an average value) based on the number of invalid pages in a plurality of blocks. That is, here, a block having an absolute or relatively large number of invalid pages is searched. An “invalid page” is a page that is not associated with an LBA in the address conversion table 500 and that has been programmed with data.
(X2) Next, the processor copies the data in the valid page (the page associated with the LBA in the address translation table 500) included in the block found in (x1) to the page of another block, and addresses The association with the LBA in the conversion table 500 is updated to the copy destination page. By this processing, all pages in the block found at (x1) are set as invalid pages. That is, the block is an invalid block. An invalid block is a block in which all pages are invalid pages (in other words, a block that does not include a valid page specified from the PBA assigned to the LBA). An invalid block is a block that may be erased.

  In the reclamation process according to the present embodiment, a plurality of invalid blocks (blocks that are candidates for erasure) are managed, and the erase process for invalid blocks may be performed when the number of erased blocks is equal to or less than a threshold value. The threshold value may be determined according to the write performance of the FM module 100.

  On the other hand, according to the characteristics of the memory chip 120, when the PE interval (elapsed time from program to erase) is short, the number of electrons and hole traps generated in the oxide insulating film of the cell is long. Many occur in comparison with For this reason, the reliability of a block having a short PE interval may be low.

  In contrast to the above characteristics, in the present embodiment, in the erase process that occurs at the reclamation opportunity, the erase process is not performed for blocks whose PE interval is equal to or less than the PE threshold. As an exception, if the number of erased blocks is depleted, erase processing may be performed on blocks whose elapsed time from the Last page program date and time 607 is equal to or less than the PE threshold value in order to secure erased blocks. At this time, the block to be erased may be the block having the longest elapsed time from the last page program date and time 607 among a plurality of blocks whose elapsed time from the last page program date and time 607 is equal to or less than the PE threshold. Note that the erase process may be performed by the processor 115 executing the erase program 1143, for example.

  FIG. 14 shows an example of the reclamation process flow.

  The reclamation process is started when a predetermined event is detected, for example, when it is detected that the number of erased blocks in the FM module 100 is equal to or less than a predetermined threshold.

  The processor 115 identifies blocks having an absolute or relatively large number of invalid pages 609 from the block management table 600 (S1401). The block selected in S1401 may be a block in which data is programmed on the last page.

  The processor 115 identifies the Last page program date and time 607 of the block identified in S1401 (“candidate block” in the description of FIG. 14) (S1402).

  The processor 115 calculates the difference between the value of the Last page program date and time 607 specified in S1402 and the current date and time to obtain the elapsed time from the Last page program date and time 607 for the candidate block (S1403).

  The processor 115 checks whether or not the elapsed time calculated in S1403 is less than the PE threshold (S1404). If the elapsed time obtained in S1403 is less than the PE threshold (S1404: Yes), the candidate block is canceled (S1405), and S1401 is performed again. In S1405, the processor 115 may write, for example, the number of the canceled candidate block in the RAM 114 so that the canceled candidate block is not selected again. The reason why the processing as in S1405 is performed is that the reliability regarding data retention may be reduced in the block whose elapsed time obtained in S1403 is less than the PE threshold.

  On the other hand, when the elapsed time obtained in S1403 is equal to or greater than the PE threshold (S1404: No), the processor 115 copies all the valid page data in the candidate block to the page of another block (S1406). Then, the processor 115 associates the PBA of the copy destination page with the LBA associated with the PBA of the valid page of the candidate block instead of the PBA (update of the address conversion table 500). By this process, all pages in the candidate block become invalid pages. That is, the candidate block becomes an invalid block. If the candidate block acquired in S1401 is already an invalid block, it is not necessary to execute this step, and the processor 115 can execute the process of S1407 after the process of S1404.

  The processor 115 performs an erase process on the invalid block created in S1406. (S1407).

  The processor 115 adds 1 to the erase count 604 of the block for which the erase process has been performed in S1406. Then, the processor 115 registers the erased block (candidate block) in the wear leveling management queue 700 based on the number of erases after the addition (S1408). Thereby, the candidate block is associated with the level of the erase count range to which the erase count after addition of the candidate block belongs.

  The above is the description of the reclamation process in the present embodiment. In this embodiment, the elapsed time from the Last page program date 607 is compared with the PE threshold, but the elapsed time to be compared is not limited to this. For example, the elapsed time from the first page program date and time 606 to the present time may be compared with the PE threshold. The last page program date and time 607 may not be an actual measurement value, and may be a value predicted from the first page program date and time 606, for example.

  As described so far, in this embodiment, an erase process is performed on blocks whose elapsed time from the Last page program date and time 607 is equal to or greater than the PE threshold, and an erase process is not performed on blocks whose elapsed time is less than the PE threshold. . Also, data is programmed on the first page of a block whose elapsed time from the previous erase date and time 605 is less than or equal to the EP threshold, and data is not programmed on the first page of a block whose elapsed time exceeds the EP threshold (the erase is not included in that block). After processing, data is programmed into the first page of the block). In addition, when the elapsed time from the first page program date and time 606 is equal to or less than the PP threshold, the data is programmed to the page following the last program page. With the above control, it is possible to suppress a decrease in reliability related to data retention of the FM module 100. In addition, since it is ensured that the PE interval is equal to or greater than the PE threshold, it is possible to delay the time when the number of erasures reaches the upper limit, so that the life of the FM module 100 can be expected to be extended.

  Example 2 will be described below. At this time, differences from the first embodiment will be mainly described, and description of common points with the first embodiment will be omitted or simplified (this is the same for the third embodiment).

  In the first embodiment, the minimum time (PE threshold) of the PE interval is defined, but in the second embodiment, instead of defining the PE threshold, it is possible for each block in response to a command from the host computer 10. Control is performed to ensure the PE interval as much as possible.

  FIG. 15 shows an example of the PE interval management queue 1500.

  The PE interval management queue 1500 is one piece of management information stored in the RAM 114. The PE interval management queue 1500 is grouped according to the elapsed time from the last page program date to the current date (hereinafter referred to as program elapsed time). Management information in which the PBA Group of the invalid block corresponding to the elapsed time range of each group is registered. The PE interval management queue 1500 includes a program elapsed time 1501 and a PBA Group 1502.

  The program elapsed time 1501 is information indicating the program elapsed time.

  According to the example of FIG. 15, the program elapsed time is divided into four levels. As the block group belonging to the longest program elapsed time, there is a block group whose program elapsed time is 30 minutes or more, and then the program progress such as a block group whose program elapsed time is 20 minutes or more and 29 minutes or less. Blocks are classified according to a certain range of time. In this embodiment, the program elapsed time is managed up to the minute order and is not managed for the second order, but the unit of the program elapsed time may not be limited to the minute.

  The PBA Group 1502 stores the head address of the PBA Group 1502 indicating the corresponding block for each program elapsed time level (range). The PBA Group 1502 is registered as a FIFO-type queue, and a block is newly registered at the end of the queue.

  In the second embodiment, invalid blocks are managed using the PE interval management queue 1500. When the number of invalid blocks falls below a certain number, an invalid block is created by invalid block generation processing (for example, reclamation processing), and the generated invalid block is based on the program elapsed time of the invalid block. Registered in the management queue 1500. Details of these will be described later.

  In the second embodiment, the PE interval management queue 1500 is updated regularly or irregularly, for example, every 10 minutes. Specifically, each time the FM controller 110 updates the PE interval management queue 1500, the FM controller 110 measures the time from the updated time to the current time. If the program elapsed time of the invalid block at time T (when the measured time has passed 10 minutes) belongs to a level above the level to which the invalid block belongs at time T, the FM controller 110 The PBA of the first page of the invalid block is registered at the end of the upper level queue.

  In this embodiment, the queue 1500 is changed every 10 minutes, but the update of the queue 1500 is not limited to every 10 minutes. For example, the queue 1500 may be updated every second.

  Next, the invalid block generation process in the present embodiment will be described.

  FIG. 16 is a schematic diagram showing a block use cycle in the second embodiment.

  The data recording block group 1601 is a block group conceptually showing a block including an effective page. The FM controller 110 grasps the data recording block group 1601 from the block management table 600. Further, when the number of blocks registered in the invalid block group 1602 becomes equal to or less than a certain number, the FM controller 110 determines that blocks whose invalid pages are greater than or equal to the reference value from the data recording block group 1601 (that is, invalid pages are absolute Or relatively many blocks). The selected block is a reclamation candidate block. Then, the FM controller 110 copies all valid pages of the reclamation candidate block to pages of other blocks.

  Next, the FM controller 110 changes the correspondence destination of the LBA corresponding to the valid page of the reclamation candidate block from the valid page of the reclamation candidate block to its copy destination page. As a result, all valid pages of the reclamation candidate block become invalid pages. As a result, the reclamation candidate block becomes an invalid block. The invalid block generated in this way is registered in the invalid block group 1602.

  The invalid block group 1602 is a block group in which invalid blocks (blocks in which all pages are invalid pages) are registered. The FM controller 110 registers the invalid block at the level of the PE interval management queue 1500 corresponding to the program elapsed time of the invalid block. When the number of blocks constituting the erased block group 1603 falls below a certain number, the FM controller 110 selects a block whose program elapsed time is equal to or greater than a reference value from the invalid block group 1602 and sets the selected invalid block as the selected invalid block. On the other hand, erased blocks are generated by performing erase processing. The erased block generated in this way is registered in the erased block group 1603. Note that the reference value of the program elapsed time may be a predetermined PE threshold value of the program elapsed time, or may be a value (for example, an average value) based on the program elapsed times of a plurality of invalid blocks constituting the invalid block group 1602. . That is, the invalid block to be selected is an invalid block whose program elapsed time is absolute or relatively long.

  The erased block group 1603 is a block group in which erased blocks are registered. The FM controller 110 registers the erased block in the wear leveling management queue 700.

  The FM controller 110 is an erased block when a write command from the host computer 10 is generated and the number of program blocks (blocks with no recordable data until the last page and having recordable pages) becomes less than a certain number. A block whose erase count is equal to or less than the reference value is selected from the group 1603, and the write data received from the host computer 10 is programmed into the page in the selected block. Thereby, the block becomes a data recording block (intermediate program block). The reference value for the number of erases may be a predetermined threshold value for the number of erases, or may be a value (for example, an average value) based on the number of erases of a plurality of erased blocks constituting the erased block group 1603. In other words, the erased block to be selected is an erased block whose erase count is absolute or relatively small.

  Hereinafter, the process performed in Example 2 will be described in detail.

  FIG. 17 shows an example of the flow of invalid block generation processing. For example, the processor 115 can execute the processing described in FIG. 17 by executing the invalid block generation program 1144 (see FIG. 19).

  The processor 115 selects an invalid block candidate (hereinafter, invalid candidate block) from the data recording block group (S1701). Specifically, the processor 115 refers to the block management table 600 and selects a block having an absolute or relatively large value stored in the number of invalid pages 609 as an invalid candidate block. At this time, the processor 115 may select a block with the largest number of invalid pages from the table 600 as an invalid candidate block. Further, there is a threshold for the number of invalid pages as a reference for generating invalid blocks, and the processor 115 may select a block whose value registered in the number of invalid pages 609 is equal to or greater than the threshold as an invalid candidate block.

  The processor 115 identifies the Last page program date and time 607 for the invalid candidate block selected in S1701 (S1702).

  The processor 115 calculates the elapsed time (program elapsed time) from the Last page program date and time 607 specified in S1702 to the present (S1703).

  The processor 115 copies all valid pages in the invalid candidate block selected in S1701 to empty pages of other blocks (pages that are neither valid data nor invalid data and no data is recorded), and the valid page of the copy source is The correspondence destination of the associated LBA is changed from the valid page of the copy source to the copy destination page (S1704). By this processing, all pages in the invalid candidate block become invalid pages, and invalid candidate blocks become invalid blocks.

  The processor 115 registers an invalid block (a candidate block in which all pages are invalid pages) in the level corresponding to the program elapsed time calculated in S1704 in the PE interval management queue 1500 (S1705). For example, when the program elapsed time calculated in S1703 is 12 minutes, the processor 115 puts the PBA of the first page of the invalid candidate block on the line in the PE interval management queue 1500 within the PE interval of 10 minutes to 19 minutes. Record.

  The above is the description of the invalid block generation process in the present embodiment.

  Next, the erase process in the present embodiment will be described.

  FIG. 18 shows an example of the erase process flow.

  In the first step of the erase process, the processor 115 refers to the PE interval management queue 1500 and selects a block from the level with the longest processor elapsed time (S1801). In the description of FIG. 18, the block selected in S1801 is referred to as an “erase candidate block”.

  More specifically, the processor 115 refers to the PE interval management queue 1500 and registers the first block (registered in the group) of the level with the longest processor elapsed time (the highest level) (30 minutes or more in the example of FIG. 15). Among all the blocks, the block registered most recently) is specified. At this time, when there is no block registered at the highest level, the processor 115 selects a block from the next higher level (in the example of FIG. 15, within 20 minutes to 29 minutes). As described above, when a block cannot be specified, the processor 115 lowers the level by one step and selects a block from that level. In this way, the block search range is sequentially changed to a level with a low processor elapsed time until a block can be acquired.

  The processor 115 refers to the block management table 600 and specifies the value of the erase count 604 of the row corresponding to the erase candidate block (S1802).

  The processor 115 notifies the FM-IF 116 of the PBA indicating the erase candidate block and the erase command, and the FM-IF 116 notifies the block number including the erase candidate block and transmits the erase command. (S1803).

  The processor 115 increments the number of erases specified in S1802 by 1 (S1804). Thereby, the new number of erases of the erase candidate block is determined.

  The processor 115 registers the candidate block (erased block) subjected to the erase process in S1803 at the corresponding level in the wear leveling management queue 700 using the number of erases calculated in S1804. Also, a new erase count is registered in the block management table 600 erase count 604 (S1805).

  According to the second embodiment, the erase process is preferentially performed on invalid blocks having a long program elapsed time. Thereby, the PE interval of all blocks can be made longer. As a result, the number of electron traps and hole traps generated at a short PE interval is reduced, and high reliability is expected.

  In addition, with such high reliability, the number of blocks that are determined to be unusable for data storage can be reduced, and the upper limit of the number of erasures of usable blocks can be substantially increased. it can.

  In addition, the minimum time regulation of the PE interval in the first embodiment and the control for ensuring the PE interval in the present embodiment as much as possible (that is, the first embodiment and the second embodiment) may be implemented in combination.

  Up to this point, an example has been described in which the minimum time of the PE interval is limited in the normal processing (Example 1) or the PE interval is controlled to be long (Example 2). By shortening the PE interval, it can be expected that a large amount of electron traps and hole traps are suppressed, and a decrease in reliability (data retention reliability) related to data retention in the nonvolatile semiconductor memory can be expected.

  In the third embodiment, a block with low data retention reliability is detected during operation, and by increasing the PE interval of the block, the generated hole traps and electron traps can be reduced and the data retention reliability can be improved. I can expect. That is, according to the present embodiment, blocks that cannot be used can be reduced.

  A nonvolatile semiconductor memory generally has a finite data retention period. For this reason, it is desirable to perform a process of reading data and copying it to another place at regular intervals. Such processing is generally called “refresh processing”. In the nonvolatile semiconductor memory, the number of faulty bits increases with time after data recording. For this reason, the FM controller 110 can periodically or irregularly read the entire storage area in the FM module 100 and inspect the number of failure bits generated in each page. This processing is called “verification processing” in the present embodiment.

  FIG. 20 shows an example of a table representing the relationship between the elapsed days and the failure bit threshold.

  As the number of days elapses after the data is programmed, the memory failure bits increase. Therefore, according to the table 2000 shown in FIG. 20, if the value of the elapsed days 2001 (for example, the number of days from when data is programmed to a certain page (for example, the first page or the last page)) is long, the failure bit threshold value 2002 is expensive. The failure bit threshold is a threshold for the number of failure bits.

  In this embodiment, in at least one of the read process (read command process from the host computer 10), the refresh process, and the verify process, the FM controller 110 determines the number of days (for example, a certain page (for example, the first page) for a block. Alternatively, the failure bit threshold 2002 corresponding to the number of days from the time the data is programmed to the last page) is specified. The FM controller 110 detects a block (hereinafter referred to as a dangerous block) in which the number of failed bits (or the average number of failed bits of all ECC CWs in the block) is equal to or greater than a failed bit threshold. More specifically, the FM controller 110 first reads data from the page in the block in any of the processes described above. Then, the FM controller 110 acquires the number of failed bits for each ECC that configures the page. Next, the FM controller 110 identifies a block in which the number of failed bits is equal to or greater than the failed bit threshold value as a dangerous block. The failure bit threshold value may be a value equal to or less than the number of bits that can be corrected by ECC.

  Blocks determined as dangerous blocks are subject to invalid block generation processing described in the second embodiment. The FM controller 110 copies the data of all pages included in the dangerous block to another block, and updates the address conversion table 500. By this processing, the dangerous block becomes an invalid block. Then, the FM controller 110 registers the invalid block in a dangerous block management queue (not shown). The dangerous block management queue is a FIFO-type queue, and is registered at the end of the queue when the block is registered in the queue.

  In the third embodiment, the invalid block is registered in the PE interval management queue 1500 as in the second embodiment.

  FIG. 21 shows an example of the management screen 2100.

  The management screen 2100 is a screen displayed on the management computer 11. The management computer 11 manages a plurality (or one) of FM modules 100.

  The management screen 2100 displays IDs (module lists) of a plurality of FM modules 100 managed by the management computer 11. The user can select one or more FM module IDs in the module list.

  The management screen 2100 has a time display area 2101, and a block display screen 2102 is displayed on the front surface of the screen 2100. On this screen 2102, information related to the FM module selected by the user from a plurality of FM module IDs is displayed. The management computer 11 collects management information from a plurality of FM modules 100, and all or part of the management information may be displayed on at least one of the screens 2100 and 2102.

  In the time display area 2101, “allowable minimum PE interval” and “allowable maximum EP interval” are displayed. In this embodiment, the “allowable minimum PE interval” (that is, the PE threshold) and the “allowable maximum EP interval” (that is, the EP threshold) cannot be changed from the management screen 2100 in this embodiment, but at least one of these thresholds It may be changed from this screen 2100 by the user.

  The block display screen 2102 displays “total number of blocks” and “number of dangerous blocks” for the FM module corresponding to the FM module ID selected by the user from the module list. The “total number of blocks” is the total number of blocks included in the FM module 100 selected by the user, and the “dangerous block number” is the number of dangerous blocks among those blocks. As described above, the dangerous block is a block in which the number of failed bits is equal to or greater than the failed bit threshold.

  FIG. 22 shows an example of the erase process flow.

  In the present embodiment, as described above, blocks whose failure bit number is greater than or equal to the failure bit threshold are managed as dangerous blocks. The FM controller 110 prevents the dangerous block from being erased as much as possible. This is because the memory chip 120 has a characteristic that if the data is left in a programmed state, the number of failed bits generated in the recording data at the next programming time is reduced. The dangerous block is controlled to become a block to be erased after the program elapsed time of the block has passed a predetermined time.

  The processor 115 determines whether or not the number of block selections managed by the FM module 100 is less than a predetermined threshold (S2201). At this time, the threshold is, for example, 100,000.

  When the block selection number is less than the threshold (S2201: Yes), the processor 115 selects an invalid block from the PE interval management queue 1500 (S2202), as in the second embodiment. The processor 115 increments the block selection number by one. Therefore, the aforementioned “number of block selections” indicates the number of times an invalid block that is not a dangerous block is selected. Since the processing from S2204 to S2207 is substantially the same as S1802 to S1805 (see FIG. 18) of the second embodiment, description thereof is omitted.

  On the other hand, if the block selection number is equal to or greater than the predetermined threshold (S2201: No), the processor 115 acquires a block (erase candidate block in the description of FIG. 22) from the dangerous block management queue (S2208). The fact that the block selection number has increased from zero to a threshold value or more means that the dangerous block has been left unselected for the time until the block selection number has increased from zero to the threshold value or more. Therefore, there is a possibility that the number of trouble bits generated in the recording data at the next program in the dangerous block is reduced. The dangerous block is preferably a block in which some data is programmed.

  The processor 115 sets the block selection number to an initial value (for example, 0) (S2209). Thereby, thereafter, the dangerous block is not selected as the erase candidate block until the block selection number increases again to the threshold value or more.

  After S2209, the processor 115 performs the process of S2204.

  FIG. 23 shows an example of the flow of read processing.

  The processing from S2301 to S2304 is almost the same as S1301 to S1304 in FIG.

  The processor 115 identifies the number of faulty bits in the read source block (S2305).

  The processor 115 identifies the failure bit threshold corresponding to the program elapsed days of the read source block from the table 2000 shown in FIG. 20, and checks whether or not the number of failure bits identified in S2305 is less than the identified failure bit threshold ( S2306).

  When the number of failure bits is less than the failure bit threshold value (S2306: Yes), the processor 115 transfers the corrected data to the host computer 10 (S1305).

  On the other hand, when the specified number of failed bits is equal to or greater than the failed bit threshold (S2306: No), the processor 115 registers the read source block as a dangerous block (S2307).

  According to the third embodiment, a dangerous block is selected as an erase candidate block at a lower frequency than an invalid block that is not a dangerous block. As a result, the PE interval of the dangerous block is extended. When the PE interval is extended, electron traps and hole traps in the oxide film of the dangerous block are detrapped, and the data holding capability of the dangerous block is restored, so that the data holding reliability can be maintained again. As a result, the number of blocks that cannot be used is reduced, the number of erasures that can be used is increased, and the life of the FM module 100 is expected to be extended.

  In addition, according to the above description, the dangerous block is a block whose failure bit number is greater than or equal to the failure bit threshold value, but the comparison between the failure bit number and the failure bit threshold value is a predetermined unit such as data unit, page unit, block unit, etc. It may be done in units of.

Further, the dangerous block may be a block corresponding to at least one of the following (1) and (2) instead of or in addition to the block having the number of failed bits equal to or greater than the failed bit threshold.
(1) The time required for the program is less than the first reference value.
(*) When the block deteriorates, holes are formed in the oxide insulating film. There is a possibility that N electrons are put into FG (floating gate), but less than N electrons are put into FG, and the rest may enter holes of the oxide insulating film. In this case, since the number of injected electrons is less than N, the time required for programming is shortened.
(*) The first reference value may be a predetermined threshold value, or may be a value (for example, an average value) based on a program time (time required for programming) of a plurality of blocks. That is, this (1) may be that “the time required for the program is absolute or relatively long”.
(2) The time required for erasing is less than the second reference value.
(*) When the block deteriorates, it is difficult for electrons to come out of the FG in the erase process.
(*) The second reference value may be a predetermined threshold value, or may be a value (for example, an average value) based on the erase time (time required for the erase process) of a plurality of blocks. That is, this (2) may be that “the time required for erasing is absolute or relatively short”.

  Although several embodiments have been described above, the present invention is not limited to these embodiments.

  For example, the LBA may be multistage. For example, the LBA specified by the host computer 10 is the first LBA of the area in the logical volume, and the second LBA recognized by the FM module 100 is associated with the first LBA. Thus, the PBA may be associated with the second-stage LBA. Even in multiple stages, the PBA is indirectly associated with the first stage LBA.

  Further, for example, the third embodiment includes the first and second embodiments, but the second embodiment may not be included. In this case, for example, in S2202 of FIG. 22, a block having an absolute or relatively large number of invalid pages may be selected, and in S2203, the number of block selections may be incremented by one.

  100 ... FM module, 110 ... FM controller, 120 ... memory (nonvolatile semiconductor memory)

Claims (14)

Each, and a plurality of flash memory chips including a plurality of blocks is a unit of data erase,
A controller that is connected to the plurality of flash memory chips and that performs data programming and data erasing on the block;
Each block has a plurality of pages which are units of data program,
The controller is
Generate multiple invalid blocks,
For each of the plurality of invalid blocks, managing the latest program time, which is the time at which data was recently programmed in the block,
Erasing data in an invalid block having a relatively long elapsed program time that is an elapsed time from the most recent program time among the plurality of invalid blocks;
Flash memory module.   The plurality of invalid blocks is more than a certain number of invalid blocks;
  The controller maintains more invalid blocks than the certain number by newly creating invalid blocks when the number of invalid blocks becomes equal to or less than the certain number.
The flash memory module according to claim 1.   The controller manages the logical address and physical address of each of the plurality of pages in association with each other,
  The invalid block is a block that does not include a valid page identified from the physical address associated with the logical address.
The flash memory module according to claim 1 or 2. The controller detects a dangerous block which is a block in which data is programmed and there is a risk of lowering reliability.
In the control of the timing of the erase process is performed on the block based on the recent program time, the controller preferentially selects the invalid block as the erase target block instead of the previous SL dangerous blocks,
The flash memory module according to claim 1 . In controlling the timing at which erase processing is performed for a block based on the latest program time, the controller
If the block selection number, which is the number of times the invalid block has been selected, is less than a predetermined value, select the invalid block as the erase process target block, and update the block selection number.
If the number of blocks selected is equal to or greater than a predetermined value, selecting the danger block as the erase target block, it returns the value of the block selection number to an initial value,
The flash memory module according to claim 4 . The dangerous block is a block having a failure bit number equal to or greater than a failure bit threshold value,
The controller identifies a failure bit threshold corresponding to the elapsed program time of a block from a plurality of failure bit thresholds, and if the number of failure bits of the block is equal to or greater than the identified failure bit threshold, the block is identified as the danger bit. Detect as a block,
The flash memory module according to claim 5 . The elapsed program time is a first elapsed time that is an elapsed time from the time when data is recently programmed on the last page, and an elapsed time that is an elapsed time from the time when data is recently programmed on a page other than the last page. 2 elapsed time,
The elapsed program time for the controller that detects the dangerous block is the second elapsed time,
The flash memory module according to claim 6 . Each, and multiple including a plurality of flash memory modules block which is a unit of data erase,
A flash controller connected to the plurality of flash memory modules and performing data programming and data erasing on the block;
Each block has a plurality of pages which are units of data program,
The flash controller
Generate multiple invalid blocks,
For each of the plurality of invalid blocks, managing the latest program time, which is the time at which data was recently programmed in the block,
Erasing data in an invalid block having a relatively long elapsed program time that is an elapsed time from the most recent program time among the plurality of invalid blocks;
Storage device.   The plurality of invalid blocks is more than a certain number of invalid blocks;
  The controller maintains more invalid blocks than the certain number by newly creating invalid blocks when the number of invalid blocks becomes equal to or less than the certain number.
The storage device according to claim 8.   The controller manages the logical address and physical address of each of the plurality of pages in association with each other,
  The invalid block is a block that does not include a valid page identified from the physical address associated with the logical address.
The storage apparatus according to claim 8 or 9. The flash controller detects a dangerous block that is a block in which data is programmed because there is a risk of lowering reliability.
In the control of the timing of the erase process is performed on the block based on the recent program time, the flash controller preferentially selects the invalid block as the erase target block instead of the previous SL dangerous blocks,
The storage apparatus according to any one of claims 8 to 10 . In controlling the timing at which erase processing is performed on the block based on the latest program time, the flash controller
If the block selection number, which is the number of times the invalid block has been selected, is less than a predetermined value, select the invalid block as the erase process target block, and update the block selection number.
If the number of blocks selected is equal to or greater than a predetermined value, selecting the danger block as the erase target block, it returns the value of the block selection number to an initial value,
The storage apparatus according to claim 11 . The dangerous block is a block having a failure bit number equal to or greater than a failure bit threshold value,
The flash controller specifies a failure bit threshold corresponding to the elapsed program time of a block from a plurality of failure bit thresholds, and if the number of failure bits of the block is greater than or equal to the specified failure bit threshold, the block is Detect as dangerous blocks,
The storage device according to claim 12 . The elapsed program time is a first elapsed time that is an elapsed time from the time when data is recently programmed on the last page, and an elapsed time that is an elapsed time from the time when data is recently programmed on a page other than the last page. 2 elapsed time,
The elapsed program time for the flash controller for detecting the dangerous block is the second elapsed time.
The storage apparatus according to claim 13 .

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