JP2007172066A - Memory controller and flash memory system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a creation unit of an address conversion table. <P>SOLUTION: The correspondence between a physical zone comprising a plurality of physical blocks and a logical zone comprising a plurality of sectors, and the correspondence between a physical segment given by dividing the physical zone with a predetermined number of division and a logical segment given by dividing the logical zone with the number of division are managed, and the physical blocks in the physical segment are assigned to an exclusive block or a common block. Data corresponding to the logical segment in correspondence with the physical segment including the exclusive block is written into the exclusive block, and data corresponding to the logical zone in correspondence with the physical zone including the common block is written in the common block. The address conversion table is created for each logical segment. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a memory controller and a flash memory system including the memory controller.

  In recent years, flash memory, which is a non-volatile storage medium, has been actively developed, and is widely used as a storage medium for information devices (host systems) such as digital cameras.

  As the data handled by such devices has increased in capacity, the storage capacity of flash memory has also increased. In order to smoothly manage the storage area of the flash memory having such a large capacity, a method of managing the storage area by dividing it into a plurality of zones has been used in recent years (see, for example, Patent Document 1).

  More specifically, the storage area of a conventional flash memory having a plurality of zones is partitioned and managed in the form shown in FIG. 6, for example.

  That is, a specific physical block address (PBA) is assigned to each physical block that is a unit of data erasing and includes a predetermined number of pages that are units of physical data reading and writing. Each physical block is classified into one of a plurality of physical zones, and a unique physical zone number (PZN) is assigned to each physical zone. In the example of FIG. 6, a total of 2048 physical blocks are assigned consecutive PBAs # 0 to # 2047, and a total of 512 physical blocks PBA # 0 to # 511 are assigned to the physical zone of PZN # 0. A total of 512 physical blocks of PBA # 512 to # 1023 belong to the physical zone of PZN # 1, a total of 512 physical blocks of PBA # 1024 to # 1535 belong to the physical zone of PZN # 2, and PBA # A total of 512 physical blocks 1536 to # 2047 belong to the physical zone of PZN # 3.

  Each page is assigned a physical page address (PPA). The PPA has a form in which a page number (PN), which is a serial number of the page in the physical block, is added to the lower level of the PBA of the physical block to which the page belongs.

  On the other hand, the address space on the host system side is managed by an LBA (Logical Block Address) which is a serial number assigned to an area divided in units of sectors (512 bytes). Further, a group of a plurality of sectors is called a logical block, and a group of a plurality of logical blocks is called a logical zone. The serial number assigned to the logical block is called a logical block number (LBN), and the serial number assigned to the logical zone is called a logical zone number (LZN). Further, the serial number in each logical zone of the logical block included in each logical zone is called a logical zone block number (LZIBN).

  Therefore, when the number of logical blocks included in each logical zone is n, the quotient when LBN is divided by n corresponds to LZN, and the remainder corresponds to LZIBN.

  In addition, one physical zone is allocated to each logical zone, and data corresponding to each logical block included in the logical zone is written to a physical block included in the physical zone allocated to the logical zone. Further, LZIBN (or LBN) of the logical block corresponding to the data is written in the redundant area of the physical block in which the data is written.

  Note that the correspondence between the physical block and the logical block changes every time data is written or erased. Therefore, an address conversion table is created in order to manage the correspondence between the two at each time point, and the address conversion table is updated each time the correspondence changes. This address conversion table can be created for each logical zone. That is, since the correspondence relationship between the logical zone and the physical zone is set in advance, address conversion is performed by referring to the LZIBN written in the redundant area of the physical block included in the physical zone for which the address conversion table is to be created. A table can be created.

  Here, even if the information (hereinafter referred to as logical address information) specifying the logical block to be written in the redundant area is LBN, an address conversion table can be created, but generally LZIBN with a small amount of data is used. Is written in the redundant area as logical address information.

  Each logical zone is assigned a predetermined number of sectors set according to the storage capacity of the physical zone. In the example of FIG. 6, LBA # 0 to # 15999 sectors are in the LZN # 0 logical zone, LBA # 16000 to # 31999 sectors are in the LZN # 1 logical zone, and LBA # 32000 is in the LZN # 2 logical zone. ... To # 47999, and LBA # 48000 to # 63999 are assigned to the logical zone of LZN # 3, respectively. In this example, one page of the flash memory corresponds to one sector, and each physical block is composed of 32 pages.

The 16000 sectors assigned to each logical zone are managed as logical blocks in units of 32 sectors in which LBAs are continuous in the logical zone. Therefore, in other words, 32 sectors with consecutive LBAs are assigned as logical blocks, and 500 logical blocks with consecutive LBNs (LZIBN # 0 to # 499) are allocated to each logical zone. Here, the number of sectors included in the logical block is set as appropriate so that the capacities of one logical block and one or a plurality of physical blocks coincide. In addition, since data is stored in the LBA order in each page of the physical block, based on the correspondence between the logical block included in each logical zone and the physical block included in the physical zone corresponding to the logical zone. The access destination in the flash memory can be specified.
In addition, since the storage capacity of the flash memory has increased, it is not necessary to create an address conversion table for every logical zone at startup, but to create an address conversion table for the logical zone that is the access target each time. ing.
JP 2005-18490 A

However, if the correspondence between logical blocks and physical blocks is managed in logical zone units (logical zone and physical zone units corresponding to each other) as described above, all logical blocks included in the logical zone are targeted. The physical zone (physical block included in the physical zone) corresponding to the logical zone cannot be accessed unless the address conversion table is created. Therefore, as the size of each logical zone and physical zone increases, the time required to create the address translation table increases, and therefore the time from when an access request is received from the host system to when access is started increases.
In addition, if the size of the logical zone and physical zone is reduced, the time required to create the address translation table can be shortened. However, when bad blocks are concentrated in a specific physical zone, the necessary number of effective blocks is secured in that physical zone. Probability of becoming impossible increases. In other words, if the size of the logical zone and the physical zone is reduced while maintaining the ratio (a: b) of the physical block number b included in the physical zone to the logical block number a included in the logical zone, the specific physical zone is defective. When blocks are concentrated, the probability that the number of effective blocks necessary in the physical zone cannot be secured increases. Here, if the ratio (a: b) is changed to increase the reserve number (ba), which is the difference between the logical block number a and the physical block number b, the necessary number of effective blocks cannot be secured. Although the probability can be lowered, the capacity that can be stored in the flash memory is reduced.

  The present invention has been made in view of the above circumstances, a memory controller capable of reducing the size of the address conversion table without reducing the size of the logical zone and the physical zone, and a flash memory system including the memory controller. The purpose is to provide.

In order to achieve the above object, the memory controller of the present invention provides:
A memory controller that controls access to a flash memory in response to a command from a host system,
Correspondence between a physical zone that collects a plurality of physical blocks that are erase units in the flash memory and a logical zone that collects a plurality of sectors that are access units in the host system, and a physical that divides the physical zone by a predetermined number Address management means for managing a correspondence relationship between a segment and a logical segment obtained by dividing the logical zone by the number of divisions;
A physical block in the physical segment is assigned to an occupied block or a shared block, and data corresponding to the logical segment corresponding to the physical segment including the occupied block is written to the occupied block, and the shared block is written to the shared block. Writing means for writing data corresponding to the logical zone corresponding to the physical zone including the shared block;
It is characterized by providing.

The number of physical blocks included in the physical segment is preferably a power of 2.
The shared block is preferably the first or last physical block in the physical segment.

  The flash memory system of the present invention includes the memory controller configured as described above and a flash memory.

  According to the present invention, an address conversion table can be created in units of logical segments and physical segments obtained by dividing a logical zone and a physical zone by a predetermined number of divisions. Therefore, it is possible to create an address translation table for an area to be accessed in a shorter time than when creating an address translation table for each logical zone and physical zone. Even if bad blocks are concentrated on a specific physical segment, physical blocks (shared blocks) in other physical segments belonging to the same physical zone can be used. The probability that the number cannot be secured can be kept low.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram schematically showing a flash memory system 1 according to the present invention. As shown in FIG. 1, the flash memory system 1 includes a flash memory 2 and a controller 3 that controls the flash memory 2.

  The flash memory system 1 is connected to the host system 4 via the external bus 13. The host system 4 includes a CPU (Central Processing Unit) for controlling the entire operation of the host system 4, a companion chip for transferring information to and from the flash memory system 1, and the like. The host system 4 may be various information processing apparatuses such as a personal computer and a digital still camera that process various types of information such as characters, sounds, and image information.

  The flash memory 2 is a non-volatile memory and includes a register and a memory cell array. The flash memory 2 writes or reads data by copying data between a register and a memory cell.

  The memory cell array includes a plurality of memory cell groups and word lines. Each memory cell group includes a plurality of memory cells connected in series. The word line is for selecting a specific memory cell in the memory cell group. Data is copied between the selected memory cell and the register via the word line, that is, data is copied from the register to the selected memory cell, or data is copied from the selected memory cell to the register. .

  A memory cell constituting the memory cell array is constituted by a MOS transistor having two gates. Here, the upper gate and the lower gate are referred to as a control gate and a floating gate, respectively. By injecting charges (electrons) into the floating gate or discharging charges (electrons) from the floating gate, data can be obtained. Is written or data is erased.

  Since the floating gate is surrounded by an insulator, the injected electrons are held for a long period of time. Note that, when electrons are injected into the floating gate, a high voltage at which the control gate is on the high potential side is applied between the control gate and the floating gate. Further, when electrons are discharged from the floating gate, a high voltage at which the control gate becomes a low potential side is applied between the control gate and the floating gate.

  Here, a state where electrons are injected into the floating gate is a write state, which corresponds to a logical value “0”. The state in which electrons are discharged from the floating gate is an erased state, which corresponds to a logical value “1”.

  Such an address space of the flash memory 2 is shown in FIG. The address space of the flash memory 2 is composed of “pages” and “blocks (physical blocks)”.

  A page is a processing unit in a data read operation and a data write operation performed in the flash memory 2. The physical block is a processing unit in the data erasing operation performed in the flash memory 2, and is composed of a plurality of pages.

  In the flash memory 2 shown in FIG. 2, one page is composed of a user area 25 of 1 sector (512 bytes) and a redundant area 26 of 16 bytes, and one physical block is composed of 32 pages. Yes. There is a flash memory in which one page is composed of a 4-sector user area and a 64-byte redundant area, and one physical block is composed of 64 pages. The user area 25 is an area for storing user data supplied from the host system 4.

  The redundant area 26 is an area for storing additional data such as an error correction code, logical address information, and a block status (flag).

  The error collection code is data for detecting and correcting an error included in the data stored in the user area 25.

  The logical address information is information for specifying a logical block corresponding to the data when valid data is stored in the user area 25 of at least one page included in each physical block of the flash memory 2. It is. As this logical address information, the logical zone block number LZIBN or the logical block number LBN can be used, but the logical zone block number LZIBN having a small number of bits is often used.

  For a physical block in which valid data is not stored in the user area 25, logical address information is not stored in the redundant area 26 of the block.

  Therefore, by determining whether or not logical address information is stored in the redundant area 26, it is possible to determine whether or not valid data is stored in the physical block including the redundant area 26. . That is, when no logical address information is stored in the redundant area 26, no valid data is stored in the physical block.

  As described above, one physical block includes a plurality of pages. Data cannot be overwritten on these pages. For this reason, even when only the data stored in one page is rewritten, the data stored in all the pages in the physical block including the page must be rewritten.

  That is, in normal data rewriting, data stored in all pages of a physical block including a page to be rewritten is written to another erased physical block. At this time, as for the data stored in the page where the data is not changed, the previously stored data is rewritten as it is.

  In rewriting data as described above, normally, the rewritten data is written in a physical block different from the physical block stored previously. For this reason, the correspondence relationship between the logical block address and the physical block address dynamically changes every time data is rewritten in the flash memory 2.

  Therefore, it is necessary to manage the correspondence between the logical block and the physical block, and this correspondence is managed by the address conversion table. This address conversion table is created based on logical address information (LZIBN or LBN) stored in the redundant area 26 of each physical block. Note that the address conversion itself between the logical address and the physical address by the address conversion table is well known.

  The block status (flag) is a flag indicating whether the block is good or bad. A block in which data cannot be normally written is determined as a defective block, and a block status (flag) indicating a defective block is written in the redundant area 26.

  Such a flash memory 2 receives data, address information, internal commands, and the like from the controller 3 and performs various processes such as a data read process, a write process, a block erase process, and a transfer process.

  Here, the internal command is a command for the controller 3 to instruct the flash memory 2 to execute processing, and the flash memory 2 operates in accordance with the internal command given from the controller 3. In contrast, the external command is a command for the host system 4 to instruct the flash memory system 1 to execute processing.

  As shown in FIG. 1, the controller 3 includes a microprocessor 6, a host interface block 7, a work area 8, a buffer 9, a flash memory interface block 10, an ECC (error collection code) block 11, ROM (Read Only Memory) 12. The controller 3 constituted by these functional blocks is integrated on one semiconductor chip. Each functional block will be described below.

  The microprocessor 6 controls the overall operation of the controller 3 in accordance with a program stored in the ROM 12. For example, the microprocessor 6 reads a command set defining various processes from the ROM 12, supplies the command set to the flash memory interface block 10, and causes the flash memory interface block 10 to execute processes.

  As shown in FIG. 3, the host interface block 7 includes a command register R1, a sector number register R2, and an LBA register R3, and exchanges data, address information, status information, external commands, etc. with the host system 4. To do. Data or the like supplied from the host system 4 to the flash memory system 1 is taken into the flash memory system 1 (for example, the buffer 9) using the host interface block 7 as an entrance. Data supplied from the flash memory system 1 to the host system 4 is supplied to the host system 4 through the host interface block 7 as an exit.

  A work area 8 shown in FIG. 1 is a work area in which data necessary for controlling the flash memory 2 is temporarily stored, and includes a plurality of SRAM (Static Random Access Memory) cells.

  The buffer 9 temporarily stores data read from the flash memory 2 and data to be written to the flash memory 2. That is, data read from the flash memory 2 is held in the buffer 9 until the host system 4 can receive the data, and data to be written to the flash memory 2 is stored until the flash memory 2 becomes writable. It is held in the buffer 9.

  The flash memory interface block 10 exchanges data, address information, status information, internal commands, and the like with the flash memory 2 via the internal bus 14. More specifically, the flash memory interface block 10 includes an address processing unit, a command register, an instruction processing block, and the like. As shown in FIG. 3, the address processing unit includes a physical block address register R11, a page number register R12, and a counter R13. The instruction processing block executes processing according to the sequence command set in the command register R21.

  The physical block address register R11 sets the physical block address PBA of the physical block to be accessed in the flash memory 2. The PBA set in the physical block address register R11 is determined based on the address conversion table created in the work area 8. This address conversion table is created in units of logical segments and physical segments corresponding to each other. The logical segment and the physical segment will be described later.

In the page number register R12, the page number PN of the first page to be accessed is set as an initial value. In the counter R13, the number of pages to be accessed in the physical block to be accessed is set as an initial value.
The command register R21 is set with a sequence command that instructs processing to be executed by the flash memory interface block 10.

  The instruction processing block outputs an internal command, a physical address, etc. for controlling the flash memory 2 according to the sequence command set in the command register R21.

  The flash memory interface block 10 supplies the flash memory 2 with internal commands, address information, and the like output from the instruction processing block, thereby causing the flash memory 2 to execute reading and writing. Here, the physical address for specifying the page to be accessed is generated based on the PBA set in the physical block address register R11 and the set value set in the page number register R12. Each time one page is accessed, the set value set in the counter R13 is decremented (subtracted by 1), and the set value set in the page number register R12 is incremented (added by 1). When the set value set in the counter R13 becomes 0, a series of access processing ends.

  The ECC block 11 generates an error correction code added to data to be written to the flash memory 2 and detects and corrects an error included in the read data based on the error correction code added to the read data.

  The ROM 12 is a non-volatile storage element that stores a program that defines a processing procedure performed by the microprocessor 6. Specifically, the ROM 12 stores a program that defines a processing procedure such as creation of an address conversion table, for example.

  Next, a logical address / physical address conversion process realized by the flash memory system configured as described above will be described.

In the present embodiment, as shown in FIG. 4, a logical zone is composed of 960 logical blocks, and a physical zone is composed of 1024 physical blocks. One physical block is composed of 32 pages, and one page corresponds to one sector.
The logical zone is divided into 32 logical segments, and the physical zone is also divided into 32 physical segments. Here, a serial number assigned to a logical segment in each logical zone is referred to as a logical segment number LSN, and a serial number assigned to a physical segment in each physical zone is referred to as a physical segment number PSN.

  The correspondence between the logical zone and the physical zone is set in advance. In this embodiment, the physical zone of PZN # 0 is assigned to the logical zone of LZN # 0, the physical zone of PZN # 1 is assigned to the logical zone of LZN # 1, and PZN # is assigned to the logical zone of LZN # 2. Two physical zones are allocated, and similarly, one physical zone is sequentially allocated to one logical zone.

  The correspondence relationship between the logical segments of LSN # 0 to # 31 included in the logical zone and the physical segments of PSN # 0 to # 31 included in the physical zone is also set in advance. FIG. 4 shows the correspondence between the logical segments and the physical segments in the logical zone of LZN # 0 and the physical zone of PZN # 0 that have a correspondence relationship with each other. Here, the physical segment of PSN # 0 is allocated to the logical segment of LSN # 0, the physical segment of PSN # 1 is allocated to the logical segment of LSN # 1, and the physical segment of PSN # 2 is allocated to the logical segment of LSN # 2 In the same manner, one physical segment is assigned to one logical segment.

  Each physical segment of PSN # 0 to # 31 is made up of 32 physical blocks, the head block of which is assigned to a shared block, and 31 physical blocks other than the shared block are assigned to dedicated blocks. The private block is a physical block that is allocated only to the logical blocks included in the logical segments in the corresponding relationship, and the shared block is the logical block belonging to any logical segment of LSN # 0 to # 31. It is a physical block that can be used as a data write destination corresponding to the block.

  Here, when the number of physical blocks included in each physical segment is a power of 2, the PSN of the physical segment to which each logical block of PZIBN # 0 to # 1023 included in each physical zone belongs is represented by a binary number in PZIBN. It can be determined by a specific bit when expressed. In the present embodiment, each physical zone includes 1024 physical blocks, and each physical segment includes 32 physical blocks.

  Therefore, PZIBN can be represented by 10 bits, and the upper 5 bits of the PZIBN correspond to the PSN, and the lower 5 bits correspond to the intra-segment block number PSIBN indicating the serial number assigned to the physical block in the physical segment. When the physical block of PSIBN # 0 of each physical segment is a shared block, the upper 5 bits of PZIBN of the shared block correspond to the shared block number SBN indicating the serial number assigned to the shared block in the physical zone. For example, a physical block whose PZIBN is “11 0000 0011” is a private block of PSIBN # 3 of the physical segment of PSN # 24, and a physical block whose PZIBN is “11 0000 0000” is a shared block of SBN # 24 .

  On the other hand, each logical segment of LSN # 0 to # 31 is composed of 30 logical blocks. Data corresponding to the logical block included in each logical segment is stored in a physical segment occupying block or a shared block of physical segments PSN # 0 to # 31 (shared block of SBN # 0 to # 31) that have a corresponding relationship with each other. Written. That is, the data corresponding to the logical block included in the logical segment of LSN # 0 is written to the occupied block of the physical segment of PSN # 0 or the shared block of SBN # 0 to # 31 and included in the logical segment of LSN # 1. The data corresponding to the logical block to be written is written to the occupied block of the physical segment of PSN # 1 or the shared block of SBN # 0 to # 31, and similarly corresponds to the logical block included in the logical segment of LSN # 31. Data is written into the occupied block of the physical segment of PSN # 31 or the shared block of SBN # 0 to # 31.

  Here, the LSN of the logical segment to which each logical block of LZIBN # 0 to # 959 included in each logical zone belongs is obtained by dividing LZIBN by the number of logical blocks included in each logical segment. For example, the logical block of LZIBN # 32 belongs to the logical segment of LSN # 1 because the quotient of 32 ÷ 30 is 1, and the logical block of LZIBN # 76 is the logical segment of LSN # 2 because the quotient of 76 ÷ 30 is 2. Belongs. That is, the LSN corresponds to a quotient obtained by dividing LZIBN by the number of logical blocks included in each logical segment. Further, LZIBN of the logical block corresponding to the written data is written in the redundant area 26 of the physical block in which the data is written.

  Next, address conversion table creation processing will be described. When there is an access request from the host system 4, the controller 3 creates an address conversion table with reference to LZIBN written in the redundant area of the physical block included in the physical zone to be accessed.

  FIG. 5 is an example of an address conversion table created in a logical block included in LSN # 1 whose access target is LZN # 0 (logical block included in a range of LZIBN # 30 to # 59 of LZN # 0).

  When this address conversion table is created, the LZIBN written in the redundant area of the private block included in the physical segment of PSN # 1 and the redundant area 26 of the shared block of SBN # 0 to 31 is referred to. For the shared blocks of SBN # 0 to S31, it is preferable to create an auxiliary table showing the correspondence between SBN and LZIBN. If this auxiliary table has been created, when creating the address translation table, refer to the LZIBN written in the redundant area 26 of the occupied block of the physical segment corresponding to the logical segment to be accessed and this auxiliary table. do it.

  In the address conversion table shown in FIG. 5, physical blocks corresponding to logical blocks of LZIBN # 30 to 59 are indicated by PSIBN for private blocks and SBN for shared blocks. The block type is information for determining whether the corresponding physical block is indicated by PSIBN or SBN. When it is “0”, it is determined as PSIBN, and when it is “1”, it is determined as SBN. To do. If there is no corresponding physical block such as LZIBN # 35, the private block PSIBN # 0 that does not exist in the corresponding location of the address translation table is written.

When the number of physical blocks included in each physical segment is k, PSN, PSIBN, and PZIBN satisfy the following relational expression.
PZIBN = k × PSN + PSIBN
Therefore, when the number of physical blocks included in each physical segment is 32 and the PSN is # 1, the PZIBN of the physical block corresponding to PSIBN “0 0001” is # 33 (32 × 1 + 1), and the PSIBN “0 0111”. The PZIBN of the physical block corresponding to “# 39” is # 39 (32 × 1 + 7).

  In actual processing, PZIBN can be obtained by adding PSIBN in binary number to the lower side of PSN in binary number. For example, PZIBN “00 0010 0001” is obtained by adding PSIBN “0 0001” to the lower side of PSN “0 0001”, and PSIBN “0 0111” is added to the lower side of PSN “0 0001”. PZIBN “00 0010 0111” is determined.

Further, when the number of physical blocks included in each physical segment is k, SBN and PZIBN satisfy the following relational expression.
PZIBN = k × SBN
Therefore, when the number of physical blocks included in each physical segment is 32, the PZIBN of the physical block corresponding to SBN “0 0000” is # 0 (32 × 0), and the physical block corresponding to SBN “0 0011” The PZIBN is # 96 (32 × 3).

  In actual processing, PZIBN can be obtained by adding 5-bit “0” to the lower side of the SBN in binary notation. For example, PZIBN “00 0000 0000” is obtained by adding “0 0000” to the lower side of SBN “0 0000”, and PZIBN “00 0000” is added to the lower side of SBN “0 0011”. 00 0110 0000 "is determined.

  The address conversion table for each logical segment as described above may indicate the correspondence between the logical block and the physical block by the correspondence between the logical block number LZIBN in the logical zone and the physical block number PZIBN in the physical zone. In this case, the block type as described above becomes unnecessary.

  Next, read processing in the flash memory system 1 will be described.

  In this read process, the process is executed based on the number of sectors set in the sector number register R2 of the host interface block 7, the leading value of the LBA set in the LBA register R3, and the external command set in the command register R1. . This reading process is started when an external command is set in the command register R1.

  The microprocessor 6 accesses the logical zone number LZN to be accessed, the block number LZIBN in the logical zone, and the logical segment number based on the head LBA set in the LBA register R3 and the number of sectors to be accessed set in the sector number register R2. Find the LSN. Here, the LBN is obtained by deleting the lower 5 bits of the LBA, and by dividing this LBN by the number of logical blocks included in the logical zone (960), the LZN corresponding to the quotient and the LZIBN corresponding to the remainder are also obtained. Is required. Further, the LSN corresponding to the quotient is obtained by dividing this LZIBN by the number of logical blocks (30) included in the logical segment. If the access target area extends over a plurality of logical blocks, LZN, LZIBN, and LSN are obtained for each logical block.

  Next, based on the logical zone number LZN, the logical zone block number LZIBN, and the logical segment number LSN thus obtained, the physical block address PBA of the physical block corresponding to the logical block is obtained. When the access target area extends over a plurality of logical blocks, the PBA is obtained for each logical block.

The process for obtaining the PBA will be specifically described.
First, it is confirmed whether or not the logical segment address conversion table corresponding to the access target LZN and LSN has been created. If the address conversion table has not been created, an area for creating the address conversion table is secured in the work area 8. In this area allocation, the block type and the writing location where PSIBN or SBN is written are secured in the order of LZIBN, and the block type is initially set to information indicating “occupied block” and PSIBN is initially set to information indicating “no data”. Subsequently, the private block redundant area 26 included in the physical segment specified by the PZN and PSN corresponding to the access target LZN and LSN and the shared block included in the physical zone specified by the PZN corresponding to the access target LZN LZIBN (logical address information) written in the redundant area 26 is read out. Furthermore, the PSIBN or SBN of the physical block in which the LZIBN has been written is written in the write location corresponding to the read LZIBN. When SBN is written, the corresponding block type is changed to information “1” indicating “shared block”.

  Next, PZIBN corresponding to the access target LZIBN is obtained based on the created address conversion table. Here, when the corresponding physical block is a private block, PZIBN is obtained by adding PSIBN to the lower side of the PSN. When the corresponding physical block is a shared block, PZIBN is obtained by adding “0 0000” to the lower side of the SBN.

  Subsequently, the physical block address PBA (= 1024 × PZN + PZIBN) is obtained by adding the number of physical blocks for the physical zone existing before the physical zone PZN to the obtained intra-physical block number PZIBN. Note that 1024 is the number of physical blocks included in the physical zone.

  Next, the microprocessor 6 sets the physical block address PBA of the physical block to be accessed in the physical block address register R11 of the flash memory interface block 10, and the page number register R12 of the page to start reading in the physical block. A page number is set, the number of pages to be read is set in the counter R13, and a sequence command for instructing data reading is set in the command register R21. If the access target specified by the number of sectors set in the sector number register R2 and the LBA set in the LBA register R3 does not extend over a plurality of logical blocks, the number of sectors set in the sector number register R2 Is set in the counter R13, and the lower 5 bits of the LBA set in the LBA register R3 are set in the page number register R12. When the access target extends over a plurality of logical blocks, the range of the LBA to be accessed is divided for each logical block, and the number of sectors included in each divided LBA range is set in the counter R13, and each divided LBA The lower 5 bits of the first LBA in the range are set in the page number register R12.

  The instruction processing block of the flash memory interface block 10 outputs internal commands for controlling the flash memory 2, address information, and the like according to the sequence command set in the command register R21, and reads and reads data from the flash memory 2. The stored data is stored in the buffer 8. The microprocessor 6 provides the data stored in the buffer 9 to the host system 4 via the host interface block 7 and the external bus 13.

  Here, the operation of the flash memory interface block 10 will be specifically described. The flash memory interface block 10 supplies the flash memory 2 with a physical page address obtained by adding (concatenating) the set value set in the page number register R12 to the PBA set in the physical block address register R11 according to the sequence command. The data is read from the page corresponding to the physical page address, and the read data is stored in the buffer 9.

  Each time one page of data is read, the set value set in the counter R13 is decremented (subtracted by 1), the set value set in the page number register R12 is incremented (added by 1), and the counter Data is read sequentially until the set value set in R13 becomes 0, and the read data is stored in the buffer 9.

Next, the writing process in the flash memory system 1 will be described.
Also in the case of the write process, processing is executed based on the number of sectors set in the sector number register R2 of the host interface block 7, the leading value of the LBA set in the LBA register R3, and the external command set in the command register R1. The Even in the case of this writing process, the process starts when an external command is set in the command register R1.

  Similarly to the case of the read process, the logical zone number LZN to be accessed, the block number LZIBN in the logical zone, and the logical segment number LSN are also set to the access target set in the head LBA set in the LBA register R3 and the sector number register R2. It is obtained based on the number of sectors.

  The conversion from the logical address to the physical address in the writing process is basically the same as the above-described reading process. That is, also in the case of write processing, the PBA of the physical block to be accessed is obtained based on the address conversion table.

  Subsequently, if the page to which data of the physical block to be accessed is written is an empty page, data is written to the empty page. If the page is not an empty page, the empty block is searched, and data is detected in the detected empty block. Write. When searching for a free block, the free block of the private block included in the physical segment corresponding to the logical segment to be accessed is searched first, and if there is no free block of the private block, it is included in the physical zone to be accessed. The free block of the shared block to be searched is searched.

  When data is written in the empty block, LZIBN corresponding to the data is written in the redundant area 26 of the empty block in which the data is written. Furthermore, the part where the correspondence relationship between the logical block and the physical block is changed is updated in the address conversion table.

  As described above, in the flash memory system 1 according to the present embodiment, the LZN of the logical zone to which the logical block to be accessed and the LSN of the logical segment belong are specified based on the LBA, and correspond to the specified LZN and LSN. PZN and PSN are required. When writing data, data is written to the private block included in the physical segment specified by PZN and PSN, but the private block included in this physical segment has become a bad block. If there is no more empty block, data is written to the shared block of the physical zone to which this physical segment belongs.

In addition, this invention is not limited to the said embodiment, A various deformation | transformation and application are possible.
For example, in the above embodiment, one shared block is arranged at the head of one physical segment, but a physical block used as a shared block is arbitrary. That is, any physical block of LSIBN # 1 to 31 of each physical segment can be used as a shared block. Furthermore, it is possible to arrange not only one shared physical block in each physical segment but also a plurality of shared blocks. For example, the physical blocks of PSIBN # 0 and # 1 may be shared blocks.

  Also, the number of logical zones, the number of logical blocks in the logical zone, the number of logical segments in the logical zone, the number of logical blocks in the logical segment, the number of physical zones, the number of physical blocks in the physical zone, the physical zone The number of physical segments and the number of physical blocks in the physical segment can be set as appropriate as long as they are consistent with each other.

  In the above description, the number of physical zones, the number of physical blocks in the physical zone, the number of physical segments in the physical zone, and the number of physical blocks in the physical segment are all powers of 2. It does not have to be a power.

1 is a block diagram schematically showing a flash memory system according to an embodiment of the present invention. It is a figure which shows roughly the structure of the address space of the flash memory of embodiment of this invention. It is a block diagram which shows the structure of a host interface block and a flash memory interface block. It is a figure for demonstrating the correspondence of a logical address and a physical address. It is a figure which shows an example of an address conversion table. It is a figure which shows schematically the structure of the address space of the conventional flash memory.

Explanation of symbols

1 Flash memory system 2 Flash memory 3 Controller 4 Host system 6 Microprocessor 7 Host interface block 8 Work area 9 Buffer 10 Flash memory interface block 11 ECC block 12 ROM
13 External bus 14 Internal bus 25 User area 26 Redundant area

Claims (4)

A memory controller that controls access to a flash memory in response to a command from a host system,
Correspondence between a physical zone that collects a plurality of physical blocks that are erase units in the flash memory and a logical zone that collects a plurality of sectors that are access units in the host system, and a physical that divides the physical zone by a predetermined number Address management means for managing a correspondence relationship between a segment and a logical segment obtained by dividing the logical zone by the number of divisions;
A physical block in the physical segment is assigned to an occupied block or a shared block, and data corresponding to the logical segment corresponding to the physical segment including the occupied block is written to the occupied block, and the shared block is written to the shared block. Writing means for writing data corresponding to the logical zone corresponding to the physical zone including the shared block;
A memory controller comprising:   The memory controller according to claim 1, wherein the number of physical blocks included in the physical segment is a power of two.   The memory controller according to claim 1, wherein the shared block is a first physical block or a last physical block in the physical segment. The memory controller according to any one of claims 1 to 3, and a flash memory.
A flash memory system characterized by that.

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