JP5978777B2 - Imaging device - Google Patents

Description

  This case relates to an imaging apparatus.

  An infrared imaging device known as an imaging device measures the surface temperature of an object in a non-contact manner at a remote position by incident infrared rays, and is used for detecting the shape of the object. Infrared imaging devices are used in a wide range of applications such as measuring devices and control devices in production lines, medical diagnostic devices, and night vision cameras and sensor devices.

  An infrared imaging device forms an image of incident infrared rays using a reflecting mirror or a lens, and acquires an image by converting it into an electrical signal. For example, the infrared sensor array includes a plurality of sensor elements arranged in a two-dimensional matrix and a readout circuit that reads pixel data from the sensor elements. The plurality of sensor elements and the readout circuit are formed on different substrates and are connected to each other through conductive bumps. The sensor element substrate is made of, for example, gallium arsenide (GaAs), while the readout circuit substrate is made of silicon (Si) or the like.

  Regarding an infrared imaging device, for example, Patent Document 1 discloses a technique for identifying a change in a pixel signal due to noise.

JP 2011-142558 A

  The high-sensitivity infrared imaging device is cooled to a temperature equivalent to, for example, liquid nitrogen (for example, about 80 (K)) during operation in order to prevent generation of dark current due to heat of the device itself. Here, since the substrates described above are made of different materials and have different linear thermal expansion coefficients, stress is applied to the bumps between the substrates by the cooling.

  If the number of sensor elements (that is, the number of pixels) and the surface area of the substrate are increased for the purpose of increasing the resolution, the stress increases as the surface area increases. And so on. On the other hand, even when the number of pixels is increased without changing the surface area, the distance between the bumps is narrowed, which may cause a short circuit. Short circuits and breaks result in pixel defect problems.

  Accordingly, the present invention has been made in view of the above problems, and an object thereof is to provide an imaging apparatus capable of effectively increasing the resolution.

In order to solve the above problems, an imaging device described in the present specification includes a sensor substrate on which a plurality of sensor elements are arranged, a circuit board including a readout circuit that reads pixel data from the plurality of sensor elements, and the sensor A plurality of bumps provided between the substrate and the circuit board, wherein the plurality of sensor elements are connected in series two by two , and the two sensor elements connected in series are the plurality of sensor elements The bump is connected to the readout circuit via a common bump, and the sensor substrate is provided with a selection circuit that selects a readout target of the pixel data by the readout circuit from the two sensor elements. The selection circuit includes two diodes connected in parallel with the two sensor elements so that the polar directions are opposite to each other .

  The imaging device described in this specification has an effect that the resolution can be effectively increased.

It is a perspective view of an infrared imaging device. It is sectional drawing which shows partially the cross section by the II-II line | wire of FIG. 1 about the infrared imaging device which concerns on a comparative example. FIG. 3 is a sectional view partially showing a section taken along line III-III in FIG. 2. It is sectional drawing which shows partially the cross section by the II-II line | wire of FIG. 1 about the infrared imaging device which concerns on an Example. FIG. 5 is a cross-sectional view partially showing a cross section taken along line VV in FIG. 4. It is a circuit diagram which shows an example of a reading circuit. It is a circuit diagram which shows an example of a selection circuit and a pixel acquisition part. It is a time chart which shows operation | movement of a pixel acquisition part. It is sectional drawing which shows an example of the laminated body for forming a sensor element and a diode. It is sectional drawing which shows an example of the laminated structure of a sensor element and a diode.

  FIG. 1 is a perspective view of an infrared imaging device. The infrared imaging device is an imaging device that senses infrared IR emitted from an imaging target, generates pixel data corresponding to the intensity of the infrared IR for each pixel, and outputs the pixel data. The infrared imaging device has, for example, a rectangular chip shape of 5 to 20 (mm) square size.

  The infrared imaging device includes a sensor substrate 1 and a circuit substrate 2 that face each plate. The sensor substrate 1 is made of, for example, gallium arsenide (GaAs). The sensor substrate 1 includes a plurality of sensor elements as many as the number of pixels arranged in a two-dimensional matrix along the plate surface, and generates pixel data from infrared IR incident on the plate surface 10. The sensor element is, for example, a quantum well type photodetector (QWIP: Quantum Well Infrared Photodetector).

  The circuit board 2 is formed of silicon, for example, and includes a readout circuit that reads pixel data from a plurality of sensor elements. Note that the thicknesses of the sensor substrate 1 and the circuit substrate 2 are, for example, 5 (μm) and 600 (μm), respectively.

  FIG. 2 is a cross-sectional view partially showing a cross section taken along line II-II in FIG. 1 for an infrared imaging device according to a comparative example. 3 is a sectional view partially showing a section taken along line III-III in FIG. A plurality of bumps 3 are provided between the sensor substrate 1 and the circuit substrate 2.

  Each of the plurality of bumps 3 is formed of a conductive material such as indium. Each of the plurality of bumps 3 connects a plurality of sensor elements 9 arranged on the sensor substrate 1 to a readout circuit included in the circuit substrate 2 one by one. That is, one sensor element 9 is connected to the readout circuit via one bump 3. The bump 3 and the readout circuit are connected by means such as soldering or pressure bonding.

  Therefore, in this example, when the number of sensor elements 9, that is, the number of pixels is increased in order to increase the resolution, the number of bumps 3 is also increased by the same amount. Therefore, if the surface area of the sensor substrate 1 is constant, The distance L between the bumps 3 is narrowed, causing the above-described problem. The interval L between the bumps 3 in this example is, for example, 10 to 20 (μm).

  On the other hand, FIG. 4 is a sectional view partially showing a section taken along line II-II in FIG. 1 for the infrared imaging device according to the embodiment, and FIG. 5 is a section taken along line V-V in FIG. It is sectional drawing shown partially. 4 and 5, the same reference numerals are given to configurations common to those in FIGS. 2 and 3, and descriptions thereof are omitted.

  In the present embodiment, the plurality of sensor elements 4 and 5 are connected to the readout circuit included in the circuit board 2 via the common bump 3 among the plurality of bumps 3. That is, the plurality of bumps 3 are shared by the two sensor elements 4 and 5, respectively. One sensor element 4 is arranged so as to overlap the bump 3 in plan view, and is arranged so as to be alternately arranged with the other sensor element 5. The two sensor elements 4 and 5 may be adjacent to each other so that the distance to the bump 3 is the shortest, but is not limited thereto.

  Compared with the comparative example (see FIGS. 2 and 3), the infrared imaging device according to the present embodiment has the same distance L (or pitch) and size of the bumps 3 and the surface areas of the sensor elements 4 and 5. Is small. Therefore, as shown in FIG. 4, the infrared imaging element according to the present embodiment is provided with more sensor elements 4 and 5 than the comparative example without changing the number of bumps 3 and the surface area of the sensor substrate 1. Is possible. The surface shapes of the sensor elements 9, 4, and 5 are not limited to the octagon illustrated, and may be other shapes such as a rectangle.

  Pixel data generated by the two sensor elements 4 and 5 are sequentially read out as pixel signals by the readout circuit formed on the circuit board 2 through the common bump 3. FIG. 6 is a circuit diagram illustrating an example of the readout circuit.

  The readout circuit includes a plurality of pixel acquisition units 20, a plurality of output transistors 21, a plurality of row selection transistors 22, a plurality of column selection transistors 24, a load transistor 26, a vertical scanning unit 27, and a horizontal scanning unit 28. And an amplifier 29. Note that FIG. 6 shows only a part of a plurality of identical circuit elements.

  Each of the plurality of pixel acquisition units 20 is connected to the two sensor elements 4 and 5 via the bump 3, and sequentially acquires pixel data from the sensor elements 4 and 5 by time division. The pixel acquisition unit 20 is connected to the control terminal of the output transistor 21 and outputs pixel data as a pixel signal via the output transistor 21. The output transistor 21 has one terminal connected to the power supply line 231 to which the power supply voltage is applied, and the other terminal connected to one terminal of the row selection transistor 22.

  The row selection transistor 22 has a control terminal connected to the vertical scanning unit 27 via a row selection line 250, while the other terminal is connected to one terminal of the column selection transistor 24 via a column selection line 230. The other terminal of the column selection transistor 24 is connected to the input terminal of the amplifier 29 via the output line 251, while the control terminal is connected to the horizontal scanning unit 28.

  The load transistor 26 has one terminal connected to the input terminal of the amplifier 29 via the output line 251, and the other terminal is supplied with a ground potential. The load transistor 26 causes a constant current to flow from the output line 251 to the ground according to the voltage applied to the control terminal.

  The vertical scanning unit 27 sequentially selects one of the plurality of row selection lines 250 by time division and applies a predetermined voltage to turn on the row selection transistor 22 connected to the selected line 250. On the other hand, the horizontal scanning unit 28 sequentially selects one of the plurality of column selection transistors 24 by time division and performs on control by applying a predetermined voltage.

  Thereby, one of the plurality of pixel acquisition units 20 is connected to the output line 251 through the row selection transistor 22 in the on state and the column selection transistor 24 in the on state so as to be conductive. The pixel signal of the pixel acquisition unit 20 is output to the output terminal P of the amplifier 29 via the output line 251. That is, in the readout circuit, the pixel acquisition unit 20 is provided corresponding to each pixel, and sequentially outputs pixel signals of the pixel acquisition unit 20 corresponding to the selected row and column by time division.

  As described above, the pixel acquisition unit 20 outputs the pixel data of the two sensor elements 4 and 5 by time division. For this reason, the sensor substrate 1 is provided with a selection circuit for selecting a reading target of pixel data by the reading circuit from the sensor elements 4 and 5 connected via the common bump 3. FIG. 7 is a circuit diagram illustrating an example of the selection circuit and the pixel acquisition unit 20.

  The selection circuit 6 includes first and second diodes 61 and 62 connected in parallel with the first and second sensor elements 4 and 5, respectively, so that the polar directions are opposite to each other. The first and second sensor elements 4 and 5 are connected in series with each other, and are connected to the pixel acquisition unit 20 via a common bump 3.

  More specifically, the first sensor element 4 has one electrode connected to one end of the bump 3 and the other electrode connected to one of the electrodes of the second sensor element 5. The second sensor element 5 has the other electrode connected to the common electrode Q. The first and second diodes 61 and 62 have anode electrodes connected to each other and have opposite polarities. A control voltage Vc for determining a pixel data read target is applied to the common electrode Q from the first and second sensor elements 4 and 5. The common electrode Q may be an external terminal.

  The pixel acquisition unit 20 includes a drive transistor 201, a reset transistor 202, a storage capacitor 203, an operational amplifier 204, a voltage source 205, a pair of sampling transistors 206 and 207, and a holding capacitor 208. The drive transistor 201 has a pair of terminals connected to the other end of the bump 3 and the inverting input terminal (−) of the operational amplifier 204. The drive transistor 201 is on / off controlled by a drive signal INT input to a control terminal.

  The storage capacitor 203, the operational amplifier 204, and the voltage source 205 constitute an integration circuit. The storage capacitor 203 has one terminal connected to the inverting input terminal (−) of the operational amplifier 204 and the other terminal connected to the output terminal of the operational amplifier 204. The non-inverting input terminal (+) of the operational amplifier 204 is supplied with the reference voltage Vref from the voltage source 205. The pair of terminals of the reset transistor 202 are connected to the inverting input terminal (−) and the output terminal of the operational amplifier 204, respectively. The reset transistor 202 is ON / OFF controlled by a reset signal RST input to the control terminal.

  The output terminal of the operational amplifier 204 is connected to one terminal of the pair of sampling transistors 206 and 207. One terminal of the sampling transistor 207 is connected to each other. The pair of sampling transistors 206 and 207 are controlled so that both are turned on or both are turned off by the sample hold signals SH and SHB inputted to the respective control terminals. The holding capacitor 208 has one end connected to the other terminal of the pair of sampling transistors 206 and 207 and the gate electrode of the output transistor 21 described above, and the other end grounded.

  According to the configuration described above, when the drive signal INT is input to the control terminal of the drive transistor 201, the drive transistor 201 is turned on and becomes conductive. At this time, since the potential of the inverting input terminal (−) of the operational amplifier 204 is controlled to be the reference potential Vref given to the non-inverting input terminal (+), the potential of the bump 3 also becomes the reference potential Vref.

  Here, when the potential Vc of the common electrode Q is higher than the reference potential Vref, the first and second diodes 61 and 62 are turned on and off, respectively, so that the terminals of the first sensor element 4 are short-circuited. A bias voltage Vc−Vref is applied to the two-sensor element 5. For this reason, only pixel data of the second sensor element 5 is output to the pixel acquisition unit 20.

  On the other hand, when the potential Vc of the common electrode Q is lower than the reference potential Vref, the first and second diodes 61 and 62 are in an off state and an on state, respectively, so that the terminals of the second sensor element 5 are short-circuited. A bias voltage Vref−Vc is applied to the sensor element 4. Therefore, only the pixel data of the first sensor element 4 is output to the pixel acquisition unit 20.

  In this way, by controlling so that the potential Vc of the common electrode Q is higher than the reference potential Vref or lower than the reference potential Vref, the first sensor element 4 or the second sensor element 5 is controlled. Pixel data is selectively output. The output pixel data is stored in the storage capacitor 203 as a charge amount. Since the storage capacitor 203 is short-circuited at both ends when the reset signal RST is input to the control terminal of the reset transistor 202, the charge amount becomes zero.

  The pixel data stored in the storage capacitor 203 is transferred to the holding capacitor 208 and held when the sample hold signal SH is input to the control terminal of the sampling transistor 207. The pixel data held in the holding capacitor 208 is output to the output terminal P as a pixel signal via the output transistor 21 when the image acquisition unit 20 is selected by the vertical scanning unit 27 and the horizontal scanning unit 28 described above. Is done. FIG. 8 is a time chart showing the operation of the pixel acquisition unit at this time.

  The control voltage Vc is controlled to be higher than the reference voltage Vref in the period T1 and lower than the reference voltage Vref in the period T2. This control is performed by, for example, an external oscillation circuit.

  In each of the periods T1 and T2, when the drive signal INT and the reset signal RST are input, the drive transistor 201 becomes conductive and the charge amount of the storage capacitor 203 becomes zero. After the reset is released, the storage capacitor 203 stores, as pixel data, charges by the second sensor element 5 in the period T1, and charges by the first sensor element 4 in the period T2. Here, the input times ts1 and ts2 of the drive signal INT are integration times of the integration circuit.

  After each of the periods T1 and T2, the sample and hold signal SH is input, whereby the pixel data stored in the storage capacitor 203 is transferred to the storage capacitor 208 and stored. Note that the pixel data of the second sensor element 5 held in the holding capacitor 208 is output as a pixel signal via the output transistor 21 during the integration time ts2 of the period T2. As described above, the first and second sensor elements 4 and 5 alternately output pixel data by time division in accordance with the drive signal INT.

  The first and second sensor elements 4 and 5 and the first and second diodes 61 and 62 are easily formed from the stacked body 10 illustrated in FIG. The stacked body 10 includes a common electrode layer 70, a pixel separation layer 71, a lower electrode layer 72, a first Schottky junction layer 73, a first intermediate electrode layer 74, an absorption layer 75, a second intermediate electrode layer 76, and a second Schottky. The bonding layer 77 and the upper electrode layer 78 are formed by being stacked in this order.

The structure of each layer 70 to 78 will be described. The common electrode layer 70 is formed of a GaAs semiconductor having an n-type impurity concentration of 1.0 × 10 ¹⁸ (cm ⁻³ ). The pixel isolation layer 71 is formed of a GaAs semiconductor having a thickness of about 100 (nm) and an n-type impurity concentration of 5.1 × 10 ¹⁶ (cm ⁻³ ). The lower electrode layer 72 is formed of a GaAs semiconductor having an n-type impurity concentration of 1.0 × 10 ¹⁸ (cm ⁻³ ).

The first and second Schottky junction layers 73 and 77 are each formed of a GaAs semiconductor having a thickness of about 100 (nm) and an n-type impurity concentration of 5.1 × 10 ¹⁶ (cm ⁻³ ). Has been. The first and second intermediate electrode layers 74 and 76 are each formed of a GaAs semiconductor having a thickness of about 400 (nm) and an n-type impurity concentration of 1.0 × 10 ¹⁸ (cm ⁻³ ). ing. The upper electrode layer 78 is formed of a GaAs semiconductor having an n-type impurity concentration of 1.0 × 10 ¹⁸ (cm ⁻³ ). For example, the absorption layer 75 is formed by alternately laminating a plurality of barrier layers formed of an AlGaAs semiconductor and a plurality of well layers formed of a GaAs semiconductor to which an n-type impurity is added. In addition, the sensor element 9 in the comparative example described above is formed by a stacked body of the absorption layer 75 and the intermediate electrode layers 74 and 76 described above.

  Each of the layers 70 to 78 is formed by, for example, an epitaxial growth method, a plasma CVD (Chemical Vapor Deposition) method, a thin film forming technique such as sputtering and vapor deposition, printing, plating, or a combination thereof, but the forming method is not limited. The stacked body 10 is etched using, for example, a dry etching technique such as ion milling, and further thin film forming processing is performed, whereby the sensor elements 4 and 5 and the selection circuit 6 are obtained.

  FIG. 10 is a cross-sectional view showing an example of a laminated structure of the sensor elements 4 and 5 and the selection circuit 6. The layers 70a to 78a and 70b to 78b included in the two laminates illustrated in FIG. 10 are obtained from the layers 70 to 78 described above, respectively.

  The second sensor element 5 is formed of first and second intermediate electrode layers 74a and 76a and an absorption layer 75a, and the first sensor element 4 includes first and second intermediate electrode layers 74b and 76b and an absorption layer 75b. It is formed by. The common electrode P is formed by the common electrode layer 70a. When infrared rays are incident, electrons are excited from the ground level to the excited level in the absorption layers 75a and 75b by light absorption in the quantum well. Then, when a bias voltage is applied between the first and second intermediate electrode layers 74a, 76a, 74b, and 76b, electrons are taken out of the quantum well, and a photocurrent that becomes pixel data is generated. The pixel separation layers 71a and 71b electrically separate the common electrode layers 70a and 70b from the sensor elements 5 and 4, respectively.

  A first ohmic electrode 80 is formed on the exposed surface of one end of the common electrode layer 70a. The first ohmic electrode 80 is connected to the first Schottky electrode 82 formed on the exposed surface at one end of the second Schottky junction layer 77a through the wiring 81 extending in the stacking direction. The first Schottky electrode 82 and the second Schottky junction layer 77a function as the second diode 62 by forming a Schottky junction.

  A second ohmic electrode 83 is formed on the upper surface of one end of the upper electrode layer 78a. The second ohmic electrode 83 is connected to a third ohmic electrode 85 formed on the exposed surface at one end of the lower electrode layer 72b via a wiring 84 extending in the stacking direction. With this configuration, the first and second sensor elements 4 and 5 are connected in series with each other.

  Bumps 3 are formed on the upper surface of the other upper electrode layer 78b. Further, a fourth ohmic electrode 86 is formed on the upper surface of one end of the upper electrode layer 78b. The fourth ohmic electrode 86 is connected to a second Schottky electrode 88 formed on the exposed surface of one end of the first Schottky junction layer 73b through a wiring 87 extending in the stacking direction. The second Schottky electrode 88 and the first Schottky junction layer 73b function as the first diode 61 by forming a Schottky junction.

  Thus, by forming the first and second diodes 61 and 62 so as to be connected in parallel with the sensor elements 4 and 5, when a forward bias voltage is applied to each of the diodes 61 and 62, the sensor element It is possible to short-circuit between the terminals 4 and 5. In addition, the 1st and 2nd diodes 61 and 62 are not limited to this, You may be comprised by another form.

  As described above, in the infrared imaging device according to the present embodiment, a plurality of sensor elements 4 and 5 formed on the sensor substrate are connected to the readout circuit via the common bump 3 two by two. . For this reason, the infrared imaging device according to the present embodiment can increase the sensor elements 4 and 5 without reducing the interval between the bumps 3 even if the surface area of the device is constant.

  The selection circuit 6 selects a pixel data read target by the reading circuit from the sensor elements 4 and 5 connected via the common bump 3. Thereby, each pixel data of the two sensor elements 4 and 5 is selectively read out through the single bump 3. Therefore, the infrared imaging device according to the present embodiment can effectively increase the resolution.

  In the above-described embodiment, each bump 3 is shared by the two sensor elements 4 and 5, but is not limited to this. For example, three sensor elements are individually connected to a switch element such as a transistor, and pixel data of each sensor element is selectively output via a common bump 3 by performing on / off control of the switch element. May be.

  Although the contents of the present invention have been specifically described above with reference to the preferred embodiments, it is obvious that those skilled in the art can take various modifications based on the basic technical idea and teachings of the present invention. It is.

DESCRIPTION OF SYMBOLS 1 Sensor board 2 Circuit board 20 Pixel acquisition part 3 Bump 4, 5, 9 Sensor element 6 Selection circuit 61, 62 Diode

Claims (2)

A sensor substrate on which a plurality of sensor elements are arranged;
A circuit board including a readout circuit for reading out pixel data from the plurality of sensor elements;
A plurality of bumps provided between the sensor substrate and the circuit substrate;
The plurality of sensor elements are connected in series two by two,
The two sensor elements connected in series are connected to the readout circuit via a common bump among the plurality of bumps,
The sensor substrate is provided with a selection circuit for selecting a readout target of the pixel data by the readout circuit from the two sensor elements ,
2. The imaging apparatus according to claim 1, wherein the selection circuit includes two diodes connected in parallel to the two sensor elements so that polar directions are opposite to each other . The imaging apparatus according to claim 1, wherein the two sensor elements are adjacent to each other.

Images