JP2009290171A - Solid-state imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging device which can prevent a leakage current from a signal line even when the signal line is electrostatically protected. <P>SOLUTION: In a first electrostatic protection circuit 11 for electrostatically protecting scan lines 3a in a solid-state imaging device 100, first high-potential side protection diodes 91a and first low-potential side protection diodes 91b in a mutually reverse-biased state are connected between a first high-potential line 71a and scan lines 3a and between a first low-potential line 71b and the scan lines 3a. In a second electrostatic protection circuit 12 for electrostaically protecting data lines 6a, second high-potential side protection diodes 92a and second low-potential side protection diodes 92b in a mutually reverse-biased state are connected between a second high-potential line 72a and the data lines 6a and between a second low-potential line 72b and the data lines 6a. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device that converts incident light into an electrical signal.

In medical image diagnosis, non-destructive inspection, and the like, imaging is performed using radiation such as X-rays. However, since it is difficult to realize a reduction optical system when imaging radiation, imaging at an equal magnification is required. Accordingly, since a large area imaging surface is required for medical image diagnosis, non-destructive inspection, etc., a solid-state imaging device in which various thin films are deposited on a substrate such as glass and a plurality of pixels are arranged in a matrix is used. It is done. In addition, when a two-dimensional image sensor is configured by a solid-state imaging device, an imaging surface having a large area is required. Therefore, various thin films are deposited on a substrate such as glass to form a plurality of pixels in a matrix.

Specifically, a plurality of scanning lines extending in a predetermined direction and a plurality of data lines extending in a direction intersecting with these scanning lines are formed and scanned in the imaging region on the base substrate. A field effect transistor controlled by a scanning line and a photoelectric conversion element electrically connected to the data line through the field effect transistor are provided at a position corresponding to each intersection of the line and the data line. A plurality of pixels are formed. Therefore, if the field-effect transistor is turned on / off by a scanning signal supplied via the scanning line, a signal corresponding to the charge accumulated in each pixel can be detected via the data line (Patent Document 1). reference).
Japanese Patent No. 3144091

However, such a solid-state imaging device is easily affected by static electricity either in the middle of the manufacturing process or in the state of the finished product after manufacturing, but no proposal has been made for protection from such static electricity. .

Here, the inventor of the present application proposes electrostatic protection in a solid-state imaging device, and as such an electrostatic protection circuit, as shown in FIG. 12, an electrostatic protection circuit 1 used in a liquid crystal device.
4 can be applied. The electrostatic protection circuit 14 shown in FIG.
lator silicon) type two semiconductor elements with drain and gate connected
A bidirectional diode element 9 in which S-type diodes 91 and 92 are connected in parallel in the opposite direction is connected between a signal line 90 such as a scanning line or a data line and a common wiring 70. When attention is paid to one of the MIS diodes 91 and 92 in the bidirectional diode element 9, since there is a relationship as shown in FIG. 13 between the applied voltage and the flowing current value, a reverse bias is applied. If it is, the leakage current is small.

However, in the case of a solid-state imaging device, it is strongly required to have low speciality and low power consumption such as a high resolution of 12 bits or more, though the signal level is extremely small compared to a liquid crystal device. Therefore, there is a problem that the electrostatic protection circuit 14 shown in FIG. 12 cannot be used for the solid-state imaging device. That is, in the electrostatic protection circuit 14 shown in FIG. 12, when a potential is applied to the bidirectional diode element 9, the two MIS diodes 9
Since one of the forward biases 1 and 92 is applied with a forward bias, the leakage current caused by the forward bias cannot be ignored. Therefore, when the signal line 90 is a data line, a leakage current generated between the data line and the common wiring 70 deteriorates an electric signal generated in response to light reception in each pixel. In addition, when the signal line 90 is a scanning line, power consumption increases due to a leakage current generated between the scanning line and the common wiring 70, and battery life is shortened when battery driving is performed. Problems occur.

In view of the above problems, an object of the present invention is to provide a solid-state imaging device capable of suppressing a leakage current from a signal line even when electrostatic protection of the signal line is performed.

In order to solve the above problems, in the present invention, a plurality of scanning lines extending in a predetermined direction and a plurality of scanning lines extending in a direction intersecting with the plurality of scanning lines in an imaging region on the substrate. A field effect type having a data line and a plurality of bias lines and controlled by the scanning line in each of a plurality of pixels arranged at positions corresponding to the intersections of the scanning line and the data line And a photoelectric conversion element including a first electrode electrically connected to the data line through the field effect transistor and a second electrode electrically connected to the bias line. In the solid-state imaging device, a first electrostatic protection circuit is formed on one signal line of the plurality of scanning lines and the plurality of data lines, and the first electrostatic protection circuit includes the first electrostatic protection circuit. High potential above the maximum potential applied to the signal line An applied first high potential line, a first low potential line to which a low potential lower than the lowest potential applied to the one signal line is applied, and the one signal line and the first high potential line. A first high-potential side protection diode electrically connected in a reverse-biased state between the first signal line and the first low-potential line and a first low-potential line electrically connected in a reverse-biased state. And a potential-side protection diode.

In the present invention, a first electrostatic protection circuit is formed on one of the scanning lines and the data lines, and the first electrostatic protection circuit includes a first high potential line and a first low potential line. And a first high-potential side protection diode in a reverse bias state between one signal line and the first high-potential line, and a first one in a reverse bias state between one signal line and the first low-potential line. A low-potential side protection diode is provided. Therefore, in the first electrostatic protection circuit, the first high potential side protection diode and the first
Since the low potential side protection diode is always in the reverse bias state, the leakage current from the signal line can be ignored. In addition, since one signal line is provided with the first high potential line and the first low potential line, it is possible to set a potential suitable for the potential of one signal line to the first high potential line and the first low potential line. it can. Therefore, when one of the signal lines is a data line, it can be detected with high resolution even when the level of the electric signal generated in response to light reception in each pixel is small. Further, when one of the signal lines is a scanning line, power consumption can be reduced.

In the present invention, it is preferable that a second electrostatic protection circuit is formed on the other signal line of the plurality of scanning lines and the plurality of data lines, and in this case, the second electrostatic protection circuit is formed. The circuit includes a second high potential line to which a high potential equal to or higher than the highest potential applied to the other signal line and a second potential to which a low potential equal to or lower than the lowest potential applied to the other signal line is applied. A low potential wire,
A second electrically connected in a reverse bias state between the other signal line and the second high potential line;
A configuration including a high potential side protection diode and a second low potential side protection diode electrically connected in a reverse bias state between the other signal line and the second low potential line is adopted. be able to. With this configuration, even when an electrostatic protection circuit is provided on the other signal line, the leakage current from the other signal line can be ignored.

In the present invention, a configuration in which different potentials are applied to the first high potential line, the first low potential line, the second low potential line, and the second high potential line can be employed. .

In the present invention, a second electrostatic protection circuit is formed on the other signal line of the plurality of scanning lines and the plurality of data lines, and the second electrostatic protection circuit A second high potential line to which a high potential equal to or higher than the highest potential applied to the signal line is applied, and a second low potential line to which a low potential equal to or lower than the lowest potential applied to the other signal line is applied. You may employ | adopt the structure provided with the protective diode electrically connected in one reverse wiring state between one wiring and said one wiring and said other signal line. That is, in the first electrostatic protection circuit for one of the scanning lines and the data lines, electrostatic protection is performed on both the high potential side and the low potential side, and the second electrostatic protection circuit for the other signal line. Then, only electrostatic protection of one of the high potential side and the low potential side is performed. Even in such a configuration, even when an electrostatic protection circuit is provided on the other signal line, the leakage current from the other signal line can be ignored.

In this case, a configuration in which different potentials are applied to the first high potential line, the first low potential line, and the one wiring line can be employed.

In the present invention, in the first electrostatic protection circuit and the second electrostatic protection circuit, wirings of the first high potential line and the second high potential line, and the first low potential line and the second It is preferable that at least one of the low-potential lines is electrically connected to be applied with the same potential.

For example, in the first electrostatic protection circuit and the second electrostatic protection circuit, the first high potential line and the second high potential line, or the first low potential line and the second low potential line are electrically connected. It is possible to adopt a configuration in which the same potential is applied in a connected manner. In the first electrostatic protection circuit and the second electrostatic protection circuit, the first high potential line and the second high potential line are electrically connected to each other, and the same potential is applied. A configuration in which a low potential line and the second low potential line are electrically connected and the same potential is applied may be adopted. In any of these cases, the first high potential line, the first low potential line, the second low potential line, and the second high potential line are each independently formed around the imaging region. Thus, the space for forming the high potential line and the low potential line can be narrowed. In addition, since the number of necessary potentials can be reduced, the power supply circuit can be simplified.

In the present invention, in the electrostatic protection circuit configured for the scanning line, the field effect transistor is turned off to a potential applied to the high potential line or a potential applied to the low potential line. It is preferable to use a gate-off voltage for turning on, a gate-on voltage for turning on the field effect transistor, or a bias voltage applied to the bias line. With this configuration, in order to use the potential supplied to the pixel,
The power supply circuit can be simplified.

In the present invention, in the electrostatic protection circuit configured for the data line, the bias applied to the bias line is applied to the potential applied to the high potential line or the potential applied to the low potential line. Preferably a voltage is used. With such a configuration, since the potential supplied to the pixel is used, the power supply circuit can be simplified.

In the present invention, each of the protection diodes is an MIS type diode in which a drain and a gate are connected to each other in an MIS type semiconductor element. In the electrostatic protection circuit configured for the data line, one protection diode is provided. The sum of the channel widths of the protective diodes electrically connected to the data lines is preferably 1/10 times or less of the sum of the channel widths of the field effect transistors electrically connected to one data line. . With this configuration, it is possible to prevent data deterioration due to leakage from the data line through the protection diode.

Embodiments of the present invention will be described below. In the drawings to be referred to in the following description, the scales of the layers and the members are different from each other in order to make the layers and the members large enough to be recognized on the drawings. In the case of a field effect transistor, the source and drain are interchanged depending on the conductivity type and the direction of current flow. In the present invention, for convenience, the side to which the photoelectric conversion element is connected is defined as the drain, and the signal line (data The side to which the line is connected is the source.

In the present invention, the first electrostatic protection circuit is formed on one of the scanning line and the data line. Of the first to fourth embodiments described below, the first to third embodiments employ a configuration in which a second electrostatic protection circuit is formed on the other signal line of the scanning lines and the data lines. Yes. Here, the first electrostatic circuit and the second electrostatic protection circuit are not limited to the electrostatic protection of the scanning line or the data line, but in the following description, electrostatic protection for the scanning line is performed. The circuit is the first electrostatic protection circuit, and the electrostatic protection circuit for the data line is the second.
This will be described as an electrostatic protection circuit. However, in the present invention, the electrostatic protection circuit for the data line is the first.
An electrostatic protection circuit may be used, and the electrostatic protection circuit for the scanning line may be configured as a second electrostatic protection circuit.

[Embodiment 1]
(overall structure)
FIG. 1 is a block diagram showing an electrical configuration of the solid-state imaging device according to Embodiment 1 of the present invention. 2A and 2B are a circuit diagram illustrating each pixel configuration of the solid-state imaging device according to Embodiment 1 of the present invention, and a circuit diagram illustrating another pixel configuration. FIG. 3 is an explanatory diagram schematically showing the appearance of the solid-state imaging device according to Embodiment 1 of the present invention.

The solid-state imaging device 100 shown in FIG. 1 has a plurality of scanning lines 3a extending in the X direction and a plurality of data lines 6a extending in the Y direction intersecting the X direction. A pixel 100a is arranged at each position corresponding to the intersection of the scanning line 3a and the data line 6a.
An imaging region 100c is configured by regions in which 00a is arranged in a matrix. In each of the plurality of pixels 100a, a photoelectric conversion element 80 that generates electric charge according to the amount of incident light and a field effect transistor 30 electrically connected to the photoelectric conversion element 80 are formed. The photoelectric conversion element 80 is composed of a PIN photodiode.

The scanning line 3 a is electrically connected to the gate of the field effect transistor 30, the data line 6 a is electrically connected to the source of the field effect transistor 30, and the drain of the field effect transistor 30 is electrically connected to the photoelectric conversion element 80. It is connected to the. In this embodiment, the bias line 5a extends so as to be parallel to the data line 6a, and the bias line 5a is electrically connected to the photoelectric conversion element 80. A constant potential is applied to the bias line 5 a, and the photoelectric conversion element 80.
Apply reverse bias to. The bias line 5a may be configured to extend in parallel with the scanning line 3a. In applying the constant potential to the bias line 5a, the present embodiment employs a configuration in which a plurality of bias lines 5a are electrically connected to one main line.

The plurality of scanning lines 3a are connected to the scanning line driving circuit 110, and the field effect transistor 30 of each pixel 100a is sequentially turned on and off by the scanning signal (gate pulse) output from the scanning line driving circuit 110. The plurality of data lines 6a are connected to the readout circuit 120, and in conjunction with the on / off operation of the field effect transistor 30, an electrical signal corresponding to the amount of incident light at each pixel 100a is sequentially transmitted via the data line 6a. It is output to the reading circuit 120. The readout circuit 120 includes a so-called charge sensing amplifier that includes an operational amplifier and a capacitor.

As shown in FIG. 2A, in this embodiment, the drain of the field effect transistor 30 is electrically connected to the first electrode 81a (cathode) of the photoelectric conversion element 80, and the bias line 5a is connected to the photoelectric conversion element 80. The second electrode 85a (anode) is electrically connected. As shown in FIG. 2B, the first electrode 81a of the photoelectric conversion element 80 that is electrically connected to the drain of the field effect transistor 30 may be used as an anode. In this case, the bias line 5a The second electrode 85a of the photoelectric conversion element 80 that is electrically connected to the cathode serves as a cathode.

Each of the plurality of pixels 100a includes a storage capacitor 80a, and the storage capacitor 8
One electrode of 0a is electrically connected to the drain of the field effect transistor 30 similarly to the first electrode 81a of the photoelectric conversion element 80, and the other electrode of the storage capacitor 80a is connected to the photoelectric conversion element 80.
The second electrode 85a is electrically connected to the bias line 5a. For this reason, the storage capacitor 80 a is electrically connected in parallel to the photoelectric conversion element 80. In addition to the configuration formed by a depletion layer or the like generated in the photoelectric conversion element 80 when a reverse bias is applied to the photoelectric conversion element 80, the storage capacitor 80a, and the capacitance component formed by the depletion layer,
Separately, the photoelectric conversion element 80 is also configured by forming a storage capacitor electrically connected in parallel to the pixel 100a. In any case, the storage capacitor 80a is composed of the photoelectric conversion element 8.
The electric field generated at 0 and stored in the storage capacitor 80a corresponds to the amount of light received by the pixel 100a.

In the solid-state imaging device 100, the scanning line 3a and the data line 6 described with reference to FIG.
a, bias line 5a, pixel 100a (photoelectric conversion element 80, field effect transistor 30,
The storage capacitor 90) is formed on the base substrate 10 shown in FIG. Here, the base substrate 10
The substantially central region is an imaging region 100c in which a plurality of the pixels 100a are arranged in a matrix.
Used as In the example shown in FIG. 3, the scanning line driving circuit 110 and the reading circuit 12
0 is formed separately from the base substrate 10. For this reason, in the base substrate 10,
Flexible substrates 150 and 160 on which driving ICs (not shown in FIG. 3) are mounted are connected to a peripheral region surrounding the imaging region 100c on the outside.

(Pixel configuration)
4A and 4B are respectively a plan view of a plurality of adjacent pixels 100a and a cross-sectional view of one of them in the solid-state imaging device 100 according to Embodiment 1 of the present invention. (B)
Corresponds to a cross-sectional view when the solid-state imaging device 100 is cut at a position corresponding to the line A1-A1 ′ of FIG. In FIG. 4A, the scanning line 3a and the thin film formed simultaneously therewith are indicated by a thin solid line, the data line 6a and the thin film formed simultaneously therewith are indicated by a thin one-dot chain line, and the semiconductor film of the field effect transistor 30 The (active layer) is indicated by a thin and short dotted line, and the bias line 5a is indicated by a two-dot chain line. The first electrode 81a of the photoelectric conversion element 80 is indicated by a thin and long dotted line, the semiconductor film of the photoelectric conversion element 80 is indicated by a thick solid line, and the second electrode 85a of the photoelectric conversion element 80 is indicated by a thick and long dotted line. .

As shown in FIG. 4A, on the base substrate 10, the scanning lines 3a and the data lines 6a extend in a direction intersecting each other, corresponding to the intersection of the scanning lines 3a and the data lines 6a. A pixel 100a is formed at each position. A bias line 5a extends so as to be parallel to the data line 6a. In this embodiment, the data line 6a extends in the Y direction along the boundary region at a position overlapping the boundary region of the adjacent pixel 100a in the X direction, and the bias line 5a is connected to the pixel 100.
It extends in the Y direction through the center in the X direction of a. The scanning line 3a extends in the X direction along the boundary region between the pixels 100a adjacent in the Y direction.

In the pixel 100a, a photoelectric conversion element 80 formed of a PIN photodiode and a field effect transistor 30 electrically connected to the photoelectric conversion element 80 are formed. A field effect transistor is formed by a part of the scanning line 3a. 30 gate electrodes 3b are formed, and a source electrode 6b of the field effect transistor 30 is formed by a part of the data line 6a. In the pixel configuration of this embodiment, as illustrated in FIG. 2A, the drain electrode 6d of the field effect transistor 30 is electrically connected to the first electrode 81a (cathode) of the photoelectric conversion element 80, and the bias line 5a. Is electrically connected to the second electrode 85a (anode) of the photoelectric conversion element 80.

A cross-sectional configuration and the like of the pixel 100a will be described with reference to FIGS. FIG.
), In the solid-state imaging device 100 shown in (b), the base substrate 10 is made of a quartz substrate, a heat-resistant glass substrate, or the like. Of the surfaces 10x and 10y on both sides, the upper surface 10x has a field effect transistor. 30 is formed. The field effect transistor 30 includes the scanning line 3a.
Part of the gate electrode 3b, the gate insulating film 21, the semiconductor film 1a made of an amorphous silicon film constituting the active layer of the field effect transistor 30, and the contact layer made of an amorphous silicon film doped with high-concentration N-type impurities 4a and 4b have a bottom gate structure laminated in this order. Of the semiconductor film 1a, the data line 6a overlaps with the source electrode 6b via the contact layer 4a at the end on the source side, and the drain electrode 6d passes through the contact layer 4b at the end on the drain side. overlapping. The data line 6a and the drain electrode 6d are made of a conductive film formed simultaneously. For example, the scanning line 3a has a thickness of 50 nm.
A laminated film of about a molybdenum film and an aluminum film with a thickness of about 250 nm. The semiconductor film 1a is an amorphous silicon film having a thickness of about 150 nm, for example, and the gate insulating film 21 is a silicon nitride film having a thickness of about 400 nm, for example. Contact layer 4a, 4b
Is a high-concentration N-type amorphous silicon film having a thickness of about 50 nm, for example, and the data line 6a includes, for example, a molybdenum film having a thickness of about 50 nm, an aluminum film having a thickness of about 250 nm, and a thickness of It consists of a laminated film of molybdenum films of about 50 nm.

A lower insulating film 22 made of a silicon nitride film having a thickness of about 400 nm is formed on the surface side of the data line 6a and the drain electrode 6d. In the upper layer of the lower insulating film 22,
A first electrode 81a of the photoelectric conversion element 80 is formed, and the first electrode 81a is in contact with and electrically connected to the upper surface of the drain electrode 6d inside the contact hole 22a formed in the lower insulating film 22. Yes. In this way, the first electrode 81a is electrically connected to the drain of the field effect transistor 30 on the lower layer side than the first electrode 81a. The first electrode 81a is made of, for example, an aluminum film having a thickness of about 100 nm.

Over the first electrode 81a, a high-concentration N-type semiconductor film 82a made of an amorphous silicon film doped with a high-concentration N-type impurity, an I-type semiconductor film 83a (intrinsic semiconductor film) made of an intrinsic amorphous silicon film, A high-concentration P-type semiconductor film 84a made of an amorphous silicon film doped with high-concentration P-type impurities is laminated, and a second electrode 85a is laminated on the upper layer of the high-concentration P-type semiconductor film 84a. The first electrode 81a, the high concentration N-type semiconductor film 82a,
The photoelectric conversion element 80 is configured as a PIN photodiode by the I-type semiconductor film 83a, the high-concentration P-type semiconductor film 84a, and the second electrode 85a. The second electrode 85a is made of, for example, an ITO film having a thickness of about 90 nm, and the photoelectric conversion element 80 is formed of the translucent second electrode 8.
Light incident from the side of 5a is detected.

In this embodiment, a plurality of thin films (first electrode 81a, high-concentration N) constituting the photoelectric conversion element 80 are used for the purpose of avoiding a decrease in reliability and yield due to a decrease in withstand voltage at the level difference of the photoelectric conversion element 80. Type semiconductor film 82a, I type semiconductor film 83a, high concentration P type semiconductor film 84a, and second
Of the electrodes 85a), only the first electrode 81a is formed in a region overlapping with the contact hole 22a, but the entire photoelectric conversion element 80 (first electrode 81a, high-concentration N-type semiconductor film 82a, I
All of the type semiconductor film 83a, the high-concentration P-type semiconductor film 84a, and the second electrode 85a) may be formed in a region overlapping the contact hole 22a.

On the upper layer side of the photoelectric conversion element 80, an upper insulating film 23 made of an inorganic insulating film such as a silicon nitride film having a thickness of about 400 nm is formed on the entire surface of the imaging region 100c. A bias line 5a is formed in the upper layer. Here, the upper insulating film 23
The contact hole 23a is formed at a position overlapping the second electrode 85a. For this reason, the bias line 5a overlaps the second electrode 85a inside the contact hole 23a, and the second
The electrode 85a is electrically connected. The bias line 5a is made of, for example, a laminated film of a molybdenum film having a thickness of about 50 nm, an aluminum film having a thickness of about 250 nm, and a molybdenum film having a thickness of about 50 nm.

A surface protective layer 24 made of a silicon nitride film or the like having a thickness of about 400 nm is formed on the upper side of the bias line 5a. When the solid-state imaging device 100 is used for medical image diagnosis, non-destructive inspection, or the like using radiation such as X-rays, a visible light beam is emitted by the surface protective layer 24 itself or by a phosphor or the like on the surface protective layer 24. A scintillator that converts to When imaging other than X-rays is performed, if there is a scintillator corresponding to each wavelength of light, light of that wavelength can also be imaged.
It is not limited to a line imaging device.

(Operation)
FIG. 5 is an explanatory diagram showing signal waveforms during one scanning period in the imaging operation of the solid-state imaging device according to Embodiment 1 of the present invention. 1 and 5, the solid-state imaging device 1 of the present embodiment
In 00, a bias voltage VB having a potential lower than that of the data line 6a is applied to the bias line 5a, and the photoelectric conversion element 80 is biased in the reverse direction. As a result, charges are stored. Then, after the photoelectric conversion elements 80 of the respective pixels 100a arranged in the imaging region 100c are uniformly reverse-biased, the imaging data is irradiated to the imaging region 100c as light. As a result, a charge corresponding to the amount of light is generated inside the photoelectric conversion element 80, and the amount of charge in the photoelectric conversion element 80 changes. next,
The potentials of the plurality of scanning lines 3a are sequentially switched from the gate-off voltage Vgl to the gate-on voltage Vgh, the field effect transistors 30 are sequentially turned on, and the charge of the photoelectric conversion element 80 is transferred to the data line 6a.
To release. Here, the time for reading one line of data in the direction of the scanning line 3a is defined as one horizontal scanning period shown in FIG. At this time, the potential change of the data line 6a is read by the reading circuit 120 electrically connected to the data line 6a.

In such an operation, before the field effect transistor 30 is turned on, the data line 6
The preset potential Vp is applied to a to reset the data line 6a, and the read circuit 120 reads the amount of change from the preset potential Vp. Such reading is preferably performed while the field effect transistor 30 is turned on. This is because a feedthrough voltage V2 is generated when turning off, which causes a reading error. It is not always necessary to use the preset operation by applying the preset potential Vp. However, if the preset operation is not performed, the imaging data in the direction of the data line 6a is integrated into the data line 6a, and accurate reading is easy. It becomes difficult to do.

(Configuration of first electrostatic protection circuit)
6 (a), 6 (b), and 6 (c) each show a solid-state imaging device 100 according to Embodiment 1 of the present invention.
FIG. 3 is a circuit diagram showing the configuration of the first electrostatic protection circuit provided for the scanning line 3a, the plan view showing the planar configuration of the first electrostatic protection circuit, and the cross section showing the sectional configuration of the first electrostatic protection circuit FIG. 6C corresponds to a cross-sectional view taken along the line B-B1 ′ of FIG.

In the solid-state imaging device 100 according to this embodiment, since the base substrate 10 is an insulating substrate, the influence of static electricity is exerted in the middle of the manufacturing process of the solid-state imaging device 100 or in the state of the finished product after the manufacturing is completed. Easy to receive. Therefore, in the present embodiment, the first electrostatic protection circuit 11 described below with reference to FIGS. 1 and 6 is configured for the scanning line 3a.

As shown in FIG. 1 and FIG. 6A, in the first electrostatic protection circuit 11 for the scanning line 3a,
First, on the base substrate 10, a first high potential line 71a to which a high potential equal to or higher than the maximum potential applied to the scanning line 3a is applied so as to surround the imaging region 100c, and a minimum potential applied to the scanning line 3a. A first low potential line 71b to which the following low potential is applied is formed. The first high potential line 71a and the first low potential line 71b are each independently formed as a common line surrounding the imaging region 100c, and different potentials are applied thereto.

In the first electrostatic protection circuit 11, the scanning line 3 a is located outside the imaging region 100 c in the base substrate 10 at a position corresponding to each intersection of the plurality of scanning lines 3 a and the first high potential lines 71 a.
The scanning line 3a at a position corresponding to the intersection of the first high potential side protection diode 91a electrically connected to the first high potential line 71a in a reverse bias state and the scanning line 3a and the first low potential line 71b.
And a first low-potential side protection diode 91b electrically connected to the first low-potential line 71b in a reverse bias state.

The first high potential line 71a, the first low potential line 71b, and the first high potential side protection diode 91a.
, And the first low-potential side protection diode 91b are formed simultaneously with various wirings and semiconductor elements formed in the imaging region 100c, as described below with reference to FIGS. 6B and 6C. Become.

First, in each of the first high potential line 71a and the first low potential line 71b, the portion extending in the Y direction intersecting the scanning line 3a is formed simultaneously with the data line 6a described with reference to FIG. The portion extending in the X direction parallel to the scanning line 3a is made of the conductive film formed simultaneously with the scanning line 3a described with reference to FIG. 4 and intersects the scanning line 3a. The portion extending in the direction to be connected and the portion extending in parallel with the scanning line 3a are electrically connected via a contact hole formed in the insulating film.

The first high-potential side protection diode 91a is composed of a MIS type diode element in which a drain and a gate are connected in a MIS type semiconductor element having substantially the same configuration as the field effect transistor 30 described with reference to FIG. That is, the first high-potential side protection diode 91a is
Gate electrode 3f, gate insulating film 21, semiconductor film 1f made of amorphous silicon film, contact layers 4g, 4h made of amorphous silicon film doped with high-concentration N-type impurities
Has a bottom gate structure laminated in this order. Of the semiconductor film 1f, a part of the first high potential line 71a overlaps with an end part on the source side through a contact layer 4h, and a drain electrode is provided with an end part on the drain side through a contact layer 4g. 6h overlaps. A lower insulating film 22 is formed on the surface side of the first high potential line 71a and the drain electrode 6h, and the upper layer of the lower insulating film 22 is formed on the upper side of the photoelectric conversion element 80 described with reference to FIG. 1 electrode 81a
The relay electrode 81d is formed at the same time.

The relay electrode 81d is electrically connected to the drain electrode 6h via a contact hole 22f formed in the lower insulating film 22, and a contact hole 22e formed in the lower insulating film 22 and the gate insulating film 21. Is electrically connected to the scanning line 3a.
In the first high potential side protection diode 91a configured as described above, the source connected to the first high potential line 71a functions as a cathode, and the drain connected to the scanning line 3a functions as an anode.

Similar to the first high potential side protection diode 91a, the first low potential side protection diode 91b has a drain and a gate in the MIS type semiconductor element having substantially the same configuration as the field effect transistor 30 described with reference to FIG. It consists of a connected MIS type diode element. That is, the first low potential side protection diode 91b includes the gate electrode 3e, the gate insulating film 21, the semiconductor film 1e made of an amorphous silicon film, and the contact layers 4e and 4f made of an amorphous silicon film doped with a high concentration N-type impurity. The bottom gate structure is stacked in this order, and the first end of the semiconductor film 1e is connected to the first end via the contact layer 4e.
A part of the low potential line 71b is overlapped, and the source electrode 6g is overlapped with the end portion on the source side through the contact layer 4f. Further, the lower insulating film 22 is formed on the surface side of the first low potential line 71b and the source electrode 6g, and the photoelectric conversion element 80 described with reference to FIG. 4 is formed on the upper layer of the lower insulating film 22. A relay electrode 81c formed simultaneously with the first electrode 81a is formed.

The relay electrode 81c is electrically connected to the first low potential line 71b through a contact hole 22b formed in the lower insulating film 22, and is formed in the lower insulating film 22 and the gate insulating film 21. It is electrically connected to the gate electrode 3e through the contact hole 22c. Further, the relay electrode 81d is a contact hole 22d formed in the lower insulating film 22.
Is electrically connected to the source electrode 6g. In the first low potential side protection diode 91b configured as described above, the drain connected to the first low potential line 71b functions as an anode, and the source connected to the scanning line 3a functions as a cathode.

(Configuration of second electrostatic protection circuit)
FIGS. 7A, 7B, and 7C are circuit diagrams each showing a configuration of a second electrostatic protection circuit provided for the data line 6a in the solid-state imaging device 100 to which the present invention is applied. 7 is a plan view showing a planar configuration of the electrostatic protection circuit, and a sectional view showing a sectional configuration of the second electrostatic protection circuit; FIG.
FIG. 7C corresponds to a cross-sectional view taken along the line C-C1 ′ of FIG. In the solid-state imaging device 100 of this embodiment,
For the data line 6a, a second electrostatic protection circuit 12 described below with reference to FIGS. 1 and 7 is configured by using a configuration substantially similar to that of the scanning line 3a.

As shown in FIGS. 1 and 7A, in the second electrostatic protection circuit 12 for the data line 6a, first, the highest voltage applied to the data line 6a on the base substrate 10 so as to surround the imaging region 100c. A second high potential line 72a to which a high potential equal to or higher than the potential is applied and a second low potential line 72b to which a low potential lower than the lowest potential applied to the data line 6a is applied are formed. Such second
The high potential line 72a and the second low potential line 72b are each independently formed as a common line surrounding the imaging region 100c, and different potentials are applied thereto. In the present embodiment, the second low potential line 72b has a potential (bias voltage V
Apply the same potential as in B). Therefore, the plurality of bias lines 5a are all electrically connected to the second low potential line 72b, and the second low potential line 72b is connected to the plurality of bias lines 5a.
Functions as a main line for Here, since the bias line 5a and the second low potential line 72b are formed between different layers, a structure in which they are electrically connected via a contact hole formed in the insulating film is employed.

Further, in the second electrostatic protection circuit 12, the data line 6a and the second high potential line are disposed in the outer region of the imaging region 100c in the base substrate 10 at a position corresponding to the intersection of the data line 6a and the second high potential line 72a. The data line 6a and the second low potential line 72b at a position corresponding to the intersection of the data line 6a and the second low potential line 72b; And a second low potential side protection diode 92b electrically connected in a reverse bias state.

The second high potential line 72a, the second low potential line 72b, and the second high potential side protection diode 92a.
As shown in FIGS. 7B and 7C, the second low potential side protection diode 92b is formed simultaneously with various wirings and semiconductor elements formed in the imaging region 100c.

First, both the second high potential line 72a and the second low potential line 72b have the portion extending in the X direction intersecting the data line 6a at the same time as the scanning line 3a described with reference to FIG. A portion made of the conductive film formed and extending in the Y direction parallel to the data line 6a is made of a conductive film formed simultaneously with the data line 6a described with reference to FIG. The portion extending in the intersecting direction and the portion extending in parallel with the data line 6a are electrically connected via a contact hole formed in the insulating film.

The second high potential side protection diode 92a is composed of a MIS type diode element in which a drain and a gate are connected in a MIS type semiconductor element having substantially the same configuration as that of the field effect transistor 30 described with reference to FIG. That is, the second high potential side protection diode 92a is
Gate electrode 3g, gate insulating film 21, semiconductor film 1i made of amorphous silicon film, contact layers 4i, 4j made of amorphous silicon film doped with high-concentration N-type impurities
Are stacked in this order, and in the semiconductor film 1i, a source electrode 6j overlaps with an end on the source side via a contact layer 4i, and an end on the drain side has A part of the data line 6a overlaps with the contact layer 4i. A lower insulating film 22 is formed on the surface side of the source electrode 6j and the data line 6a, and the first layer of the photoelectric conversion element 80 described with reference to FIG. A relay electrode 81g formed simultaneously with the electrode 81a is formed.

The relay electrode 81g is electrically connected to the source electrode 6j through a contact hole 22j formed in the lower insulating film 22, and the lower insulating film 22 and the gate insulating film 2 are connected.
1 is electrically connected to the second high-potential line 72a through the contact hole 22i formed in FIG. In the second high potential side protection diode 92a configured as described above, the second high potential line 72a is used.
The source connected to this side functions as a cathode, and the drain connected to the data line 6a side functions as an anode.

Although the illustration of the cross section of the second low potential side protection diode 92b is omitted, like the second high potential side protection diode 92a, the MIS having substantially the same configuration as the field effect transistor 30 described with reference to FIG. MIS in which drain and gate are connected in a type semiconductor device
Type diode element. That is, the second low potential side protection diode 92b includes a gate electrode 3e, a gate insulating film 21, a semiconductor film 1j made of an amorphous silicon film, and a contact layer made of an amorphous silicon film doped with high-concentration N-type impurities in this order. The semiconductor film 1j has a stacked bottom gate structure, and the drain side end of the semiconductor film 1j overlaps the drain electrode 6k via a contact layer, and the source side end passes through a contact layer. Part of the data line 6a overlaps. Further, the drain electrode 6k and the data line 6a
A lower-layer insulating film 22 is formed on the surface side of the relay electrode, and a relay electrode formed simultaneously with the first electrode 81a of the photoelectric conversion element 80 described with reference to FIG. 81h is formed. Here, the relay electrode 81 h is electrically connected to the drain electrode 6 k through the contact hole 22 n formed in the lower layer side insulating film 22, and is formed in the lower layer side insulating film 22 and the gate insulating film 21. The gate electrode 3h and the second low potential line 72b are electrically connected via the contact holes 22p and 22r. Second configured in this way
In the low potential side protection diode 92b, the drain connected to the second low potential line 72b functions as an anode, and the source connected to the data line 6a functions as a cathode.

In the second electrostatic protection circuit 12 configured as described above, two protection diodes (a second high potential side protection diode 92a and a second low potential side protection diode 92b) are connected to one data line 6a. However, the sum W1 of the channel widths of the second high potential side protection diode 92a and the second low potential side protection diode 92b connected to one data line 6a is equal to each pixel connected to one data line 6a. The total channel width of the field effect transistor 30 of 100a is set smaller than W2. Therefore, even if the potential of the data line 6a leaks through the second high potential side protection diode 92a and the second low potential side protection diode 92b,
The effect of such a leak can be ignored. For the sum W1 of the channel widths of the second high potential side protection diode 92a and the second low potential side protection diode 92b, one data line 6
1 of the total channel width W2 of the field effect transistor 30 of each pixel 100a connected to a.
/ 10 times or less is preferable, and 1/100 times is more preferable. That is, if the channel width of the field effect transistor 30 of each pixel 100a is about 10 μm and the number N to be connected is 100, the channel width of the second high potential side protection diode 92a and the second low potential side protection diode 92b. Is W 1 or less, preferably 100 μm or less, and more preferably 10 μm or less. Even if the potential of the data line 6a leaks through the field effect transistor 30 of each pixel 100a, the influence of the leak can be ignored.

(Potential supplied to high potential line and low potential line)
1 and 5 again, in the first electrostatic protection circuit 11, the first high potential line 71a includes
A potential equal to or higher than the gate-on voltage Vgh for turning on the field effect transistor 30 is applied, and the first
It is necessary to apply a potential equal to or lower than the gate-off voltage Vgl for turning off the field effect transistor 30 to the low potential line 71b. Therefore, in this embodiment, the gate-on voltage Vgh is applied to the first high potential line 71a, and the gate-off voltage Vgl is applied to the first low potential line 71b.

In the second electrostatic protection circuit 12, a potential higher than the highest potential applied to the data line 6a is applied to the second high potential line 72a, and the data line 6a is applied to the second low potential line 72b. It is necessary to apply a potential lower than the lowest potential. Here, after the data line 6a is set to the preset potential Vp, it moves to the high potential side by the feedthrough potential V1. Such feedthrough voltage V1
Is a potential at which the data line 6a is swung when the gate voltage is set to the gate-on voltage Vgh. Here, the parasitic capacitance between the scanning line 3a of one pixel and the data line 6a (parasitic capacitance of the field effect transistor 3, the capacitance at the intersection of the scanning line 3a and the data line 6a, etc.) is Cp, and the data line capacitance is Cd. Then, the following formula (Cp / Cd) × (Vgh−Vgl)
become that way.

Here, the sum of the preset potential Vp and the feedthrough voltage V1 is the maximum value of the potential applied to the data line 6a. Generally, the feedthrough voltage V1 depends on the design, but 1V
It is as follows. Therefore, in this embodiment, a potential that is 1 V or more higher than the preset potential Vp is applied to the second high potential line 72a.

(Main effects of this form)
As described above, in the solid-state imaging device 100 of the present embodiment, the scanning line 3a and the data line 6
1a, a first electrostatic protection circuit 11 is formed on the scanning line 3a.
The first high potential line 71a and the first low potential line 71b are provided, and the scanning line 3a and the first low potential line 71b are provided.
A first high potential side protection diode 91a in a reverse bias state is provided between the high potential line 71a and a first low potential side protection diode 9 in a reverse bias state is provided between the scanning line 3a and the first low potential line 71b.
1b. For this reason, in the first electrostatic protection circuit 11, the first high-potential side protection diode 91a and the first low-potential side protection diode 91b are always in the reverse bias state. Even when 11 is provided, the leakage current from the scanning line 3a can be set to a very low level.

Further, since the first high potential line 71a and the first low potential line 71b are provided in the scanning line 3a, potentials suitable for the potential of the scanning line 3a are set in the first high potential line 71a and the first low potential line 71b. be able to. Therefore, in the current-voltage characteristic shown in FIG. 13, the reverse bias voltage applied to the first high potential side protection diode 91a and the first low potential side protection diode 91b is low, so that the first electrostatic protection circuit with respect to the scanning line 3a. Even when 11 is provided, the leakage current from the scanning line 3a is at a negligible level.

Therefore, according to this embodiment, the power consumption of the solid-state imaging device 100 can be reduced. For example, in the solid-state imaging device 100, a battery can be used as a drive source.

Further, in the solid-state imaging device 100 of the present embodiment, the second electrostatic protection circuit 12 is formed on the data line 6 a, and the second electrostatic protection circuit 12 also has the second high potential, like the first electrostatic protection circuit 11. A second low potential line 72b and a second high potential side protection diode 92a in a reverse bias state between the data line 6a and the second high potential line 72a, and the data line 6a and the second low potential line 72b. A second low potential side protection diode 92b in a reverse bias state is provided between the low potential line 72b. For this reason, in the second electrostatic protection circuit 12, as in the first electrostatic protection circuit 11, the second high potential side protection diode 92a and the second low potential side protection diode 92b are always in the reverse bias state. Even when the second electrostatic protection circuit 12 is provided for 6a, the leakage current from the data line 6a can be set to an extremely low level.

The data line 6a is provided with separate constant potential lines (second high potential line 72a and second low potential line 72b) separately from the first high potential line 71a and the first low potential line 71b for the scanning line 3a. Therefore, a potential suitable for the potential of the data line 6a is set to the second high potential line 72a and the second low potential line 72.
b can be set. Accordingly, in the current-voltage characteristics shown in FIG. 13, since the reverse bias voltage applied to the second high potential side protection diode 92a and the second low potential side protection diode 92b is low, the second electrostatic protection circuit is applied to the data line 6a. Even when 12 is provided, the leakage current from the data line 6a is at a negligible level.

Therefore, according to the present embodiment, an electrical signal generated in response to light reception in each pixel 100a is not deteriorated due to a leakage current from the data line 6a, so that the solid-state imaging device 1 with high resolution is obtained.
00 can be realized.

The first high potential line 7 to which different potentials are applied to the scanning line 3a and the data line 6a, respectively.
1a, the first low potential line 71b, the second high potential line 72a, and the second low potential line 72b, a potential difference occurs between the scanning line 3a and the data line 6a, and the field effect transistor provided in each pixel 100a. There is a concern that electrostatic breakdown may occur at 30. However, the scanning line 3a intersects the first high potential line 71a, the first low potential line 71b, the second high potential line 72a, and the second low potential line 72b, and the data line 6a is also the first high potential line 71a. First low potential line 71b, second high potential line 72a
And the second low potential line 72b. For this reason, as shown in FIG. 1, a capacitance C is parasitic at each intersection. Therefore, the four wirings (first high potential line 71a, first low potential line 71b
, The second high potential line 72a and the second low potential line 72b) are coupled via the capacitor C, so that a large potential difference does not occur between the scanning line 3a and the data line 6a. Electrostatic breakdown does not occur in the transistor 30.

Further, in this embodiment, in the first electrostatic protection circuit 11, the gate-on voltage Vgh is applied to the first high potential line 71a, and the gate-off voltage Vgl is applied to the first low potential line 71b. In the second electrostatic protection circuit 12, the bias voltage VB is applied to the second low potential line 72b. That is, a constant potential supplied to each pixel 100a is applied to the first high potential line 71a, the first low potential line 71b, and the second low potential line 72b. Therefore, the first electrostatic protection circuit 11 includes the first
Even when the high potential line 71 a and the first low potential line 71 b are provided and the second high potential line 72 a and the second low potential line 72 b are provided in the second electrostatic protection circuit 12, A power supply circuit that generates a potential to be applied to the high potential line 72a may be provided, and there is an advantage that the circuit configuration of the power supply unit can be simplified.

[Embodiment 2]
FIG. 8 is a block diagram showing an electrical configuration of the solid-state imaging device according to Embodiment 2 of the present invention. Since the basic configuration of this embodiment is the same as that of Embodiment 1, common portions are denoted by the same reference numerals and description thereof is omitted.

As shown in FIG. 8, in the solid-state imaging device 100 of the present embodiment, the first electrostatic protection circuit 11 for the scanning line 3a is formed outside the imaging region 100c on the base substrate 10 as in the first embodiment. The first electrostatic protection circuit 11 includes a first high potential line 71a to which a high potential equal to or higher than the highest potential applied to the scanning line 3a and a low potential equal to or lower than the lowest potential applied to the scanning line 3a. And a first low potential line 71b to which a potential is applied. The first electrostatic protection circuit 11 includes a first high potential side protection diode 91a electrically connected to the scanning line 3a and the first high potential line 71a in a reverse bias state, and the scanning line 3a and the first low potential. A first low potential side protection diode 91b electrically connected to the line 71b in a reverse bias state.

Further, in the solid-state imaging device 100 of the present embodiment, as in the first embodiment, the second electrostatic protection circuit 12 for the data line 6a is formed outside the imaging region 100c on the base substrate 10, and the first 2 The electrostatic protection circuit 12 was applied with a second high potential line 72a to which a high potential higher than the maximum potential applied to the data line 6a was applied and a low potential lower than the lowest potential applied to the data line 6a. And a second low potential line 72b. The second electrostatic protection circuit 12 includes a second high potential side protection diode 92a electrically connected to the data line 6a and the second high potential line 72a in a reverse bias state, and the data line 6a and the second low potential potential. And a second low potential side protection diode 92b electrically connected to the line 72b in a reverse bias state.

Here, the first high potential line 71a and the second high potential line 72a are electrically connected to form one common line surrounding the imaging region 100c, and the common line (first high potential line) The gate-on voltage Vgh is applied to the 71a and the second high potential line 72a) as a high potential equal to or higher than the highest potential applied to both the scanning line 3a and the data line 6a. The first low potential line 71b
And the second low potential line 72b are electrically connected to form one common line surrounding the imaging region 100c, and the common lines (the first high potential line 71a and the second high potential line 72a). The bias voltage VB is applied as a low potential below the lowest potential applied to both the scanning line 3a and the data line 6a.

In the solid-state imaging device 100, the first high potential line 71a, the first low potential line 71b, the first high potential side protection diode 91a, the first low potential side protection diode 91b, the second high potential line 72a,
The configurations of the second low potential line 72b, the second high potential side protection diode 92a, and the second low potential side protection diode 92b are the same as those in the first embodiment. For this reason, the first high potential line 71a and the first low potential line 71b extending in the Y direction are formed of a conductive film formed simultaneously with the data line 6a, and the second high potential line 72a extending in the X direction and The second low potential line 72b is composed of a conductive film formed simultaneously with the scanning line 3a. Therefore, when the first high potential line 71a and the second high potential line 72a are electrically connected and the first low potential line 71b and the second low potential line 72b are electrically connected, for example, FIG. A contact hole is formed in the gate insulating film 21 and the lower insulating film 22 described with reference to FIG. 4B, and the first high potential line 7 is formed using the contact hole.
1a and the second high potential line 72a may be connected, and the first low potential line 71b and the second low potential line 72b may be connected.

As described above, in the solid-state imaging device 100 of the present embodiment as well, the first electrostatic protection circuit 11 for the scanning line 3a and the second electrostatic protection circuit 12 for the data line 6a are the same as in the first embodiment.
Since a reverse bias voltage is applied to the high potential side protection diode 91a, the first low potential side protection diode 91b, the high potential side protection diode 92a, and the second low potential side protection diode 92b, the scanning line 3a and the data line 6a The leakage current from can be made to a very low level. Therefore, according to the present embodiment, since the power consumption of the solid-state imaging device 100 can be reduced, in the solid-state imaging device 100, a battery can be used as a drive source,
The solid-state imaging device 100 with high resolution can be realized.

In this embodiment, the gate-on voltage V is applied to the first high potential line 71a and the second high potential line 72a.
Since gh is applied and the bias potential VB is applied to the first low potential line 71b and the second low potential line 72b, there is an advantage that it is not necessary to provide a new power supply circuit.

In this embodiment, the gate-on voltage V is applied to the first high potential line 71a and the second high potential line 72a.
Since gh is applied and the bias potential VB is applied to the first low potential line 71b and the second low potential line 72b, it is applied to the first low potential side protection diode 91b and the second high potential side protection diode 92a. Although the reverse bias voltage to be applied is higher than that in the first embodiment, the leakage current can be greatly reduced as compared with the electrostatic protection circuit shown in FIG.

[Modification of Embodiment 2]
In the second embodiment, the first high potential line 71a and the second high potential line 72a are electrically connected to form a single common line surrounding the imaging region 100c, and the first low potential line 71a and the second high potential line 72a are electrically connected. Potential line 7
1b and the second low potential line 72b are electrically connected to form a single common line surrounding the imaging region 100c, but a configuration in which only one wiring is electrically connected is adopted. Also good.

That is, for the first high potential line 71a and the second high potential line 72a, the imaging region 1 is individually set.
On the other hand, the first low potential line 71b and the second low potential line 72b may be electrically connected to form one common line surrounding the imaging region 100c. Or first
The low potential line 71b and the second low potential line 72b are individually formed so as to surround the imaging region 100c, while the first high potential line 71a and the second high potential line 72a are electrically connected to each other to capture the imaging region. One common line surrounding 100c may be formed.

[Embodiment 3]
FIG. 9 is a block diagram showing an electrical configuration of the solid-state imaging device according to Embodiment 3 of the present invention. Since the basic configuration of this embodiment is the same as that of Embodiment 1, common portions are denoted by the same reference numerals and description thereof is omitted.

As shown in FIG. 9, in the solid-state imaging device 100 of the present embodiment as well, in the same way as in the first and second embodiments, the first electrostatic protection circuit 11 for the scanning line 3a is located outside the imaging region 100c on the base substrate 10.
The first electrostatic protection circuit 11 includes a first high potential line 71a to which a high potential equal to or higher than the maximum potential applied to the scanning line 3a and a minimum potential applied to the scanning line 3a. And a first low potential line 71b to which the following low potential is applied. The first electrostatic protection circuit 11 includes a first high potential side protection diode 91a electrically connected to the scanning line 3a and the first high potential line 71a in a reverse bias state, and the scanning line 3a and the first low potential. A first low potential side protection diode 91b electrically connected to the line 71b in a reverse bias state.

Also in the solid-state imaging device 100 of the present embodiment, the second electrostatic protection circuit 12 for the data line 6a is formed outside the imaging region 100c on the base substrate 10 as in the first and second embodiments.

However, in the present embodiment, the second electrostatic protection circuit 12 includes the second low potential line 72b to which a low potential lower than the lowest potential applied to the data line 6a is applied. Unlike the first embodiment, the second high potential line 72a described with reference to FIGS. 1 and 8 is not provided. Therefore, in the present embodiment, the second electrostatic protection circuit 12 includes the second low potential side protection diode 92b electrically connected to the data line 6a and the second low potential line 72b in a reverse bias state. The second high potential side protection diode 92a described with reference to FIGS. 1 and 8 is not provided.

Therefore, the first low potential line 71b and the second low potential line 72b are electrically connected to form one common line surrounding the imaging region 100c, and the common line (first low potential line) The bias potential VB is applied to the 71b and the second low potential line 72b) as a low potential lower than the lowest potential applied to both the scanning line 3a and the data line 6a. The first high potential line 71a itself forms a common line surrounding the imaging region 100c, and the common line (first high potential line 71a) has a potential higher than the highest potential applied to the scanning line 3a. As a high potential, the gate-on voltage V
gh is applied.

In the solid-state imaging device 100, the first high potential line 71a, the first low potential line 71b, the first high potential side protection diode 91a, the first low potential side protection diode 91b, the second low potential line 72b,
The configurations of the second low potential side protection diode 92b are the same as those in the first embodiment. Therefore, the first high potential line 71a and the first low potential line 71b extending in the Y direction are the data lines 6a.
And the second low potential line 72b extending in the X direction is formed of a conductive film formed simultaneously with the scanning line 3a.
And a conductive film formed simultaneously. Further, the portion extending in the X direction of the first high potential line 71a is composed of a conductive film formed simultaneously with the scanning line 3a.

As described above, in the solid-state imaging device 100 of the present embodiment as well, the first electrostatic protection circuit 11 for the scanning line 3a and the second electrostatic protection circuit 12 for the data line 6a are the same as in the first embodiment.
Since the reverse bias voltage is applied to the high potential side protection diode 91a, the first low potential side protection diode 91b, and the second low potential side protection diode 92b, the leakage current from the scanning line 3a and the data line 6a is extremely low. Can be a level. Therefore, according to this embodiment, the power consumption of the solid-state imaging device 100 can be reduced.
In the solid-state imaging device 100, a battery can be used as a driving source and the resolution is high.
Can be realized.

In this embodiment, since the gate-on voltage Vgh is applied to the first high potential line 71a and the bias potential VB is applied to the first low potential line 71b and the second low potential line 72b, a new power supply circuit is provided. There is an advantage that it is not necessary to provide it.

In this embodiment, the gate-on voltage V is applied to the first high potential line 71a and the second high potential line 72a.
Since gh is applied and the bias potential VB is applied to the first low potential line 71b and the second low potential line 72b, it is applied to the first low potential side protection diode 91b and the second high potential side protection diode 92a. Although the reverse bias voltage to be applied is higher than that in the first embodiment, the leakage current can be greatly reduced as compared with the electrostatic protection circuit shown in FIG.

[Embodiment 4]
FIG. 10 is a block diagram showing an electrical configuration of the solid-state imaging device according to Embodiment 4 of the present invention. Since the basic configuration of this embodiment is the same as that of Embodiment 1, common portions are denoted by the same reference numerals and description thereof is omitted.

As shown in FIG. 10, in the solid-state imaging device 100 of the present embodiment as well, in the same manner as in the first, second, and third embodiments, the first electrostatic protection circuit for the scanning line 3a is provided outside the imaging region 100c on the base substrate 10. 11, the first electrostatic protection circuit 11 includes a first high potential line 71a to which a high potential equal to or higher than the highest potential applied to the scanning line 3a is applied, and a lowest applied to the scanning line 3a. And a first low potential line 71b to which a low potential equal to or lower than the potential is applied. The first electrostatic protection circuit 11 includes a first high potential side protection diode 91a electrically connected to the scanning line 3a and the first high potential line 71a in a reverse bias state, and the scanning line 3a and the first low potential. A first low potential side protection diode 91b electrically connected to the line 71b in a reverse bias state.

However, in the present embodiment, unlike the first, second, and third embodiments, the second electrostatic protection circuit 12 described with reference to FIGS. 1, 8, 9, and 10 is not provided.

Therefore, the first high potential line 71a itself forms a common line surrounding the imaging region 100c, and the common line (first high potential line 71a) is higher than the highest potential applied to the scanning line 3a. The gate-on voltage Vgh is applied as a high potential. Further, the first low potential line 71b itself forms a common line surrounding the imaging region 100c, and the common line (the first low potential line 71b) is formed.
In b), the gate-off voltage Vgl is applied as a low potential lower than the lowest potential applied to the scanning line 3a. Therefore, in this embodiment, the bias potential VB is applied to the plurality of bias lines 5a via the dedicated main line 5s.

In the solid-state imaging device 100, the configurations of the first high potential line 71a, the first low potential line 71b, the first high potential side protection diode 91a, and the first low potential side protection diode 91b are the same as those in the first embodiment. It is. For this reason, the first high potential line 71a and the first low potential line 71b extending in the Y direction are formed of a conductive film formed simultaneously with the data line 6a, and the first high potential line 71a and the first low potential line 71b. Of these, the portion extending in the X direction is composed of a conductive film formed simultaneously with the scanning line 3a.

Thus, in the solid-state imaging device 100 of the present embodiment as well, in the first electrostatic protection circuit 11 for the scanning line 3a, the first high potential side protection diode 91a and the first low potential side protection diode 91b are the same as in the first embodiment. Since the reverse bias voltage is applied to the first and second electrodes, the leakage current from the scanning line 3a can be set to an extremely low level. Therefore, according to this embodiment, the solid-state imaging device 1
Therefore, the battery can be used as a drive source in the solid-state imaging device 100.

In this embodiment, since the gate-on voltage Vgh is applied to the first high potential line 71a and the gate-off voltage Vgl is applied to the first low potential line 71b and the second low potential line 72b, a new power supply circuit is provided. There is an advantage that it is not necessary to provide it.

[Other embodiments]
In the first embodiment, as shown in FIG. 2A, the drain of the field effect transistor is electrically connected to the first electrode 81a (cathode) of the photoelectric conversion element 80, and the bias line 5a is photoelectrically converted. Although it was electrically connected to the second electrode 85a (anode) of the element 80, FIG.
As shown in FIG. 4, the first electrode 81a of the photoelectric conversion element 80 that is electrically connected to the drain of the field effect transistor may be used as an anode. In this case, the photoelectric conversion element that is electrically connected to the bias line 5a The 80 second electrode 85a serves as a cathode. Figure 2
In the case of the configuration shown in (b), the basic operation is the same, for example, a reverse bias is applied to the photoelectric conversion element 80 via the bias line 5a. 11 is different from the pattern shown in FIG. Therefore, in the first embodiment, a potential 1V higher than the preset potential Vp is applied to the second high potential line 72a, and the second low potential line 72b is
Although a bias voltage is applied, in the configuration shown in FIG. 2B, a potential 1V lower than the preset potential Vp is applied to the second low potential line 72b, and a bias voltage VB is applied to the second high potential line 72a. What is necessary is just to apply.

In the first to fourth embodiments, a PIN photodiode is used as the photoelectric conversion element 80. However, the present invention is not limited to this, and a PN photodiode may be used.
A Schottky photoelectric conversion element 80 may be used.

In the first to fourth embodiments, the TFT using an amorphous silicon film has been described as an example of the field effect transistor 30. However, a thin film transistor using a microcrystalline silicon film, a polysilicon film, or a single crystal silicon layer is used as an electric field. The effect transistor 30 may be used.
In the first to fourth embodiments, the base substrate 10 is used as the field effect transistor 30.
Gate electrode 3b, gate insulating film 21 and semiconductor film 2a (from the lower layer side toward the upper layer side)
Although the bottom gate structure in which the active layer) is sequentially stacked is provided, the top gate structure in which the semiconductor film (active layer), the gate insulating film, and the gate electrode are sequentially stacked from the lower layer side to the upper layer side of the base substrate 10. The structure provided with may be sufficient. When such a top gate structure is employed, when the light is incident from the gate electrode side, the gate electrode is made of ITO.
If a translucent conductive film such as a film is used, light can be efficiently incident on the active layer.
The structure of the field effect transistor 30 may be any of a staggered type, an inverted staggered type, a coplanar type, and an inverted coplanar type.

In the first to fourth embodiments, the N-type field effect transistor 30 is used as the pixel switching element. However, the P-type field effect transistor 30 is used as the pixel switching element.
May be used. In this case, if the above description and polarity are reversed, the same configuration as in the first to fourth embodiments can be realized.

It is a block diagram which shows the electric constitution of the solid-state imaging device concerning Embodiment 1 of this invention. (A), (b) is the circuit diagram which shows each pixel structure of the solid-state imaging device to which this invention is applied, and the circuit diagram which shows another pixel structure. It is explanatory drawing which shows typically the external appearance of the solid-state imaging device to which this invention is applied. (A), (b) is the top view of a some adjacent pixel in the solid-state imaging device which concerns on Embodiment 1 of this invention, respectively, and sectional drawing for the one. It is explanatory drawing which shows the signal waveform in 1 scanning period in the imaging operation in the solid-state imaging device which concerns on Embodiment 1 of this invention. (A), (b), (c) is a circuit diagram showing the configuration of the first electrostatic protection circuit provided for the scanning line in the solid-state imaging device according to Embodiment 1 of the present invention. It is a top view which shows the plane structure of an electrostatic protection circuit, and sectional drawing which shows the cross-sectional structure of a 1st electrostatic protection circuit. (A), (b), (c) is a circuit diagram showing the configuration of the second electrostatic protection circuit provided for the data line in the solid-state imaging device according to Embodiment 1 of the present invention. It is a top view which shows the plane structure of an electrostatic protection circuit, and sectional drawing which shows the cross-sectional structure of a 2nd electrostatic protection circuit. It is a block diagram which shows the electric constitution of the solid-state imaging device concerning Embodiment 2 of this invention. It is a block diagram which shows the electrical constitution of the solid-state imaging device concerning Embodiment 3 of this invention. It is a block diagram which shows the electrical constitution of the solid-state imaging device concerning Embodiment 4 of this invention. It is explanatory drawing which shows the signal waveform in 1 scanning period in the imaging operation in another solid-state imaging device to which this invention is applied. It is a circuit diagram which shows the conventional electrostatic protection circuit. It is explanatory drawing which shows the current-voltage characteristic of the MIS type diode element used for the electrostatic protection circuit.

Explanation of symbols

3a ... scanning line, 5a ... bias line, 6a ... data line, 10 .... base substrate, 11 ....
First electrostatic protection circuit, 12 Second electrostatic protection circuit, 30 Field effect transistor, 7
1a... First high potential line, 71b... First low potential line, 72a... Second high potential line, 72b.
Second low potential line, 80... Photoelectric conversion element, 81 a... First electrode of photoelectric conversion element, 85 a.
Second electrode of photoelectric conversion element, 91a, first high potential side protection diode, 91b, first low potential side protection diode, 92a, second high potential side protection diode, 92b, second low potential side protection diode Diode, 100... Solid-state imaging device, 100 a .. Pixel, 100 c.

Claims (9)

In the imaging region on the substrate, there are a plurality of scanning lines extending in a predetermined direction, a plurality of data lines extending in a direction intersecting with the plurality of scanning lines, and a plurality of bias lines. And
A field effect transistor controlled by the scan line and a plurality of pixels arranged at positions corresponding to the intersections of the scan line and the data line, and the data line via the field effect transistor In a solid-state imaging device in which a first electrode electrically connected to a photoelectric conversion element including a second electrode electrically connected to the bias line is formed,
A first electrostatic protection circuit is formed on one signal line of the plurality of scanning lines and the plurality of data lines,
The first electrostatic protection circuit includes a first high potential line to which a high potential equal to or higher than the highest potential applied to the one signal line and a low potential equal to or lower than the lowest potential applied to the one signal line. , A first high-potential side protection diode electrically connected in a reverse bias state between the one signal line and the first high-potential line, and the one signal A solid-state imaging device comprising: a first low-potential side protection diode electrically connected in a reverse bias state between a line and the first low-potential line. A second electrostatic protection circuit is formed on the other signal line of the plurality of scanning lines and the plurality of data lines,
The second electrostatic protection circuit includes a second high potential line to which a high potential equal to or higher than the highest potential applied to the other signal line and a low potential equal to or lower than the lowest potential applied to the other signal line. , A second high potential side protection diode electrically connected in a reverse bias state between the other signal line and the second high potential line, and the other signal. The solid-state imaging device according to claim 1, further comprising a second low-potential side protection diode electrically connected in a reverse bias state between the line and the second low-potential line. 3. The solid according to claim 2, wherein different potentials are respectively applied to the first high potential line, the first low potential line, the second low potential line, and the second high potential line. Imaging device. A second electrostatic protection circuit is formed on the other signal line of the plurality of scanning lines and the plurality of data lines,
The second electrostatic protection circuit includes a second high potential line to which a high potential equal to or higher than the highest potential applied to the other signal line and a low potential equal to or lower than the lowest potential applied to the other signal line. And a protection diode electrically connected in a reverse bias state between the one wiring and the other signal line. The solid-state imaging device according to claim 1. 5. The solid-state imaging device according to claim 4, wherein different potentials are respectively applied to the first high potential line, the first low potential line, and the one wiring. In the first electrostatic protection circuit and the second electrostatic protection circuit, the first high potential line and the second high potential line, and the first low potential line and the second low potential line are connected to each other. 5. The solid-state imaging device according to claim 2, wherein at least one of the wirings is electrically connected and the same potential is applied thereto. In the electrostatic protection circuit configured for the scanning line, the potential applied to the high potential line or the potential applied to the low potential line is for turning off the field effect transistor. The gate-off voltage, a gate-on voltage for turning on the field effect transistor, or a bias voltage applied to the bias line is used. Solid-state imaging device. In the electrostatic protection circuit configured for the data line, the potential applied to the high potential line,
The solid-state imaging device according to claim 1, wherein a bias voltage applied to the bias line is used as a potential applied to the low potential line. Each of the protective diodes is a MIS type diode in which a drain and a gate are connected in a MIS type semiconductor element,
In the electrostatic protection circuit configured for the data line, the sum of the channel widths of the protection diodes electrically connected to one data line is the field effect electrically connected to the one data line. 9. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is not more than 1/10 times the sum of channel widths of the type transistors.