JP5811239B2 - Integrated circuit device and electronic apparatus - Google Patents

Description

  The present invention relates to an integrated circuit device, an electronic device, and the like.

  In recent years, motion sensors such as gyro sensors and acceleration sensors have attracted attention. By using such a motion sensor, for example, camera shake correction or intuitive operation input in a game machine can be realized. As a prior art of an apparatus that receives a detection signal from such a sensor device and performs A / D conversion processing and filter processing, there is a technology disclosed in Patent Document 1, for example.

  By the way, in the gyro sensor or the acceleration sensor, an angular velocity (or angular acceleration) or acceleration detection signal is output as a DC voltage detection voltage signal. Then, the application side integrates the angular velocity and acceleration obtained from the detected voltage signal by software processing, and obtains the angle, velocity, distance, and the like.

  However, the DC voltage level of the detection voltage signal from the gyro sensor or the acceleration sensor has a DC offset due to process variation or the like. Therefore, if the detected voltage signal having such a DC offset is integrated as described above to obtain the angle, speed, and distance, the error becomes very large.

  In this regard, in the above-described prior art disclosed in Patent Document 1, the detection voltage signal from the sensor device is input to the amplifier circuit, and the output signal of the amplifier circuit is A / D converted by the A / D converter, thereby obtaining the detection signal. The corresponding digital data is obtained.

  However, if the operating power supply voltage of the sensor device varies in this case, the DC voltage level of the detection voltage signal also varies. Accordingly, the digital data obtained by the A / D converter also fluctuates, and for example, errors in angles, speeds, and distances obtained by integration of software processing at the subsequent stage become large.

JP 2009-20829 A

  According to some aspects of the present invention, it is possible to provide an integrated circuit device, an electronic device, and the like that can realize A / D conversion with high accuracy of a detection signal from a sensor device.

  According to one embodiment of the present invention, a power supply circuit that generates a power supply voltage, and the A / D conversion defined by the power supply voltage that operates based on the power supply voltage supplied from the power supply circuit and that operates based on the supplied power supply voltage A / D converter that performs A / D conversion on a signal corresponding to a detection signal from the sensor device, and the power supply voltage is supplied from the power supply circuit, and the supplied power supply voltage is supplied to the sensor device. The present invention relates to an integrated circuit device including a power supply terminal to be supplied.

  According to one embodiment of the present invention, the power supply circuit generates a power supply voltage and supplies the generated power supply voltage to the A / D converter. Then, the A / D converter operates by being supplied with the power supply voltage, and A / D conversion is performed on the signal corresponding to the detection signal from the sensor device within the A / D conversion range defined by the supplied power supply voltage. I do. The power supply circuit supplies the generated power supply voltage to the sensor device via the power supply terminal. Then, the sensor device operates based on the supplied power supply voltage and outputs a detection signal to the integrated circuit device. This makes it possible to establish a ratiometric relationship between the power supply voltage of the sensor device and the power supply voltage of the A / D converter. Therefore, even when the power supply voltage fluctuates, the fluctuation of the output digital data of the A / D converter can be minimized, and the A / D conversion with high accuracy of the detection signal from the sensor device can be performed. realizable.

  In the aspect of the invention, the power supply circuit may include a reference voltage generation circuit that generates a reference voltage, and a regulator that generates the power supply voltage based on the generated reference voltage.

  With this configuration, the reference voltage generated by the reference voltage generation circuit is adjusted by the regulator, so that a power supply voltage with high accuracy can be generated.

  In one embodiment of the present invention, the regulator includes a voltage divider circuit that divides a voltage between the power supply voltage and a low-potential-side power supply voltage, the reference voltage is supplied to a first input node, and the voltage divider circuit And an operational amplifier in which the voltage from the voltage dividing tap is supplied to the second input node.

  In this way, for example, the operational amplifier operates so that the voltage at the first input node is equal to the voltage at the second input node. The voltage can be output to the output node.

  In one embodiment of the present invention, the voltage divider circuit includes a plurality of resistors, and outputs a divided voltage to each voltage divider tap of the plurality of voltage divider taps of the plurality of resistors, and the ladder resistor A power supply voltage setting resistor circuit provided in series with the circuit and having a variable resistance value, and selecting one voltage dividing tap among the plurality of voltage dividing taps of the ladder resistor circuit as the voltage fine adjustment tap; And a first selection circuit that supplies a voltage from the selected voltage fine adjustment tap to the second input node of the operational amplifier.

  In this way, it is possible to finely adjust the power supply voltage output from the output node by selecting the fine voltage adjustment tap from the plurality of voltage division taps of the ladder resistor circuit by the first selection circuit. Become.

  In one embodiment of the present invention, an analog front-end circuit that operates based on the power supply voltage is included, and the voltage divider circuit analogizes one voltage divider tap of the plurality of voltage divider taps of the ladder resistor circuit. A second selection circuit may be included that selects as a ground tap and supplies an analog ground voltage from the selected analog ground tap to the analog front end circuit.

  In this way, it is possible to generate not only the power supply voltage but also the analog ground voltage by using one voltage dividing circuit. Further, when the power supply voltage changes, the analog ground voltage also changes in conjunction with it, and the power supply voltage and the analog ground voltage can be linked.

  In the aspect of the invention, the second selection circuit may include, from the plurality of voltage division taps, a voltage division tap according to a power supply voltage setting result in the power supply voltage setting resistor circuit, the analog ground It may be selected as a tap for use.

  In this way, the analog ground voltage according to the power supply voltage can be set by selecting the analog ground tap from among the plurality of voltage dividing taps of the ladder resistor circuit.

  According to another aspect of the present invention, the regulator includes an analog front-end circuit that operates based on the power supply voltage, and the regulator supplies the analog ground voltage from the analog ground tap of the voltage divider circuit to the analog front-end circuit. May be supplied.

  In this way, it is possible to supply the power supply voltage and the analog ground voltage generated by the same voltage dividing circuit to the analog front end circuit to operate the analog front end circuit, and to detect the detection signal from the sensor device. A / D conversion with high accuracy can be realized.

  In one aspect of the present invention, the analog front-end circuit receives a detection signal from the sensor device, and sends a signal at which the analog ground voltage becomes a center voltage in an A / D conversion range to the A / D converter. An output amplifier circuit may be included.

  In this way, the amplification circuit of the analog front-end circuit to which the power supply voltage and the analog ground voltage generated by the same voltage dividing circuit are supplied, the signal whose analog ground voltage becomes the center voltage in the A / D conversion range is A / D converter to output. Since the center voltage of the A / D conversion range is defined by the analog ground voltage, and the upper limit voltage is defined by the power supply voltage, the A / D converter performs A / D conversion on the signal from the amplifier circuit, thereby further A / D conversion with high accuracy can be realized.

  In one aspect of the present invention, the amplifier circuit adds a voltage signal obtained by adding a voltage corresponding to a difference between a first signal and a second signal constituting a channel signal from the sensor device to the analog ground voltage. It may be output.

  In this way, even when the detection signal of the sensor device is transmitted by a voltage corresponding to the difference between the first signal and the second signal, the A / D conversion range is set to a wide range centering on the analog ground voltage. Thus, A / D conversion can be performed.

  In the aspect of the invention, the amplifier circuit may be configured by a switched capacitor circuit that cancels an offset voltage of an operational amplifier included in the amplifier circuit.

  In this way, by using the switched capacitor circuit, it is possible to reduce the measurement error due to the superposition of the offset voltage of the operational amplifier, and thus it is possible to realize more accurate A / D conversion.

  In one aspect of the present invention, the analog front-end circuit includes a first channel first signal constituting a first channel signal of the sensor device and a second channel constituting a second channel signal of the sensor device. A first signal and a third channel first signal constituting a third channel signal from the sensor device are input, and the first channel first signal is output as the first signal in the first channel measurement period. The first multiplexer outputs the second channel first signal as the first signal in the second channel measurement period, and outputs the third channel first signal as the first signal in the third channel measurement period. A first channel second signal constituting the first channel signal and a second channel second signal constituting the second channel signal. And a third channel second signal constituting the third channel signal, and the first channel second signal is output as a second signal in the first channel measurement period, and the second channel measurement is performed. A second multiplexer that outputs the second channel second signal as the second signal in a period, and outputs the third channel second signal as the second signal in the third channel measurement period; The amplifier circuit may output a signal corresponding to a difference between the first signal from the first multiplexer and the second signal from the second multiplexer.

  In this way, when the signal of each channel is composed of the first and second signals, the signal corresponding to the difference between the first and second signals of each channel is A / D converted in a time division manner. It becomes like this. Therefore, A / D conversion of a signal corresponding to the difference between the first and second signals can be realized with a small circuit scale.

  In one embodiment of the present invention, a signal from the amplifier circuit, a fourth channel signal from the sensor device, a fifth channel signal, and a sixth channel signal are input, and the first channel measurement is performed. In the period, the second channel measurement period, and the third channel measurement period, the signal from the amplifier circuit is output as the third signal, and in the fourth channel measurement period, the signal of the fourth channel is used as the third signal. A third multiplexer that outputs the fifth channel signal as the third signal in the fifth channel measurement period and outputs the sixth channel signal as the third signal in the sixth channel measurement period; The A / D converter may perform A / D conversion on the third signal from the third multiplexer.

  In this way, in the first channel measurement period to the third channel measurement period, the signal corresponding to the difference between the first and second signals from the sensor device is A / D converted in a time division manner, and the fourth channel measurement period In the sixth channel measurement period, the signal from the sensor device can be A / D converted in a time division manner.

  In the aspect of the invention, the sensor device may include a gyro sensor that outputs the first channel signal, the second channel signal, and the third channel signal, the fourth channel signal, and the fifth channel signal. An acceleration sensor that outputs a channel signal and a sixth channel signal. The first channel signal, the second channel signal, and the third channel signal from the gyro sensor are each about an X axis. Angular velocity or angular acceleration detection signal, Y-axis angular velocity or angular acceleration detection signal, Z-axis angular velocity or angular acceleration detection signal, the fourth channel signal from the acceleration sensor, and the fifth channel signal. The sixth channel signals may be X-axis direction acceleration detection signals, Y-axis direction acceleration detection signals, and Z-axis direction acceleration detection signals, respectively. There.

  If it does in this way, about the 1st and 2nd signal which constitutes the angular velocity or angular acceleration detection signal from a 3 axis gyro sensor, the difference signal will be generated in an amplifier circuit, and A / D converter will perform A / D Can be converted. On the other hand, the acceleration detection signal from the triaxial acceleration sensor can be directly input to the A / D converter and A / D converted. Therefore, it is possible to provide a measurement system suitable for a 6-axis motion sensor including a 3-axis gyro sensor and a 3-axis acceleration sensor.

  In the aspect of the invention, the first multiplexer, the second multiplexer, and the third multiplexer may be laid out between the amplifier circuit and the A / D converter.

  According to this configuration, the first to third channel signals input from the sensor device via the terminal of the integrated circuit device are efficiently input to the amplifier circuit via the first multiplexer and the second multiplexer. become able to. Further, the signals of the fourth channel to the sixth channel input from the sensor device via the terminal of the integrated circuit device can be efficiently input to the A / D converter via the third multiplexer. This makes it possible to minimize the situation where the voltage of each signal fluctuates due to noise or the like, or a voltage drop occurs.

  In the aspect of the invention, the A / D converter may be laid out at a position closer to the power supply circuit than the analog front end circuit.

  In this way, the voltage drop of the power supply voltage when supplying the power supply voltage from the power supply circuit to the A / D converter can be minimized. Therefore, a ratiometric relationship is maintained between the power supply voltage of the sensor device and the power supply voltage of the A / D converter, and the measurement accuracy of the sensor detection signal can be improved.

  Another aspect of the invention relates to an electronic device including any one of the integrated circuit devices described above.

1 is a configuration example of an integrated circuit device according to an embodiment. Explanatory drawing about A / D conversion of the detection signal from a sensor device. The structural example of a power supply circuit. 2 shows a detailed configuration example of a power supply circuit. Explanatory drawing about power supply voltage setting, analog ground voltage setting, and voltage fine adjustment. 2 is a detailed configuration example of an integrated circuit device according to the present embodiment. FIG. 6 is an operation explanatory diagram of the integrated circuit device of the present embodiment. FIGS. 8A to 8C are explanatory diagrams of first and second signals constituting each channel signal. 9A is an explanatory diagram of the operation of the amplifier circuit, and FIG. 9B is an example in which the first and second signals constituting each channel signal are differential signals. FIG. 10A and FIG. 10B are configuration examples of an amplifier circuit including a switched capacitor circuit. Operation | movement explanatory drawing of the amplifier circuit comprised by a switched capacitor circuit. A configuration example in the case of sharing a sampling switch element and a multiplexer switch element. 6 is a layout example of an integrated circuit device. 1 is a configuration example of an electronic device including an integrated circuit device according to an embodiment.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Configuration Example FIG. 1 shows a configuration example of an integrated circuit device (circuit device) of this embodiment. The integrated circuit device includes an analog front-end circuit AFE, an A / D converter ADC, a control unit 50, and a power supply circuit 60. The integrated circuit device of the present embodiment is not limited to the configuration shown in FIG. 1, and various modifications such as omitting some of the components (for example, the control unit, AFE) and adding other components. Is possible.

  The power supply circuit 60 generates a power supply voltage VDDA for an analog circuit. Also, the power supply voltage VDDL for digital circuits and the analog ground voltage AGND (analog reference voltage) are generated. The power supply circuit 60 can include, for example, a reference voltage generation circuit that generates a reference voltage and a regulator that generates the power supply voltage VDDA and the analog ground voltage AGND based on the generated reference voltage.

  The analog front end circuit AFE is an analog circuit that operates when the power supply voltage 60 is supplied from the power supply circuit 60. A detection signal VQ from the sensor device 30 is input to the analog front end circuit AFE via a terminal PVQ. Then, the analog front end circuit AFE outputs a signal AQ corresponding to the detection signal VQ to the A / D converter ADC. Here, the signal AQ corresponding to the detection signal VQ may be the detection signal VQ itself, or a signal that the detection signal VQ is input to the A / D converter ADC via another circuit element (such as a multiplexer). It may be.

  The power supply circuit 60 supplies an analog ground voltage AGND to the analog front end circuit AFE that operates based on the power supply voltage VDDA. The analog front end circuit AFE includes an amplifier circuit AMP. The amplifier circuit AMP receives the detection signal VQ from the sensor device 30 and outputs a signal that causes the analog ground voltage AGND to become the center voltage VCT of the A / D conversion range RAD as shown in FIG. Output to D converter ADC. Specifically, for example, the amplifier circuit AMP outputs a voltage signal obtained by adding a voltage corresponding to the difference between the first signal and the second signal constituting the channel signal VQ of the sensor device 30 to the analog ground voltage AGND. .

  As will be described later with reference to FIGS. 10A and 10B, the amplifier circuit AMP can be configured by a switched capacitor circuit that cancels the offset voltage of the operational amplifier OP included in the amplifier circuit AMP.

  The A / D converter ADC is supplied with the power supply voltage VDDA from the power supply circuit 60 and operates based on the supplied power supply voltage VDDA. Then, A / D conversion is performed on the signal AQ corresponding to the detection signal VQ from the sensor device 30. Specifically, A / D conversion is performed on the signal AQ within an A / D conversion range defined by the power supply voltage VDDA (for example, an A / D conversion range having VDDA as an upper limit voltage). Then, the obtained digital data DQ is output to the control unit 50. Here, the A / D conversion of the signal AQ corresponding to the detection signal VQ may be an A / D conversion of the detection signal VQ itself, or the detection signal VQ is an analog front end such as a multiplexer or an amplifier circuit AMP. A / D conversion of a signal input through another circuit element in the circuit AFE may be used.

  As the A / D converter ADC, for example, a successive approximation A / D converter (for example, 10 to 16 bits) can be employed. The successive approximation type A / D converter includes, for example, a comparison circuit, a successive approximation register, and a D / A converter, and performs A / D conversion on a signal obtained by sampling (sample / hold) an input signal by successive approximation operation. To output digital data. As the A / D converter ADC, an A / D converter other than the successive approximation type can be adopted.

  The controller 50 performs various digital processes based on the digital data DQ from the A / D converter ADC. Specifically, digital filter processing is performed based on the digital data DQ. The control unit 50 also controls each circuit block in the integrated circuit device. That is, control signals are output to the analog front end circuit AFE, the A / D converter ADC, the analog front end circuit AFE, and the power supply circuit 60 to control the operation of these circuit blocks. The function of the control unit 50 can be realized by a logic circuit such as a gate array (G / A).

  The integrated circuit device of this embodiment includes a power supply terminal PVDA. The power supply terminal PVDA is a terminal (pad) that is supplied with the power supply voltage VDDA from the power supply circuit 60 and supplies the supplied power supply voltage VDDA to the sensor device 30. The sensor device 30 performs a sensor operation based on the supplied power supply voltage VDDA, and outputs a detection signal VQ obtained by the sensor operation to a terminal (pad) PVQ of the integrated circuit device.

  That is, as shown in FIG. 2, the sensor device 30 such as an acceleration sensor outputs a DC voltage signal as the detection signal VQ. Since the A / D converter ADC operates based on the power supply voltage VDDA from the power supply circuit 60, the A / D conversion range RAD of the A / D converter ADC has an upper limit voltage that is the power supply voltage VDDA, and a lower limit. The voltage is in a range where the low-potential-side power supply voltage VSS (= 0 V). That is, the A / D conversion range (dynamic range) is a range defined by the power supply voltage VDDA. When the analog ground voltage AGND = VDDA / 2 is the center voltage of the A / D conversion range RAD and the voltage of the input signal AQ to the A / D converter ADC is AGND = VDDA / 2, A / D The converter ADC outputs center code digital data DQ. For example, when the sensor device 30 is an acceleration sensor, if the acceleration is zero, a center code is output from the A / D converter ADC.

  However, in conventional integrated circuit devices, the power supply voltage of the sensor device 30 and the power supply voltage of the A / D converter ADC are different power supply voltages supplied from different power supply circuits. A ratiometric relationship was not maintained between the voltage and the power supply voltage of the A / D converter ADC. For this reason, for example, if the power supply voltage of the sensor device 30 and the power supply voltage of the A / D converter ADC become different voltages due to power supply fluctuation or the like, the code of the digital data DQ output from the A / D converter ADC also fluctuates. Resulting in. For example, when the acceleration is 0, the digital data DQ of the center code should be output, but if the power supply voltage fluctuates, the digital data DQ different from the center code is output. Therefore, the subsequent application side determines that an electronic device (a camera, a game controller, or the like) on which the acceleration sensor is mounted does not actually move but moves. In particular, when the application side in the subsequent stage integrates acceleration and calculates speed and distance, fluctuations in digital data due to fluctuations in the power supply voltage are accumulated by the integration process, resulting in a very large error.

  In this regard, in this embodiment, as shown in FIG. 1, the power supply circuit 60 generates the power supply voltage VDDA, and the generated power supply voltage VDDA is supplied to the A / D converter ADC in the integrated circuit device. It is also supplied to the sensor device 30 via the power terminal PVDA. Therefore, a ratiometric relationship is established between the power supply voltage of the sensor device 30 and the power supply voltage of the A / D converter ADC. Therefore, even when the power supply voltage VDDA varies, the variation in the output digital data DQ of the A / D converter ADC can be minimized. Therefore, for example, when the sensor device 30 is an acceleration sensor, the electronic device on which the acceleration sensor is mounted is not moving, and the acceleration is zero, the digital data DQ of the center code is received from the A / D converter ADC. Will be output. For this reason, even when the subsequent application side calculates the speed and distance by accumulating the acceleration, it is possible to suppress the occurrence of a situation in which the fluctuation of the digital data is accumulated by the accumulation process and the error becomes large. Therefore, A / D conversion with high accuracy of the detection signal from the sensor device 30 can be realized.

2. Configuration of Power Supply Circuit FIG. 3 shows a configuration example of the power supply circuit 60 used in the integrated circuit device of this embodiment. The power supply circuit of FIG. 3 includes a reference voltage generation circuit 62 that generates a reference voltage VREF, and a regulator REG.

  The regulator REG generates the power supply voltage VDDA based on the reference voltage VREF generated by the reference voltage generation circuit 62. As shown in FIG. 1, the generated power supply voltage VDDA is supplied to the A / D converter ADC. Further, the power supply voltage VDDA is supplied to the sensor device 30 via the power supply terminal PVDA. The regulator REG includes a voltage dividing circuit 64 and an operational amplifier OPR.

  The voltage dividing circuit 64 is a circuit that divides the voltage between the power supply voltage VDDA and the low-potential-side power supply voltage VSS, and includes a VDD node (high-potential-side power supply node) and a VSS node (low-potential-side power supply node). Between. Specifically, the voltage dividing circuit 64 includes a plurality of resistors R1 to RN. The plurality of resistors R1 to RN are provided in series between the output nodes NVDA and VSS of VDDA. The voltage dividing circuit 64 includes a drive transistor TRD (P-type transistor) whose gate is controlled by an output signal VOP from the operational amplifier OP. The drive transistor TRD is provided between the VDD node and the output node NVDA of VDDA.

  The operational amplifier OPR is supplied with the reference voltage VREF from the reference voltage generation circuit 62 at the first input node NA1 (non-inverting input node). Further, the voltage VFB from the voltage dividing tap TP1 of the voltage dividing circuit 64 is supplied to the second input node NA2. In FIG. 3, the voltage dividing tap TP1 is a connection node between the resistor Rm and the resistor Rm + 1.

  The operational amplifier OPR operates so that the reference voltage VR and the voltage VFB from the voltage dividing tap TP1 are equal. Therefore, if the total resistance value of the resistors R1 to RN is RA and the total resistance value of the resistors Rm + 1 to RN is RB, the power supply voltage VDDA = (RA / RB) · VREF is output from the output node NVDA. . For example, if the position of the voltage dividing tap TP1 is made variable, the voltage of VDDA can be finely adjusted.

  FIG. 4 shows a detailed configuration example of the power supply circuit 60. FIG. 4 shows a detailed configuration example of the voltage dividing circuit 64. The voltage dividing circuit 64 includes a ladder resistor circuit RLAC and a power supply voltage setting resistor circuit RAJC. Further, it includes a first selection circuit SEL1 and a second selection circuit SEL2.

  The ladder resistor circuit RLAC has a plurality of resistors. The plurality of resistors are provided between the output node NVDA and the VSS node of the power supply voltage VDDA. The ladder resistor circuit RLAC outputs (generates) a divided voltage to each voltage dividing tap of the plurality of voltage dividing taps of the plurality of resistors. For example, corresponding divided voltages are output to the voltage dividing taps of TP21 to TP2j and TP11 to TP1i.

  The power supply voltage setting resistor circuit RAJC is a resistor circuit provided in series with the ladder resistor circuit RLAC and having a variable resistance value. The power supply voltage setting resistor circuit RAJC includes a plurality of resistors and switch elements SW31 to SW3k. The plurality of resistors of the power supply voltage setting resistor circuit RAJC are provided in series between the ladder resistor circuit RLAC and the VSS node. The switch elements SW31 to SW3k are provided between the plurality of voltage dividing taps TP31 to TP3k of the plurality of resistors and the VSS node.

  In FIG. 4, since the switch element SW32 is on, the voltage division tap TP32 is selected as the power supply voltage setting tap, and the voltage division tap TP32 is set to VSS = 0V. That is, due to the bypass to the VSS node via the switch element SW32, the resistor provided between the voltage dividing tap TP32 and the VSS node does not function as a voltage dividing resistor. Therefore, the total resistance value of voltage dividing circuit 64 is set to the total resistance value of the resistors provided between output node NVDA and tap TP32.

  The first selection circuit SEL1 selects one voltage division tap among the plurality of voltage division taps TP11 to TP1i of the ladder resistor circuit RLAC as a fine voltage adjustment tap. Then, the voltage VFB from the selected voltage fine adjustment tap is supplied to the second input node NA2 of the operational amplifier OPR. Specifically, the first selection circuit SEL1 includes a plurality of switch elements SW11 to SW1i. These switch elements SW11 to SW1i are provided between the voltage dividing taps TP11 to TP1i of the ladder resistor circuit RLAC and the second input node NA2 of the operational amplifier OPR.

  In FIG. 4, since the switch element SW12 is on, the voltage division node TP12 is selected as a fine voltage adjustment tap, and the voltage VFB from the voltage division node TP12 is supplied to the second input node NA2 of the operational amplifier OPR. Will be. Here, the fine adjustment of the voltage by the voltage fine adjustment tap means an adjustment having a narrower adjustment range than the adjustment of the VDDA voltage setting by the power supply voltage setting resistor circuit RAJC.

  The second selection circuit SEL2 selects one voltage division tap among the plurality of voltage division taps TP21 to TP2j of the ladder resistor circuit RLAC as an analog ground tap. Then, the analog ground voltage AGND from the selected analog ground tap is output. As a result, the regulator REG can supply the analog ground voltage AGND from the analog ground tap of the voltage dividing circuit 64 to the analog front end circuit AFE that operates based on the power supply voltage VDDA as shown in FIG. .

  Specifically, the second selection circuit SEL2 includes a plurality of switch elements SW21 to SW2j and an operational amplifier OPAG. The switch elements SW21 to SW2j are provided between the plurality of voltage division taps TP21 to TP2j of the ladder resistor circuit RLAC and the first input node NB1 (non-inverting input node) of the operational amplifier OPAG. The operational amplifier OPAG is a voltage follower-connected operational amplifier in which the output node and the second input node NB2 (inverted input node) are connected.

  In FIG. 4, since the switch element SW22 is turned on, the voltage division node TP22 is selected as an analog ground tap, and the voltage from the voltage division node TP22 is supplied to the first input node NB1 of the operational amplifier OPAG. The voltage from the voltage division node TP22 is impedance-converted by a voltage follower-connected operational amplifier OPAG and output as an analog ground voltage AGND.

  Further, the second selection circuit SEL2 selects, as an analog ground tap, a voltage division tap corresponding to the setting result of the power supply voltage VDDA in the power supply voltage setting resistor circuit RAJC from among the plurality of voltage division taps TP21 to TP2j. .

  That is, the switch elements SW21 to SW2j of the second selection circuit SEL2 and the switch elements SW31 to SW3k of the power supply voltage setting resistor circuit RAJC are on / off controlled in conjunction with each other. Specifically, when the voltage setting of VDDA is changed by the on / off control of the switch elements SW31 to SW3k of the power supply voltage setting resistor circuit RAJC, for example, AGND = VDDA / 2 in conjunction with the change of the setting. The switch elements SW21 to SW2j of the second selection circuit SEL2 are on / off controlled so that the above relationship holds.

  The on / off control of the switch elements SW11 to SW1i, SW21 to SW2j, and SW31 to SW3k is performed by the control unit 50 in FIG. The switch elements SW11 to SW1i, SW21 to SW2j, and SW31 to SW3k are realized by CMOS transistors (N-type transistors), transfer gates, or the like.

  FIG. 5 is an explanatory diagram of power supply voltage setting, analog ground voltage setting, and voltage fine adjustment according to the present embodiment.

  For example, by controlling ON / OFF of the switch elements SW31 to SW3k of the power supply voltage setting resistor circuit RAJC, as shown in FIG. 5, 3.4V, 3.3V, 3.2V,... The power supply voltage VDDA is set.

  For example, various types of sensor devices 30 to which the integrated circuit device of this embodiment is connected can be considered. When the operating power supply voltage of the sensor device 30 to which the integrated circuit device is connected is 3.4 V, the on / off control of the switch elements SW31 to SW3k of the power supply voltage setting resistor circuit RAJC is performed as shown in FIG. In addition, by setting the total number of resistance stages of the voltage dividing circuit 64 to 3456, for example, VDDA = 3.4V is set. Then, VDDA = 3.4 V is supplied to the sensor device 30 through the power supply terminal PVDA.

  On the other hand, when the operating power supply voltage of the sensor device 30 to which the integrated circuit device is connected is 3.3 V, the total number of resistance stages of the voltage dividing circuit 64 is set to 3520, for example, by ON / OFF control of the switch elements SW31 to SW3k. By doing so, VDDA is set to 3.3V. Then, VDDA = 3.3 V is supplied to the sensor device 30 through the power supply terminal PVDA.

  Thus, even when various types of sensor devices 30 are connected to the integrated circuit device of the present embodiment, the power supply voltage VDDA corresponding to the operation power supply voltage of the sensor device 30 is supplied via the power supply terminal PVDA. become able to.

  When the total number of resistance stages of the voltage dividing circuit 64 changes in this way, the analog ground voltage deviates from AGND = VDDA / 2.

  Therefore, in the present embodiment, the second selection circuit SEL2 uses a voltage dividing tap corresponding to the setting result of the power supply voltage VDDA by the on / off control of the switch elements SW31 to SW3k in the power supply voltage setting resistor circuit RAJC for the analog ground. Select as a tap.

  For example, as shown in FIG. 5, when the total number of resistance stages is set to 3456 by the power supply voltage setting resistor circuit RAJC in order to set VDDA = 3.4V, the second selection circuit SEL2 has the number of stages 1728 = The voltage division tap of 3456/2 is selected as the analog ground tap. Thus, when VDDA = 3.4V is set, an analog ground voltage of AGND = VDDA / 2 = 1.7V can be supplied to the analog front end circuit AFE of FIG. As a result, A / D conversion as shown in FIG. 2 and FIG. 9A described later can be realized.

  At this time, as shown in FIG. 5, the first selection circuit SEL1 selects a voltage division tap corresponding to the number of stages of 1200 to 1263, thereby finely adjusting the power supply voltage VDDA. That is, for example, when the power supply voltage VDDA fluctuates due to the fluctuation of the reference voltage VREF due to process fluctuation or the like, the first selection circuit SEL1 performs fine adjustment of VDDA so that the power supply voltage VDDA becomes 3.4V. . This fine adjustment is performed, for example, in a shipping process after the manufacture of the integrated circuit device, and information on the on / off setting of the switch elements SW11 to SW1i of the first selection circuit SEL1 at that time is stored in a fuse circuit or a nonvolatile memory. Is done. By doing so, it becomes possible to minimize the fluctuation of the power supply voltage VDDA caused by the process fluctuation of the integrated circuit device.

  On the other hand, when the total number of resistance stages is set to 3520 by the power supply voltage setting resistor circuit RAJC in order to set VDDA = 3.3 V, the second selection circuit SEL2 has a voltage at which the number of stages becomes 1760 = 3520/2. Select the split tap as an analog ground tap. In this way, when VDDA = 3.3V is set, an analog ground voltage of AGND = VDDA / 2 = 1.65V can be supplied to the analog front end circuit AFE.

  At this time, as shown in FIG. 5, the first selection circuit SEL1 performs fine adjustment of the power supply voltage VDDA by selecting voltage dividing taps corresponding to the number of stages 1264 to 1327. As a result, it is possible to finely adjust the fluctuation of the power supply voltage VDDA caused by the process fluctuation of the integrated circuit device.

  As described above, according to the power supply circuit 60 of FIG. 4, the power supply voltage VDDA can be set to various voltages depending on, for example, the type of the sensor device 30. Even when the setting of the power supply voltage VDDA is changed in this way, as shown in FIG. 5, the switching element on / off in the power supply voltage setting resistor circuit RAJC and the switch in the second selection circuit SEL2 are changed. The on / off of the element is controlled in conjunction. Therefore, an analog ground voltage satisfying AGND = VDDA / 2 is supplied to the analog front end circuit AFE, and A / D conversion as shown in FIGS. 2 and 9A can be realized. Further, the fine adjustment of the power supply voltage VDDA by the selection circuit SEL1 makes it possible to minimize the fluctuation of the power supply voltage VDDA due to the process fluctuation of the integrated circuit device.

  Then, the setting of the power supply voltage, the setting of AGND, and the fine adjustment of the power supply voltage can be realized by using one voltage dividing circuit 64 having a single path of a plurality of resistors connected in series as shown in FIG. . Accordingly, the circuit scale of the integrated circuit device can be reduced and the value of the current flowing through the resistor path can be reduced compared with the case where the number of series connection paths of a plurality of resistors is two or more, thereby saving power. It becomes like this.

3. Detailed Configuration Example FIG. 6 shows a detailed configuration example of the integrated circuit device of this embodiment. In the detailed configuration example of FIG. 6, the sensor device 30 includes a gyro sensor 10 and an acceleration sensor 20. As the gyro sensor 10, an angular velocity sensor such as a vibration type that detects angular velocity from Coriolis force due to rotation of the vibrator, an angular acceleration sensor that detects angular acceleration from change in capacitance or inertia force, and the like are adopted. it can. As the acceleration sensor 20, a capacitance type sensor that detects a change in position at a movable part supported by a beam structure as a change in capacitance, or a piezoresistive type that detects a change in position of a diaphragm by a piezoresistive element. Sensors and gas temperature distribution type sensors can be used. The gyro sensor 10 and the acceleration sensor 20 may be integrally mounted in the same package (housing), or may be mounted in different packages.

  In FIG. 6, an angular velocity (or angular acceleration) detection signal around the X axis, an angular velocity (or angular acceleration) detection signal around the Y axis, and an angular velocity (or angular acceleration) detection signal around the Z axis are: The detection voltage signals VQ1, VQ2, and VQ3 of the channels CH1, CH2, and CH3 are output from the sensor device 30 (gyro sensor), respectively. Reference voltage signals VR1, VR2, and VR3, which are reference voltages for the detection voltage signals VQ1, VQ2, and VQ3 of CH1, CH2, and CH3, are output from the sensor device 30 (gyro sensor).

  The signal VQ4 of the fourth channel CH4, the signal VQ5 of the fifth channel CH6, and the signal VQ6 of the sixth channel CH6 from the sensor device 30 (acceleration sensor) are respectively an acceleration detection signal in the X-axis direction and an acceleration in the Y-axis direction. It becomes a detection signal and an acceleration detection signal in the Z-axis direction.

  Note that an external passive filter composed of a resistor and a capacitor (R11, C11, etc.) is provided at the terminals (pads) of the signals VQ1 to VR3. Further, capacitors for stabilizing the potential (C4 and the like) are provided at the terminals of the signals VQ4 to VQ6.

  The integrated circuit device of FIG. 6 includes a first multiplexer MUX1, a second multiplexer MUX2, a third multiplexer MUX3, and an amplifier circuit AMP. These first multiplexer MUX1 to third multiplexer MUX3 and the amplifier circuit AMP constitute an analog front end circuit AFE. The integrated circuit device includes an A / D converter ADC, a control unit 50, and a power supply circuit 60. The integrated circuit device according to the present embodiment is not limited to the configuration shown in FIG. 6, and various modifications such as omitting some of the components or adding other components are possible.

  The first multiplexer MUX1 receives the first channel first signal VQ1 constituting the signal of the first channel CH1, the second channel first signal VQ2 constituting the signal of the second channel CH2, and the signal of the third channel CH3. The third channel first signal VQ3 to be configured is input, and the first signal SG1 is output. Specifically, in the first channel measurement period, the first channel first signal VQ1 is output as the first signal SG1. On the other hand, in the second channel measurement period, the second channel first signal VQ2 is output as the first signal SG1, and in the third channel measurement period, the third channel first signal VQ3 is output as the first signal SG1.

  The second multiplexer MUX2 receives the first channel second signal VR1 constituting the signal of the first channel CH1, the second channel second signal VR2 constituting the signal of the second channel CH2, and the signal of the third channel CH3. The third channel second signal VR3 to be configured is input, and the second signal SG2 is output. Specifically, in the first channel measurement period, the first channel second signal VR1 is output as the second signal SG2. On the other hand, in the second channel measurement period, the second channel second signal VR2 is output as the second signal SG2, and in the third channel measurement period, the third channel second signal VR3 is output as the second signal SG2.

  The amplifier circuit AMP receives the first signal SG1 from the first multiplexer MUX1 and the second signal SG2 from the second multiplexer MUX2. Then, a signal AMQ corresponding to the difference (difference voltage) between the first signal SG1 and the second signal SG2 is output. Here, the signal corresponding to the difference between the first and second signals SG1 and SG2 is the difference signal itself between the first and second signals SG1 and SG2, or a signal obtained by multiplying the difference signal by a gain.

  The third multiplexer MUX3 includes a signal AMQ from the amplifier circuit AMP, a signal VQ4 on the fourth channel CH4 from the sensor device 30 (acceleration sensor), a signal VQ5 on the fifth channel CH5, and a signal on the sixth channel CH6. VQ6 is input. The third multiplexer MUX3 outputs the signal AMQ from the amplifier circuit AMP as the third signal SG3 in the first channel measurement period, the second channel measurement period, and the third channel measurement period. Further, in the fourth channel measurement period, the signal VQ4 of the fourth channel CH4 is output as the third signal SG3, and in the fifth channel measurement period, the signal VQ5 of the fifth channel CH5 is output as the third signal SG3. In the sixth channel measurement period, the signal of the sixth channel CH6 is output as the third signal SG3.

  The A / D converter ADC performs A / D conversion on the third signal SG3 from the third multiplexer MUX3. Here, the A / D conversion for the third signal SG3 refers to A / D conversion of the third signal SG3 itself directly output from the third multiplexer MUX3, and other circuit elements from the third multiplexer MUX3. For example, A / D conversion of a signal input to the A / D converter ADC.

  The controller 50 performs various digital processes based on the digital data DQ from the A / D converter ADC. Specifically, the digital filter 52 of the control unit 50 performs digital filter processing based on the digital data DQ. The function of the control unit 50 can be realized by a logic circuit such as a gate array (G / A).

  The digital filter 52 performs low-pass filter processing with a cutoff frequency equal to or lower than ½ of the sampling frequency of the A / D converter ADC, and removes signals of frequency components other than the frequency component of the desired signal. For example, when the A / D converter ADC is sampling at a frequency of 1 kHz, the digital filter 52 performs a low-pass filter process with a cutoff frequency of 250 Hz or 125 Hz, for example. By performing the low-pass filter processing in the integrated circuit device in this way, it becomes possible to reduce the processing load of a subsequent microcomputer (MCU) connected to the integrated circuit device.

  The control unit 50 controls each circuit block in the integrated circuit device. For example, the control unit 50 outputs control signals SCAM, SCAD, and SCPW to control the amplifier circuit AMP, the A / D converter ADC, and the power supply circuit 60. Control signals SCM1, SCM2, and SCM3 are output to control signal selection in the multiplexers MUX1, MUX2, and MUX3.

  The power supply circuit 60 generates a power supply voltage VDDA for analog circuits and an analog ground voltage AGND (analog reference voltage). The generated power supply voltage VDDA is supplied to the amplifier circuit AMP and the A / D converter ADC, and the analog ground voltage AGND is supplied to the amplifier circuit AMP. The power supply circuit supplies the power supply voltage VDDA to the sensor device 30 via the power supply terminal.

  The amplifier circuit AMP and the A / D converter ADC operate based on the power supply voltage VDDA supplied from the power supply circuit 60. The amplifier circuit AMP is a voltage obtained by adding a voltage corresponding to the difference between the first and second signals SG1 and SG2 to the analog ground voltage AGND serving as the center voltage of the A / D conversion range of the A / D converter ADC. The signal is output as signal AMQ.

  FIG. 7 is an operation explanatory diagram of the configuration example of FIG. As shown in FIG. 7, in the first channel measurement period TCH1, the signals VQ1 and VR1 are selected by the multiplexers MUX1 and MUX2, respectively, and the amplifier circuit AMP outputs the differential voltage signal VDF1 between VQ1 and VR1 as the output signal AMQ. To do. The multiplexer MUX3 outputs the differential voltage signal VDF1 as the third signal SG3 to the A / D converter ADC. Similarly, in the second channel measurement period TCH2, the multiplexer MUX3 outputs the differential voltage signal VDF2 between the signals VQ2 and VR2 as the third signal SG3 to the A / D converter ADC. In the third channel measurement period TCH3, the multiplexer MUX3 outputs the differential voltage signal VDF3 between the signals VQ3 and VR3 as the third signal SG3 to the A / D converter ADC.

  On the other hand, in the fourth channel measurement period TCH4, the multiplexer MUX3 selects the signal VQ4 from the sensor device 30 and outputs it as the third signal SG3 to the A / D converter ADC. Similarly, the multiplexer MUX3 selects the signals VQ5 and VQ6 in the fifth and sixth channel measurement periods TCH5 and TCH6, respectively, and outputs them as the third signal SG3 to the A / D converter ADC.

  FIG. 8A is an explanatory diagram showing the relationship between the signals VQ1 and VQ2 and the signals VR1 and VR2. As shown in the figure, the first channel first signal VQ1 is a signal of the first detection voltage of the channel CH1, and the first channel second signal VR1 is a signal of the first reference voltage serving as a reference of the first detection voltage. It is. The second channel first signal VQ2 is a signal of the second detection voltage of the second channel, and the second channel second signal VR2 is a signal of the second reference voltage serving as a reference for the second detection voltage. The relationship between the third channel first signal VQ3 and the third channel second signal VR3 is also the same.

  In the following description, the detection voltages indicated by the signals VQ1, VQ2, and VQ3 are appropriately expressed as detection voltages VQ1, VQ2, and VQ3, and the reference voltages indicated by the signals VR1, VR2, and VR3 are appropriately set to the reference voltage VR1, It is written as VR2 and VR3.

  The gyro sensor 10 of the sensor device 30 in FIG. 6 includes an X-axis sensor that detects an angular velocity around the X axis, a Y-axis sensor that detects an angular velocity around the Y axis, and a Z-axis sensor that detects an angular velocity around the Z axis. Built in. That is, these independent X-axis sensor, Y-axis sensor, and Z-axis sensor are mounted in one package (housing). The X-axis sensor outputs signals VQ1 and VR1 of channel CH1, the Y-axis sensor outputs signals VQ2 and VR2 of channel CH2, and the Z-axis sensor outputs signals VQ3 and VR3 of channel CH3.

  The angular velocity around the X axis is represented by a differential voltage VDF1 between the detection voltage VQ1 and the reference voltage VR1, and the angular velocity around the Y axis is represented by a differential voltage VDF2 between the detection voltage VQ2 and the reference voltage VR2. The same applies to the angular velocity around the Z axis.

  In this case, the X-axis, Y-axis, and Z-axis sensors are composed of independent sensor units, so the reference voltage (analog ground voltage of each sensor unit) serving as a reference for the detection voltage varies depending on the process. The voltage becomes different because of the above. For example, in FIG. 8A, the reference voltage VR1 of the channel CH1 is lower than the reference voltage VR2 of the channel CH2, and there is a voltage difference ΔVR between VR1 and VR2.

  For example, FIG. 8B shows a configuration example of each sensor for the X axis, the Y axis, and the Z axis of the gyro sensor 10. Each sensor includes a vibrator 310 (physical quantity transducer in a broad sense), a drive circuit 320, and a detection circuit 330. The detection circuit 330 includes an amplification circuit 332, a synchronous detection circuit 334, and a filter unit 336. Then, the drive circuit 320 drives the vibrator 310 with the drive signal, and the detection signal from the vibrator 310 is input to the amplification circuit (QV conversion circuit) 332 of the detection circuit 330. The synchronous detection circuit 334 performs synchronous detection on the output signal of the amplifier circuit 332 based on the synchronous signal from the drive circuit 320 and extracts a desired signal. Then, the filter unit 336 performs low-pass filter processing for removing unnecessary signals, and outputs a signal of the detection voltage VQ (VQ1, VQ2, VQ3) and a signal of the reference voltage VR (VR1, VR2, VR3).

  Here, as shown in FIG. 8C, the detection voltage VQ is a DC voltage proportional to the angular velocity (dps). For example, the higher the angular velocity, the higher the voltage of VQ.

  The X-axis, Y-axis, and Z-axis sensors in FIG. 6 output the detection voltage and the reference voltage as a pair, and as shown in FIG. 8C, the difference voltage between the detection voltage and the reference voltage is It represents the magnitude of the angular velocity.

  Therefore, the multiplexer MUX1 in FIG. 6 selects the detection voltages VQ1, VQ2, and VQ3 and outputs them to the amplifier circuit AMP in each measurement period of the channels CH1, CH2, and CH3 as shown in FIG. Further, the multiplexer MUX2 selects the reference voltages VR1, VR2, and VR3 and outputs them to the amplifier circuit AMP in each measurement period of the channels CH1, CH2, and CH3. The amplifier circuit AMP generates differential voltages of VDF1 = VQ1-VR1, VDF2 = VQ2-VR2, and VDF3 = VQ3-VR3 in the measurement periods of the channels CH1, CH2, and CH3, respectively.

  As described above, according to the present embodiment, even when the X-axis, Y-axis, and Z-axis sensors in FIG. 6 output the detection voltage and the reference voltage as a pair, the differential voltage between the detection voltage and the reference voltage. Can be appropriately A / D converted by the A / D converter ADC. Therefore, as shown in FIG. 8A, even when the reference voltage is different between channels, high-accuracy measurement can be realized.

  According to the present embodiment, even when the sensor device 30 outputs a 6-channel signal as shown in FIG. 6, it is not necessary to provide six amplifier circuits, and only one amplifier circuit AMP is provided. It becomes like this. That is, the number of amplifier circuits AMP can be reduced by performing time division processing using the multiplexers MUX1, MUX2, and MUX3. As a result, the circuit scale of the integrated circuit device can be greatly reduced, and both improvement in detection accuracy and downsizing of the integrated circuit device can be achieved.

  In FIG. 6, the analog ground voltage AGND is supplied to the amplifier circuit AMP. As shown in FIG. 9A, the analog ground voltage AGND is the center voltage VCT of the A / D conversion range RAD of the A / D converter ADC.

  The amplifier circuit AMP outputs a voltage signal AMQ obtained by adding a voltage VDF (difference voltage between the detection voltage and the reference voltage) corresponding to the difference between the signals SG1 and SG2 to the analog ground voltage AGND that is the center voltage VCT.

  In this way, even when the angular velocity detection signal is transmitted by the differential voltage between the detection voltage and the reference voltage, the A / D conversion range RAD is set to a wide range centering on AGND, and the differential voltage is set to A / D. D conversion is possible. As a result, the A / D conversion of the angular velocity detection signal that makes the best use of the dynamic range of the A / D converter ADC becomes possible, and the detection accuracy can be improved.

  In addition, according to the configuration of FIG. 6, it is possible to provide an optimal measurement system for a 6-axis motion sensor including a 3-axis gyro sensor and a 3-axis acceleration sensor. That is, for the first and second signals constituting the angular velocity detection signal from the 6-axis motion sensor, the differential voltage signal is generated in the amplifier circuit AMP and can be A / D converted by the A / D converter ADC. On the other hand, the single-ended acceleration detection signal from the motion sensor can be input to the A / D converter ADC via the multiplexer MUX3 and A / D converted. Then, the three-channel angular velocity detection signal and the three-channel acceleration detection signal from the motion sensor are time-divisionally measured and A / D converted as shown in FIG. . Further, as described in FIG. 8A and the like, the angular velocity detection signal and the acceleration detection signal can be detected with high accuracy.

  For example, when the angular velocity and acceleration are integrated by a microcomputer at the subsequent stage to obtain the angle, velocity, and distance, if the DC offset of the angular velocity and acceleration is large, the DC offset is integrated and an error in the angle, velocity, and distance is obtained. There will be a situation that will become larger. When such a situation occurs, the electronic device on which the motion sensor is mounted is detected as rotating or moving even if the electronic device is not actually rotating or moving.

  In this regard, according to the present embodiment, the DC offset of angular velocity and acceleration can be minimized. Therefore, it is possible to prevent a situation in which an electronic device is detected as rotating or moving even if it is not actually rotating or moving.

  In the above description, the case where the first and second signals output from the channels CH1, CH2, and CH3 of the sensor device 30 are the detection voltage signal and the reference voltage signal as illustrated in FIG. However, the present embodiment is not limited to this. For example, as shown in FIG. 9B, the first signal and the second signal output from the channels CH1 to CH3 are differential signals VP and VN that are in a balanced relationship with a predetermined voltage level (center voltage) as a reference. There may be. That is, the first signal may be a positive signal constituting a differential signal, and the second signal may be a negative signal constituting a differential signal. Taking FIG. 6 as an example, the first channel first signal VQ1 and the first channel second signal VR1 are first differential signals in a balanced relationship with reference to a predetermined voltage level, and the second channel first signal VQ2 and the second channel second signal VR2 may be a second differential signal in a balanced relationship with a predetermined voltage level as a reference. The same applies to the signals VQ3 and VR3.

  Thus, even when the first and second signals are differential signals, multiplexers MUX1 and MUX2 are provided, the amplifier circuit AMP outputs a differential voltage, and the A / D converter ADC performs A / D conversion. This makes it possible to achieve both improvement in detection accuracy and downsizing of the integrated circuit device.

4). Amplifier Circuit FIG. 10A shows a configuration example of the amplifier circuit AMP. The amplifier circuit AMP is configured by a switched capacitor circuit that cancels the offset voltage of the operational amplifier OP included in the amplifier circuit AMP. Here, the offset voltage of the operational amplifier OP is an input conversion offset voltage, for example, an offset voltage between the first and second input nodes NI1 and NI2 of the operational amplifier OP.

  Note that the amplifier circuit AMP of the present embodiment is not limited to the configuration of FIG. 10A, and various components such as omitting some of the components, adding other components, and changing the connection relationship thereof. Can be implemented. A circuit that is not a switched capacitor circuit (for example, a circuit having an amplifier, a D / A converter, and an offset adjustment register) may be used as the amplifier circuit AMP.

  The amplifier circuit AMP in FIG. 10A includes an operational amplifier OP and an offset canceling capacitor COF. The offset canceling capacitor COF has a first input node NI1 (inverted input node) of an operational amplifier OP (voltage-follower-connected operational amplifier) whose analog input voltage AGND is set at the second input node NI2 (non-inverted input node). And the ANGD node. Then, charges corresponding to the offset voltage of the operational amplifier OP are stored (accumulated). Specifically, one end of the capacitor COF is connected to the first input node NI1 and to the output node NPQ of the operational amplifier OP via the switch element SW3. On the other hand, the other end of the capacitor COF is connected to the AGND node via the switch element SW1.

  The second input node (non-inverting input node) of the operational amplifier OP is set to the analog ground voltage AGND. By doing so, as described with reference to FIG. 9A, the amplifier circuit AMP generates the first and second signals with respect to the analog ground voltage AGND serving as the center voltage VCT of the A / D conversion range RAD. It becomes possible to output a voltage signal obtained by adding the differential voltages.

  The amplifier circuit AMP includes a sampling capacitor CS provided between the input node NI of the amplifier circuit AMP and the first input node NI1 of the operational amplifier OP. Specifically, one end of the sampling capacitor CS is connected to the first input node NI1 of the operational amplifier OP, and the other ends of the sampling capacitor CS are the first sampling switch element SWS1 and the second sampling switch element SWS2. Connected to the other end. The first signal SG1 and the second signal SG2 are input to one ends of the first sampling switch element SWS1 and the second sampling switch element SWS2, respectively.

  As shown in FIG. 10A, the offset canceling capacitor COF is provided between the first input node NI1 and the first node NOF of the operational amplifier OP. The amplifier circuit AMP further includes a first switch element SW1, a second switch element SW2, and a third switch element SW3.

  The first switch element SW1 is provided between the first node NOF and the node of the analog ground voltage AGND. The first switch element SW1 is turned on in the first period T1, and is turned off in the second period T2.

  The second switch element SW2 is provided between the first node NOF and the output node NPQ of the operational amplifier OP. The second switch element SW2 is turned off in the first period T1 and turned on in the second period T2.

  The third switch element SW3 is provided between the output node NPQ and the first input node NI1 of the operational amplifier OP. The third switch element SW3 is turned on in the first period T1, and is turned off in the second period T2.

  The amplifier circuit AMP includes a fourth switch element SW4. The fourth switch element SW4 is provided between the output node NPQ of the operational amplifier OP and the output node NQ of the amplifier circuit AMP. The fourth switch element SW4 is turned off in the first period T1, and turned on in the second period T2.

  The switch elements SW1 to SW4, SWS1, and SWS2 are realized by, for example, CMOS transistors (N-type transistors), transfer gates, and the like. In this embodiment, the case where the period following the first period T1 is the second period T2 will be described as an example. However, the period following the second period T2 may be the first period T1.

  FIG. 11 is a signal waveform diagram for explaining the operation of the amplifier circuit AMP. In FIG. 11, the H level of the signal indicates that the corresponding switch element is on, and the L level of the signal indicates that the corresponding switch element is off.

  FIG. 10A shows the on / off state of each switch element in the first period T1, which is the sampling period of the switched capacitor circuit, and FIG. 10B shows the hold period (output period). The ON / OFF state of each switch element in the second period T2 is shown.

  As shown in FIGS. 10A and 11, in the first period T1, the switch elements SWS1, SW1, and SW3 are turned on, and the switch elements SWS2, SW2, and SW4 are turned off. When the switch elements SWS1 and SW1 are turned on, a charge corresponding to a differential voltage between the voltage of the signal SG1 and the voltage obtained by adding the offset voltage of the operational amplifier OP to the analog ground voltage AGND is accumulated in the capacitor CS. When the switch element SW3 is turned on, the operational amplifier OP becomes a so-called voltage follower connection, and charges corresponding to the offset voltage of the operational amplifier OP are accumulated in the capacitor COF. Further, when the switch element SW4 is turned off, the connection between the output node NPQ of the operational amplifier OP and the output node NQ of the amplifier circuit AMP is cut off.

  As shown in FIGS. 10B and 11, in the second period T2, the switch elements SWS2, SW2, and SW4 are turned on, and the switch elements SWS1, SW1, and SW3 are turned off. When the switch elements SWS2, SW2, and SW4 are turned on, a voltage obtained by adding the differential voltage between the signals SG1 and SG2 to the analog ground voltage AGND is output to the output node NQ of the amplifier circuit AMP.

  For example, in FIG. 10A, the voltages of the signals SG1 and SG2 are represented as VQ and VR, respectively, and the capacitance values of the capacitors CS and COF are represented as C1 and C2. Further, the offset voltage of the operational amplifier OP is represented as VOF, and the analog ground voltage is represented as AGND.

  Then, in the first period T1 in FIG. 10A, the potential of the node NI becomes VQ, the potential of the node NI1 becomes AGND + VOF, and the potential of the node NOF becomes AGND. Therefore, the electric charges Q1 and Q2 accumulated in the capacitors CS and COF are expressed by the following expressions (1) and (2).

Q1 = C1. (VQ-AGND-VOF) (1)
Q2 = -C2 · VOF (2)
On the other hand, the output voltage of the node NQ in the second period T2 in FIG. Then, in the second period T2, the potential of the node NI becomes VR, the potential of the node NI1 becomes AGND + VOF, and the potential of the node NOF becomes VPQ. Accordingly, the electric charges Q1 ′ and Q2 ′ accumulated in the capacitors CS and COF are expressed by the following equations (3) and (4).

Q1 '= C1. (VR-AGND-VOF) (3)
Q2 ′ = C2 · (VPQ−AGND−VOF) (4)
Then, the following equation (5) is established by the law of charge conservation.

Q1 + Q2 = Q1 ′ + Q2 ′ (5)
Then, the following expression (6) is obtained by substituting the above expressions (1) to (4) into the above expression (5).

VPQ = (C1 / C2). (QV-VR) + AGND (6)
Therefore, as described in FIG. 9A, the voltage VDF = (C1 / C2) · (QV−VR) corresponding to the difference between the signals SG1 and SG2 is added to AGND at the output node NQ of the amplifier circuit AMP. The output voltage VPQ is output.

  Further, as apparent from the above equation (6), the offset voltage VOF of the operational amplifier OP is canceled and does not appear in the output voltage VPQ. Therefore, a so-called offset-free amplifier circuit AMP can be realized.

  That is, in the above-described prior art of Patent Document 1, a plurality of D / A converters and a plurality of offset adjustment registers are required to cancel the offset voltage of an operational amplifier or the like, which increases the circuit scale. is there. In particular, in order to increase the accuracy of measurement, the number of bits of the D / A converter becomes large, which leads to further scale-up of the circuit. Further, the conventional technique has a problem that the offset cancellation process becomes complicated and the processing load of the control unit becomes excessive.

  In this regard, according to the amplifier circuit AMP having the configuration of FIG. 10A, the offset voltage of the operational amplifier OP is canceled by analog processing. By canceling the offset voltage of the operational amplifier OP in this way, the output voltage VPQ, which is the measurement voltage, is also highly accurate, and the sensor output can be measured with high accuracy. Further, since a D / A converter and an offset adjustment register are not required, the circuit scale can be greatly reduced and power saving can be realized. In addition, there is an advantage that high-precision measurement is possible without using a D / A converter having a large number of bits.

  Particularly when the number of channels of the sensor device is large as shown in FIG. 6, it is effective to use the amplifier circuit AMP of the switched capacitor circuit as shown in FIG. That is, by using a switched capacitor circuit having an offset cancel function as the amplifier circuit AMP, signals of a plurality of channels can be measured with high accuracy in a time division manner. Further, it is not necessary to provide an amplifier circuit corresponding to each channel as in the prior art, and it is only necessary to provide one amplifier circuit AMP. Therefore, the circuit can be reduced in size and power consumption can be realized. Further, since the control process of the control unit 50 is merely switching the signal selection of the multiplexers MUX1, MUX2, and MUX3 and controlling the operation of the amplifier circuit AMP and the A / D converter ADC, the processing load on the control unit 50 can be reduced. .

  Note that the sampling switch elements SWS1 and SWS2 in FIGS. 10A and 10B can be shared with the switch elements of the multiplexers MUX1 and MUX2 in FIG. FIG. 12 is a diagram illustrating a configuration example in the case where the switching elements of the multiplexers MUX1 and MUX2 are shared as described above.

  For example, in the first channel measurement period TCH1, the functions of the switch elements SWS1 and SWS2 of FIGS. 10A and 10B are realized by the switch elements SWQ1 and SWR1 of the multiplexers MUX1 and MUX2 of FIG.

  That is, in the first period T1 of the first channel measurement period TCH1, the switch element SWQ1 in FIG. 12 is turned on and the switch element SWR1 is turned off. Accordingly, the switch element SWS1 shown in FIG. 10A is turned on and the switch element SWS2 is turned off, and the detection voltage VQ1 is applied to one end of the capacitor CS.

  In the second period T2 of the first channel measurement period TCH1, the switch element SWQ1 in FIG. 12 is turned off and the switch element SWR1 is turned on. Thus, the switching element SWS1 and the switching element SWS2 shown in FIG. 10B are turned off and the reference voltage VR1 is applied to one end of the capacitor CS.

  In the second channel measurement period TCH2, the functions of the switch elements SWS1 and SWS2 in FIGS. 10A and 10B are realized by the switch elements SWQ2 and SWR2 of the multiplexers MUX1 and MUX2.

  That is, in the first period T1 of the second channel measurement period TCH2, the switch element SWQ2 is turned on and the switch element SWR2 is turned off. Accordingly, the switch element SWS1 shown in FIG. 10A is turned on and the switch element SWS2 is turned off, and the detection voltage VQ2 is applied to one end of the capacitor CS.

  In the second period T2 of the second channel measurement period TCH2, the switch element SWQ2 is turned off and the switch element SWR2 is turned on. Thus, the switching element SWS1 and the switching element SWS2 shown in FIG. 10B are turned off and the reference voltage VR2 is applied to one end of the capacitor CS.

  The third channel measurement period TCH3 is the same as described above, and the functions of the switch elements SWS1 and SWS2 are realized by the switch elements SWQ3 and SWR3 of the multiplexers MUX1 and MUX2.

  Thus, by sharing the switching element of the multiplexer and the sampling switching element of the switched capacitor circuit, the circuit can be further reduced in size and simplified.

5. Integrated Circuit Device Layout FIG. 13 shows an example layout layout of an integrated circuit device (IC) of this embodiment. In the integrated circuit device of FIG. 13, the amplifier circuit AMP and multiplexers MUX1, MUX2, and MUX3, the A / D converter ADC, the control unit 50 (gate array circuit), and the power supply circuit 60 that constitute the analog front end circuit AFE. Is laid out.

  In the I / O region RIO1, terminals (pads) for signals VQ1 to VR3 from the gyro sensor 10 of FIG. 6 are arranged. The signal lines of the signals VQ1 to VR3 are wired from the I / O region RIO1 to the multiplexers MUX1 and MUX2, and the signals VQ1 to VR3 are input to the multiplexers MUX1 and MUX2. The signal lines of the output signals SG1 and SG2 of the multiplexers MUX1 and MUX2 are wired from the multiplexers MUX1 and MUX2 to the amplifier circuit AMP.

  Further, terminals (pads) for signals VQ4 to VQ6 from the acceleration sensor 20 are arranged in the I / O region RIO2. Then, signal lines for the signals VQ4 to VQ6 are wired from the I / O region RIO2 to the multiplexer MUX3, and the signals VQ4 to VQ6 are input to the multiplexer MUX3. The signal line of the output signal AMQ of the amplifier circuit AMP is input from the amplifier circuit AMP to the multiplexer MUX3. A signal line of the output signal SG3 of the multiplexer MUX3 is wired from the multiplexer MUX3 to the A / D converter ADC.

  As shown in FIG. 13, the multiplexers MUX1, MUX2, and MUX3 are laid out between the amplifier circuit AMP and the A / D converter ADC. For example, in FIG. 13, the first direction is D1, the direction orthogonal to D1 is the second direction D2, the opposite direction of the first direction D1 is the third direction D3, and the opposite direction of the second direction D2 is The fourth direction is D4. Then, the amplifier circuit AMP is disposed on the D2 direction side of the multiplexers MUX1 and MUX2. A multiplexer MUX3 is arranged on the D4 direction side of the multiplexers MUX1 and MUX2. An A / D converter ADC is arranged on the D4 direction side of the multiplexer MUX3.

  Then, the multiplexers MUX1, MUX2, and MUX3 are arranged between the amplifier circuit AMP and the A / D converter ADC in this way, so that the signals VQ1 to VR3 from the I / O region RIO1 are converted into the multiplexers MUX1 and MUX2. Thus, the signal can be efficiently input to the amplifier circuit AMP. Further, the signals VQ4 to VQ6 from the I / O region RIO2 can be efficiently input to the A / D converter ADC via the multiplexer MUX3. As a result, it is possible to minimize such a situation that the voltages of the signals VQ1 to VR3 and VQ4 to VQ6 fluctuate due to noise or the like, or a voltage drop occurs. In addition, even when the sensor device 30 has a large number of channels, the size of the wiring regions of the signals VQ1 to VR3 and VQ4 to VQ6 from the sensor device 30 can be minimized, thereby reducing the area of the integrated circuit device. I can plan.

  In FIG. 13, a power supply circuit 60 is disposed on the D1 direction side of the A / D converter ADC. The control unit 50 is disposed on the D2 direction side of the power supply circuit 60 and on the D1 direction side of the analog front end circuit AFE. With such an arrangement, it is possible to realize an efficient layout arrangement of the control unit 50 that is a digital circuit block, the power supply circuit 60 that is an analog circuit block, an analog front-end circuit AFE, an A / D converter ADC, and the like. .

  In FIG. 13, a terminal (pad) PVDA of the power supply voltage VDDA is arranged on the D4 direction side of the power supply circuit 60. In other words, the VDDA terminal PVDA is arranged in the immediate vicinity of the power supply circuit 60. The power supply circuit 60 supplies the generated power supply voltage VDDA to the external sensor device 30 via the terminal PVDA. At this time, by arranging the terminal PVDA in the vicinity of the power supply circuit 60, it is possible to minimize a voltage drop or the like of VDDA when the power supply voltage VDDA is supplied to the sensor device 30. Since the voltage drop of the power supply voltage VDDA is minimized, a ratiometric relationship is maintained between the power supply voltage of the sensor device 30 and the power supply voltage of the A / D converter ADC as described in FIG. The measurement accuracy of the sensor detection signal can be improved.

  In FIG. 13, the A / D converter ADC is laid out at a position closer to the power supply circuit 60 than the analog front-end circuit AFE (amplifier circuit AMP, multiplexers MUX1 to MUX3). That is, the distance between the power supply circuit 60 and the A / D converter ADC is shorter than the distance between the power supply circuit 60 and the analog front end circuit AFE.

  For example, the power supply circuit 60 supplies the generated power supply voltage VDDA to the A / D conversion ADC and the amplifier circuit AMP via the power supply line. As described with reference to FIG. 2, if the ratiometric relationship is not maintained between the power supply voltage of the sensor device 30 and the power supply voltage of the A / D converter ADC, the measurement accuracy of the sensor detection signal deteriorates.

  In this regard, in FIG. 13, the A / D converter ADC is laid out at a position closer to the power supply circuit 60 than the analog front end circuit AFE (amplifier circuit AMP, etc.), and the power supply circuit 60 and the A / D converter are arranged. A VDDA power line is connected to the ADC through a short path. Therefore, the voltage drop of VDDA when the power supply voltage VDDA is supplied from the power supply circuit 60 to the A / D converter ADC can be minimized. Therefore, a ratiometric relationship is maintained between the power supply voltage of the sensor device 30 and the power supply voltage of the A / D converter ADC, and the measurement accuracy of the sensor detection signal can be improved.

  In this way, in FIG. 13, since both the power supply line from the power supply circuit 60 to the power supply terminal PVDA and the power supply line from the power supply circuit 60 to the A / D converter ADC can be connected by a short path, the sensor detection signal is measured. The accuracy can be further improved.

6). Electronic Device Next, a configuration example of an electronic device including the integrated circuit device of the present embodiment will be described with reference to FIG. Note that the electronic apparatus of the present embodiment is not limited to the configuration shown in FIG. 14, and various modifications such as omitting some of the components or adding other components are possible.

  The electronic apparatus of FIG. 14 includes the sensor device 30 and the integrated circuit device 500 of the present embodiment. Further, a processing unit 510, a storage unit 520, a wireless circuit 530, and an antenna 540 can be included.

  The sensor device 30 (physical quantity transducer) detects various physical quantities (angular velocity, acceleration, angular acceleration, force, mass, etc.). Then, the physical quantity is converted into current (charge), voltage or the like and output as a detection signal.

  The integrated circuit device 500 receives the detection signal from the sensor device 30, performs A / D conversion of the detection signal, and performs arithmetic processing (signal processing) on the digital data after A / D conversion if necessary. Then, the obtained digital data is output to the processing unit 510 or the like.

  The processing unit 510 performs various digital processes on the digital data. The function of the processing unit 510 is realized by, for example, a microcomputer. The storage unit 520 temporarily stores digital data and the like. The function of the storage unit 520 is realized by a memory such as a RAM.

  The radio circuit 530 performs modulation processing on the digital data obtained by the integrated circuit device 500 and transmits the digital data to an external device (an electronic device on the other side) using the antenna 540. The antenna 540 may be used to receive data from an external device and perform ID authentication, control the sensor device 30, and the like.

  According to the configuration of FIG. 14, information detected by the sensor device 30 can be transmitted to an external device, and various electronic devices having a wireless function and a sensor function can be realized.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, a term described at least once together with a different term having a broader meaning or the same meaning in the specification or the drawings can be replaced with the different term in any part of the specification or the drawings. Further, the configurations and operations of the integrated circuit device and the electronic device are not limited to those described in this embodiment, and various modifications can be made.

AFE analog front end circuit, AMP amplifier circuit, ADC A / D converter,
PVDA power supply terminal, VDDA power supply voltage,
AGND Analog ground voltage, RAD A / D conversion range,
REG regulator, OPR, OPAG operational amplifier, R1-RN resistance,
RLAC ladder resistor circuit, RAJC power supply voltage setting resistor circuit,
SEL1 first selection circuit, SEL2 second selection circuit,
TP11 to TP1i, TP21 to TP2j, TP31 to TP3k Voltage dividing tap,
SW11 to SW1i, SW21 to SW2j, SW31 to SW3k switch elements,
MUX1 to MUX3 first multiplexer to third multiplexer,
CH1 to CH6 1st channel to 6th channel,
VQ1 to VQ3 first channel first signal to third channel first signal,
VR1 to VR3 first channel second signal to third channel second signal,
VQ4 to VQ6 4th channel to 6th channel signals,
TCH1 to TCH6 1st channel measurement period to 6th channel measurement period,
OP operational amplifier, SW1 to SW4, SWS1, SWS2 switch element,
CS sampling capacitor, COF offset canceling capacitor,
10 gyro sensor, 20 acceleration sensor, 30 sensor device,
50 control unit, 52 digital filter, 60 power supply circuit,
62 reference voltage generating circuit, 64 voltage dividing circuit,
310 vibrator, 320 drive circuit, 330 detection circuit, 332 amplification circuit,
334 Synchronous detection circuit, 336 filter unit, 500 integrated circuit device,
510 processing unit, 520 storage unit, 530 wireless circuit, 540 antenna

Claims (16)

A power supply circuit for generating a power supply voltage and supplying the power supply voltage to the sensor device ;
Operates on the basis of the previous SL power supply voltage, the A / D conversion range defined by the power supply voltage, and A / D converter for performing A / D conversion of the signal corresponding to the detection signal from the sensor device,
An analog front-end circuit that operates based on the power supply voltage;
Only including,
The detection signal is
A first channel first signal and a first channel second signal that the sensor device detects and outputs a first physical quantity;
A second channel first signal and a second channel second signal output by the sensor device detecting and outputting a second physical quantity;
Including
The analog front-end circuit is
The first channel first signal and the second channel first signal are input, the first channel first signal is output during a first channel measurement period, and the second channel first signal is output during a second channel measurement period. A first multiplexer that outputs one signal;
The first channel second signal and the second channel second signal are input, the first channel second signal is output in the first channel measurement period, and the second channel measurement period is the second channel measurement period. A second multiplexer for outputting a channel second signal;
An amplifier circuit to which a signal from the first multiplexer and a signal from the second multiplexer are input;
Integrated circuit device, which comprises a. In claim 1,
  The first channel first signal and the first channel second signal are a first differential signal in a balanced relationship with a predetermined voltage level as a reference,
  The integrated circuit device, wherein the second channel first signal and the second channel second signal are second differential signals in a balanced relationship with a predetermined voltage level as a reference. In claim 1 or 2,
The first channel first signal and the first channel second signal are signals that have been synchronously detected by amplifying a signal from a first physical quantity transducer that detects the first physical quantity of the sensor device. ,
The second channel first signal and the second channel second signal are signals that have been synchronously detected by amplifying a signal from a second physical quantity transducer that detects the second physical quantity of the sensor device. An integrated circuit device. In any one of Claims 1 thru | or 3,
The detection signal includes a third channel first signal and a third channel second signal that the sensor device detects and outputs a third physical quantity,
  The first multiplexer includes:
  The third channel first signal is input, and the third channel first signal is output in a third channel measurement period,
  The second multiplexer is
  The integrated circuit device, wherein the third channel second signal is input, and the third channel second signal is output in the third channel measurement period. In any one of Claims 1 thru | or 4 ,
The integrated circuit device, wherein the A / D converter is laid out at a position closer to the power supply circuit than the analog front end circuit. In any one of Claims 1 thru | or 5,
  The integrated circuit device, wherein the A / D converter performs A / D conversion of a signal input via the amplifier circuit. In any one of Claims 1 thru | or 6 ,
The power supply circuit is
A reference voltage generation circuit for generating a reference voltage;
And a regulator that generates the power supply voltage based on the generated reference voltage. In claim 7 ,
The regulator is
A voltage dividing circuit that divides a voltage between the power supply voltage and a low-potential-side power supply voltage that is lower than the power supply voltage, and outputs the voltage from a voltage dividing tap ;
The reference voltage is supplied to the first input node, the integrated circuit device, which comprises an operational amplifier a voltage from said voltage division tap is supplied to the second input node. In claim 8 ,
The voltage divider circuit is:
A ladder resistor circuit having a plurality of resistors and outputting a divided voltage to each of a plurality of voltage dividing taps of the plurality of resistors;
A power supply voltage setting resistor circuit provided in series with the ladder resistor circuit and having a variable resistance value;
One voltage division tap of the plurality of voltage division taps of the ladder resistor circuit is selected as a voltage fine adjustment tap, and a voltage from the selected voltage fine adjustment tap is selected as the second voltage of the operational amplifier. And a first selection circuit for supplying the input node. In claim 9 ,
Before Symbol voltage divider circuit,
One voltage division tap of the plurality of voltage division taps of the ladder resistor circuit is selected as an analog ground tap, and an analog ground voltage from the selected analog ground tap is selected with respect to the analog front end circuit. An integrated circuit device comprising a second selection circuit to be supplied. In claim 10 ,
The second selection circuit includes:
An integrated circuit device, wherein a voltage division tap corresponding to a power supply voltage setting result in the power supply voltage setting resistor circuit is selected as the analog ground tap from the plurality of voltage division taps. In claim 8 or 9 ,
Before Symbol regulators,
An integrated circuit device, wherein an analog ground voltage from an analog ground tap of the voltage dividing circuit is supplied to the analog front end circuit. In claim 12 ,
The amplifier circuit of the analog front end circuit is:
Integrated circuit device the analog ground voltage is characterized that you outputting a signal which becomes a center voltage of the A / D conversion range on the A / D converter. In claim 13 ,
The amplifier circuit is
In the first channel measurement period, relative to the analog ground voltage, and outputs a voltage signal obtained by adding a voltage corresponding to a difference between the first channel first signal and said first channel second signal,
In the second channel measurement period, relative to the analog ground voltage, and outputs a voltage signal obtained by adding a voltage corresponding to a difference between the second channel first signal and the second channel second signal Integrated circuit device. An electronic apparatus comprising the integrated circuit device according to any one of claims 1 to 14. A power supply circuit for generating a power supply voltage;
  A first physical quantity transducer for detecting a first physical quantity;
  A second physical quantity transducer for detecting a second physical quantity;
  It operates based on the power supply voltage, outputs a first channel first signal and a first channel second signal based on a signal from the first physical quantity transducer, and outputs a signal from the second physical quantity transducer. A circuit for outputting a second channel first signal and a second channel second signal based on,
  An A / D converter operating based on the power supply voltage;
  An analog front-end circuit that operates based on the power supply voltage;
  Including
  The analog front-end circuit is
  The first channel first signal and the second channel first signal are input, the first channel first signal is output during a first channel measurement period, and the second channel first signal is output during a second channel measurement period. A first multiplexer that outputs one signal;
  The first channel second signal and the second channel second signal are input, the first channel second signal is output in the first channel measurement period, and the second channel measurement period is the second channel measurement period. A second multiplexer for outputting a channel second signal;
  An amplifier circuit to which a signal from the first multiplexer and a signal from the second multiplexer are input;
  Including
  The A / D converter performs an A / D conversion on a signal from the amplifier circuit in an A / D conversion range defined by the power supply voltage.

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