JP5809492B2 - Complementary metal oxide semiconductor (CMOS) time-delay integration (TDI) sensor for X-ray imaging applications - Google Patents

Description

  The present invention relates generally to the field of solid state image sensors, and more particularly to complementary metal oxide semiconductor (CMOS) time delay integration (TDI) sensors for use in X-ray image scan applications.

  The present invention relates to a time delay integration (TDI) type complementary metal oxide semiconductor (CMOS) linear image sensor applied to high-speed X-ray image scanning applications. Time delay integration (TDI) image sensors have very low integrated input optical signals when used in high speed line scan applications. In normal line scan applications, one way to increase the integrated input optical signal is to decrease the scan speed, which increases the integration time. This time delay integration (TDI) sensor increases the optical signal of the line scan detector system without sacrificing scan speed. This time delay integration (TDI) sensor is typically implemented using a charge transfer device such as a charge coupled device (CCD).

In a charge coupled device (CCD) time delay integration (TDI) array, each detector pixel contains N stages of time delay integration (TDI) locations. For example, an M-pixel linear detector includes a two-dimensional M × N stage charge coupled device (CCD) array, and each pixel has N stages of charge coupled devices (CCD) parallel to the scanning direction. During the operation of the first stage charge coupled device (CCD), the optical signal is integrated in an integration time corresponding to one line time (Line Time).
This signal charge moves from the first stage of the charge coupled device (CCD) to the second stage, and the object to be scanned also moves from the first stage of the charge coupled device (CCD) to the second stage in synchronization with the movement of the signal charge. Move to the stage. This second stage charge coupled device (CCD) integrates signal charge for the same object during a second integration time. Therefore, at the end of the integration time, the signal charge of the second stage charge coupled device (CCD) is twice the signal charge received from the first stage.
Subsequently, the signal charge of the second stage charge coupled device (CCD) moves to the third stage in synchronization with the movement of the object. In addition to receiving the signal from the second stage, the third stage charge coupled device (CCD) integrates the optical signal again. When this process is repeated and the final N-stage charge coupled device (CCD) is reached, the optical signal increases N times. Then, signals of M pixels are sequentially read using an output charge coupled device (CCD) shift register.

This charge coupled device (CCD) time delay integration (TDI) imaging system is widely used in visible high speed industrial inspection applications such as computed tomography (CT scan) and dental panoramic tomography and medical X-ray scanning applications. However, X-ray industrial inspection applications have certain drawbacks.
In an X-ray industrial inspection system, the pixel size of this detector is usually considerably larger than the pixel size of a normal charge coupled device (CCD) sensor. In this type of application, the required pixel size range is from a few millimeters to tens of millimeters. As the pixel size increases, the charge-coupled device (CCD) scan speed drops significantly, making it unsuitable for this type of application.

  A second drawback of this charge coupled device (CCD) time delay integration (TDI) imaging system is that it is very susceptible to damage by X-ray radiation. In medical x-ray scanning applications, the x-ray energy and dose used are typically much lower than industrial inspection applications. In medical applications, the X-ray dose is not only regulated by the US Food and Drug Administration (FDA), but because of human soft tissue, the amount of energy is usually lower than 100K electron volts (ev). For industrial applications, it is determined according to the type of test material required, and the range of energy used is from 50K eV to 15M eV. In industrial inspection systems, there is no regulation of X-ray dose, so the dose used is much higher than the dose used for medical scan systems. Accumulation of radiation exposure of charge-coupled device (CCD) sensors under x-rays increases its dark current and shifts its well-type potential, which may reduce its usable life.

  It is an object of the present invention to implement a complementary metal oxide semiconductor (CMOS) detector system that can alleviate the drawbacks of charge coupled device (CCD) detectors in X-ray industrial inspection systems. Signal charges in the charge region do not move from one complementary metal oxide semiconductor (CMOS) circuit to another complementary metal oxide semiconductor (CMOS) circuit, so a complementary metal oxide semiconductor (CMOS) circuit It is more difficult to implement a time delay integration (TDI) sensor using

  Accordingly, it is an object of the present invention to provide a time delay integration (TDI) image sensor structure that can be implemented using standard complementary metal oxide semiconductor (CMOS) fabrication processes.

  Another object of the present invention is a time delay integration (TDI) image sensor detector that is suitable for use in systems with greater pixel-to-pixel distances, such as X-ray industrial inspection systems, without sacrificing readout speed. To provide a system.

  A further object of the present invention is to allow complementary metal oxide semiconductor (CMOS) circuits to be separated from photodiode detectors so that the complementary metal oxide semiconductor (CMOS) circuits can be easily shielded and damaged by X-ray radiation. Is to provide a time delay integration (TDI) detection system.

The present invention integrates an input optical signal using a photodiode as a detector. Each time delay integration (TDI) stage (number of stages) includes a photodiode detector, a plurality of amplifiers, a plurality of storage capacitors, and a plurality of switches. Each photodiode is connected to an integrating amplifier, an adder circuit, and a plurality of storage circuits. This integral sum function can be performed in single or multiple amplifiers. This storage circuit is implemented using a storage capacitor and a buffer amplifier.
The photo signal and reset voltage are simultaneously held using correlated double sample and hold (CDS) technology. A correlated double sample and hold (CDS) photo signal (signal and reset) voltage is transmitted to the next time delay integration (TDI) stage for addition and no offset noise accumulates. The next time delay integration (TDI) stage in the sequence not only integrates the photo signal during one integration time (line time), but also the correlated double sample hold accumulated from the previous time delay integration (TDI) stage. (CDS) voltage is received. The summing circuit combines the current and the correlated double sample and hold (CDS) photo signal of the previous time delay integration (TDI) stage and outputs this new correlated double sample and hold (CDS) voltage to the storage circuit. The accumulated correlated double sample and hold (CDS) voltage is transmitted to the next time delay integration (TDI) stage.
By repeating this process until the final time delay integration (TDI) stage is reached, the differential amplifier reads the correlated double sample and hold (CDS) signal. Typically, reading is performed using a digital scan shift register similar to a standard complementary metal oxide semiconductor (CMOS) linear photodiode array (PDA). The operation of this time delay integration (TDI) function includes charge integration, addition, and accumulation and transfer of correlated double sample and hold (CDS) signals, which are controlled by multiple control switches and a set of timing signals. The

There are a number of advantages of the present invention for implementing a time delay integration (TDI) sensor using complementary metal oxide semiconductor (CMOS) circuits. First, any peripheral device such as an amplifier, timing generator or driver can be integrated with a photodiode using standard commercial complementary metal oxide semiconductor (CMOS) manufacturing processes. It can then be implemented with large pixel size detectors, such as 0.8 millimeters to several millimeters pixel sizes.
This is particularly beneficial for X-ray scanning applications where the required pixel size is large, such as inspection of cargo containers or oil transport pipes. It is well known that charge coupled devices (CCDs) are excellent for operation with smaller pixel sizes. When the pixel size increases, the speed of the charge coupled device (CCD) decreases significantly. Thus, complementary metal oxide semiconductor (CMOS) time delay integration (TDI) sensors are suitable for use in X-ray industrial scan applications.
Third, it is well known that charge coupled devices (CCD) and complementary metal oxide semiconductor (CMOS) circuits are susceptible to damage from X-ray radiation. During this complementary metal oxide semiconductor (CMOS) implementation, the peripheral circuits are integrated on the same chip as the photodiode array, but the photodiode detectors have sufficient spacing or gaps. Therefore, the peripheral circuit can be covered with a heavy metal such as lead and shielded to easily avoid damage caused by X-ray radiation.

  The advantage of implementing a time delay integration (TDI) detector system using a complementary metal oxide semiconductor (CMOS) circuit is that any standard complementary metal oxide semiconductor (CMOS) manufacturing process can be used during any operation. The clock pulse generator and the signal processing circuit can be integrated on a single chip. Thereby, manufacturing cost can be reduced.

  Another advantage of implementing an X-ray time delay integration (TDI) detector system using complementary metal oxide semiconductor (CMOS) circuits is that it can be performed at larger pixel sizes and at very high scan rates. is there.

  A further advantage of using a complementary metal oxide semiconductor (CMOS) circuit to implement a time delay integration (TDI) detector system is that the complementary metal oxide semiconductor (CMOS) circuit and the photodiode can be separated. . Thereby, a complementary metal oxide semiconductor (CMOS) circuit can be appropriately shielded to avoid damage caused by X-ray radiation.

FIG. 2 shows a complementary metal oxide semiconductor (CMOS) time delay integration (TDI) stage of the present invention. FIG. 2 is a diagram showing one row of TDI pixels having N TDI stages and a block diagram of a digital scan shift register. It is a block diagram which shows that an output differential amplifier reads a video signal. It is a timing chart of TDI sensor operation. FIG. 3 shows another preferred embodiment of the present invention. It is another timing chart of TDI sensor operation.

  In order that the foregoing and other objects and advantages of the present invention will become apparent to those skilled in the art, the best mode for carrying out the present invention will now be described with reference to the drawings.

  1-4 illustrate a preferred embodiment of the present invention. FIG. 1 shows a circuit diagram of a time delay integration (TDI) stage 100. FIG. 2 shows a pixel circuit diagram of a linear detector of an N-stage time delay integration (TDI) stage. The M pixel array includes M rows of circuits as shown in FIG. FIG. 3 shows a block diagram of a correlated double sample and hold (CDS) differential amplifier when reading a signal in the last time delay integration (TDI) stage. FIG. 4 shows a timing chart of the time delay integration (TDI) sensor operation.

As shown in FIG. 1, each time delay integration (TDI) stage 100 includes a photodiode 101, a summing capacitor 102, an integrating summing amplifier 103, and a correlated double sample and hold (CDS) circuit 104. The integration summing amplifier 103 includes an amplifier A1, an integration capacitor C1, and a reset switch SW1. The integration capacitor C1 and the reset switch SW1 are connected via the input and output terminals of the amplifier A1. A correlated double sample and hold (CDS) circuit 104 includes two input switches SW2 and SW3, a first storage circuit including a capacitor C2 and a buffer amplifier A2, a transfer switch SW4, a second including a capacitor C3 and a buffer amplifier A3. A storage circuit, a third storage circuit including a capacitor C4 and a buffer amplifier A4, and two output switches SW5 and SW6 are included.
Summing capacitor 102 is used to receive a reset and photo signal voltage from each previous time delay integration (TDI) stage. An integrating summing amplifier 103 is used to reset the photodiode 101 and integrate and add the reset and photo signal voltages of each previous time delay integration (TDI) stage and its own photodiode 101. A correlated double sample and hold (CDS) circuit 104 is used to sample and hold the combined reset and photo signal voltages from the output of the integrating summing amplifier 103.

  FIG. 2 shows a single row pixel with N series discrete time delay integration (TDI) circuits. Each individual time delay integration (TDI) stage is a replica of the time delay integration (TDI) stage 100, with the first stage 50 and the final stage 200 being different. Since the time delay integration (TDI) first stage 50 has no previous stage, the plate of the summing capacitor 52 is grounded. In the final stage 200, buffer amplifiers A3 and A4 are replaced by buffer amplifiers 205 and 206 with larger drive capacitance, driving the larger capacitive load of output differential amplifier 20, as shown in FIG. In order to make resetting and readout of the photo signal convenient, the output switches SW5 and SW6 of the final stage 200 are replaced with a set of switches 207. The switch 207 is driven by SM representing the output from the digital scan shift register 10. The scan shift register 10 sequentially reads out each pixel of an M-stage array similar to a standard photodiode array. The switches SW1 to SW6 included in each time delay integration (TDI) stage are driven by the same clock pulse as shown in FIG.

Referring to FIG. 1, during operation, the photodiode 101 and the integrating summing amplifier 103 are reset by closing the switch SW1 before starting the photo signal integration process. At the same time, the switches SW2 and SW6 are also closed. By closing the switch SW6, the reset voltage stored on the capacitor C4 is transferred to the next time delay integration (TDI) stage. For this reason, the reset voltage of the previous time delay integration (TDI) stage and the reset and voltage of the amplifier 103 are added via the addition capacitor 102. The combined reset voltage is stored on the capacitor C2 via the switch SW2.
To initiate the integration process at each time delay integration (TDI) stage, switch SW1 is opened, followed by switches SW2 and SW6. As shown in the timing chart of FIG. 4, there is a delay between opening SW2 and SW1 (SW1 opens earlier than SW2). This indicates that the amplifier A1 performs setting before sampling the reset voltage in the capacitor C2.

  Once the integration process begins, SW5 is closed and the photo signal stored on capacitor C3 is transferred to the next time delay integration (TDI) stage. Therefore, the photo signal of the previous time delay integration (TDI) stage and the photo signal of the current time delay integration (TDI) stage from the photodiode 101 are added via the addition capacitor 102. When this integration cycle ends, the switch SW3 is closed and the combined photo signal is sampled and stored in the capacitor C3. After switch SW3 is opened, switch SW4 is closed and the reset voltage stored on C2 is transferred to capacitor C4. The photodiode 101 and the amplifier A1 are reset again and the next integration cycle is started. This process is repeated until the last time delay integration (TDI) stage 200 is reached, as shown in FIG.

  The scan shift register 10 is started by the start of the pulse SI, and signals are sequentially read from a linear array of M pixels similar to a standard photodiode array. When a pixel is addressed by the output SM of the scan shift register 10, the reset and photo signal voltage of this pixel is transferred to a correlated double sample and hold (CDS) output differential amplifier 20 used for processing. A gain stage 30 can be added to increase the signal level. Thus, as shown in FIG. 4, a single-ended video signal is obtained.

  FIG. 5 illustrates another preferred embodiment of the present invention and describes a time delay integration (TDI) stage. The only difference between the circuits of FIG. 1 and FIG. 5 is that the function of the integrating summing amplifier 103 in FIG. 1 is replaced by the integrating amplifier 60 and the summing amplifier 70 of FIG. The correlated double sample and hold (CDS) circuit of FIGS. 1 and 5 is the same. The integrating amplifier 60 includes an amplifier A1a, an integrating capacitor C1a, and a reset switch SW1a. The function of the integrating amplifier 60 is to reset the photodiode 101 and integrate the photo signal in the integrating capacitor C1a. Summing amplifier 70 includes an amplifier A1b, an integration capacitor C1b, and a reset switch SW1b. The function of the summing amplifier 70 is to reset the photodiode 101 via the summing capacitor 61 and add the reset and photovoltage received from the previous time delay integration (TDI) stage via the summing capacitor 62. is there.

  The correlated double sample and hold (CDS) circuit 104 then performs the same sample and hold function as described above. The timing diagram of FIG. 4 needs to be slightly modified to separate the integration function and the addition function.

  As shown in FIGS. 1 and 4, the correlated double sample and hold (CDS) circuit 104 uses two parallel independent storage circuits to transmit the reset signal and the photo signal. As an alternative, a chain storage circuit can be used, and this reset signal and photo signal are transmitted one at a time via this chain. The advantage of using a single chain storage circuit is that the reset voltage and the photo signal have the same offset caused by the buffer amplifier. Thus, this offset can be completely removed by subsequent time delay integration (TDI) stages.

  The present invention has another preferred embodiment, and the time delay integration (TDI) stage shown in FIG. 1 can be alternatively operated in the time series shown in FIG. In this operation mode, the difference between the reset signal and the photo signal is first acquired before adding the reset signal and the photo signal accumulated in the correlated double sample and hold (CDS) circuit 104 to the photo signal of the photodiode 101. can do. The accumulated photo signal can be sampled and held in the capacitor C3, the reset signal of the photodiode 101 can also be sampled and held in the capacitor C2, and is not combined with the reset signal of the previous time delay integration (TDI) stage. The advantages of the present invention are maintained by the two types of operation modes represented by the timing charts of FIGS.

  Similarly, the new operation mode shown in FIG. 6 can be applied to the time delay integration (TDI) circuit of FIG. 5 with slight timing correction, so that it is convenient to separate the integration and addition functions.

  The preferred embodiments described above are merely examples of the present invention, and various changes can be derived from the present invention.

20 integrating amplifier 30 gain stage 50 first stage 52 adding capacitor 60 integrating amplifier 61 adding capacitor 62 adding capacitor 70 adding capacitor 100 TDI stage 101 photodiode 102 adding capacitor 103 integrating adding amplifier 104 correlated double sample and hold (CDS) circuit 200 final Stage 205 Buffer amplifier 206 Buffer amplifier 207 Switch

Claims (24)

An integration input amplifier comprising an integration input terminal, an addition input terminal that can be joined to or separated from the integration input terminal, an output terminal, an integration capacitor, and a reset switch;
A photodetector connected to the integral input terminal of the integral summing amplifier;
A summing capacitor having a first electrode connected to the output of a previous time delay integration (TDI) stage and a second electrode connected to the summing input terminal of the integrating summing amplifier;
A correlated duplex comprising a plurality of switches and a plurality of storage circuits, comprising an input terminal connected to the output terminal of the integrating summing amplifier and an output terminal connected to the summing capacitor of a subsequent time delay integration (TDI) stage A sample hold (CDS) circuit;
Including
First, the reset switch is closed to reset the integrating summing amplifier, and when the reset switch is subsequently opened, the photodetector reset signal and correlated double sample hold of the previous time delay integration (TDI) stage The reset signal accumulated in the (CDS) circuit is added and immediately sampled and held by the correlated double sample and hold (CDS) circuit,
Thereafter, the integrating summing amplifier starts integration of the photo signal of the photodetector,
At the same time, the integrated photo signal of the photodetector and the photo signal stored in the correlated double sample and hold (CDS) circuit of the previous time delay integration (TDI) stage are added together to form one combined photo signal. And sampled and held by the correlated double sample and hold (CDS) circuit,
The combined photo signal and the reset signal are held in the correlated double sample and hold (CDS) circuit and prepared for transmission to the subsequent time delay integration (TDI) stage;
A complementary metal oxide semiconductor (CMOS) time delay integration (TDI) sensor.   The complementary metal oxide semiconductor (CMOS) time delay integration (TDI) sensor of claim 1, wherein the integrating summing amplifier includes one or more stages.   The integration input terminal and the addition input terminal are joined to form one input terminal, and the integration capacitor of the integration addition amplifier includes a first electrode connected to the input terminal and a second electrode connected to the output terminal. The complementary metal oxide semiconductor (CMOS) time delay integration (TDI) sensor according to claim 1, wherein: It said integrating summing amplifier is an analog amplifier, single or characterized in that it comprises a differential input, a complementary metal oxide semiconductor (CMOS) TDI (TDI) type sensor according to claim 3.   The integration summing amplifier includes a two-stage amplifier, the first stage amplifier performs integration of the photo signal, the second stage amplifier performs an addition function, and the input of the first stage amplifier is the integration summing amplifier. The input of the second stage amplifier is connected to the output of the first stage amplifier and becomes the addition input terminal of the integral addition amplifier, and the output of the second stage amplifier is the output of the integration addition amplifier. The complementary metal oxide semiconductor (CMOS) time delay integration (TDI) sensor according to claim 1, wherein the sensor is a terminal.   The first stage amplifier is an analog amplifier and has a single or differential input, the first electrode of the integration capacitor is connected to the integration input terminal, and the second electrode of the integration capacitor is connected to the first stage amplifier. 6. The complementary metal oxide semiconductor (CMOS) time delay integration (TDI) sensor of claim 5, wherein the sensor is connected to an output.   The second stage amplifier is an analog amplifier, having a single or differential input, further comprising an additional capacitor, the first electrode of the additional capacitor being connected to the input of the second stage amplifier, and the second stage of the additional capacitor. 6. The complementary metal oxide semiconductor (CMOS) time delay integration (TDI) sensor of claim 5, wherein two electrodes are connected to the output of the second stage amplifier.   The complementary metal oxide semiconductor (CMOS) time delay integration (TDI) sensor according to claim 1, wherein the photodetector comprises a photosensitive diode capable of converting light into current.   The complementary metal oxide semiconductor (CMOS) time delay integration (TDI) method of claim 1, wherein the storage circuit of the correlated double sample and hold (CDS) circuit comprises a storage capacitor and a buffer amplifier. Sensor.   The complementary metal of claim 1, wherein the combined reset signal and the combined photo signal are transmitted in parallel in an independent storage circuit of the correlated double sample and hold (CDS) circuit. Oxide semiconductor (CMOS) time delay integration (TDI) sensor.   The combined reset signal and the combined photo signal are transmitted within a single chain of the storage circuit, and the combined reset signal and the combined photo signal are one at a time by each of the storage circuits. The complementary metal oxide semiconductor (CMOS) time delay integration (TDI) sensor according to claim 1, wherein the sensor is transmitted at a time.   The photodetector, the integrating summing amplifier, and the correlated double sample and hold (CDS) circuit are integrated on a single substrate, and a plurality of the integrating summing amplifier and the correlated double sample and hold (CDS) circuit therein. The plurality of photodetectors are physically isolated, and the plurality of integrating summing amplifiers and the correlated double sample-and-hold (CDS) circuit receive light rays while the plurality of photodetectors are exposed to harmful radiation. The complementary metal oxide semiconductor (CMOS) time delay integration (TDI) sensor of claim 1, wherein the sensor is shielded to avoid harmful radiation when exposed. An integration input amplifier comprising an integration input terminal, an addition input terminal that can be joined to or separated from the integration input terminal, an output terminal, an integration capacitor, and a reset switch;
A photodetector connected to the integral input terminal of the integral summing amplifier;
A summing capacitor having a first electrode connected to the output of a previous time delay integration (TDI) stage and a second electrode connected to the summing input terminal of the integrating summing amplifier;
A correlated duplex comprising a plurality of switches and a plurality of storage circuits, comprising an input terminal connected to the output terminal of the integrating summing amplifier and an output terminal connected to the summing capacitor of a subsequent time delay integration (TDI) stage A sample hold (CDS) circuit;
Including
First, the reset switch is closed to reset the integrating summing amplifier, and when the reset switch is subsequently opened, a reset signal is generated and sampled and held by the correlated double sample and hold (CDS) circuit,
The integrating summing amplifier then initiates integration of the photo signal of the photodetector and generates a cumulative signal, which is the integrated photo signal of the photo detector when the integrated photo signal of the previous time delay integration (TDI) stage. The sum of the difference from the reset signal that was sampled and held in the correlated double sample and hold (CDS) circuit and held in the correlated double sample and hold (CDS) circuit of the previous time delay integration (TDI) stage The accumulated signal is sampled and held by the correlated double sample and hold (CDS) circuit;
The accumulated signal and the reset signal are held in the correlated double sample and hold (CDS) circuit and prepared for transmission to a subsequent time delay integration (TDI) stage;
A complementary metal oxide semiconductor (CMOS) time delay integration (TDI) sensor.   14. The complementary metal oxide semiconductor (CMOS) time delay integration (TDI) sensor of claim 13, wherein the integrating summing amplifier includes one or more stages.   The integration input terminal and the addition input terminal are joined to form one input terminal, and the integration capacitor of the integration addition amplifier includes a first electrode connected to the input terminal and a second electrode connected to the output terminal. 14. The complementary metal oxide semiconductor (CMOS) time delay integration (TDI) sensor according to claim 13. It said integrating summing amplifier is an analog amplifier, single or characterized in that it comprises a differential input, a complementary metal oxide semiconductor (CMOS) TDI (TDI) type sensor according to claim 15.   The integration summing amplifier includes a two-stage amplifier, the first stage amplifier performs integration of the photo signal, the second stage amplifier performs an addition function, and the input of the first stage amplifier is the integration summing amplifier. The input of the second stage amplifier is connected to the output of the first stage amplifier to become the addition input terminal of the integral addition amplifier, and the output of the second stage amplifier is the integration input amplifier. 14. A complementary metal oxide semiconductor (CMOS) time delay integration (TDI) sensor according to claim 13, wherein the sensor is an output terminal.   The first stage amplifier is an analog amplifier and has a single or differential input, the first electrode of the integration capacitor is connected to the integration input terminal, and the second electrode of the integration capacitor is connected to the first stage amplifier. 18. A complementary metal oxide semiconductor (CMOS) time delay integration (TDI) sensor according to claim 17, wherein the sensor is connected to an output.   The second stage amplifier is an analog amplifier, having a single or differential input, further comprising an additional capacitor, the first electrode of the additional capacitor being connected to the input of the second stage amplifier, and the second stage of the additional capacitor. The complementary metal oxide semiconductor (CMOS) time delay integration (TDI) sensor of claim 17, wherein two electrodes are connected to the output of the second stage amplifier.   14. The complementary metal oxide semiconductor (CMOS) time delay integration (TDI) sensor of claim 13, wherein the photodetector comprises a photosensitive diode capable of converting light into current.   The complementary metal oxide semiconductor (CMOS) time delay integration (TDI) method of claim 13, wherein the storage circuit of the correlated double sample and hold (CDS) circuit comprises a storage capacitor and a buffer amplifier. Sensor.   14. The complementary metal oxide semiconductor (CMOS) according to claim 13, wherein the reset signal and the accumulated signal are transmitted in parallel in an independent accumulation circuit of the correlated double sample and hold (CDS) circuit. Time delay integration (TDI) type sensor.   The reset signal and the cumulative signal are transmitted within a single chain of the storage circuit, and the reset signal and the cumulative signal are transmitted one at a time by each of the storage circuits. 14. A complementary metal oxide semiconductor (CMOS) time delay integration (TDI) sensor according to 13.   The photodetector, the integrating summing amplifier, and the correlated double sample and hold (CDS) circuit are integrated on a single substrate, and a plurality of the integrating summing amplifier and the correlated double sample and hold (CDS) circuit therein. The plurality of photodetectors are physically isolated, and the plurality of integrating summing amplifiers and the correlated double sample-and-hold (CDS) circuit receive light rays while the plurality of photodetectors are exposed to harmful radiation. 14. The complementary metal oxide semiconductor (CMOS) time delay integration (TDI) sensor of claim 13, wherein the sensor is shielded to avoid harmful radiation when exposed.

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