JP5459894B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device having a memory element and a method for manufacturing the semiconductor device.

2. Description of the Related Art In recent years, attention has been focused on an individual recognition technique in which an ID (individual identification number) is given to an individual object to clarify information such as a history of the object and to be useful for production and management. Among them, development of semiconductor devices capable of transmitting and receiving data without contact is underway. As such a semiconductor device, RFID (Radio Frequency Identification) (ID tag, IC tag, IC chip, RF tag (Radio Frequency), wireless tag, electronic tag, wireless chip), etc. are especially used in the company, market, etc. Has begun to be introduced.

Many of these semiconductor devices have a circuit using a semiconductor substrate such as silicon (Si) (hereinafter also referred to as an IC (Integrated Circuit) chip) and an antenna, and the IC chip is a memory circuit (hereinafter also referred to as a memory). And a control circuit. In addition, an organic thin film transistor (hereinafter also referred to as TFT) using an organic compound, an organic memory, or the like has been actively developed for a control circuit, a memory circuit, and the like (see, for example, Patent Document 1).
Japanese Unexamined Patent Publication No. 7-22669

However, in a memory circuit using an organic compound in which an organic compound is provided between a pair of electrodes to form a memory element, depending on the size of the memory circuit, if the thickness of the organic compound layer is large, current does not flow easily and driving There is a problem that the voltage rises. On the other hand, if the film thickness of the organic compound layer is thin, it is easily affected by dust and irregularities on the surface of the electrode layer, resulting in variations in memory characteristics (such as write voltage). There is a problem that normal writing is not possible.

Therefore, an object of the present invention is also to provide a technique capable of manufacturing a highly reliable semiconductor device with high yield without complicating an apparatus and a process.

In the present invention, a memory element in which an organic compound layer is provided between conductive layers functioning as a pair of electrodes is used as the memory element. The shape of the memory element is determined by the stacked structure of the first electrode layer, the organic compound layer, and the second electrode layer. The inventors manufactured 1024 memory elements having different sizes of 2 μm × 2 μm, 3 μm × 3 μm, and 5 μm × 5 μm, respectively, applied a write voltage to each memory element, and performed electrical writing. For each size of storage element, the number of storage elements that failed to be written was divided by the total number (1024) to calculate the write failure rate. The write voltage was also changed to 8V, 9V, 10V, 11V, and 12V, and the write failure rate Pf (%) of each size of the memory element was calculated at each voltage value. FIG. 15A shows the relationship between the write voltage and the write failure rate Pf of each size of the memory element. The structure of the memory element is a stacked structure of a first conductive layer, an insulating layer, an organic compound layer, and a second conductive layer, a titanium film having a thickness of 100 nm as the first conductive layer, and a thickness of 1 nm as the insulating layer. A calcium fluoride film (CaF ₂ ) and an α-NPD film having a thickness of 10 nm were stacked as the organic compound layer, and an aluminum film having a thickness of 200 nm was formed as the second conductive layer.

FIG. 15A shows the write failure rate Pf of each memory element with respect to the write voltage. 15A to 15C, the diamond-shaped dots are 2 μm × 2 μm in size, the square dots are 3 μm × 3 μm in size, and the triangle dots are 5 μm × 5 μm in size. The write failure rate with respect to the write voltage of the storage element.

In FIG. 15A, the write failure rate tended to decrease as the write voltage increased in each size of the memory element, but there was a variation in the decrease state, and the write voltage of each memory element. The straight line drawn by the writing failure rate with respect to was shifted and did not overlap.

Next, normalization was performed on data of memory elements having different sizes. Normalization is performed by the length of the side and the size of the area, respectively. FIG. 15B is a graph obtained by normalizing and re-plotting the data by the length of the side, and FIG. 15 (C). The standardization method will be described in detail below.

The peripheral length of the 5 μm × 5 μm storage element corresponds to the side length of 5/3 storage elements of 3 μm × 3 μm. Thus, the peripheral length of one memory element of 5 μm × 5 μm corresponds to 5 / L memory elements having the length of the side L. Since the write failure rate of the memory element is Pf, each size of the memory element is normalized by the length of the side, and the side normalized write failure rate (hereinafter also referred to as Pfd) is Pf ^{(5 / L)} (%) It becomes. FIG. 15B shows the relationship between the write voltage (V) and the side normalized write failure rate Pfd (Pf ^{(5 / L)} (%)) in each size of the memory element.

Similarly, the data of each storage element was normalized by area. The area size of the memory element of 5 μm × 5 μm corresponds to the area size of ^two memory elements (5/3) of 3 μm × 3 μm. Thus the size of the area of the memory element one portion of 5 [mu] m × 5 [mu] m is, (5 / L) of the memory element of the length of the side L corresponding to ^two minutes. Writing failure rate of the storage element so Pf, the memory element of each size is standardized in size of the area, area normalized writing failure rate (hereinafter, also referred to as Pfs) is the Pf (5 / L) ² square Will be. In the memory element of each size, indicating a write voltage (V) and area normalized writing failure rate Pfs (Pf of (5 / ^{L) 2} squares (%)) the relationship in FIG. 15 (C).

The graph obtained by normalizing the data of each memory element in FIG. 15B by the length of the side shows a write failure rate Pfd that is almost the same for the write voltage at 2 μm × 2 μm, 3 μm × 3 μm, and 5 μm × 5 μm. Is shown. On the other hand, the graph in which the data of each memory element in FIG. 15C is normalized by the area is similar to that in FIG. There is a variation in the state of decrease in the failure rate Pfs, and there is a deviation in the straight line drawn by the write failure rate Pfs with respect to the write voltage of each storage element. For each size of storage element, the data variation of each storage element is reduced by standardizing by the side, so the write failure rate of the storage element is not the size of the area but the peripheral length. It was found to be greatly affected.

Therefore, the present invention proposes a shape focusing on the peripheral length in the shape of the memory element having the same area. In the present invention, in the memory element B, when the shape of the memory element B is a rectangle (or a square) having the same area, the ratio of the long side (b) to the short side (a) (X = b / a) is Larger is preferable. In the present invention, the ratio (X) of the long side to the short side is preferably 3 or more, and more preferably 6 or more. Considering the storage element A that is a square having the same peripheral length (dB = 2a + 2b) as the storage element B, the length dA of one side of the storage element A that is a square is dA = (a + b) / 2. An area SA of a certain memory element A is SA = ((a + b) / 2) ² . On the other hand, since the area SB of the memory element B is SB = ab, the ratio of the area SB of the memory element B to the area SA of the memory element A that is a square when the ratio (X) of the long side to the short side is 3 or more. Y (Y = SB / SA) is 0.75 or less, and when the ratio (X) of the long side to the short side is 6 or more, the area of the memory element B with respect to the area SA of the memory element A that is square. Y which is the ratio of SB is 0.5 or less.

Note that in this specification, the ratio of the long side to the short side of the rectangle having the same area as the memory element and the same peripheral length is the length of the long side divided by the length of the short side. . Similarly, the ratio of the area of the memory element to the square area having the same peripheral length as the memory element is a value obtained by dividing the area of the memory element by the square area having the same peripheral length as the memory element. .

In the present invention, a memory element in which an organic compound layer is provided between a conductive layer (a first conductive layer and a second conductive layer) functioning as a pair of electrodes is used as the memory element. Therefore, the memory element is a stacked region including at least the first conductive layer, the organic compound layer, and the second conductive layer, and the shape of the memory element is the shape of the stacked body. Therefore, the shape of the memory element can be controlled by the shapes of the first conductive layer, the organic compound layer, and the second conductive layer. Alternatively, an insulating layer serving as a partition can be selectively formed over the first conductive layer, and a region of the organic compound layer formed in contact with the first conductive layer can be selectively controlled.

In the present invention, the shape of the memory element is a rectangle having an uneven portion around it, a zigzag shape having one or more bent portions, a comb shape, a ring shape having an opening (space) inside (ring shape, ring shape, A shape such as a so-called donut shape is used. Moreover, the shape which has a cut | notch (notch) in a rectangle (square) may be sufficient. In addition, a rectangle having a large ratio between the long side and the short side, and an ellipse having a large ratio between the long diameter and the short diameter can be used.

Note that in this specification, a semiconductor device refers to a device that can function by utilizing semiconductor characteristics. A semiconductor device such as an integrated circuit including a memory element or a chip including a processor circuit can be manufactured using the present invention.

One of the semiconductor devices of the present invention includes a memory element including an organic compound layer between a first conductive layer and a second conductive layer, and at least of the first conductive layer and the second conductive layer. One upper surface shape is bent.

One of the semiconductor devices of the present invention includes a memory element including an organic compound layer between a first conductive layer and a second conductive layer, and at least of the first conductive layer and the second conductive layer. One upper surface shape is a comb-tooth shape.

One of the semiconductor devices of the present invention includes a memory element including an organic compound layer between a first conductive layer and a second conductive layer, and at least of the first conductive layer and the second conductive layer. One upper surface shape is a ring shape.

One of the semiconductor devices of the present invention includes a memory element including an organic compound layer between a first conductive layer and a second conductive layer, and at least of the first conductive layer and the second conductive layer. One upper surface shape is a rectangular shape having a cut.

One embodiment of the semiconductor device of the present invention includes a first conductive layer, an insulating layer having an opening on the first conductive layer, an organic compound layer in the opening on the first conductive layer, and a first layer on the organic compound layer. The memory element includes two conductive layers, and the upper surface shape of the opening is bent.

One embodiment of the semiconductor device of the present invention includes a first conductive layer, an insulating layer having an opening on the first conductive layer, an organic compound layer in the opening on the first conductive layer, and a first layer on the organic compound layer. And the upper surface of the opening has a comb shape.

One embodiment of the semiconductor device of the present invention includes a first conductive layer, an insulating layer having an opening on the first conductive layer, an organic compound layer in the opening on the first conductive layer, and a first layer on the organic compound layer. And the opening has a ring shape.

One embodiment of the semiconductor device of the present invention includes a first conductive layer, an insulating layer having an opening on the first conductive layer, an organic compound layer in the opening on the first conductive layer, and a first layer on the organic compound layer. And a top surface of the opening is a rectangular shape having a cut.

According to one method for manufacturing a semiconductor device of the present invention, a first conductive layer having a bent upper surface shape is formed, an organic compound layer is formed over the bent first conductive layer, and the organic compound layer is formed on the organic compound layer. A memory element in which the second conductive layer is formed to have a bent top surface is manufactured.

According to one method for manufacturing a semiconductor device of the present invention, a first conductive layer having a comb-like upper surface shape is formed, an organic compound layer is formed on the first conductive layer having a comb shape, and the organic compound layer is formed on the organic compound layer. Then, a second conductive layer is formed to produce a memory element having a comb-like upper surface shape.

According to one method for manufacturing a semiconductor device of the present invention, a first conductive layer having a ring shape on an upper surface is formed, an organic compound layer is formed on the ring-shaped first conductive layer, and a second conductive layer is formed on the organic compound layer. A conductive element is formed to manufacture a memory element having a ring shape on the upper surface.

According to one method for manufacturing a semiconductor device of the present invention, a first conductive layer having a rectangular shape whose top surface has a cut is formed, an organic compound layer is formed over the ring-shaped first conductive layer, and the organic compound layer is formed on the organic compound layer. A second conductive layer is formed on the top surface to form a rectangular memory element whose top surface has a cut.

In one embodiment of the method for manufacturing a semiconductor device of the present invention, a first conductive layer is formed, an insulating layer having an opening whose upper surface shape is bent is formed over the first conductive layer, and the first conductive layer is formed over the first conductive layer. An organic compound layer is formed in the bent opening, a second conductive layer is formed on the organic compound layer, and a memory element having a bent upper surface shape is manufactured.

According to one method for manufacturing a semiconductor device of the present invention, a first conductive layer is formed, an insulating layer having a comb-shaped opening on the top surface is formed over the first conductive layer, and the first conductive layer is formed. An organic compound layer is formed in the comb-shaped opening, and a second conductive layer is formed on the organic compound layer, whereby a memory element having a comb-shaped top surface is manufactured.

In one embodiment of the method for manufacturing a semiconductor device of the present invention, a first conductive layer is formed, an insulating layer having an opening having a ring shape on the top surface is formed over the first conductive layer, and the opening over the first conductive layer is formed. An organic compound layer is formed on the organic compound layer, a second conductive layer is formed on the organic compound layer, and a memory element having a ring shape on the top surface is manufactured.

In one embodiment of the method for manufacturing a semiconductor device of the present invention, a first conductive layer is formed, an insulating layer having a rectangular opening whose top surface shape has a cut is formed over the first conductive layer, and the first conductive layer is formed. An organic compound layer is formed in the opening on the layer, a second conductive layer is formed on the organic compound layer, and a memory element having a rectangular shape whose top surface has a cut is manufactured.

In the above semiconductor device, there is a case where the first conductive layer and the second conductive layer are partially in contact with each other or the film thickness of the organic compound layer is changed after writing the semiconductor device.

According to the present invention, the characteristics of the memory element are stabilized without variation and normal writing can be performed. Therefore, a highly reliable semiconductor device can be manufactured with high yield without complicating the device and the process.

Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in structures of the present invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated.

(Embodiment 1)
In this embodiment mode, a memory element to which the present invention is applied will be described with reference to FIGS.

The present invention proposes a shape of a memory element having the same area, focusing on the peripheral length of the memory element. First, a memory element B configured to include a first conductive layer, an organic compound layer, and a second conductive layer is considered.

In a rectangle having the same area as the memory element B where the area SB is SB = ab, if the rectangle has a short side a and a long side b (may be a square), the length dB around the rectangle is dB = 2a + 2b. Considering a square storage element A having the same peripheral length as the storage element B, the length dA of one side of the storage element A is dA = (a + b) / 2, and the storage element A is a square, so the area SA Is SA = ((a + b) / 2) ² .

The areas of the memory element A and the memory element B are compared. The area SA of the memory element A is SA = ((a + b) / 2) ² , and the area SB of the memory element B is SB = ab. The ratio Y of the area SB of the memory element B to the area SA of the memory element A that is a square is Y = SB / SA = ab / ((a + b) / 2) ² , and the long side b and the short side of the memory element B are short. If the ratio b / a of side a is X (X = b / a), then Y = 4X / (X + 1) ² . FIG. 9 shows the relationship between the ratio X of the long side b and the short side a of the memory element B and the area ratio Y of the memory element B to the memory element A. Since the long side b> the short side a, the ratio X is 1 or more.

As shown in FIG. 9, the ratio Y of the area of the memory element B and the area of the square memory element A having the same peripheral length decreases as the ratio X between the long side and the short side increases. In the present invention, when considering the shape of the memory element as a rectangle (which may be a square) of the same area, the ratio of the long side b to the short side a (X = b / a) is larger. Is preferred. In particular, the ratio of the long side to the short side (X) is preferably 3 or more, and more preferably 6 or more. When the ratio (X) of the long side to the short side is 3 or more, Y, which is the ratio of the area SB of the memory element B to the area SA of the square memory element, is 0.75 or less, and further, the long side and the short side When the ratio (X) is 6 or more, the ratio Y of the area SB of the memory element B to the area SA of the memory element A that is a square is 0.5 or less.

In the present invention, a memory element in which an organic compound layer is provided between a conductive layer (a first conductive layer and a second conductive layer) functioning as a pair of electrodes is used as the memory element. Therefore, the memory element is a stacked region including at least the first conductive layer, the organic compound layer, and the second conductive layer, and the shape of the memory element is the shape of the stacked body. Therefore, the shape of the memory element can be controlled by the shapes of the first conductive layer, the organic compound layer, and the second conductive layer. For example, in order to form the memory element in the above shape, the first conductive layer is formed in a desired shape. A memory element reflecting the shape of the first conductive layer is formed by stacking an organic compound layer and a second conductive layer on the first conductive layer formed in a desired shape. Alternatively, an insulating layer serving as a partition can be selectively formed over the first conductive layer, and a region of the organic compound layer formed in contact with the first conductive layer can be selectively controlled.

In the present invention, the shape of the memory element is a rectangle having an uneven portion around it, a zigzag shape having one or more bent portions, a comb shape, or a ring shape (ring shape) having an opening (space) inside. Is used. In addition, a rectangle having a large ratio between the long side and the short side, and an ellipse having a large ratio between the long diameter and the short diameter can be used.

1 and 18 are a cross-sectional view and a top view of the memory element of this embodiment mode. 1A to 1C and FIGS. 18A to 18C are top views of memory elements, which are examples of memory elements having different shapes in FIGS. 1A to 1C and FIGS. 18A to 18C are cross-sectional views taken along the line KL in FIG. 1D, and as shown in FIG. The memory element has a stacked structure of a first conductive layer 35, an organic compound layer 36, and a second conductive layer 37. 1A to 1C and FIGS. 18A to 18C each illustrate a memory element region including a stack of a first conductive layer, an organic compound layer, and a second conductive layer.

The top surface shape of the memory element 41 in FIG. 1A is bent so as to be folded into a square wave shape, and has a shape meandering left and right. In addition, the bent portion in the upper surface shape of the memory element 41 is an example of a square shape, but it may have a curvature and a rounded shape. Moreover, the bending part may be single or plural. The memory element 42 in FIG. 1B is a comb-like conductive layer, and has a plurality of recesses on one side of a rectangle. This recess may be plural or singular, and FIG. 1 (B) has a recess on only one side and shows an example of a comb tooth shape. However, a recess may be provided on the other side, as shown in FIG. If a recess is provided also on the side facing in parallel with the side having the recess, the bone-shaped conductive layer can be obtained. The memory element 43 in FIG. 1C is a conductive layer (also referred to as a so-called spiral shape) having a bent portion so as to spiral toward the center of the memory element. The bent portion of the memory element 43 in FIG. 1C is also square, but the bent portion may have a curvature and a round shape as in FIG. Further, the memory element 43 may be provided with a concavo-convex portion in the peripheral portion as shown in FIG.

The storage element 44 in FIG. 18A has a shape having a similar rectangular space in the center of the rectangular storage element 44. The memory element 45 in FIG. 18B has a shape having two circular spaces near the center inside the elliptical memory element 45. The storage element 46 in FIG. 18C has a circular space inside the circular storage element 46 and has a ring shape. In FIG. 18, the space included in the memory element indicates that at least one of the first conductive layer, the organic compound layer, and the second conductive layer is not formed, and the stack of the memory elements is not formed. Therefore, FIG. 18 does not necessarily indicate that no space is formed inside the memory element, but indicates that no memory element is formed.

Since the memory element having the shape as shown in FIGS. 1 and 18 is manufactured in a shape having a bent portion or unevenness, the peripheral length of the memory element becomes long. Therefore, in such a memory element, when a rectangle having the same area is considered, the ratio of the long side to the short side (the ratio of the long side to the short side) increases as the peripheral length increases. In the present invention, the ratio of the long side to the short side (the ratio of the long side to the short side) is preferably 3 or more, and more preferably 6 or more. Further, when a square is formed with the same peripheral length as the memory element of this embodiment, the area of the square is larger than the area of the memory element of this embodiment. In the present invention, the ratio of the square area to the area of the memory element relative to the square area is preferably 0.75 or less, and more preferably 0.5 or less.

Such a memory element of this embodiment can perform normal writing and can reduce a writing failure rate. In addition, the writing characteristics of the plurality of memory elements are stabilized without variation. Therefore, by using such a memory element, a semiconductor device with high reliability in writing can be manufactured.

Alternatively, as illustrated in FIGS. 16A to 16C, an insulating layer may be provided between the organic compound layer and the conductive layer.

The organic compound layer 52, the organic compound layer 62, and the organic compound layer 72 may be formed using the same material as that of the organic compound layer 36 in FIG.

FIG. 16A illustrates an example in which an insulating layer 51 is provided between the first conductive layer 50 and the organic compound layer 52, and the second conductive layer 53 is provided over the organic compound layer 52. In FIG. 16B, the insulating layer 61 is formed over the organic compound layer 62 provided over the first conductive layer 60, and the second conductive layer 63 is provided over the insulating layer 61. In FIG. 16C, a first conductive layer 70, a first insulating layer 71, an organic compound layer 72, a second insulating layer 74, and a second conductive layer 73 are stacked. A first insulating layer 71 is provided between the organic compound layer 72 and the organic compound layer 72, and a second insulating layer 74 is provided between the organic compound layer 72 and the second conductive layer 73.

In this embodiment mode, the insulating layer 51, the insulating layer 61, the first insulating layer 71, and the second insulating layer 74 have insulating properties, and are very thin (the thickness of the insulating layer is 4 nm or less, preferably 0.1 nm or more and 2 nm or less), and depending on the material and manufacturing method thereof, the shape as a continuous film is not shown, and it may be a discontinuous island shape. In other drawings in this specification, the insulating layer is described as a continuous layer. However, the insulating layer includes a case where the insulating layer has a discontinuous island shape.

It is considered that tunneling of carriers can be performed by the insulating layer existing at the interface between the conductive layer and the organic compound layer, and a tunnel current flows. When a voltage is applied between the first conductive layer and the second conductive layer, a current flows through the organic compound layer to generate heat. And when the temperature of an organic compound layer rises to a glass transition temperature, the material which forms an organic compound layer turns into a composition which has fluidity | liquidity. The composition having fluidity flows (moves) without maintaining the solid state shape, and changes its shape. Accordingly, the film thickness of the organic compound layer becomes nonuniform, the organic compound layer is deformed, and a part of the first conductive layer and the second conductive layer are in contact with each other, and the first conductive layer and the second conductive layer are Is short-circuited. In some cases, the electric field concentrates on the thin region of the organic compound layer, and the first conductive layer and the second conductive layer are short-circuited due to the influence of the high electric field. Therefore, the conductivity of the memory element before and after voltage application changes.

In a semiconductor device, after writing into the semiconductor device, the first conductive layer and the second conductive layer may be partially in contact with each other or the thickness of the organic compound layer may change.

By providing the insulating layer 51, the insulating layer 61, the first insulating layer 71, and the second insulating layer 74, characteristics such as the writing voltage of the memory element are stabilized without variation, and normal writing is performed in each element. Is possible. Further, by providing the insulating layer, the carrier injecting property is improved, so that the organic compound layer can be thickened. Therefore, it is possible to prevent the memory element from being short-circuited in the initial state before energization.

In the present invention, the insulating layer is formed using an inorganic insulator or organic compound that is thermally and chemically stable and into which carriers are not injected. Specific examples of inorganic insulators and organic compounds that can be used for the insulating layer are described below.

In the present invention, as an inorganic insulator that can be used for the insulating layer, lithium oxide (Li ₂ O), sodium oxide (Na ₂ O), potassium oxide (K ₂ O), rubidium oxide (Rb ₂ O), beryllium oxide (BeO), magnesium oxide (MgO), calcium oxide (CaO), strontium oxide (SrO), barium oxide (BaO), scandium oxide (Sc ₂ O ₃ ), zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ) , Rutherfordium oxide (RfO ₂ ), tantalum oxide (TaO), technetium oxide (TcO), iron oxide (Fe ₂ O ₃ ), cobalt oxide (CoO), palladium oxide (PdO), silver oxide (Ag ₂ O), oxidation aluminum _{(Al 2 O} 3), gallium oxide _{(Ga 2 O} 3), bismuth oxide (Bi O ₃₎ may be an oxide such as.

In the present invention, as other inorganic insulators that can be used for the insulating layer, lithium fluoride (LiF), sodium fluoride (NaF), potassium fluoride (KF), rubidium fluoride (RbF), cesium fluoride ( CsF), beryllium fluoride (BeF ₂ ), magnesium fluoride (MgF ₂ ), calcium fluoride (CaF ₂ ), strontium fluoride (SrF ₂ ), barium fluoride (BaF ₂ ), aluminum fluoride (AlF ₃ ) Fluoride such as nitrogen trifluoride (NF ₃ ), sulfur hexafluoride (SF ₆ ), silver fluoride (AgF), manganese fluoride (MnF ₃ ) can be used.

In the present invention, other inorganic insulators that can be used for the insulating layer include lithium chloride (LiCl), sodium chloride (NaCl), potassium chloride (KCl), beryllium chloride (BeCl ₂ ), calcium chloride (CaCl ₂ ), Barium chloride (BaCl ₂ ), aluminum chloride (AlCl ₃ ), silicon chloride (SiCl ₄ ), germanium chloride (GeCl ₄ ), tin chloride (SnCl ₄ ), silver chloride (AgCl), zinc chloride (ZnCl), titanium tetrachloride (TiCl ₄ ), titanium trichloride (TiCl ₃ ), zirconium chloride (ZrCl ₄ ), iron chloride (FeCl ₃ ), palladium chloride (PdCl ₂ ), antimony trichloride (SbCl ₃ ), antimony dichloride (SbCl ₂ ), chloride Strontium (SrCl ₂ ), thallium chloride (TlCl), Chlorides such as copper chloride (CuCl), manganese chloride (MnCl ₂ ), and ruthenium chloride (RuCl ₂ ) can be used.

In the present invention, other inorganic insulators that can be used for the insulating layer include potassium bromide (KBr), cesium bromide (CsBr), silver bromide (AgBr), barium bromide (BaBr ₂ ), silicon bromide. Bromides such as (SiBr ₄ ) and lithium bromide (LiBr) can be used.

In the present invention, other inorganic insulators that can be used for the insulating layer include sodium iodide (NaI), potassium iodide (KI), barium iodide (BaI ₂ ), thallium iodide (TlI), silver iodide. (AgI), titanium iodide _(TiI 4), calcium iodide _(CaI 2), iodide silicon _(SiI 4), it can be used an iodide such as cesium iodide (CsI).

In the present invention, as other inorganic insulators that can be used for the insulating layer, lithium carbonate (Li ₂ CO ₃ ), potassium carbonate (K ₂ CO ₃ ), sodium carbonate (Na ₂ CO ₃ ), magnesium carbonate (MgCO ₃₎ ), Calcium carbonate (CaCO ₃ ), strontium carbonate (SrCO ₃ ), barium carbonate (BaCO ₃ ), manganese carbonate (MnCO ₃ ), iron carbonate (FeCO ₃ ), cobalt carbonate (CoCO ₃ ), nickel carbonate (NiCO ₃ ) Carbonates such as copper carbonate (CuCO ₃ ), silver carbonate (Ag ₂ CO ₃ ), and zinc carbonate (ZnCO ₃ ) can be used.

In the present invention, other inorganic insulators that can be used for the insulating layer include lithium sulfate (Li ₂ SO ₄ ), potassium sulfate (K ₂ SO ₄ ), sodium sulfate (Na ₂ SO ₄ ), magnesium sulfate (MgSO ₄ ). ), Calcium sulfate (CaSO ₄ ), strontium sulfate (SrSO ₄ ), barium sulfate (BaSO ₄ ), titanium sulfate (Ti ₂ (SO ₄ ) ₃ ), zirconium sulfate (Zr (SO ₄ ) ₂ ), manganese sulfate (MnSO ₄ ), iron sulfate (FeSO ₄ ), diferric trisulfate (Fe ₂ (SO ₄ ) ₃ ), cobalt sulfate (CoSO ₄ ), cobalt sulfate (Co ₂ (SO ₄ ) ₃ ), nickel sulfate (NiSO ₄ ), Copper sulfate (CuSO ₄ ), silver sulfate (Ag ₂ SO ₄ ), zinc sulfate (ZnSO ₄ ), aluminum sulfate (Al ₂ (SO ₂ ) ₄ ) ₃ ), indium sulfate (In ₂ (SO ₄ ) ₃ ), tin sulfate (SnSO ₄ ), tin sulfate (Sn (SO ₄ ) ₂ ), antimony sulfate (Sb ₂ (SO ₄ ) ₃ ), bismuth sulfate ( Sulfates such as Bi ₂ (SO ₄ ) ₃ ) can be used.

In the present invention, as other inorganic insulators that can be used for the insulating layer, lithium nitrate (LiNO ₃ ), potassium nitrate (KNO ₃ ), sodium nitrate (NaNO ₃ ), magnesium nitrate (Mg (NO ₃ ) ₂ ), nitric acid Calcium (Ca (NO ₃ ) ₂ ), strontium nitrate (Sr (NO ₃ ) ₂ ), barium nitrate (Ba (NO ₃ ) ₂ ), titanium nitrate (Ti (NO ₃ ) ₄ ), zirconium nitrate (Zr (NO _{3) 4} ), manganese nitrate (Mn (NO ₃ ) ₂ ), iron nitrate (Fe (NO ₃ ) ₂ ), iron nitrate (Fe (NO ₃ ) ₃ ), cobalt nitrate (Co (NO ₃ ) ₂ ), nickel nitrate _{(Ni (NO 3) 2)} , copper nitrate _{(Cu (NO 3) 2)} , silver nitrate (AgNO _3), zinc nitrate _{(Zn (NO 3) 2)} , aluminum nitrate (Al NO _{3) 3),} indium nitrate _{(In (NO 3) 3)} , tin nitrate _{(Sn (NO 3) 2)} , can be used nitrates such as bismuth nitrate _{(Bi (NO 3) 3)} .

In the present invention, other inorganic insulators that can be used for the insulating layer include nitrides such as aluminum nitride (AlN) and silicon nitride (SiN), lithium carboxylate (LiCOOCH ₃ ), potassium acetate (KCOOCH ₃ ), and acetic acid. Sodium (NaCOOCH ₃ ), magnesium acetate (Mg (COOCH ₃ ) ₂ ), calcium acetate (Ca (COOCH ₃ ) ₂ ), strontium acetate (Sr (COOCH ₃ ) ₂ ), barium acetate (Ba (COOCH ₃ ) ₂ ), etc. Can be used.

In the present invention, as the inorganic insulator that can be used for the insulating layer, one or more of the above inorganic insulators can be used.

In the present invention, as an organic compound that can be used for the insulating layer, polyimide, acrylic, polyamide, benzocyclobutene, polyester, novolac resin, melamine resin, phenol resin, epoxy resin, silicon resin, furan resin, diallyl phthalate resin, siloxane Resin can be used.

In the present invention, other organic compounds that can be used for the insulating layer include 4,4′-bis [N- (1-naphthyl) -N-phenyl-amino] -biphenyl (abbreviation: α-NPD), 4′-bis [N- (3-methylphenyl) -N-phenyl-amino] -biphenyl (abbreviation: TPD), 4,4 ′, 4 ″ -tris (N, N-diphenyl-amino) -triphenyl Amine (abbreviation: TDATA), 4,4 ′, 4 ″ -tris [N- (3-methylphenyl) -N-phenyl-amino] -triphenylamine (abbreviation: MTDATA) and 4,4′-bis ( N- (4- (N, N-di-m-tolylamino) phenyl) -N-phenylamino) biphenyl (abbreviation: DNTPD) and other aromatic amine-based compounds (that is, having a benzene ring-nitrogen bond) Phthalocyanine : _H 2 Pc), copper phthalocyanine (abbreviation: CuPc), or vanadyl phthalocyanine (abbreviation: VOPc), and phthalocyanine compounds such as, 2Me-TPD, FTPD, TPAC , OTPAC, Diamine, PDA, triphenylmethane (abbreviation: TPM), STB Etc. can be used.

In the present invention, as another organic compound that can be used for the insulating layer, tris (8-quinolinolato) aluminum (abbreviation: Alq ₃ ), tris (4-methyl-8-quinolinolato) aluminum (abbreviation: Almq ₃ ), bis (10-hydroxybenzo [h] -quinolinato) beryllium (abbreviation: BeBq ₂ ), bis (2-methyl-8-quinolinolato) -4-phenylphenolato-aluminum (abbreviation: BAlq), etc. A material composed of a metal complex or the like, bis [2- (2-hydroxyphenyl) benzoxazolate] zinc (abbreviation: Zn (BOX) ₂ ), bis [2- (2-hydroxyphenyl) benzothiazolate] zinc (abbreviation: Metals having an oxazole or thiazole ligand such as Zn (BTZ) ₂ ) Materials such as complexes, 2- (4-biphenylyl) -5- (4-tert-butylphenyl) -1,3,4-oxadiazole (abbreviation: PBD), 1,3-bis [5- (p- tert-butylphenyl) -1,3,4-oxadiazol-2-yl] benzene (abbreviation: OXD-7), 3- (4-tert-butylphenyl) -4-phenyl-5- (4-biphenylyl) ) -1,2,4-triazole (abbreviation: TAZ), 3- (4-tert-butylphenyl) -4- (4-ethylphenyl) -5- (4-biphenylyl) -1,2,4-triazole (Abbreviation: p-EtTAZ), bathophenanthroline (abbreviation: BPhen), bathocuproin (abbreviation: BCP), 5,6,11,12-tetraphenyltetracene (abbreviation: rubrene), hexaphenylbenzene Zen, t-butylperylene, 9,10-di (phenyl) anthracene, coumarin 545T, etc., dendrimer, 4-dicyanomethylene-2-methyl-6- [2- (1,1,7,7-tetramethyl-9 -Jurolidyl) ethenyl] -4H-pyran (abbreviation: DCJT), 4-dicyanomethylene-2-t-butyl-6- [2- (1,1,7,7-tetramethyljulolidin-9-yl) ethenyl ] -4H-pyran (abbreviation: DCJTB), periflanthene, 2,5-dicyano-1,4-bis [2- (10-methoxy-1,1,7,7-tetramethyljulolidin-9-yl) ethenyl Benzene, N, N′-dimethylquinacridone (abbreviation: DMQd), coumarin 6,9,9′-bianthryl, 9,10-diphenylanthracene (abbreviation: DPA) and 9,1 0-bis (2-naphthyl) anthracene (abbreviation: DNA), 2,5,8,11-tetra-t-butylperylene (abbreviation: TBP), BMD, BDD, 2,5-bis (1-naphthyl)- 1,3,4-oxadiazole (abbreviation: BND), BAPD, BBOT, TPQ1, TPQ2, MBDQ, or the like can be used.

In the present invention, polyacetylenes, polyphenylene vinylenes, polythiophenes, polyanilines, polyphenylene ethynylenes, and the like can be used as other organic compounds that can be used for the insulating layer. Examples of the polyparaphenylene vinylene include poly (paraphenylene vinylene) [PPV] derivatives, poly (2,5-dialkoxy-1,4-phenylene vinylene) [RO-PPV], poly (2- (2′- Ethyl-hexoxy) -5-methoxy-1,4-phenylenevinylene) [MEH-PPV], poly (2- (dialkoxyphenyl) -1,4-phenylenevinylene) [ROPh-PPV] and the like. Examples of polyparaphenylene include derivatives of polyparaphenylene [PPP], poly (2,5-dialkoxy-1,4-phenylene) [RO-PPP], poly (2,5-dihexoxy-1,4-phenylene). ) And the like. The polythiophene series includes polythiophene [PT] derivatives, poly (3-alkylthiophene) [PAT], poly (3-hexylthiophene) [PHT], poly (3-cyclohexylthiophene) [PCHT], poly (3-cyclohexyl). -4-methylthiophene) [PCHMT], poly (3,4-dicyclohexylthiophene) [PDCHT], poly [3- (4-octylphenyl) -thiophene] [POPT], poly [3- (4-octylphenyl) -2,2 bithiophene] [PTOPT] and the like. Examples of the polyfluorene series include polyfluorene [PF] derivatives, poly (9,9-dialkylfluorene) [PDAF], poly (9,9-dioctylfluorene) [PDOF], and the like.

In the present invention, PFBT, a carbazole derivative, anthracene, coronene, perylene, PPCP, BPPC, Boryl Anthracene, DCM, QD, Eu (TTA) ₃ phen, or the like may be used as another organic compound that can be used for the insulating layer. it can.

In the present invention, as the organic compound that can be used for the insulating layer, one or more of the above organic compounds can be used.

In the present invention, the insulating layer can be formed using one or more of the above inorganic insulators and the above organic compounds. In the present invention, the insulating layer has an insulating property.

For the insulating layer, a vapor deposition method such as co-evaporation, a coating method such as a spin coating method, or a sol-gel method can be used. In addition, a droplet discharge (ejection) method (an ink jet method depending on the method) that can selectively eject (eject) droplets of a composition prepared for a specific purpose to form a predetermined pattern. ), A method by which an object can be transferred or drawn in a desired pattern, such as various printing methods (screen (stencil) printing, offset (lithographic) printing, relief printing or gravure (intaglio printing), etc. Method) can also be used.

A first conductive layer 35, a first conductive layer 50, a first conductive layer 60, a first conductive layer 70, a second conductive layer 37, a second conductive layer 53, a second conductive layer 63, and As the conductive layer used for the second conductive layer 73, a highly conductive element, compound, or the like is used. Typically, gold (Au), silver (Ag), platinum (Pt), nickel (Ni), tungsten (W), chromium (Cr), molybdenum (Mo), iron (Fe), cobalt (Co), From one element selected from copper (Cu), palladium (Pd), carbon (C), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), etc. or an alloy containing a plurality of such elements A single layer or a laminated structure can be used. Examples of the alloy containing a plurality of the above elements include an alloy containing Al and Ti, Al, an alloy containing Ti and C, an alloy containing Al and Ni, an alloy containing Al and C, and Al and Ni. An alloy containing C or an alloy containing Al and Mo can be used.

The first conductive layer 35, the first conductive layer 50, the first conductive layer 60, the first conductive layer 70, the second conductive layer 37, the second conductive layer 53, and the second conductive layer 63. In addition, for the second conductive layer 73, one or more of indium (In), tin (Sn), lead (Pb), bismuth (Bi), calcium (Ca), antimony (Sb), and zinc (Zn) are used. . In addition, one or more of magnesium (Mg), manganese (Mn), cadmium (Cd), thallium (Tl), tellurium (Te), and barium (Ba) may be used. A plurality of the metal materials may be included, or an alloy including one or more of the materials may be used. Examples of alloys that can be used include indium tin alloys (InSn), magnesium indium alloys (InMg), phosphorus indium alloys (InP), arsenic indium alloys (InAs), chromium indium alloys (InCr), and the like. .

A first conductive layer 35, a first conductive layer 50, a first conductive layer 60, a first conductive layer 70, a second conductive layer 37, a second conductive layer 53, a second conductive layer 63, and A light-transmitting material having a light-transmitting property with respect to visible light can be used for the second conductive layer 73. As the light-transmitting conductive material, indium tin oxide (ITO), indium tin oxide containing silicon oxide (ITSO), organic indium, organic tin, zinc oxide, or the like can be used. Indium zinc oxide containing zinc oxide (ZnO) (IZO (indium zinc oxide)), ZnO doped with gallium (Ga), tin oxide (SnO ₂ ), indium oxide containing tungsten oxide, tungsten oxide Indium zinc oxide containing, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, or the like may also be used.

The organic compound layer 36, the organic compound layer 52, the organic compound layer 62, and the organic compound layer 72 are formed of an organic compound whose conductivity is changed by an optical action or an electrical action. The organic compound layer 36, the organic compound layer 52, the organic compound layer 62, and the organic compound layer 72 may be provided as a single layer, or a plurality of layers may be stacked.

Organic compounds that can constitute the organic compound layer 36, the organic compound layer 52, the organic compound layer 62, and the organic compound layer 72 include organic resins represented by polyimide, acrylic, polyamide, benzocyclobutene, epoxy, and the like. Can be used.

In addition, as an organic compound that can constitute the organic compound layer 36, the organic compound layer 52, the organic compound layer 62, and the organic compound layer 72 and whose conductivity is changed by an optical action or an electric action, a hole is used. An organic compound material having a transport property or an organic compound material having an electron transport property can be used.

As an organic compound material having a hole-transport property, 4,4′-bis [N- (1-naphthyl) -N-phenyl-amino] -biphenyl (abbreviation: α-NPD), 4,4′-bis [ N- (3-methylphenyl) -N-phenyl-amino] -biphenyl (abbreviation: TPD) or 4,4 ′, 4 ″ -tris (N, N-diphenyl-amino) -triphenylamine (abbreviation: TDATA) ), 4,4 ′, 4 ″ -tris [N- (3-methylphenyl) -N-phenyl-amino] -triphenylamine (abbreviation: MTDATA) and 4,4′-bis (N- (4- (N, N-di-m-tolylamino) phenyl) -N-phenylamino) biphenyl (abbreviation: DNTPD) and other aromatic amine-based compounds (that is, having a benzene ring-nitrogen bond) and phthalocyanines (abbreviation: H ₂ Pc), copper lid Phthalocyanine compounds such as Russianine (abbreviation: CuPc) and vanadyl phthalocyanine (abbreviation: VOPc) can be used. The substances described here are mainly substances having a hole mobility of 10 ⁻⁶ cm ² / Vs or higher.

As an organic compound material having an electron transporting property, tris (8-quinolinolato) aluminum (abbreviation: Alq ₃ ), tris (4-methyl-8-quinolinolato) aluminum (abbreviation: Almq ₃ ), bis (10-hydroxybenzo [ h] -quinolinato) beryllium (abbreviation: BeBq ₂ ), bis (2-methyl-8-quinolinolato) -4-phenylphenolato-aluminum (abbreviation: BAlq), etc., and a metal complex having a quinoline skeleton or a benzoquinoline skeleton Materials can be used. In addition, bis [2- (2-hydroxyphenyl) benzoxazolate] zinc (abbreviation: Zn (BOX) ₂ ), bis [2- (2-hydroxyphenyl) benzothiazolate] zinc (abbreviation: Zn (BTZ) A material such as a metal complex having an oxazole-based or thiazole-based ligand such as ₂ ) can also be used. In addition to metal complexes, 2- (4-biphenylyl) -5- (4-tert-butylphenyl) -1,3,4-oxadiazole (abbreviation: PBD), 1,3-bis [5- (P-tert-butylphenyl) -1,3,4-oxadiazol-2-yl] benzene (abbreviation: OXD-7), 3- (4-tert-butylphenyl) -4-phenyl-5- ( 4-biphenylyl) -1,2,4-triazole (abbreviation: TAZ), 3- (4-tert-butylphenyl) -4- (4-ethylphenyl) -5- (4-biphenylyl) -1,2, 4-triazole (abbreviation: p-EtTAZ), bathophenanthroline (abbreviation: BPhen), bathocuproin (abbreviation: BCP), and the like can be used. The substances mentioned here are mainly substances having an electron mobility of 10 ⁻⁶ cm ² / Vs or higher.

The organic compound layer 36, the organic compound layer 52, the organic compound layer 62, and the organic compound layer 72 can be formed using a vapor deposition method, an electron beam vapor deposition method, a sputtering method, a CVD method, or the like. Moreover, when forming an organic compound layer using a plurality of materials, it can be formed by simultaneously forming each material, a co-evaporation method by resistance heating evaporation, a co-evaporation method by electron beam evaporation, It can be formed by a combination of the same or different methods such as co-evaporation by resistance heating evaporation and electron beam evaporation, film formation by resistance heating evaporation and sputtering, and film formation by electron beam evaporation and sputtering.

Note that the organic compound layer 36, the organic compound layer 52, the organic compound layer 62, and the organic compound layer 72 are formed to have film thicknesses with which the conductivity of the memory element is changed by an optical action or an electrical action. Since the conductivity of the memory element having the above configuration changes before and after voltage application, two values corresponding to “initial state” and “after conductivity change” can be stored.

Note that the voltage applied to the memory element of the present invention may be higher than the second conductive layer in the first conductive layer, or higher in the second conductive layer than in the first conductive layer. May be. Even when the memory element has a rectifying property, a potential difference may be provided between the first conductive layer and the second conductive layer so that the voltage is applied in the forward bias direction, or the voltage is applied in the reverse bias direction. A potential difference may be provided between the first conductive layer and the second conductive layer so that is applied.

According to the present invention, the characteristics of the memory element are stabilized without variation and normal writing can be performed. Therefore, a highly reliable semiconductor device can be manufactured with high yield without complicating the device and the process.

(Embodiment 2)
In this embodiment, a structural example of a memory element included in a semiconductor device of the present invention will be described with reference to drawings. More specifically, the case where the structure of the semiconductor device is a passive matrix type will be described.

The memory element of the present invention and its operation mechanism will be described with reference to FIGS. The memory element in this embodiment can be manufactured using the same material and structure as those in Embodiment 1. Therefore, detailed description of materials and the like is omitted.

FIG. 3 shows a structural example of the semiconductor device of the present invention. A memory cell array 722 in which memory cells 721 are provided in a matrix, a circuit 726 having a reading circuit and a writing circuit, a decoder 724, and a decoder 723 are shown. Have. Note that the structure of the semiconductor device 716 shown here is merely an example, and other circuits such as a sense amplifier, an output circuit, and a buffer may be included, and a writing circuit may be provided in the bit line driver circuit.

The memory cell array 722 includes a first conductive layer connected to the bit line Bx (1 ≦ x ≦ m), a second conductive layer connected to the word line Wy (1 ≦ y ≦ n), and an organic compound layer And have. The organic compound layer is provided as a single layer or a stacked layer between the first conductive layer and the second conductive layer.

2A is a top view of the memory cell array 722, and FIGS. 2B and 2C are cross-sectional views taken along line AB in FIG. 2A. In FIG. 2A, the insulating layer 754 is omitted and not shown, but is provided as shown in FIGS. 2B and 2C.

The memory cell array 722 includes a first conductive layer 751a, a first conductive layer 751b, a first conductive layer 751c, a first conductive layer 751a, a first conductive layer 751b, and a first layer extending in the first direction. An organic compound layer 752 provided to cover the conductive layer 751c, a second conductive layer 753a, a second conductive layer 753b, and a second conductive layer 753c extending in a second direction perpendicular to the first direction; (See FIG. 2A). An organic compound layer 752 is provided between the first conductive layer 751a, the first conductive layer 751b, the first conductive layer 751c, the second conductive layer 753a, the second conductive layer 753b, and the second conductive layer 753c. Is provided. In addition, an insulating layer 754 serving as a protective film is provided so as to cover the second conductive layer 753a, the second conductive layer 753b, and the second conductive layer 753c (see FIG. 2B). Note that when there is a concern about the influence of a horizontal electric field between adjacent memory cells, the organic compound layer 752 provided in each memory cell may be separated.

FIG. 2C is a modification example of FIG. 2B, in which a first conductive layer 791a, a first conductive layer 791b, a first conductive layer 791c, an organic compound layer 792, and a first conductive layer 792 are formed over a substrate 790. 2 conductive layers 793b and an insulating layer 794 which is a protective layer. As in the first conductive layer 791a, the first conductive layer 791b, and the first conductive layer 791c in FIG. 2C, the first conductive layer may have a tapered shape, and the curvature radius may be continuous. The shape may change. Shapes such as the first conductive layer 791a, the first conductive layer 791b, and the first conductive layer 791c can be formed by a droplet discharge method or the like. When the curved surface has such a curvature, the coverage of the organic compound layer and the conductive layer to be stacked is good.

In addition, a partition wall (insulating layer) may be formed so as to cover an end portion of the first conductive layer. The partition (insulating layer) functions like a wall separating other memory elements. 6A and 6B illustrate a structure in which the end portion of the first conductive layer is covered with a partition wall (insulating layer).

6A, an organic compound layer 772 is formed over the first conductive layer 771a, the first conductive layer 771b, and the first conductive layer 771c, and the second conductive layer is formed over the organic compound layer 772. An example of forming 773b is shown. In this embodiment, a partition wall (insulating layer) 775 to be a partition wall is formed in a tapered shape so as to cover end portions of the first conductive layer 771a, the first conductive layer 771b, and the first conductive layer 771c. Is done. A partition (insulating layer) 775 is formed over the first conductive layer 771a, the first conductive layer 771b, and the first conductive layer 771c provided over the substrate 770, and the organic compound layer 772 and the second conductive layer are formed. 773b and an insulating layer 774 are formed.

In the semiconductor device illustrated in FIG. 6B, the partition wall (insulating layer) 765 has a curvature, and the curvature radius thereof is continuously changed. 6B, an organic compound layer 762 is formed over the first conductive layer 761a, the first conductive layer 761b, and the first conductive layer 761c, and a second conductive layer 763b is formed over the organic compound layer 762. An example of forming is shown. An insulating layer 764 serving as a protective layer is formed over the second conductive layer 763b. The insulating layer 764 is not necessarily formed.

The first conductive layer, the organic compound layer, and the second conductive layer in FIGS. 2 and 6 may be formed using the same materials and steps as those in Embodiment Mode 1.

In the structure of the memory cell, as the substrate 750, the substrate 760, the substrate 770, and the substrate 780, a glass substrate, a flexible substrate, a quartz substrate, a silicon substrate, a metal substrate, a stainless steel substrate, or the like can be used. The flexible substrate is a substrate that can be bent (flexible), and examples thereof include a plastic substrate made of polycarbonate, polyarylate, polyethersulfone, or the like. It is also possible to use films (made of polypropylene, polyester, vinyl, polyvinyl fluoride, vinyl chloride, etc.), paper made of fibrous materials, substrate films (polyester, polyamide, inorganic vapor deposition film, papers, etc.), etc. it can. In addition, a memory cell array 722 may be provided above a field effect transistor (FET) formed on a semiconductor substrate such as Si or above a thin film transistor (TFT) formed on a substrate such as glass. it can. Further, the substrate may be processed to have a thinner thickness by forming a memory element on the substrate or performing a polishing process, etching with a solution, or the like during the formation process.

In the memory element in FIG. 2, the first conductive layers 751a, 751b, and 751c and the second conductive layers 753a, 753b, and 753c have a peripheral portion (peripheral end portion) unevenness, and have a rectangular bent portion. It has a shape. Therefore, the memory cell 721 which is a memory element also reflects the shapes of the first conductive layer 751b and the second conductive layer 753b, and is a memory element having unevenness in the periphery instead of a rectangle (square).

Since the memory element having the shape as shown in FIG. 2 is manufactured in a shape having a bent portion or unevenness, the peripheral length of the memory element becomes long. Therefore, in such a memory element, when a rectangle having the same area is considered, the ratio of the long side to the short side increases as the peripheral length increases. In the present invention, the ratio of the long side to the short side (the ratio of the long side to the short side) is preferably 3 or more, and more preferably 6 or more. Further, when a square is formed with the same peripheral length as the memory element of this embodiment, the area of the square is larger than the area of the memory element of this embodiment. In the present invention, the ratio of the square area to the area of the memory element relative to the square area is preferably 0.75 or less, and more preferably 0.5 or less.

In the present invention, the shape of the memory element is a rectangle having an uneven portion around it, a zigzag shape having one or more bent portions, a comb shape, or a ring shape (ring shape) having an opening (space) inside. Is used. In addition, a rectangle having a large ratio between the long side and the short side, and an ellipse having a large ratio between the long diameter and the short diameter can be used.

Such a memory element of this embodiment can perform normal writing and can reduce a writing failure rate. In addition, the writing characteristics of the plurality of memory elements are stabilized without variation. Therefore, by using such a memory element, a semiconductor device with high reliability in writing can be manufactured.

As the partition wall (insulating layer) 765 and the partition wall (insulating layer) 775, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, and other inorganic insulating materials, acrylic acid, methacrylic acid, and the like Or a heat resistant polymer such as polyimide, aromatic polyamide, polybenzimidazole, or a siloxane resin. Note that a siloxane resin corresponds to a resin including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent. Further, a resin material such as a vinyl resin such as polyvinyl alcohol or polyvinyl butyral, an epoxy resin, a phenol resin, a novolac resin, an acrylic resin, a melamine resin, or a urethane resin is used. Alternatively, an organic material such as benzocyclobutene, parylene, or polyimide, or a composition material containing a water-soluble homopolymer and a water-soluble copolymer may be used. As a manufacturing method, a vapor deposition method such as a plasma CVD method or a thermal CVD method, or a sputtering method can be used. Alternatively, a droplet discharge method or a printing method (a method for forming a pattern such as screen printing or offset printing) can be used. A coating film obtained by a coating method can also be used.

Further, after a conductive layer, an insulating layer, or the like is formed by discharging a composition by a droplet discharge method, the surface may be flattened by pressing with a pressure in order to improve the flatness. As a pressing method, unevenness may be reduced by scanning a roller-shaped object on the surface, and the surface may be pressed with a flat plate-like object. A heating step may be performed when pressing. Alternatively, the surface may be softened or dissolved with a solvent or the like, and the surface irregularities may be removed with an air knife. Further, polishing may be performed using a CMP method. This step can be applied when the surface is flattened when unevenness is generated by the droplet discharge method.

As shown in FIG. 16 of Embodiment 1, the organic compound layer and the first conductive layer, or the organic compound layer and the second conductive layer, or both the first conductive layer and the second conductive layer, and the organic compound. An insulating layer may be provided between each of the layers. By providing the insulating layer, characteristics such as a write voltage of the memory element are stabilized without variation, and normal writing can be performed in each element. In addition, since the carrier injecting property is improved by providing the insulating layer, the organic compound layer can be thickened. Therefore, it is possible to prevent the memory element from being short-circuited in the initial state before energization.

  In the above structure of this embodiment, the first conductive layers 751a to 751c, the first conductive layers 761a to 761c, the first conductive layers 771a to 771c, the first conductive layers 791a to 791c, and the organic compound A rectifying element may be provided between the layer 752, the organic compound layer 762, the organic compound layer 772, and the organic compound layer 792. The element having a rectifying property is a transistor or a diode in which a gate electrode and a drain electrode are connected. In this way, by providing a rectifying diode, current flows only in one direction, so that errors are reduced and reading reliability is improved. Note that the rectifying element includes an organic compound layer 752, an organic compound layer 762, an organic compound layer 772, an organic compound layer 792, second conductive layers 753a to 753c, and second conductive layers 763a to 763c (763b only). The second conductive layers 773a to 773c (only 773b shown) and the second conductive layers 793a to 793c (only 793b shown) may be provided.

According to the present invention, the characteristics of the memory element are stabilized without variation and normal writing can be performed. Therefore, a highly reliable semiconductor device can be manufactured with high yield without complicating the device and the process.

(Embodiment 3)
In this embodiment mode, a semiconductor device having a structure different from that of Embodiment Mode 2 will be described. Specifically, the case where the structure of the semiconductor device is an active matrix type is described. The memory element in this embodiment can be manufactured using the same material and structure as those in Embodiment 1. Therefore, detailed description of materials and the like is omitted.

FIG. 5 illustrates a structural example of the semiconductor device described in this embodiment. The semiconductor device includes a memory cell array 232 in which memory cells 231 are provided in a matrix, a circuit 226, a decoder 224, and a decoder 223. The circuit 226 includes a reading circuit and a writing circuit. Note that the structure of the semiconductor device 217 shown here is merely an example, and other circuits such as a sense amplifier, an output circuit, and a buffer may be included, and a writing circuit may be provided in the bit line driver circuit.

The memory cell array 232 includes a first conductive layer connected to the bit line Bx (1 ≦ x ≦ m), a second conductive layer connected to the word line Wy (1 ≦ y ≦ n), a transistor 210a, and a memory An element 215b and a memory cell 231 are included. The memory element 215b has a structure in which an organic compound layer is sandwiched between a pair of conductive layers. The gate electrode of the transistor is connected to the word line, either the source electrode or the drain electrode is connected to the bit line, and the other is connected to one of the two terminals of the memory element. The remaining one terminal of the memory element is connected to a common electrode (potential Vcom).

4A is a top view of the memory cell array 232, and FIG. 4B is a cross-sectional view taken along line EF in FIG. 4A. In FIG. 4A, the organic compound layer 212, the second conductive layer 213, and the insulating layer 214 are omitted and not shown, but are provided as shown in FIG. 4B.

The memory cell array 232 includes a first wiring 205a and a first wiring 205b extending in a first direction and a second wiring 202 extending in a second direction perpendicular to the first direction in a matrix. It has been. The first wiring 205a and the first wiring 205b are connected to the source electrode or the drain electrode of the transistor 210a and the transistor 210b, and the second wiring 202 is connected to the gate electrode of the transistor 210a and the transistor 210b. . Further, the first conductive layer 203a and the first conductive layer 203b are connected to the source electrode or the drain electrode of the transistor 210a and the transistor 210b which are not connected to the first wiring, respectively. A memory element 215a and a memory element 215b are provided by a stacked structure of the first conductive layer 203b, the organic compound layer 212, and the second conductive layer 213. A partition wall (insulating layer) 207 (207a, 207b, 207c) is provided between each adjacent memory cell 231, and the organic compound layer 212 and the second conductive layer are formed over the first conductive layer and the partition wall (insulating layer) 207. A layer 213 is stacked. An insulating layer 214 serving as a protective layer is provided over the second conductive layer 213. Thin film transistors are used as the transistors 210a and 210b (see FIG. 4B).

The first conductive layer, the organic compound layer, and the second conductive layer in FIGS. 2 and 6 may be formed using the same materials and steps as those in Embodiment Mode 1.

In the structure of the memory cell, as the substrate 200 and the substrate 280, a glass substrate, a flexible substrate, a quartz substrate, a silicon substrate, a metal substrate, a stainless steel substrate, or the like can be used. The flexible substrate is a substrate that can be bent (flexible), and examples thereof include a plastic substrate made of polycarbonate, polyarylate, polyethersulfone, or the like. It is also possible to use films (made of polypropylene, polyester, vinyl, polyvinyl fluoride, vinyl chloride, etc.), paper made of fibrous materials, substrate films (polyester, polyamide, inorganic vapor deposition film, papers, etc.), etc. it can. In addition, a memory cell array can be provided above a field effect transistor (FET) formed on a semiconductor substrate such as Si or above a thin film transistor (TFT) formed on a substrate such as glass. .

In the memory element of FIG. 4, the first conductive layer 203 a and the first conductive layer 203 b have a peripheral portion (peripheral end portion) unevenness and have a comb shape. Therefore, the shape of the first conductive layer 203a and the first conductive layer 203b is reflected in the memory element 215a and the memory element 215b, and the memory element 215a and the memory element 215b are not rectangular (square) but comb-shaped memory elements having unevenness in the periphery.

Since the memory element having the shape as shown in FIG. 4 is manufactured in a shape having a bent portion or unevenness, the peripheral length of the memory element becomes long. Therefore, in such a memory element, when a rectangle having the same area is considered, the ratio of the long side to the short side increases as the peripheral length increases. In the present invention, the ratio of the long side to the short side (the ratio of the long side to the short side) is preferably 3 or more, and more preferably 6 or more. Further, when a square is formed with the same peripheral length as the memory element of this embodiment, the area of the square is larger than the area of the memory element of this embodiment. In the present invention, the ratio of the square area to the area of the memory element relative to the square area is preferably 0.75 or less, and more preferably 0.5 or less.

In the present invention, the shape of the memory element is a rectangle having an uneven portion around it, a zigzag shape having one or more bent portions, a comb shape, or a ring shape (ring shape) having an opening (space) inside. Is used. In addition, a rectangle having a large ratio between the long side and the short side, and an ellipse having a large ratio between the long diameter and the short diameter can be used.

Such a memory element of this embodiment can perform normal writing and can reduce a writing failure rate. In addition, the writing characteristics of the plurality of memory elements are stabilized without variation. Therefore, by using such a memory element, a semiconductor device with high reliability in writing can be manufactured.

The semiconductor device in FIG. 4B is provided over a substrate 200, and includes an insulating layer 201a, an insulating layer 201b, an insulating layer 208, an insulating layer 209, an insulating layer 211, a semiconductor layer 204a included in the transistor 210a, and a gate electrode layer. 202a, a wiring 205a also serving as a source electrode layer or a drain electrode layer, a semiconductor layer 204b included in the transistor 210b, and a gate electrode layer 202b.

As shown in FIG. 16 of Embodiment 1, the organic compound layer and the first conductive layer, or the organic compound layer and the second conductive layer, or both the first conductive layer and the second conductive layer, and the organic compound. An insulating layer may be provided between each of the layers. By providing the insulating layer, characteristics such as a write voltage of the memory element are stabilized without variation, and normal writing can be performed in each element. In addition, since the carrier injecting property is improved by providing the insulating layer, the organic compound layer can be thickened. Therefore, it is possible to prevent the memory element from being short-circuited in the initial state before energization.

An interlayer insulating layer may be provided over the transistors 210a and 210b. In the structure of FIG. 4B, the storage element 215a and the storage element 215b need to be provided in a region avoiding the source electrode layer or the drain electrode layer of the transistor 210a and the transistor 210b, but by providing an interlayer insulating layer, For example, the memory element 215a and the memory element 215b can be formed above the transistors 210a and 210b. As a result, the semiconductor device 217 can be more highly integrated.

The transistors 210a and 210b may have any structure as long as they can function as switching elements. As the semiconductor layer, various semiconductors such as an amorphous semiconductor, a crystalline semiconductor, a polycrystalline semiconductor, and a microcrystalline semiconductor can be used, and an organic transistor may be formed using an organic compound. FIG. 4B illustrates an example in which a planar thin film transistor is provided over an insulating substrate; however, a transistor can be formed with a staggered structure, an inverted staggered structure, or the like.

A material for forming a semiconductor layer included in the transistors 210a and 210b is an amorphous semiconductor (hereinafter also referred to as “AS”) manufactured by a vapor deposition method or a sputtering method using a semiconductor material gas typified by silane or germane. A polycrystalline semiconductor obtained by crystallizing the amorphous semiconductor using light energy or thermal energy, or a semi-amorphous (also referred to as microcrystal or microcrystal; hereinafter also referred to as “SAS”) semiconductor can be used. . The semiconductor layer can be formed by a known means (such as sputtering, LPCVD, or plasma CVD).

SAS is a semiconductor having an intermediate structure between amorphous and crystalline structures (including single crystal and polycrystal) and having a third state that is stable in terms of free energy and has a short-range order and a lattice. It includes a crystalline region with strain. SAS is formed by glow discharge decomposition (plasma CVD) of a gas containing silicon. As a gas containing silicon, SiH ₄ , Si ₂ H ₆ , SiH ₂ Cl ₂ , SiHCl ₃ , SiCl ₄ , SiF _4, or the like can be used. Further, F ₂ and GeF ₄ may be mixed. The gas containing silicon may be diluted with H ₂ , or H ₂ and one or more kinds of rare gas elements selected from He, Ar, Kr, and Ne. In addition, a SAS layer formed of a hydrogen-based gas may be stacked on a SAS layer formed of a fluorine-based gas as a semiconductor layer.

A typical example of an amorphous semiconductor is hydrogenated amorphous silicon, and a typical example of a crystalline semiconductor is polysilicon. Polysilicon (polycrystalline silicon) is mainly made of so-called high-temperature polysilicon using polysilicon formed through a process temperature of 800 ° C. or higher as a main material, or polysilicon formed at a process temperature of 600 ° C. or lower. And so-called low-temperature polysilicon, and polysilicon crystallized by adding an element that promotes crystallization. Of course, as described above, a semi-amorphous semiconductor or a semiconductor including a crystal phase in a part of the semiconductor layer can also be used.

As a semiconductor material, a compound semiconductor such as GaAs, InP, SiC, ZnSe, GaN, or SiGe can be used in addition to a simple substance such as silicon (Si) or germanium (Ge). Alternatively, zinc oxide (ZnO), tin oxide (SnO ₂ ), or the like which is an oxide semiconductor can be used. When ZnO is used for the semiconductor layer, the gate insulating layer is formed of Y ₂ O ₃ , Al ₂ O ₃ , TiO ₂ , A stacked layer of them is preferably used, and ITO, Au, Ti, or the like is preferably used for the gate electrode layer, the source electrode layer, and the drain electrode layer. In addition, In, Ga, or the like can be added to ZnO.

In the case where a crystalline semiconductor layer is used for the semiconductor layer, a method for manufacturing the crystalline semiconductor layer can be a known method (laser crystallization method, thermal crystallization method, or heat using an element that promotes crystallization such as nickel. A crystallization method or the like may be used. In addition, a microcrystalline semiconductor that is a SAS can be crystallized by laser irradiation to improve crystallinity. In the case where an element for promoting crystallization is not introduced, the amorphous silicon film is heated at 500 ° C. for 1 hour in a nitrogen atmosphere before irradiating the amorphous silicon film with laser light, whereby the concentration of hydrogen contained in the amorphous silicon film is set to 1 ×. Release to 10 ²⁰ atoms / cm ³ or less. This is because the film is destroyed when the amorphous silicon film containing a large amount of hydrogen is irradiated with laser light.

The method of introducing the metal element into the amorphous semiconductor layer is not particularly limited as long as the metal element can be present on the surface of the amorphous semiconductor layer or inside the amorphous semiconductor layer. For example, sputtering, CVD, A plasma treatment method (including a plasma CVD method), an adsorption method, or a method of applying a metal salt solution can be used. Among these, the method using a solution is simple and useful in that the concentration of the metal element can be easily adjusted. At this time, in order to improve the wettability of the surface of the amorphous semiconductor layer and to spread the aqueous solution over the entire surface of the amorphous semiconductor layer, irradiation with UV light in an oxygen atmosphere, thermal oxidation method, hydroxy radical It is desirable to form an oxide film by treatment with ozone water or hydrogen peroxide.

Further, in the crystallization step of crystallizing the amorphous semiconductor layer to form the crystalline semiconductor layer, an element for promoting crystallization (also referred to as a catalyst element or a metal element) is added to the amorphous semiconductor layer, and heat treatment ( Crystallization may be carried out at 550 ° C. to 750 ° C. for 3 minutes to 24 hours. As elements for promoting crystallization, metal elements for promoting crystallization of silicon include iron (Fe), nickel (Ni), cobalt (Co), ruthenium (Ru), rhodium (Rh), palladium (Pd). One or a plurality of types selected from osmium (Os), iridium (Ir), platinum (Pt), copper (Cu), and gold (Au) can be used.

In order to remove or reduce an element that promotes crystallization from the crystalline semiconductor layer, a semiconductor layer containing an impurity element is formed in contact with the crystalline semiconductor layer and functions as a gettering sink. As the impurity element, an impurity element imparting n-type conductivity, an impurity element imparting p-type conductivity, a rare gas element, or the like can be used. For example, phosphorus (P), nitrogen (N), arsenic (As), antimony (Sb ), Bismuth (Bi), boron (B), helium (He), neon (Ne), argon (Ar), Kr (krypton), and Xe (xenon) can be used. A semiconductor layer containing a rare gas element is formed over the crystalline semiconductor layer containing an element that promotes crystallization, and heat treatment (at 550 ° C. to 750 ° C. for 3 minutes to 24 hours) is performed. The element that promotes crystallization contained in the crystalline semiconductor layer moves into the semiconductor layer containing a rare gas element, and the element that promotes crystallization in the crystalline semiconductor layer is removed or reduced. After that, the semiconductor layer containing a rare gas element that has become a gettering sink is removed.

The crystallization of the amorphous semiconductor layer may be a combination of heat treatment and crystallization by laser light irradiation, or may be performed multiple times by heat treatment or laser light irradiation alone.

Alternatively, the crystalline semiconductor layer may be directly formed over the substrate by a plasma method. Alternatively, the crystalline semiconductor layer may be selectively formed over the substrate by a plasma method.

As a semiconductor, an organic semiconductor material can be used and formed by a printing method, a spray method, a spin coating method, a droplet discharge method, or the like. In this case, the number of processes can be reduced because the etching process is not necessary. As the organic semiconductor, a low molecular material, a polymer material, or the like is used, and materials such as an organic dye or a conductive polymer material can also be used. As the organic semiconductor material, a π-electron conjugated polymer material whose skeleton is composed of conjugated double bonds is desirable. Typically, a soluble polymer material such as polythiophene, polyfluorene, poly (3-alkylthiophene), a polythiophene derivative, or pentacene can be used.

In addition, as an organic semiconductor material that can be used in the present invention, there is a material that can form a semiconductor layer by processing after forming a soluble precursor. Examples of such an organic semiconductor material include polythienylene vinylene, poly (2,5-thienylene vinylene), polyacetylene, a polyacetylene derivative, and polyarylene vinylene.

When converting the precursor into an organic semiconductor, a reaction catalyst such as hydrogen chloride gas is added as well as heat treatment. Typical solvents for dissolving these soluble organic semiconductor materials include toluene, xylene, chlorobenzene, dichlorobenzene, anisole, chloroform, dichloromethane, γ-butyllactone, butyl cellosolve, cyclohexane, NMP (N-methyl-2) -Pyrrolidone), cyclohexanone, 2-butanone, dioxane, dimethylformamide (DMF), THF (tetrahydrofuran), or the like can be applied.

The gate electrode layer can be formed by a CVD method, a sputtering method, a droplet discharge method, or the like. The gate electrode layer is an element selected from Ag, Au, Cu, Ni, Pt, Pd, Ir, Rh, W, Al, Ta, Mo, Cd, Zn, Fe, Ti, Si, Ge, Zr, Ba, Alternatively, an alloy material or a compound material containing the element as a main component may be used. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus, or an AgPdCu alloy may be used. Alternatively, a single-layer structure or a multi-layer structure may be employed, for example, a two-layer structure of a tungsten nitride film and a molybdenum film, a tungsten film with a thickness of 50 nm, an alloy of aluminum and silicon with a thickness of 500 nm (Al- A three-layer structure in which a Si) film and a titanium nitride film with a thickness of 30 nm are sequentially stacked may be employed. In the case of a three-layer structure, tungsten nitride may be used instead of tungsten of the first conductive film, or aluminum instead of the aluminum and silicon alloy (Al-Si) film of the second conductive film. A titanium alloy film (Al—Ti) may be used, or a titanium film may be used instead of the titanium nitride film of the third conductive film.

A light-transmitting material having a light-transmitting property with respect to visible light can also be used for the gate electrode layer. As the light-transmitting conductive material, indium tin oxide (ITO), indium tin oxide containing silicon oxide (ITSO), organic indium, organic tin, zinc oxide, or the like can be used. Indium zinc oxide containing zinc oxide (ZnO) (IZO (indium zinc oxide)), ZnO doped with gallium (Ga), tin oxide (SnO ₂ ), indium oxide containing tungsten oxide, tungsten oxide Indium zinc oxide containing, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, or the like may also be used.

In the case where processing is required by etching to form the gate electrode layer, a mask may be formed and processed by dry etching or dry etching. Using an ICP (Inductively Coupled Plasma) etching method, the etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the substrate-side electrode, the electrode temperature on the substrate side, etc.) are appropriately set. By adjusting, the electrode layer can be etched into a tapered shape. As an etching gas, a chlorine-based gas typified by Cl ₂ , BCl ₃ , SiCl _4, CCl _4, etc., a fluorine-based gas typified by CF ₄ , SF _6, NF _3, etc., or O ₂ is appropriately used. be able to.

Although the single gate structure is described in this embodiment mode, a multi-gate structure such as a double gate structure may be used. In this case, a gate electrode layer may be provided above and below the semiconductor layer, or a plurality of gate electrode layers may be provided only on one side (above or below) of the semiconductor layer. The semiconductor layer may have impurity regions with different concentrations. For example, the vicinity of the channel region of the semiconductor layer and the region stacked with the gate electrode layer may be low-concentration impurity regions, and the outer region may be high-concentration impurity regions.

FIG. 7 shows an example using a thin film transistor having an inverted staggered structure. FIG. 7 is a cross-sectional view corresponding to a cross section taken along line GH in the semiconductor device in FIG. A transistor 290 which is a thin film transistor having an inverted staggered structure is provided over the substrate 280. The transistor 290 includes an insulating layer 288, a gate electrode layer 281, an amorphous semiconductor layer 282, a semiconductor layer 283a having one conductivity type, a semiconductor layer 283b having one conductivity type, a source or drain electrode layer 285, The other of the source electrode layer and the drain electrode layer is a first conductive layer 286 that forms a memory element. The first conductive layer 286 is selectively covered with a partition wall (insulating layer) 287a, a partition wall (insulating layer) 287b, a partition wall (insulating layer) 287c, and a partition wall (insulating layer) 287d, and is over the first conductive layer 286. An organic compound layer 292 is formed in contact with the first conductive layer 286 in addition to the partition wall (insulating layer) formation region. A second conductive layer 293 and an insulating layer 294 which is a protective layer are formed over the organic compound layer 292, so that the memory element 295 is formed.

In the memory element 295 in FIG. 7A, an organic compound layer formed in contact with the first conductive layer 286 is formed in a desired region by selectively providing a partition wall formed over the first conductive layer 286. This is an example of forming selectively. In this case, the first conductive layer and the organic compound layer are not formed in contact with each other in the region where the partition wall is formed. FIG. 7B illustrates an example in which the first conductive layer 286 is also processed into a shape corresponding to the memory element 295. In FIG. 7A, the first conductive layer 286 below the partition wall is continuously formed. In FIG. 7B, the shape of the first conductive layer also corresponds to the shape of the memory element. The first conductive layer 286a, the first conductive layer 286b, and the first conductive layer 286c may be processed. In FIG. 7B, since it is a cross-sectional view taken along line GH, the first conductive layers 286a to 286c appear discontinuous, but are continuous as shown in FIG. 4A. .

In the present invention, a memory element in which an organic compound layer is provided between a conductive layer (a first conductive layer and a second conductive layer) functioning as a pair of electrodes is used as the memory element. Therefore, the memory element is a stacked region including at least the first conductive layer, the organic compound layer, and the second conductive layer, and the shape of the memory element is the shape of the stacked body. The shape of the memory element can be controlled by the shape of each of the first conductive layer, the organic compound layer, and the second conductive layer. For example, in order to form the memory element in the above shape, the first conductive layer is formed in a desired shape. A memory element reflecting the shape of the first conductive layer is formed by stacking an organic compound layer and a second conductive layer on the first conductive layer formed in a desired shape. Alternatively, an insulating layer serving as a partition can be selectively formed over the first conductive layer, and a region of the organic compound layer formed in contact with the first conductive layer can be selectively controlled.

7A and 7B, a gate electrode layer 281, a source or drain electrode layer 285, a first conductive layer 286, and a partition wall (insulating layer) 287 are formed by a droplet discharge method. May be. The droplet discharge method is a method in which a composition containing a composition forming material that is a fluid is discharged (jetted) as droplets to form a desired pattern shape. A droplet containing a component forming material is discharged onto a region where the component is to be formed, and fixed by firing, drying, or the like to form a component having a desired pattern.

In the case of forming a conductive layer by using a droplet discharge method, a conductive layer is formed by discharging a composition containing a conductive material processed into a particulate form and fusing or fusion-bonding and solidifying by firing. In such a conductive layer (or insulating layer) formed by discharging and baking a composition containing a conductive material, the conductive layer (or insulating layer) formed by sputtering or the like is mostly a columnar structure. In many cases, a polycrystalline state having many grain boundaries is exhibited.

As shown in FIGS. 8A and 8B, a semiconductor device of the present invention can be manufactured using a single crystal semiconductor substrate. 8A is a top view of the semiconductor device, and FIG. 8B is a cross-sectional view corresponding to line I-J in FIG. 8A. As illustrated in FIG. 8, the memory element 265 a and the memory element 265 b are connected to the field effect transistor 260 a and the field effect transistor 260 b provided over the single crystal semiconductor substrate 250. Here, an insulating layer 270 is provided so as to cover the source or drain electrode layers 255a to 255d of the field effect transistor 260a and the field effect transistor 260b, and the first conductive layer 256a and the first conductive layer are provided over the insulating layer 270. The memory element 265a and the memory element 265b include the 256b, the partition wall (insulating layer) 267 (267a to 267e), the organic compound layer 262a, the organic compound layer 262b, the second conductive layer 263a, and the second conductive layer 263b. The organic compound layer such as the organic compound layer 262a and the organic compound layer 262b may be selectively provided only in each memory cell using a mask or the like. The semiconductor device illustrated in FIG. 8 also includes an element isolation region 268, an insulating layer 269, an insulating layer 261, and an insulating layer 264.

In FIG. 8, the memory element 265 a and the memory element 265 b are shaped like a U shape having a concavo-convex portion in the periphery, reflecting the shape of the opening of the partition formed over the first conductive layer. . Therefore, in FIG. 8B, which is a cross-sectional view taken along line I-J in FIG. 8A, partition walls (insulating layers) 267a to 267c are selectively formed over the first conductive layer 256a. Partition walls (insulating layers) 267c to 267e are selectively formed over the conductive layer 256b. In addition to the formation region of the partition walls (insulating layers) 267a to 267e over the first conductive layer 256a and the first conductive layer 256b, the organic compound layer 262a, the organic compound layer 262b, the second conductive layer 263a, and the second conductive layer The layers 263b are stacked to form the memory element 265a and the memory element 265b having square bent portions.

In addition, by providing the insulating layer 270 to form a memory element, the first conductive layer can be freely arranged. In other words, in the structure in FIG. 4B, the memory element 215a and the memory element 215b need to be provided in a region where the source electrode layer or the drain electrode layer of the transistor 210a and the transistor 210b are avoided. For example, the memory element 215a and the memory element 215b can be formed above the transistors 210a and 210b. As a result, the semiconductor device 217 can be more highly integrated.

Since the memory element having the shape as shown in FIG. 8 is manufactured in a shape having a bent portion or unevenness, the peripheral length of the memory element becomes long. Therefore, in such a memory element, when a rectangle having the same area is considered, the ratio of the long side to the short side increases as the peripheral length increases. In the present invention, the ratio of the long side to the short side (the ratio of the long side to the short side) is preferably 3 or more, and more preferably 6 or more. Further, when a square is formed with the same peripheral length as the memory element of this embodiment, the area of the square is larger than the area of the memory element of this embodiment. In the present invention, the ratio of the square area to the area of the memory element relative to the square area is preferably 0.75 or less, and more preferably 0.5 or less.

Such a memory element of this embodiment can perform normal writing and can reduce a writing failure rate. In addition, the writing characteristics of the plurality of memory elements are stabilized without variation. Therefore, by using such a memory element, a semiconductor device with high reliability in writing can be manufactured.

In addition, any structure of a semiconductor layer included in the transistor may be used, for example, an impurity region (including a source region, a drain region, and an LDD region) may be formed, or a p-channel type or an n-channel You may form with either type | mold. Further, an insulating layer (side wall) may be formed so as to be in contact with the side surface of the gate electrode, or a silicide layer may be formed on one or both of the source region, the drain region, and the gate electrode. As a material for the silicide layer, nickel, tungsten, molybdenum, cobalt, platinum, or the like can be used.

The materials and formation methods of the first conductive layers 203a, 203b, 256a, 256b, and 286 and the second conductive layers 213, 263a, 263b, and 293 described in this embodiment are the same as those described in Embodiment 1 above. And any of the formation methods.

In addition, the organic compound layers 212, 262 a, 262 b, and 292 can be provided using a material and a formation method similar to those of the organic compound layer described in Embodiment Mode 1.

Further, a rectifying element may be provided between the first conductive layers 203a, 203b, 256a, 256b, and 286 and the organic compound layers 212, 262a, 262b, and 292. The element having a rectifying property is a transistor or a diode in which a gate electrode and a drain electrode are connected. For example, a PN junction diode provided by stacking an N-type semiconductor layer and a P-type semiconductor layer can be used. In this way, by providing a rectifying diode, current flows only in one direction, so that errors are reduced and reading reliability is improved. Note that when a diode is provided, a diode having another structure such as a diode having a PIN junction or an avalanche diode may be used instead of a diode having a PN junction. Note that the organic compound layers 212, 262a, 262b, and 292 may be provided between the second conductive layers 213, 263a, 263b, and 293.

According to the present invention, the characteristics of the memory element are stabilized without variation and normal writing can be performed. Therefore, a highly reliable semiconductor device can be manufactured with high yield without complicating the device and the process.

(Embodiment 4)
In this embodiment, an example of the semiconductor device described in the above embodiment will be described with reference to drawings.

The semiconductor device described in this embodiment is characterized in that data can be read and written in a non-contact manner. A data transmission format is an electromagnetic which performs communication by mutual induction with a pair of coils arranged opposite to each other. There are roughly divided into a coupling system, an electromagnetic induction system that communicates using an induction electromagnetic field, and a radio system that communicates using radio waves, but any system may be used. In addition, there are two types of antennas used for data transmission. When one antenna is provided on a substrate on which a plurality of elements and memory elements are provided, the other is provided with a plurality of elements and memory elements. In some cases, a terminal portion is provided over the substrate, and an antenna provided over another substrate is connected to the terminal portion.

First, a structure example of a semiconductor device in the case where an antenna is provided over a substrate provided with a plurality of elements and memory elements will be described with reference to FIGS.

FIG. 10 illustrates a semiconductor device including an active matrix type. A transistor portion 330 including transistors 310a and 310b on a substrate 300, a transistor portion 340 including transistors 320a and 320b, insulating layers 301a, 301b, 308, and An element formation layer 335 including 311, 316, and 314 is provided, and a storage element portion 325 and a conductive layer 343 functioning as an antenna are provided above the element formation layer 335.

Note that here, the case where the memory element portion 325 or the conductive layer 343 functioning as an antenna is provided above the element formation layer 335 is shown; however, the structure is not limited thereto, and the memory element portion 325 or the conductive layer 343 functioning as an antenna is provided. Can be provided below the element formation layer 335 or in the same layer.

The memory element portion 325 includes memory elements 315a and 315b. The memory element 315a includes an organic compound layer 312 and a second conductive layer 313 stacked over the first conductive layer 306a. The memory element 315b includes The organic compound layer 312 and the second conductive layer 313 are stacked over the first conductive layer 306b. In addition, an insulating layer 314 that covers the second conductive layer 313 and functions as a protective film is formed. A partition wall (insulating layer) 307a is on the first conductive layer 306a, a partition wall (insulating layer) 307b is on the first conductive layer 306a and the first conductive layer 306b, and a partition wall (insulating layer) 307c is on the first conductive layer. Over the layer 306a and the conductive layer 341. The first conductive layer 306a and the first conductive layer 306b in which the plurality of memory elements 315a and 315b are formed are connected to the source electrode layer or the drain electrode layer of each of the transistors 310a and 310b. That is, each memory element is connected to one transistor. Further, the organic compound layer 312 is formed over the entire surface so as to cover the first conductive layers 306a and 306b and the partition walls (insulating layers) 307a, 307b, and 307c, but may be selectively formed in each memory cell. Good. Note that the memory elements 315a and 315b can be formed using any of the materials and manufacturing methods described in the above embodiment modes.

Since the memory element 315a and the memory element 315b in FIG. 10 are also formed in a shape having a bent portion or unevenness, the peripheral length of the memory element is increased. Therefore, in such a memory element, when a rectangle having the same area is considered, the ratio of the long side to the short side increases as the peripheral length increases. In the present invention, the ratio of the long side to the short side (the ratio of the long side to the short side) is preferably 3 or more, and more preferably 6 or more. Further, when a square is formed with the same peripheral length as the memory element of this embodiment, the area of the square is larger than the area of the memory element of this embodiment. In the present invention, the ratio of the square area to the area of the memory element relative to the square area is preferably 0.75 or less, and more preferably 0.5 or less.

In the present invention, the shape of the memory element is a rectangle having an uneven portion around it, a zigzag shape having one or more bent portions, a comb shape, or a ring shape (ring shape) having an opening (space) inside. Is used. In addition, a rectangle having a large ratio between the long side and the short side, and an ellipse having a large ratio between the long diameter and the short diameter can be used.

Such a memory element of this embodiment can perform normal writing and can reduce a writing failure rate. In addition, the writing characteristics of the plurality of memory elements are stabilized without variation. Therefore, by using such a memory element, a semiconductor device with high reliability in writing can be manufactured.

Further, in the memory element 315a, as described in the above embodiment, rectification is performed between the first conductive layer 306a and the organic compound layer 312 or between the organic compound layer 312 and the second conductive layer 313. You may provide the element which has. The above-described elements having a rectifying property can also be used. The same applies to the memory element 315b.

Here, the conductive layer 343 functioning as an antenna is provided over the conductive layer 342 formed using the same layer as the second conductive layer 313. Note that a conductive layer functioning as an antenna may be formed using the same layer as the second conductive layer 313.

As a material of the conductive layer 343 functioning as an antenna, gold (Au), platinum (Pt), nickel (Ni), tungsten (W), molybdenum (Mo), cobalt (Co), copper (Cu), aluminum (Al ), Manganese (Mn), titanium (Ti), or the like, or an alloy containing a plurality of such elements can be used. As a method for forming the conductive layer 343 functioning as an antenna, various printing methods such as vapor deposition, sputtering, CVD, screen printing, and gravure printing, a droplet discharge method, or the like can be used.

The transistors 310a, 310b, 320a, and 320b included in the element formation layer 335 can be provided using a p-channel TFT, an n-channel TFT, or a CMOS in which these are combined. Further, any structure of the semiconductor layer included in the transistors 310a, 310b, 320a, and 320b may be used, and for example, an impurity region (including a source region, a drain region, and an LDD region) may be formed. The p channel type or the n channel type may be used. Further, an insulating layer (side wall) may be formed so as to be in contact with the side surface of the gate electrode, or a silicide layer may be formed on one or both of the source region, the drain region, and the gate electrode. As a material for the silicide layer, nickel, tungsten, molybdenum, cobalt, platinum, or the like can be used.

Alternatively, the transistors 310a, 310b, 310c, and 310d included in the element formation layer 335 may be organic transistors in which a semiconductor layer included in the transistor is formed using an organic compound. The element formation layer 335 including an organic transistor can be formed using a printing method, a droplet discharge method, or the like. By using a printing method, a droplet discharge method, or the like, a semiconductor device can be manufactured at lower cost.

The element formation layer 335, the memory elements 315a and 315b, and the conductive layer 343 functioning as an antenna can be formed by vapor deposition, sputtering, CVD, printing, droplet discharge, or the like as described above. . Note that a different method may be used depending on each place. For example, a transistor that requires high-speed operation is provided by forming a semiconductor layer made of Si or the like on a substrate and then crystallizing it by heat treatment, and then forming a transistor that functions as a switching element above the element formation layer by a printing method or An organic transistor can be provided by a droplet discharge method.

Note that a sensor connected to the transistor may be provided. Examples of the sensor include an element that detects temperature, humidity, illuminance, gas (gas), gravity, pressure, sound (vibration), acceleration, and other characteristics by physical or chemical means. The sensor is typically formed of a semiconductor element such as a resistance element, a capacitive coupling element, an inductive coupling element, a photovoltaic element, a photoelectric conversion element, a thermoelectric element, a transistor, a thermistor, or a diode.

Next, a structure example of a semiconductor device in the case where a terminal portion is provided over a substrate provided with a plurality of elements and memory elements and an antenna provided over another terminal is connected to the terminal portion is described with reference to FIG. I will explain.

FIG. 11 illustrates a passive matrix semiconductor device, which includes a transistor portion 380 having transistors 360a and 360b on a substrate 350, a transistor portion 390 having transistors 370a and 370b, and insulating layers 351a, 351b, 358, 359, and 361. An element formation layer 385 including 366 and 384 is provided, and a conductive layer 393 functioning as an antenna provided over the substrate 396 is provided so as to be connected to the conductive layer 392 over the element formation layer 385. Note that here, the case where the memory element portion 375 or the conductive layer 393 functioning as an antenna is provided above the element formation layer 385 is shown; however, the present invention is not limited to this structure, and the memory element portion 375 is provided below the element formation layer 385. A conductive layer 393 functioning as an antenna can be provided below the element formation layer 385 in the same layer.

The memory element portion 375 includes memory elements 365a and 365b. The memory element 365a is configured by stacking an organic compound layer 362a and a second conductive layer 363a on the first conductive layer 356, and the memory element 365b includes The organic compound layer 362b and the second conductive layer 363b are stacked over the first conductive layer 356. A partition wall (insulating layer) 357 a and a partition wall (insulating layer) 357 b are formed over the first conductive layer 356, and a partition wall (insulating layer) 357 c is formed over the first conductive layer 356 and the conductive layer 391. In addition, an insulating layer 364 that functions as a protective film is formed so as to cover the second conductive layers 363a and 363b. In addition, the first conductive layer 356 in which the plurality of memory elements 365a and 365b are formed is connected to one source electrode layer or drain electrode layer of the transistor 360b. That is, the memory element is connected to the same single transistor. In addition, partition walls (insulating layers) 357a, 357b, and 357c for separating the organic compound layer 362a, the organic compound layer 362b, the second conductive layer 363a, and the second conductive layer 363b for each memory cell are provided. In the case where there is no concern about the influence of the electric field in the lateral direction in adjacent memory cells, it may be formed on the entire surface. Note that the memory elements 365a and 365b can be formed using the material or the manufacturing method described in the above embodiment modes.

Since the memory element 365a and the memory element 365b in FIG. 11 are also formed in a shape having a bent portion or an unevenness, the peripheral length of the memory element is increased. Therefore, in such a memory element, when a rectangle having the same area is considered, the ratio of the long side to the short side increases as the peripheral length increases. In the present invention, the ratio of the long side to the short side (the ratio of the long side to the short side) is preferably 3 or more, and more preferably 6 or more. Further, when a square is formed with the same peripheral length as the memory element of this embodiment, the area of the square is larger than the area of the memory element of this embodiment. In the present invention, the ratio of the area of the square to the area of the memory element is preferably 0.75 or less, and more preferably 0.5 or less.

In the present invention, the shape of the memory element is a rectangle having an uneven portion around it, a zigzag shape having one or more bent portions, a comb shape, or a ring shape (ring shape) having an opening (space) inside. Is used. In addition, a rectangle having a large ratio between the long side and the short side, and an ellipse having a large ratio between the long diameter and the short diameter can be used.

Such a memory element of this embodiment can perform normal writing and can reduce a writing failure rate. In addition, the writing characteristics of the plurality of memory elements are stabilized without variation. Therefore, by using such a memory element, a semiconductor device with high reliability in writing can be manufactured.

Also in this embodiment (the semiconductor device shown in FIGS. 10 and 11), as shown in FIG. 16 of Embodiment 1, the organic compound layer and the first conductive layer, or the organic compound layer and the second conductive layer. An insulating layer may be provided between each of the layers, or both the first conductive layer and the second conductive layer, and the organic compound layer. By providing the insulating layer, characteristics such as a write voltage of the memory element are stabilized without variation, and normal writing can be performed in each element. In addition, since the carrier injecting property is improved by providing the insulating layer, the organic compound layer can be thickened. Therefore, it is possible to prevent the memory element from being short-circuited in the initial state before energization.

A substrate including the element formation layer 385 and the memory element portion 375 and a substrate 396 provided with a conductive layer 393 functioning as an antenna are attached to each other with a resin 395 having adhesiveness. The conductive layer 392 and the conductive layer 393 on the element formation layer 385 are electrically connected through conductive fine particles 394 contained in the resin 395. In addition, a conductive layer such as a silver paste, a copper paste, or a carbon paste or a method of performing solder bonding is used to provide a substrate including the element formation layer 385 and the memory element portion 375, and a conductive layer 393 that functions as an antenna. The substrate 396 may be attached.

In this manner, a semiconductor device including a memory element and an antenna can be formed. In this embodiment mode, an element formation layer can be provided by forming a thin film transistor over a substrate, or by forming a field effect transistor over a substrate using a semiconductor substrate such as Si as the substrate. A layer may be provided. Alternatively, an SOI substrate may be used as a substrate, and an element formation layer may be provided thereover. In this case, the SOI substrate may be formed by using a method of bonding wafers or a method called SIMOX in which an insulating layer is formed inside by implanting oxygen ions into the Si substrate.

Further, the memory element portion may be provided on a substrate provided with a conductive layer functioning as an antenna. A sensor connected to the transistor may be provided.

Note that this embodiment can be freely combined with the above embodiment. In addition, the semiconductor device manufactured in this embodiment can be provided over a flexible substrate by being separated from the substrate by a separation process and bonded to a flexible substrate, so that the semiconductor device has flexibility. Can do. Flexible substrates include PET (polyethylene terephthalate), PEN (polyethylene naphthalate), PES (polyethersulfone), polypropylene, polypropylene sulfide, polycarbonate, polyetherimide, polyphenylene sulfide, polyphenylene oxide, polysulfone, polyphthalamide, etc. Substrates made of polypropylene, polyester, vinyl, polyvinyl fluoride, vinyl chloride, paper made of fibrous materials, base film (polyester, polyamide, inorganic vapor deposition film, paper, etc.) and adhesive synthetic resin film It corresponds to a laminated film with (acrylic synthetic resin, epoxy synthetic resin, etc.). The film is subjected to heat treatment and pressure treatment, and when the heat treatment and pressure treatment are performed, the film is provided on the adhesive layer provided on the outermost surface of the film or on the outermost layer. The layer (not the adhesive layer) is melted by heat treatment and bonded by pressure. Further, an adhesive layer may be provided on the substrate, or an adhesive layer may not be provided. The adhesive layer corresponds to a layer containing an adhesive such as a thermosetting resin, an ultraviolet curable resin, an epoxy resin adhesive, or a resin additive.

In the semiconductor device of the present invention, after a memory element is formed over a first substrate that can withstand process conditions (such as temperature), the semiconductor device may be transferred to the second substrate to have a memory element. In this specification, transposition means that a memory element formed over a first substrate is peeled off from the first substrate and transferred to the second substrate. That is, it can be said that the place where the memory element is provided is moved to another substrate.

Note that in the transfer step to another substrate, a peeling layer and an insulating layer are formed between the substrate and the element formation layer, a metal oxide film is provided between the peeling layer and the insulating layer, and the metal oxide film is crystallized. A method of peeling the element formation layer after weakening, an amorphous silicon film containing hydrogen is provided between the substrate and the element formation layer with high heat resistance, and the amorphous silicon film is formed by laser irradiation or etching. By removing the element formation layer, a separation layer and an insulating layer are formed between the substrate and the element formation layer, and a metal oxide film is provided between the separation layer and the insulation layer. A method for removing a part of a peeling layer by etching with a halogen fluoride gas such as a solution or NF ₃ , BrF ₃ , or ClF ₃ after being weakened by crystallization, and then peeling on the weakened metal oxide film, element type layer Mechanically delete the substrate on which the It can be used liquid or _{NF 3,} BrF _3, a method for removing by etching with halogen fluoride gas such as ClF ₃ as appropriate. In addition, a film containing nitrogen, oxygen, hydrogen, or the like (for example, an amorphous silicon film containing hydrogen, a hydrogen-containing alloy film, an oxygen-containing alloy film, or the like) is used as the separation layer, and the separation layer is irradiated with laser light for separation. A method of releasing nitrogen, oxygen, or hydrogen contained in the layer as a gas and promoting separation between the element formation layer and the substrate may be used.

A transposition step can be performed more easily by combining the above peeling methods. In other words, laser irradiation, etching of the release layer with gas or solution, mechanical deletion with a sharp knife or scalpel, etc. to make the release layer and the element formation layer easy to peel off, Separation can also be performed by force (by human hand or machine).

According to the present invention, the characteristics of the memory element are stabilized without variation and normal writing can be performed. Therefore, a highly reliable semiconductor device can be manufactured with high yield without complicating the device and the process.

(Embodiment 5)
In this embodiment, an example of a semiconductor device including the memory element described in the above embodiment will be described with reference to drawings. A top view of the semiconductor device of this embodiment is shown in FIG. 14A, and a cross-sectional view taken along line XY in FIG. 14A is shown in FIG.

As shown in FIG. 14A, a memory element portion 404 which is a semiconductor device having a memory element, a circuit portion 421, and an antenna 431 are formed over a substrate 400. 14A and 14B show a state in which a memory element portion, a circuit portion, and an antenna are formed over a substrate 400 that can withstand the manufacturing conditions in the middle of the manufacturing process. Materials and manufacturing steps may be selected and manufactured in the same manner as in Embodiment Mode 4.

A transistor 441 is provided in the memory element portion 404 and a transistor 442 is provided in the circuit portion 421 with a separation layer 452 and an insulating layer 453 provided over a substrate 400. An insulating layer 461, an insulating layer 454, and an insulating layer 455 are formed over the transistors 441 and 442. From the stack of the first conductive layer 457d, the organic compound layer 458, and the second conductive layer 459 over the insulating layer 455. A memory element 443 is formed. The organic compound layers 458 are individually separated by an insulating layer 460b functioning as a partition wall. The first conductive layer 457 d is connected to the wiring layer of the transistor 441, and the memory element 443 is electrically connected to the transistor 441.

In the semiconductor device in FIG. 14B, the second conductive layer 459 is stacked and electrically connected to the wiring layer 456a and the conductive layer 457c. Over the insulating layer 455, a conductive layer 457a and an antenna 431a, a conductive layer 457b and an antenna 431b, a conductive layer 457e and an antenna 431c, and a conductive layer 457f and an antenna 431d are stacked. The conductive layer 457e is formed in contact with the wiring layer 456b in an opening reaching the wiring layer 456b formed in the insulating layer 455, and electrically connects the antenna to the memory element portion 404 and the circuit portion 421. The conductive layer 457a, the conductive layer 457b, the conductive layer 457e, and the conductive layer 457f under the antenna 431a, the antenna 431b, and the antennas 431c and 431d provide adhesion between the insulating layer 455 and the antenna 431a, the antenna 431b, the antenna 431c, and 431d. There is also an effect to improve. In this embodiment, a polyimide film is used for the insulating layer 455, a titanium film is used for the conductive layer 457a, the conductive layer 457b, the conductive layer 457e, and the conductive layer 457f, and an aluminum film is used for the antenna 431a, the antenna 431b, the antenna 431c, and 431d. ing.

An opening (also referred to as a contact hole) is formed in the insulating layer 455 so that the first conductive layer 457d and the transistor 441, the conductive layer 457c and the wiring layer 456a, and the conductive layer 457e and the wiring layer 456b are connected to each other. When the opening is increased and the contact area between the conductive layers is increased, the resistance becomes lower. Therefore, in this embodiment, the opening where the first conductive layer 457d and the transistor 441 are connected is the smallest, and the next However, the openings are set in order so that the opening connecting the conductive layer 457c and the wiring layer 456a and the opening connecting the conductive layer 457e and the wiring layer 456b are the largest. In this embodiment, an opening connecting the first conductive layer 457d and the transistor 441 is 5 μm × 5 μm, an opening connecting the conductive layer 457c and the wiring layer 456a is 50 μm × 50 μm, and the conductive layer 457e and the wiring layer 456b are connected. The opening for connecting is set to 500 μm × 500 μm.

In this embodiment, the distance a from the insulating layer 460a to the antenna 431b is 500 μm or more, the distance b from the end of the second conductive layer 459 to the end of the insulating layer 460a is 250 μm or more, and the second conductive layer 459 is used. The distance c from the end of the insulating layer 460c to the end of the insulating layer 460c is 500 μm or more, and the distance d from the end of the insulating layer 460c to the antenna 431c is 250 μm or more. In the circuit portion 421, the insulating layer 460c is partially formed, and the transistor 442 includes a region not covered with the insulating layer 460c and a region covered with the insulating layer 460c.

By using such a semiconductor device, data (equivalent to information) is written to the memory element unit 404 by directly inputting a power supply voltage or a signal from the external input unit to the memory element unit 404, or the memory element unit 404 It becomes possible to read data from.

In addition, when a signal is not directly input to the external input unit, a radio wave received by the antenna unit is internally generated through the RF input unit, and data can be read from the storage element unit 404.

Further, the antenna may be provided so as to overlap with the memory element portion, or may be provided around the memory element portion without overlapping. When overlapping, the entire surface may overlap, or a structure where a part overlaps may be used. When the antenna unit and the memory element unit overlap each other, the malfunction of the semiconductor device due to the influence of noise, etc. on the signal when the antenna communicates or fluctuations in electromotive force generated by electromagnetic induction is reduced. Is possible, and reliability is improved. In addition, the semiconductor device can be reduced in size.

As a signal transmission method in the semiconductor device capable of inputting / outputting non-contact data described above, an electromagnetic coupling method, an electromagnetic induction method, a microwave method, or the like can be used. The transmission method may be appropriately selected by the practitioner in consideration of the intended use, and an optimal antenna may be provided according to the transmission method.

For example, when an electromagnetic coupling method or an electromagnetic induction method (for example, 13.56 MHz band) is applied as a signal transmission method in a semiconductor device, an electromagnetic induction due to a change in magnetic field density is used, and thus a conductive layer that functions as an antenna. Are formed in a ring shape (for example, a loop antenna) or a spiral shape (for example, a spiral antenna). FIGS. 17A to 17C illustrate an example of a chip-shaped semiconductor device 503 including a conductive layer 502 functioning as an antenna and an integrated circuit, which are formed over a substrate 501.

In addition, when a microwave method (for example, UHF band (860 to 960 MHz band), 2.45 GHz band, or the like) is applied as a signal transmission method in a semiconductor device, the wavelength of an electromagnetic wave used for signal transmission is considered. The length of the conductive layer functioning as an antenna may be set as appropriate. For example, the conductive layer functioning as an antenna may be linear (for example, a dipole antenna (see FIG. 17A)) or flat ( For example, it can be formed in a patch antenna (see FIG. 17B)) or a ribbon shape (see FIGS. 17C and 17D). Further, the shape of the conductive layer functioning as an antenna is not limited to a linear shape, and may be provided in a curved shape, a meandering shape, or a combination thereof in consideration of the wavelength of electromagnetic waves.

The conductive layer functioning as an antenna is formed using a conductive material by a CVD method, a sputtering method, a printing method such as screen printing or gravure printing, a droplet discharge method, a dispenser method, a plating method, or the like. Conductive materials are aluminum (Al), titanium (Ti), silver (Ag), copper (Cu), gold (Au), platinum (Pt) nickel (Ni), palladium (Pd), tantalum (Ta), molybdenum An element selected from (Mo) or an alloy material or a compound material containing these elements as a main component is formed in a single layer structure or a laminated structure.

For example, when a conductive layer that functions as an antenna is formed using a screen printing method, a conductive paste in which conductive particles having a particle size of several nanometers to several tens of micrometers are dissolved or dispersed in an organic resin is selectively used. Can be provided by printing. Conductor particles include silver (Ag), gold (Au), copper (Cu), nickel (Ni), platinum (Pt), palladium (Pd), tantalum (Ta), molybdenum (Mo) and titanium (Ti). Any one or more metal particles, silver halide fine particles, or dispersible nanoparticles can be used. In addition, as the organic resin contained in the conductive paste, one or more selected from organic resins functioning as a binder of metal particles, a solvent, a dispersant, and a coating material can be used. Typically, an organic resin such as an epoxy resin or a silicon resin can be given. In forming the conductive layer, it is preferable to fire after extruding the conductive paste. For example, in the case where fine particles containing silver as a main component (for example, a particle size of 1 nm or more and 100 nm or less) is used as the material of the conductive paste, the conductive layer is obtained by being cured by baking in a temperature range of 150 to 300 ° C. Can do. Further, fine particles mainly composed of solder or lead-free solder may be used. In this case, it is preferable to use fine particles having a particle diameter of 20 μm or less. Solder and lead-free solder have the advantage of low cost. In addition to the materials described above, ceramic, ferrite, or the like may be applied to the antenna.

Further, in the case where an electromagnetic coupling method or an electromagnetic induction method is applied and a semiconductor device provided with an antenna is provided in contact with a metal, a magnetic material having a permeability between the semiconductor device and the metal is used. It is preferable to provide it. When a semiconductor device provided with an antenna is provided in contact with a metal, an eddy current flows in the metal as the magnetic field changes, and the change in the magnetic field is weakened by the demagnetizing field generated by the eddy current, thereby reducing the communication distance. . Therefore, by providing a material having magnetic permeability between the semiconductor device and the metal, it is possible to suppress the eddy current of the metal and suppress the decrease in the communication distance. As the magnetic material, ferrite or metal thin film having high magnetic permeability and low high-frequency loss can be used.

In the case of providing an antenna, a semiconductor element such as a transistor and a conductive layer functioning as an antenna may be directly formed over one substrate, or the semiconductor element and the conductive layer functioning as an antenna may be provided separately. After being provided on the substrate, it may be provided by bonding so as to be electrically connected.

In addition, a method for inspecting the semiconductor device manufactured as described above in order to evaluate the characteristics will be described with reference to FIGS. FIG. 20A illustrates a system for automatically inspecting an antenna-mounted integrated circuit chip (also referred to as RFID (Radio Frequency Identification)) formed on a flexible substrate such as a film using a roll-to-roll method. Show. As shown in the above embodiment mode, a memory element having unevenness and a bent portion in the periphery of the memory element is used in the integrated circuit chip of the antenna-mounted integrated circuit chip.

In the inspection system shown in FIG. 20, a feed roll 601, a signal measurement circuit 603, a signal measurement antenna 604, a movable shield 609, a rotary chamber mechanism drum 620 having a plurality of slots 608, a rotary probe mechanism drum 630, a movable probe. Reference numeral 605 denotes a receiving roll 606, and the antenna-mounted integrated circuit chip 602 to be inspected is carried by the roll. The rotating chamber mechanism drum 620 is used for measurement and inspection of the antenna-mounted integrated circuit chip, and performs measurement and inspection without contact with the antenna-mounted integrated circuit chip. FIG. 20B is a top view of the antenna-mounted integrated circuit chip carried on the roll. The TEG chip 611, the inspection pad 610, the antenna 612, and the integrated circuit chip 613 are carried. The rotating probe mechanism drum 630 is configured such that the electric characteristics and LCR (coil, capacitor, resistance) characteristics of the transistors included in the integrated circuit chip are brought into contact with the TEG chip manufactured in the same process and on the same substrate as the integrated circuit chip. Is measured and evaluated. As described above, a semiconductor device using the present invention can be automatically inspected at high speed.

The memory element 443 in FIG. 14 is also formed in a shape having a bent portion or unevenness, so that the length of the periphery of the memory element is increased. Therefore, in such a memory element, when a rectangle having the same area is considered, the ratio of the long side to the short side increases as the peripheral length increases. In the present invention, the ratio of the long side to the short side (the ratio of the long side to the short side) is preferably 3 or more, and more preferably 6 or more. Further, when a square is formed with the same peripheral length as the memory element of this embodiment, the area of the square is larger than the area of the memory element of this embodiment. In the present invention, the ratio of the square area to the area of the memory element relative to the square area is preferably 0.75 or less, and more preferably 0.5 or less.

In the present invention, the shape of the memory element is a rectangle having an uneven portion around it, a zigzag shape having one or more bent portions, a comb shape, or a ring shape (ring shape) having an opening (space) inside. Is used. In addition, a rectangle having a large ratio between the long side and the short side, and an ellipse having a large ratio between the long diameter and the short diameter can be used.

Such a memory element of this embodiment can perform normal writing and can reduce a writing failure rate. In addition, the writing characteristics of the plurality of memory elements are stabilized without variation. Therefore, by using such a memory element, a semiconductor device with high reliability in writing can be manufactured.

According to the present invention, the characteristics of the memory element are stabilized without variation and normal writing can be performed. Therefore, a highly reliable semiconductor device can be manufactured with high yield without complicating the device and the process.

(Embodiment 6)
In this embodiment mode, reading or writing of data in the semiconductor device having the above structure is described.

  First, operation when data is written to a memory element in a passive matrix semiconductor device will be described with reference to FIGS. Data writing is performed by an electric action, or an electric action and an optical action. First, a case of writing data by an electric action will be described (see FIG. 3). Note that writing is performed by changing the electrical characteristics of the memory cell, but the initial state (state where no electrical action is applied) of the memory cell is data “0”, and the state where the electrical characteristic is changed is data “1”. And

  When data “1” is written in the memory cell 721, first, the memory cell 721 is selected by the decoders 723 and 724 and the selector 725. Specifically, the decoder 724 applies a predetermined voltage V2 to the word line W3 connected to the memory cell 721. In addition, the bit line B 3 connected to the memory cell 721 is connected to the circuit 726 by the decoder 723 and the selector 725. Then, the write voltage V1 is output from the circuit 726 to the bit line B3. In this way, the voltage Vw = V1−V2 is applied between the first conductive layer and the second conductive layer constituting the memory cell 721. By appropriately selecting the potential Vw, the organic compound layer provided between the conductive layers is changed physically or electrically, and data “1” is written. Specifically, at the read operation voltage, the electrical resistance between the first conductive layer and the second conductive layer in the data “1” state is significantly smaller than that in the data “0” state. It is good to change as follows. For example, it may be appropriately selected from the range of (V1, V2) = (0V, 5-15V), or (3-5V, -12--2V). The voltage Vw may be 5 to 15V, or -5 to -15V.

  Note that data “1” is controlled not to be written in the memory cell connected to the non-selected word line and the non-selected bit line. For example, unselected word lines and unselected bit lines may be set in a floating state. The first conductive layer and the second conductive layer constituting the memory cell must have characteristics such as diode characteristics that can ensure selectivity.

  On the other hand, when data “0” is written in the memory cell 721, it is not necessary to apply an electrical action to the memory cell 721. In the circuit operation, for example, as in the case of writing “1”, the memory cell 721 is selected by the decoders 723 and 724 and the selector 725, but the output potential from the circuit 726 to the bit line B3 is set to the selected word line. A voltage (for example, a voltage that does not change the electrical characteristics of the memory cell 721 between the first conductive layer and the second conductive layer constituting the memory cell 721) is set to the same level as the potential of W3 or the potential of the unselected word line. −5 to 5 V) may be applied.

  In addition to writing by an electric action, data may be written to the memory element by an optical action. A case where data is written by an optical action will be described (see FIG. 19). In this case, the second conductive layer 753a needs to transmit laser light. This is performed by irradiating the organic compound layer 752 with laser light from the side of the light-transmitting conductive layer (herein, the second conductive layer 753a). Here, a desired portion of the organic compound layer 752 is selectively irradiated with laser light to cause damage (damage) to the organic compound layer 752 (may be destroyed). Since the damaged organic compound layer is further insulated, the electric resistance is significantly increased as compared with other portions. In this manner, data is written by utilizing the change in electrical resistance between two conductive films provided with the organic compound layer 752 interposed therebetween by laser light irradiation. For example, when an organic compound layer not irradiated with laser light is set to “0” data, when writing “1” data, a desired portion of the organic compound layer is selectively irradiated with laser light and damaged. To increase the electrical resistance.

When a conjugated polymer doped with a compound that generates acid by absorbing light (a photoacid generator) is used as the organic compound layer 752, when irradiated with laser light, only the irradiated portion is conductive. Increases, and the unirradiated portion has no conductivity. Therefore, data is written by utilizing the change in the electrical resistance of the organic compound layer by selectively irradiating the organic compound layer in a desired portion with laser light. For example, in a case where an organic compound layer not irradiated with laser light is set to “0” data, when writing “1” data, a desired portion of the organic compound layer is selectively irradiated with laser light to be conductive. Increase sex.

In the case of irradiation with laser light, the change in the electrical resistance of the organic compound layer 752 depends on the size of the memory cell 721, but is realized by laser light irradiation with a diameter on the order of μm. For example, when a laser beam having a diameter of 1 μm passes at a linear velocity of 10 m / sec, the time during which the layer containing an organic compound included in one memory cell is irradiated with laser light is 100 nsec. In order to change the phase within a short time of 100 nsec, the laser power is preferably 10 mW and the power density is 10 kW / mm ² . In the case of selectively irradiating laser light, it is preferable to use a pulsed laser irradiation apparatus.

Here, an example of a laser irradiation apparatus will be briefly described with reference to FIG. A laser irradiation apparatus 1001 includes a computer (hereinafter, referred to as a PC) 1002 that executes various controls when irradiating laser light, a laser oscillator 1003 that outputs laser light, a power source 1004 of the laser oscillator 1003, and laser light. An optical system (ND filter) 1005 for attenuating light, an acousto-optic modulator (AOM) 1006 for modulating the intensity of the laser light, and a lens and an optical path for reducing the cross section of the laser light An optical system 1007 composed of a mirror for changing the angle, a moving mechanism 1009 having an X-axis stage and a Y-axis stage, a D / A conversion unit 1010 for digital-analog conversion of control data output from the PC, Acousto-optic modulator 10 according to the analog voltage output from the D / A converter 6, a driver 1012 that outputs a driving signal for driving the moving mechanism 1009, and an autofocus mechanism 1013 for focusing the laser beam on the irradiated object (FIG. 19 ( See C).

As the laser oscillator 1003, a laser oscillator that can oscillate ultraviolet light, visible light, or infrared light can be used. Examples of laser oscillators include excimer laser oscillators such as KrF, ArF, XeCl, and Xe, gas laser oscillators such as He, He—Cd, Ar, He—Ne, and HF, YAG, GdVO ₄ , YVO ₄ , YLF, and YAlO _3. A solid-state laser oscillator using a crystal doped with Cr, Nd, Er, Ho, Ce, Co, Ti, or Tm, and a semiconductor laser oscillator such as GaN, GaAs, GaAlAs, or InGaAsP can be used. In the solid-state laser oscillator, it is preferable to apply the fundamental wave or the second to fifth harmonics.

Next, an irradiation method using a laser irradiation apparatus will be described. When the substrate provided with the organic compound layer is mounted on the moving mechanism 1009, the PC 1002 detects the position of the organic compound layer to be irradiated with the laser light by a camera (not shown). Next, the PC 1002 generates movement data for moving the movement mechanism 1009 based on the detected position data.

Thereafter, the PC 1002 controls the output light amount of the acousto-optic modulator 1006 via the driver 1011, so that the laser light output from the laser oscillator 1003 is attenuated by the optical system 1005 and then the acousto-optic modulator 1006. The light amount is controlled so as to be a predetermined light amount. On the other hand, the laser light output from the acousto-optic modulator 1006 is changed in optical path and beam spot shape by the optical system 1007, condensed by a lens, and then irradiated onto the substrate 750.

At this time, according to the movement data generated by the PC 1002, the movement mechanism 1009 is controlled to move in the X direction and the Y direction. As a result, laser light is irradiated to a predetermined place, the light energy density of the laser light is converted into thermal energy, and the organic compound layer provided over the substrate 750 can be selectively irradiated with the laser light. Note that, here, an example in which the moving mechanism 1009 is moved and laser light irradiation is performed is shown; however, the laser light may be moved in the X direction and the Y direction by adjusting the optical system 1007.

As described above, the structure of the present invention in which data is written by laser light irradiation can easily manufacture a large number of semiconductor devices. Therefore, an inexpensive semiconductor device can be provided.

Next, an operation of reading data from a memory element in a passive matrix semiconductor device will be described (see FIG. 3). In reading data, the electrical characteristics between the first conductive layer and the second conductive layer constituting the memory cell are different between the memory cell having data “0” and the memory cell having data “1”. Use it. For example, the effective electrical resistance between the first conductive layer and the second conductive layer constituting the memory cell having data “0” (hereinafter simply referred to as the electrical resistance of the memory cell) is R0 at the read voltage. A method of reading data by using the difference in electric resistance when the electric resistance of the memory cell having data “1” is R1 in the read voltage will be described. Note that R1 << R0. As the reading circuit, for example, a circuit 726 using a resistance element 746 and a differential amplifier 747 shown in FIG. The resistance element 746 has a resistance value Rr, and R1 <Rr <R0. A transistor 748 may be used instead of the resistance element 746, and a clocked inverter 749 may be used instead of the differential amplifier (FIG. 3C). The clocked inverter 749 receives a signal φ or an inverted signal φ that becomes Hi when reading is performed and becomes Lo when not performing reading. Of course, the circuit configuration is not limited to FIG.

When reading data from the memory cell 721, first, the memory cell 721 is selected by the decoders 723 and 724 and the selector 725. Specifically, the decoder 724 applies a predetermined voltage Vy to the word line Wy connected to the memory cell 721. In addition, the bit line Bx connected to the memory cell 721 is connected to the terminal P of the circuit 726 by the decoder 723 and the selector 725. As a result, the potential Vp of the terminal P becomes a value determined by resistance division by the resistance element 746 (resistance value Rr) and the memory cell 721 (resistance value R0 or R1). Therefore, when the memory cell 721 has data “0”, Vp0 = Vy + (V0−Vy) × R0 / (R0 + Rr). When the memory cell 721 has data “1”, Vp1 = Vy + (V0−Vy) × R1 / (R1 + Rr). As a result, in FIG. 3B, Vref is selected to be between Vp0 and Vp1, and in FIG. 3C, the change point of the clocked inverter is selected to be between Vp0 and Vp1. Thus, Lo or Hi (or Hi or Lo) is output as the output potential Vout according to the data “0” or “1”, and reading can be performed.

  For example, the differential amplifier is operated at Vdd = 3V, and Vy = 0V, V0 = 3V, and Vref = 1.5V. Assuming that R0 / Rr = Rr / R1 = 9, if the memory cell data is “0”, Vp0 = 2.7 V and Vout is High, and if the memory cell data is “1”, Vp1 = 0.3V and Low is output as Vout. Thus, the memory cell can be read.

  According to the above method, the state of the electric resistance of the organic compound layer 752 is read as a voltage value by utilizing the difference in resistance value and resistance division. Of course, the reading method is not limited to this method. For example, in addition to using the difference in electrical resistance, reading may be performed using the difference in current value. In addition, when the electrical characteristics of the memory cell have data “0” and “1” and diode characteristics with different threshold voltages, reading may be performed using the threshold voltage difference.

  Next, operation when data is written to the memory element in the active matrix semiconductor device is described (see FIGS. 4 and 5).

  First, an operation when data is written by electrical action will be described. Note that writing is performed by changing the electrical characteristics of the memory cell, but the initial state (state where no electrical action is applied) of the memory cell is data “0”, and the state where the electrical characteristic is changed is data “1”. And

  Here, a case where data is written to the memory cell 231 in the nth row and the mth column will be described. When data “1” is written to the memory cell 231, first, the memory cell 231 is selected by the decoders 223 and 224 and the selector 225. Specifically, the decoder 224 applies a predetermined voltage V22 to the word line Wn connected to the memory cell 231. The decoder 223 and the selector 225 connect the bit line Bm connected to the memory cell 231 to a circuit 226 having a reading circuit and a writing circuit. Here, an example in which m is 3 is shown. Then, the write voltage V21 is output from the circuit 226 to the bit line B3.

  Thus, the transistor 210a included in the memory cell is turned on, the bit line is electrically connected to the memory element 215b, and a voltage of approximately Vw = Vcom−V21 is applied. Note that one electrode of the memory element is connected to the common electrode having the potential Vcom. By appropriately selecting the potential Vw, the organic compound layer provided between the conductive layers is changed physically or electrically, and data “1” is written. Specifically, at the read operation voltage, the electrical resistance between the first conductive layer and the second conductive layer in the data “1” state is significantly smaller than that in the data “0” state. It may be changed as described above, or it may be simply short-circuited. The potential may be appropriately selected from the range of (V21, V22, Vcom) = (5-15V, 5-15V, 0V), or (-12 to 0V, -12 to 0V, 3 to 5V). The voltage Vw may be 5 to 15V, or -5 to -15V.

  Note that data “1” is controlled not to be written in the memory cell connected to the non-selected word line and the non-selected bit line. Specifically, a potential (for example, 0 V) for turning off the transistor of the memory cell to be connected is applied to the non-selected word line, and the non-selected bit line is in a floating state or approximately equal to Vcom. A potential may be applied.

  On the other hand, when data “0” is written in the memory cell 231, it is not necessary to apply an electrical action to the memory cell 231. In the circuit operation, for example, as in the case of writing “1”, the memory cell 231 is selected by the decoders 223 and 224 and the selector 225, but the output potential from the circuit 226 to the bit line B3 is set to the same level as Vcom. Alternatively, the bit line B3 is brought into a floating state. As a result, a small voltage (for example, −5 to 5 V) is applied to the memory element 215b or no voltage is applied, so that the electrical characteristics do not change and data “0” writing is realized.

Next, a case where data is written by an optical action will be described. In this case, the laser irradiation is performed by irradiating the organic compound layer with laser light from the light-transmitting conductive layer side. As the laser irradiation apparatus, a passive matrix semiconductor device similar to that described with reference to FIG. 19 may be used.

When an organic compound material is used as the organic compound layer, the organic compound layer is damaged by irradiation with laser light, and the organic compound layer is oxidized or carbonized to be further insulated. Then, the resistance value of the memory element irradiated with the laser light increases, and the resistance value of the memory element not irradiated with the laser light does not change. When a conjugated polymer material doped with a photoacid generator is used, conductivity is imparted to the organic compound layer by irradiation with laser light. That is, conductivity is given to the memory element irradiated with the laser beam, and conductivity is not given to the memory element not irradiated with the laser beam.

Next, an operation when data is read by electrical action will be described. Here, the circuit 226 includes a resistance element 246 and a differential amplifier 247. However, the configuration of the circuit 226 is not limited to the above configuration, and may have any configuration.

Next, an operation in reading data by an electrical action in an active matrix semiconductor device will be described. Data is read by utilizing the fact that the electrical characteristics of the memory element 215b are different between the memory cell having data “0” and the memory cell having data “1”. For example, the electrical resistance of the memory element constituting the memory cell having data “0” is R0 at the read voltage, and the electrical resistance of the memory element constituting the memory cell having data “1” is R1 at the read voltage. A method of reading using the difference will be described. Note that R1 << R0. As the structure of the reading circuit, for example, a circuit 226 using the resistance element 246 and the differential amplifier 247 illustrated in FIG. The resistance element has a resistance value Rr, and R1 <Rr <R0. A transistor 249 may be used instead of the resistance element 246, and a clocked inverter 248 may be used instead of the differential amplifier (FIG. 5C). Of course, the circuit configuration is not limited to FIG.

  When data is read from the memory cell 231 in the xth row and the yth column, first, the memory cell 231 is selected by the decoders 223 and 224 and the selector 225. Specifically, the decoder 224 applies a predetermined voltage V24 to the word line Wy connected to the memory cell 231 to turn on the transistor 210a. In addition, the bit line Bx connected to the memory cell 231 is connected to the terminal P of the circuit 226 by the decoder 223 and the selector 225. As a result, the potential Vp of the terminal P becomes a value determined by resistance division of Vcom and V0 by the resistance element 246 (resistance value Rr) and the memory element 215b (resistance value R0 or R1). Therefore, when the memory cell 231 has data “0”, Vp0 = Vcom + (V0−Vcom) × R0 / (R0 + Rr). When the memory cell 231 has data “1”, Vp1 = Vcom + (V0−Vcom) × R1 / (R1 + Rr). As a result, in FIG. 5B, Vref is selected to be between Vp0 and Vp1, and in FIG. 5C, the change point of the clocked inverter is selected to be between Vp0 and Vp1. Thus, Lo or Hi (or Hi or Lo) is output from the output potential Vout according to the data “0” or “1”, and reading can be performed.

  For example, the differential amplifier is operated at Vdd = 3V, and Vcom = 0V, V0 = 3V, and Vref = 1.5V. Assuming that R0 / Rr = Rr / R1 = 9 and the on-resistance of the transistor 210a is negligible, when the data of the memory cell is “0”, Vp0 = 2.7V and Vout is output as High, When the data of “1” is “1”, Vp1 = 0.3V and Vout is output as Low. Thus, the memory cell can be read.

  According to the above method, the voltage value is read by utilizing the difference in resistance value of the memory element 215b and the resistance division. Of course, the reading method is not limited to this method. For example, in addition to using the difference in electrical resistance, reading may be performed using the difference in current value. In addition, when the electrical characteristics of the memory cell have data “0” and “1” and diode characteristics with different threshold voltages, reading may be performed using the threshold voltage difference.

  Since a memory element having the above structure and a semiconductor device including the memory element are nonvolatile memories, a small, thin, and lightweight semiconductor device is provided without the need to incorporate a battery for retaining data. Can do. In addition, data can be written (added) by using the insulating material used in the above embodiment as an organic compound layer, but data cannot be rewritten. Therefore, it is possible to provide a semiconductor device that prevents forgery and ensures security.

  Note that this embodiment can be freely combined with the structures of the memory element and the semiconductor device including the memory element described in the above embodiment.

(Embodiment 7)
The configuration of the semiconductor device of this embodiment will be described with reference to FIG. As shown in FIG. 12, the semiconductor device 20 of the present invention has a function of communicating data without contact, and controls the power supply circuit 11, the clock generation circuit 12, the data demodulation or modulation circuit 13, and other circuits. A circuit 14, an interface circuit 15, a memory circuit 16, a data bus 17, an antenna (antenna coil) 18, a sensor 21, and a sensor circuit 22 are included.

The power supply circuit 11 is a circuit that generates various power supplies to be supplied to each circuit inside the semiconductor device 20 based on the AC signal input from the antenna 18. The clock generation circuit 12 is a circuit that generates various clock signals to be supplied to each circuit inside the semiconductor device 20 based on the AC signal input from the antenna 18. The data demodulation or modulation circuit 13 has a function of demodulating or modulating data communicated with the reader / writer 19. The control circuit 14 has a function of controlling the memory circuit 16. The antenna 18 has a function of transmitting / receiving electromagnetic waves or radio waves. The reader / writer 19 controls communication and control with the semiconductor device and processing related to the data. The semiconductor device is not limited to the above-described configuration, and may be a configuration in which other elements such as a power supply voltage limiter circuit and hardware dedicated to cryptographic processing are added.

The memory circuit 16 includes a memory element in which an organic compound layer or a phase change layer is sandwiched between a pair of conductive layers. Note that the memory circuit 16 may include only a memory element in which an organic compound layer or a phase change layer is sandwiched between a pair of conductive layers, or may include a memory circuit having another structure. The memory circuit having another configuration corresponds to, for example, one or more selected from DRAM, SRAM, FeRAM, mask ROM, PROM, EPROM, EEPROM, and flash memory.

The sensor 21 is formed of a semiconductor element such as a resistance element, a capacitive coupling element, an inductive coupling element, a photovoltaic element, a photoelectric conversion element, a thermoelectric element, a transistor, a thermistor, or a diode. The sensor circuit 22 detects a change in impedance, reactance, inductance, voltage or current, performs analog / digital conversion (A / D conversion), and outputs a signal to the control circuit 14.

(Embodiment 8)
According to the present invention, a semiconductor device that functions as a chip having a processor circuit (hereinafter also referred to as a processor chip, a wireless chip, a wireless processor, a wireless memory, or a wireless tag) can be formed. The semiconductor device of the present invention has a wide range of uses, such as banknotes, coins, securities, certificates, bearer bonds, packaging containers, books, recording media, personal items, vehicles, foods, clothing It can be used in health supplies, daily necessities, medicines and electronic devices.

  Banknotes and coins are money that circulates in the market, and include those that are used in the same way as money in a specific area (cash vouchers), commemorative coins, and the like. Securities refer to checks, securities, promissory notes, and the like, and can be provided with a chip 90 having a processor circuit (see FIG. 13A). The certificate refers to a driver's license, a resident's card, and the like, and can be provided with a chip 91 having a processor circuit (see FIG. 13B). Personal belongings refer to bags, glasses, and the like, and can be provided with a chip 97 including a processor circuit (see FIG. 13C). Bearer bonds refer to stamps, gift cards, and various gift certificates. Packaging containers refer to wrapping paper for lunch boxes, plastic bottles, and the like, and can be provided with a chip 93 having a processor circuit (see FIG. 13D). Books refer to books, books, and the like, and can be provided with a chip 94 including a processor circuit (see FIG. 13E). The recording media refer to DVD software, video tapes, and the like, and can be provided with a chip 95 including a processor circuit (see FIG. 13F). The vehicles refer to vehicles such as bicycles, ships, and the like, and can be provided with a chip 96 including a processor circuit (see FIG. 13G). Foods refer to food products, beverages, and the like. Clothing refers to clothing, footwear, and the like. Health supplies refer to medical equipment, health equipment, and the like. Livingware refers to furniture, lighting equipment, and the like. Chemicals refer to pharmaceuticals, agricultural chemicals, and the like. Electronic devices refer to liquid crystal display devices, EL display devices, television devices (TV receivers, flat-screen TV receivers), mobile phones, and the like.

The semiconductor device of the present invention is fixed to an article by a method such as mounting on a printed board, pasting on a surface, or embedding. For example, a book is embedded in paper, and a package made of an organic resin is embedded in the organic resin, and is fixed to each article. Since the semiconductor device of the present invention realizes a small size, a thin shape, and a light weight, the design of the article itself is not impaired even after being fixed to the article. In addition, by providing the semiconductor device of the present invention in bills, coins, securities, bearer bonds, certificates, etc., an authentication function can be provided, and if this authentication function is utilized, counterfeiting can be prevented. it can. In addition, by providing the semiconductor device of the present invention in packaging containers, recording media, personal items, foods, clothing, daily necessities, electronic devices, etc., the efficiency of a system such as an inspection system can be improved.

Next, one mode of an electronic device in which the semiconductor device of the present invention is mounted will be described with reference to the drawings. An electronic device illustrated here is a mobile phone, which includes housings 2700 and 2706, a panel 2701, a housing 2702, a printed wiring board 2703, operation buttons 2704, and a battery 2705 (see FIG. 12B). The panel 2701 is detachably incorporated in the housing 2702, and the housing 2702 is fitted on the printed wiring board 2703. The shape and dimensions of the housing 2702 are changed as appropriate in accordance with the electronic device in which the panel 2701 is incorporated. A plurality of packaged semiconductor devices are mounted on the printed wiring board 2703, and the semiconductor device of the present invention can be used as one of them. The plurality of semiconductor devices mounted on the printed wiring board 2703 have any one function of a controller, a central processing unit (CPU), a memory, a power supply circuit, a sound processing circuit, a transmission / reception circuit, and the like.

The panel 2701 is connected to the printed wiring board 2703 through the connection film 2708. The panel 2701, the housing 2702, and the printed wiring board 2703 are housed in the housings 2700 and 2706 together with the operation buttons 2704 and the battery 2705. A pixel region 2709 included in the panel 2701 is arranged so as to be visible from an opening window provided in the housing 2700.

As described above, the semiconductor device of the present invention is characterized in that it is small, thin, and lightweight, and the limited space inside the housings 2700 and 2706 of the electronic device can be effectively used due to the above characteristics. .

In addition, since the semiconductor device of the present invention includes a memory element having a simple structure in which an organic compound layer is sandwiched between a pair of conductive layers, an electronic device using an inexpensive semiconductor device can be provided. In addition, since the semiconductor device of the present invention can be easily integrated, an electronic device using the semiconductor device including a large-capacity memory circuit can be provided.

In addition, a memory element included in the semiconductor device of the present invention writes data by an electric action (or an electric action and an optical action), is nonvolatile, and can additionally write data. It is characterized by. With the above feature, forgery due to rewriting can be prevented, and new data can be added and written. Therefore, an electronic device using a semiconductor device that achieves high functionality and high added value can be provided.

Note that the housings 2700 and 2706 are examples of the appearance of a mobile phone, and the electronic device according to this embodiment can be modified into various modes depending on functions and uses.

The figure explaining this invention. 6A and 6B illustrate a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. The graph which shows the relationship between ratio and area of the long side of a memory element, and a short side. 6A and 6B illustrate a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 3 is a graph showing a relationship between a write voltage of a memory element and a write failure rate. 3A and 3B each illustrate a memory element of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. The figure explaining this invention. 6A and 6B illustrate a semiconductor device of the present invention. 8A and 8B illustrate a method for inspecting a semiconductor device of the present invention.

Claims (10)

A first conductive layer;
A layer containing an organic compound on the first conductive layer;
A second conductive layer on the layer containing the organic compound,
The top surface shape of at least one of the first conductive layer and the second conductive layer is a shape having a circular space . A first conductive layer;
A layer containing an organic compound on the first conductive layer;
A second conductive layer on the layer containing the organic compound,
The semiconductor device according to claim 1, wherein an upper surface shape of at least one of the first conductive layer and the second conductive layer is a circular shape having a circular space . A first conductive layer;
A layer containing an organic compound on the first conductive layer;
A second conductive layer on the layer containing the organic compound,
Wherein at least one of the upper surface shape of the first conductive layer and the second conductive layer, wherein a an elliptical shape with a circular space. A first conductive layer;
A partition wall having an opening on the first conductive layer;
A layer containing the first on the conductive layer, an organic compound provided on the opening,
It has on the layer containing an organic compound, and a second conductive layer, and
Definitive in the opening, wherein at least one of the upper surface shape of the first conductive layer and the second conductive layer, and wherein a is a shape having a circular space. A first conductive layer;
A partition wall having an opening on the first conductive layer;
A layer containing the first on the conductive layer, an organic compound provided on the opening,
It has on the layer containing an organic compound, and a second conductive layer, and
The semiconductor device according to claim 1, wherein an upper surface shape of at least one of the first conductive layer and the second conductive layer in the opening is a circular shape having a circular space . A first conductive layer;
A partition wall having an opening on the first conductive layer;
A layer containing the first on the conductive layer, an organic compound provided on the opening,
It has on the layer containing an organic compound, and a second conductive layer, and
In the opening, wherein at least one of the upper surface shape of the first conductive layer and the second conductive layer, wherein a an elliptical shape with a circular space. In any one of Claims 1 thru | or 6,
A semiconductor device, wherein a ratio of a length in a major axis direction to a length in a minor axis direction of at least one of the first conductive layer and the second conductive layer is 3 or more. In any one of Claims 1 thru | or 7,
An area of at least one of the first conductive layer and the second conductive layer, and a square area having the same peripheral length as at least one of the first conductive layer and the second conductive layer . A semiconductor device having a ratio of 0.75 or less. In any one of Claims 1 thru | or 8,
A semiconductor device comprising an insulating layer between the first conductive layer and the layer containing an organic compound, or between the second conductive layer and the layer containing the organic compound. In any one of Claims 1 thru | or 9,
A transistor electrically connected to the first conductive layer or the second conductive layer;
The transistor includes an oxide semiconductor.

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