JP5063084B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

2. Description of the Related Art In recent years, attention has been focused on an individual recognition technique in which an ID (individual identification number) is given to an individual object to clarify information such as a history of the object and to be useful for production and management. Among them, development of semiconductor devices capable of transmitting and receiving data without contact is underway. As such a semiconductor device, RFID (Radio Frequency Identification) (ID tag, IC tag, IC chip, RF (Radio Frequency) tag, wireless tag, electronic tag, also called wireless chip), etc. are particularly used in companies, markets, etc. Has begun to be introduced.

Many of these semiconductor devices have a circuit using a semiconductor substrate such as silicon (Si) (hereinafter also referred to as an IC (Integrated Circuit) chip) and an antenna, and the IC chip is a memory circuit (hereinafter also referred to as a memory). And a control circuit.

In addition, development of semiconductor devices such as a liquid crystal display device in which thin film transistors (hereinafter also referred to as “TFTs”) are integrated on a glass substrate and an electroluminescence display device is progressing. Each of these semiconductor devices has a thin film transistor formed on a glass substrate by using a thin film formation technique, and a liquid crystal element or a light emitting element (electroluminescence (hereinafter referred to as “hereinafter referred to as“ electroluminescence ”) as a display element on various circuits constituted by the thin film transistor. Also referred to as “EL”.) An element) is formed to function as a display device.

In the manufacturing process of such a semiconductor device, in order to reduce the manufacturing cost, a process of transferring an element manufactured on a glass substrate, a peripheral circuit, or the like to an inexpensive substrate such as a plastic substrate is performed (for example, Patent Documents). 1).
JP 2002-26282 A

However, if the adhesion between the thin films constituting the element to be transferred is low, there is a problem that the element is not properly peeled off from the glass substrate and destroyed. In particular, when a memory element is formed by providing an organic compound between a pair of electrodes, film peeling tends to occur at the interface between the electrode and the organic compound layer. FIG. 15 shows a process of transposing a memory element using an organic compound layer.

FIG. 15A illustrates a memory element including a first conductive layer 80a, an organic compound layer 81a, and a second conductive layer 82a, and FIG. 15B illustrates a first conductive layer 80b and an organic compound. FIG. 15C illustrates a memory element including the first conductive layer 80c, the organic compound layer 81c, and the second conductive layer 82c. is there. Although not shown, the first substrate is provided on the first conductive layers 80a to 80c side, and the second substrate is provided on the second conductive layers 82a to 82c side. The first substrate is a substrate from which the formed memory element is peeled off, and the second substrate is a substrate from which the memory element is peeled off from the first substrate. The memory elements in FIGS. 15A to 15C receive force in the direction of the arrow in FIG. 15 from the first substrate to be peeled off and the second substrate to be peeled off.

FIG. 15A illustrates an example in which the organic compound layer 81a and the second conductive layer 82a are peeled off at the interface because the adhesion between the organic compound layer 81a and the second conductive layer 82a is poor. FIG. 15B illustrates an example in which the organic compound layer 81b and the first conductive layer 80b are peeled off at the interface because the adhesion between the organic compound layer 81b and the second conductive layer 82b is poor. Further, in FIG. 15C, since the adhesion between the organic compound layer 81c and the first conductive layer 80c and the second conductive layer 82c is poor, the organic compound layer 81c and the first conductive layer 80c are peeled off at the interface. In this example, the organic compound layer 81c and the second conductive layer 82c are peeled off at the interface. As described above, if the first conductive layer, the organic compound layer, and the second conductive layer constituting the memory element have poor adhesion, the film is peeled off at the interface in the peeling step, and the memory element is destroyed. Sometimes. Therefore, it is difficult to transpose the memory element in a good state while maintaining the shape and characteristics before peeling.

In view of such problems, the present invention provides a technology capable of manufacturing a semiconductor device having a memory element with good adhesion inside the memory element so that the transfer process can be performed in a good state while maintaining the shape and characteristics before peeling. provide. Therefore, it is an object to provide a technique capable of manufacturing a highly reliable semiconductor device with high yield without complicating an apparatus and a process.

In the present invention, a memory element in which an organic compound layer is provided between a pair of electrodes is used as the memory element. After a memory element is formed over a first substrate that can withstand process conditions (such as temperature), the memory element is transferred to the second substrate, so that a semiconductor device including the memory element is manufactured. In such a case, it is important that the first conductive layer, the organic compound layer, and the second conductive layer forming the memory element have good adhesion. If the adhesion between the stacks constituting the memory element is poor, the film is peeled off at the interface between the layers in the peeling step, and the element is destroyed, so that the transposition cannot be performed with a good shape. In this specification, good shape means that the shape before peeling is not damaged, such as film peeling or peeling residue, the shape before peeling is maintained, and the electrical characteristics and reliability of the element by the peeling process This refers to a state in which no deterioration or the like has occurred and the characteristics before peeling are maintained. In this specification, transposition means that a memory element formed over a first substrate is peeled off from the first substrate and transferred to the second substrate. That is, it can be said that the place where the memory element is provided is moved to another substrate.

In the present invention, attention is paid to the adhesion between the organic compound layer to be laminated, the first conductive layer, and the second conductive layer. The adhesion between substances is affected by a solubility parameter (SP value). The solubility parameter is a value obtained by multiplying the cohesive energy density (CED) per unit volume of one molecule by a power of 1/2.

The closer the SP value between substances, the better the adhesion between the substances. In general, the SP value of an organic compound material is smaller than that of a metal material. Therefore, in order to improve the adhesion between the organic compound layer and the conductive layer, the organic compound material used for the organic compound layer is a material having a large SP value as the organic material and the metal material used for the conductive layer has a small SP value. It is preferable to select a material and reduce the difference between the SP value of the material used for the organic compound layer and the SP value of the material used for the conductive layer.

In the present invention, as a metal material used for at least one of the first conductive layer and the second conductive layer, indium (In), tin (Sn), lead (Pb), bismuth (Bi), calcium (Ca), antimony One or more of (Sb) and zinc (Zn) are used. In addition, one or more of magnesium (Mg), manganese (Mn), cadmium (Cd), thallium (Tl), tellurium (Te), and barium (Ba) are used. A plurality of the metal materials may be included, or an alloy including one or more of the materials may be used. In particular, indium (In), tin (Sn), lead (Pb), bismuth (Bi), calcium (Ca), manganese (Mn), zinc (Zn), or a metal having a relatively low solubility parameter is included. Alloys are preferred as electrode materials. Examples of alloys that can be used include indium tin alloy (InSn), magnesium indium alloy (InMg), phosphorus alloy (InP), arsenic indium alloy (InAs), and chromium indium alloy (InCr).

On the other hand, since the SP value increases as the polarity of the organic material increases, the organic compound material used for the organic compound layer has a skeleton such as a sulfanyl group (thiol group), a cyano group, an amine structure, and a carbonyl group in the molecular structure. It is preferable to use a material.

In addition, the interfacial tension at the interface between layers in the element to be laminated also affects the adhesion between the layers. The smaller the interfacial tension between the layers, the better the adhesion between the layers, and it is difficult for defects such as film peeling to occur in the peeling process. Therefore, the element can be peeled and transferred in a good shape. The interfacial tension can be estimated from the surface tension with air, nitrogen, helium or the like, and the surface tension of the metal is larger than that of the organic material. In addition, the wettability of the metal material with the organic material is improved by oxidizing the surface. Therefore, the interface tension can be reduced by performing oxidation treatment or the like on the interface between the conductive layer using a metal material and the organic compound layer using an organic compound material. The difference between the surface tension of the organic compound layer and the surface tension of the conductive layer is preferably 1.5 N / m or less.

Examples of the treatment for reducing the interfacial tension include exposing the conductive layer to an oxygen atmosphere, and irradiating ultraviolet light in an oxygen atmosphere to generate ozone (O ₃ ) to oxidize the surface of the conductive layer. Alternatively, oxygen plasma may be contacted, or the conductive layer may be oxidized by an organic compound material contained in the organic compound at the layer interface. In addition to the oxidation treatment, nitriding treatment may be performed. Therefore, it is preferable to perform a treatment for reducing the interfacial tension on the surface in contact with at least one of the first conductive layer and the second conductive layer.

In addition, when a material in which atoms of an organic material constituting the organic compound layer and atoms of a metal material constituting the conductive layer are chemically bonded to each other is used, adhesion between the organic compound layer and the conductive layer is improved. Therefore, it is preferable.

Note that in this specification, a semiconductor device refers to a device that can function by utilizing semiconductor characteristics. A semiconductor device such as an integrated circuit including a memory element or a chip including a processor circuit can be manufactured using the present invention.

One of the semiconductor devices of the present invention includes a memory element including an organic compound layer between a first conductive layer and a second conductive layer, and at least of the first conductive layer and the second conductive layer. One includes one or more of indium, tin, lead, bismuth, calcium, manganese, and zinc.

One of the semiconductor devices of the present invention includes a memory element including an organic compound layer between a first conductive layer and a second conductive layer, and the first conductive layer and the second conductive layer are included. At least one is in contact with the organic compound layer through a film containing an oxide.

One embodiment of the semiconductor device of the present invention includes a memory element including an organic compound layer between a first conductive layer and a second conductive layer, and the first conductive layer includes an organic compound layer and an oxide. The second conductive layer is in contact with the film, and includes one or more of indium, tin, lead, bismuth, calcium, manganese, and zinc.

  In one embodiment of the method for manufacturing a semiconductor device of the present invention, a first conductive layer is formed, an organic compound layer is formed over the first conductive layer, and a second conductive layer is formed over the organic compound layer, which is stored. An element is manufactured, and at least one of the first conductive layer and the second conductive layer is formed to include one or more of indium, tin, lead, bismuth, calcium, manganese, and zinc.

  In one embodiment of the method for manufacturing a semiconductor device of the present invention, a first conductive layer is formed, an oxidation treatment is performed on the surface of the first conductive layer, and an organic compound layer is formed on the oxidized first conductive layer. A memory element is manufactured by forming a second conductive layer over the organic compound layer.

  In one embodiment of the method for manufacturing a semiconductor device of the present invention, a first conductive layer is formed, an oxidation treatment is performed on the surface of the first conductive layer, and an organic compound layer is formed on the oxidized first conductive layer. A memory element is manufactured by forming a second conductive layer over the organic compound layer, and the second conductive layer includes one or more of indium, tin, lead, bismuth, calcium, manganese, and zinc. Form with.

  According to one method for manufacturing a semiconductor device of the present invention, a first conductive layer is formed over a first substrate, an organic compound layer is formed over the first conductive layer, and a second conductive layer is formed over the organic compound layer. A memory element is formed by forming a layer, a flexible second substrate is bonded to the second conductive layer, the memory element is peeled from the first substrate, and the memory element is attached to the second conductive layer through the adhesive layer. 3. At least one of the first conductive layer and the second conductive layer is formed to include one or more of indium, tin, lead, bismuth, calcium, manganese, and zinc.

  According to one method for manufacturing a semiconductor device of the present invention, a first conductive layer is formed over a first substrate, an oxidation treatment is performed on the surface of the first conductive layer, and the oxidized first conductive layer is formed. An organic compound layer is formed, a second conductive layer is formed over the organic compound layer, a memory element is manufactured, a flexible second substrate is bonded to the second conductive layer, and the memory element is The memory element is peeled off from the first substrate and the memory element is bonded to the third substrate through the adhesive layer.

  A first conductive layer is formed on a first substrate, an oxidation treatment is performed on the surface of the first conductive layer, an organic compound layer is formed on the oxidized first conductive layer, and an organic compound layer is formed on the organic compound layer. A memory element is manufactured by forming a second conductive layer, a flexible second substrate is bonded to the second conductive layer, the memory element is peeled from the first substrate, and an adhesive layer is interposed therebetween. The memory element is bonded to the third substrate, and the second conductive layer is formed including one or more of indium, tin, lead, bismuth, calcium, manganese, and zinc. The first conductive layer can be formed over the first substrate with a peeling layer interposed therebetween.

  In the above semiconductor device, there is a case where the first conductive layer and the second conductive layer are partially in contact with each other or the film thickness of the organic compound layer is changed after writing the semiconductor device.

  According to the present invention, a semiconductor device having a memory element with good adhesion inside a memory element that can perform a transposition process in a favorable state can be manufactured. Therefore, a highly reliable semiconductor device can be manufactured with high yield without complicating the device and the process.

  Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in structures of the present invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated.

(Embodiment 1)
In this embodiment mode, a memory element to which the present invention is applied will be described with reference to FIGS.

  In the present invention, attention is paid to the adhesion between the organic compound layer to be laminated, the first conductive layer, and the second conductive layer. The adhesion between substances is affected by a solubility parameter (SP value). The solubility parameter is a value obtained by multiplying the cohesive energy density (CED) per unit volume of one molecule by a power of 1/2.

  The closer the SP value between substances, the better the adhesion between the substances. In general, the SP value of an organic compound material is smaller than that of a metal material. Therefore, in order to improve the adhesion between the organic compound layer and the conductive layer, the organic compound material used for the organic compound layer is a material having a large SP value as the organic material and the metal material used for the conductive layer has a small SP value. It is preferable to select a material and reduce the difference between the SP value of the material used for the organic compound layer and the SP value of the material used for the conductive layer. The difference between the SP value of the material used for the organic compound layer and the SP value of the material used for the conductive layer is desirably 120 or less.

In the present invention, as a metal material used for at least one of the first conductive layer and the second conductive layer, indium (In), tin (Sn), lead (Pb), bismuth (Bi), calcium (Ca), antimony One or more of (Sb) and zinc (Zn) are used. In addition, one or more of magnesium (Mg), manganese (Mn), cadmium (Cd), thallium (Tl), tellurium (Te), and barium (Ba) are used. A plurality of the metal materials may be included, or an alloy including one or more of the materials may be used. In particular, indium (In), tin (Sn), lead (Pb), bismuth (Bi), calcium (Ca), manganese (Mn), zinc (Zn), or a metal having a relatively low solubility parameter is included. Alloys are preferred as electrode materials. Examples of alloys that can be used include indium tin alloy (InSn), magnesium indium alloy (InMg), phosphorus alloy (InP), arsenic indium alloy (InAs), and chromium indium alloy (InCr).

On the other hand, since the SP value increases as the polarity of the organic material increases, the organic compound material used for the organic compound layer has a skeleton such as a sulfanyl group (thiol group), a cyano group, an amine structure, and a carbonyl group in the molecular structure. It is preferable to use a material.

FIG. 1A illustrates a memory element in which an organic compound layer 32 is provided between a first conductive layer 31 and a second conductive layer 33. In FIG. 1A, as the metal material used for the second conductive layer 33, indium (In), tin (Sn), lead (Pb), bismuth (Bi), calcium (Ca), antimony (Sb), zinc One or more of (Zn) are used. In addition, one or more of magnesium (Mg), manganese (Mn), cadmium (Cd), thallium (Tl), tellurium (Te), and barium (Ba) are used. A plurality of the metal materials may be included, or an alloy including one or more of the materials may be used. In particular, indium (In), tin (Sn), lead (Pb), bismuth (Bi), calcium (Ca), manganese (Mn), zinc (Zn), or a metal having a relatively low solubility parameter is included. Alloys are preferred as electrode materials. Examples of alloys that can be used include indium tin alloys (InSn), magnesium indium alloys (InMg), phosphorus indium alloys (InP), arsenic indium alloys (InAs), and chromium indium alloys (InCr).

  The first conductive layer 31, the organic compound layer 32, and the second conductive layer 33 illustrated in FIG. 1A have high adhesion, and thus are formed over the first substrate and then transferred to the second substrate. Due to the force applied in the process, defects such as film peeling are unlikely to occur at the layer interface. Therefore, the memory element can be peeled and transferred with a favorable shape, so that a semiconductor device can be manufactured.

  As the first conductive layer 31, an element or a compound having high conductivity is used. Typically, gold (Au), silver (Ag), platinum (Pt), nickel (Ni), tungsten (W), chromium (Cr), molybdenum (Mo), iron (Fe), cobalt (Co), From one element selected from copper (Cu), palladium (Pd), carbon (C), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), etc. or an alloy containing a plurality of such elements A single layer or a laminated structure can be used.

  In FIG. 1A, a conductive layer containing a metal material having a low solubility parameter is used for the second conductive layer 33, but a conductive layer containing a metal material having a low solubility parameter is used for the first conductive layer 31. May be. A conductive layer containing a metal material having a low solubility parameter may be used for both the first conductive layer and the second conductive layer. Such an example is shown in FIG.

  FIG. 16A illustrates a memory element in which an organic compound layer 57 is provided between the first conductive layer 55 and the second conductive layer 58. As metal materials used for the first conductive layer 55 and the second conductive layer 58, indium (In), tin (Sn), lead (Pb), bismuth (Bi), calcium (Ca), antimony (Sb), zinc One or more of (Zn) are used. In addition, one or more of magnesium (Mg), manganese (Mn), cadmium (Cd), thallium (Tl), tellurium (Te), and barium (Ba) are used. A plurality of the metal materials may be included, or an alloy including one or more of the materials may be used. In particular, indium (In), tin (Sn), lead (Pb), bismuth (Bi), calcium (Ca), manganese (Mn), zinc (Zn), or a metal having a relatively low solubility parameter is included. Alloys are preferred as electrode materials. Examples of alloys that can be used include indium tin alloys (InSn), magnesium indium alloys (InMg), phosphorus indium alloys (InP), arsenic indium alloys (InAs), and chromium indium alloys (InCr).

  The first conductive layer 55, the organic compound layer 57, and the second conductive layer 58 illustrated in FIG. 16A have good adhesion, and thus are formed over the first substrate and then transferred to the second substrate. Due to the force applied in the process, defects such as film peeling are unlikely to occur at the layer interface. Therefore, the memory element can be peeled and transferred with a favorable shape, so that a semiconductor device can be manufactured.

  In addition, the interfacial tension at the interface between layers in the element to be laminated also affects the adhesion between the layers. The smaller the interfacial tension between the layers, the better the adhesion between the layers, and it is difficult for defects such as film peeling to occur in the peeling and transposing processes. Therefore, the element can be peeled and transferred in a good shape. The interfacial tension can be estimated from the surface tension with air, nitrogen, helium or the like, and the surface tension of the metal is larger than that of the organic material. In addition, the wettability of the metal material with the organic material is improved by oxidizing the surface. Therefore, the interface tension can be reduced by performing oxidation treatment or the like on the interface between the conductive layer using a metal material and the organic compound layer using an organic compound material.

Examples of the treatment for reducing the interfacial tension include exposing the conductive layer to an oxygen atmosphere, and irradiating ultraviolet light in an oxygen atmosphere to generate ozone (O ₃ ) to oxidize the surface of the conductive layer. Alternatively, oxygen plasma may be contacted, or the conductive layer may be oxidized by an organic compound material contained in the organic compound at the layer interface. Alternatively, the conductive layer may be formed in an oxygen atmosphere. In addition to the oxidation treatment, nitridation treatment may be performed. For example, the nitridation treatment may be performed and then the oxidation treatment may be performed.

  FIG. 1B illustrates a memory element in which an organic compound layer 37 is provided between the first conductive layer 35 and the second conductive layer 38. The interface between the first conductive layer 35 and the organic compound layer 37 is subjected to a treatment for reducing the interfacial tension. In the present embodiment, a treatment region 36 is formed by performing an oxidation treatment on the interface between the first conductive layer 35 and the organic compound layer 37.

  As shown in FIG. 1B, the first conductive layer 35 is formed by forming an oxidation treatment region 36 that reduces the interfacial tension at the interface (surface) in contact with the organic compound layer 37 of the first conductive layer 35. The adhesion of the organic compound layer 37 can be improved. Therefore, defects such as film peeling at the layer interface are less likely to occur due to the force applied in the process of being transferred to the second substrate after being formed on the first substrate. Therefore, the memory element can be peeled and transferred with a favorable shape, so that a semiconductor device can be manufactured.

  As the first conductive layer 35 and the second conductive layer 38, a highly conductive element or compound is used. Typically, gold (Au), silver (Ag), platinum (Pt), nickel (Ni), tungsten (W), chromium (Cr), molybdenum (Mo), iron (Fe), cobalt (Co), From one element selected from copper (Cu), palladium (Pd), carbon (C), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), etc. or an alloy containing a plurality of such elements A single layer or a laminated structure can be used.

  A treatment region 36 is formed on the interface (surface) in contact with the organic compound layer of the first conductive layer 35 by performing a treatment for reducing the interface tension such as an oxidation treatment. For example, a titanium film may be formed on the surface of the titanium film by forming a titanium film using titanium as the first conductive layer 35 and oxidizing the titanium film. In this case, the treatment region 36 is a titanium oxide film, and the interfacial tension between the titanium oxide film and the organic compound layer 37 is reduced.

  FIG. 1B illustrates an example in which a treatment region is formed by performing treatment for reducing the first interfacial tension on the surface of the first conductive layer that is in contact with the organic compound layer. A treatment region having a low interfacial tension may be formed on the surface in contact with the organic compound layer by performing a similar treatment for reducing the interfacial tension. Moreover, you may perform the process which interface tension falls in each interface of a 1st conductive layer and a 2nd conductive layer, and an organic compound layer. Such an example is shown in FIG.

  FIG. 16B illustrates a memory element in which an organic compound layer 67 is provided between the first conductive layer 65 and the second conductive layer 68. The interface between the first conductive layer 65 and the organic compound layer 67 and the interface between the second conductive layer 68 and the organic compound layer 67 are each subjected to a treatment for reducing the interface tension. In this embodiment mode, an oxidation process is performed on the interface between the first conductive layer 65 and the organic compound layer 67 to form a treatment region 66, and the second conductive layer 68, the organic compound layer 67, and the second conductive layer 68 are formed. A treatment region 69 is also formed by performing an oxidation treatment at the interface with the substrate.

  As shown in FIG. 16B, the interface (surface) of the first conductive layer 65 in contact with the organic compound layer 67 and the interface (surface) of the second conductive layer 68 and organic compound layer 67 are in contact. By forming the oxidation treatment region 66 and the treatment region 69 that reduce the interfacial tension, the adhesion of the first conductive layer 65, the organic compound layer 67, and the second conductive layer 68 can be improved. Therefore, defects such as film peeling at the layer interface are less likely to occur due to the force applied in the process of being transferred to the second substrate after being formed on the first substrate. Therefore, the memory element can be peeled and transferred with a favorable shape, so that a semiconductor device can be manufactured.

  FIG. 16C illustrates a memory element in which an organic compound layer 77 is provided between the first conductive layer 75 and the second conductive layer 78. As a metal material used for the second conductive layer 68, one or more of indium (In), tin (Sn), lead (Pb), bismuth (Bi), calcium (Ca), antimony (Sb), and zinc (Zn) Use seeds. In addition, one or more of magnesium (Mg), manganese (Mn), cadmium (Cd), thallium (Tl), tellurium (Te), and barium (Ba) are used. A plurality of the metal materials may be included, or an alloy including one or more of the materials may be used. In particular, indium (In), tin (Sn), lead (Pb), bismuth (Bi), calcium (Ca), manganese (Mn), zinc (Zn), or a metal having a relatively low solubility parameter is included. Alloys are preferred as electrode materials. Examples of alloys that can be used include indium tin alloys (InSn), magnesium indium alloys (InMg), phosphorus indium alloys (InP), arsenic indium alloys (InAs), and chromium indium alloys (InCr).

  Further, the interface between the first conductive layer 75 and the organic compound layer 77 is subjected to a treatment for reducing the interfacial tension. In the present embodiment, the treatment region 76 is formed by performing oxidation treatment on the interface between the first conductive layer 75 and the organic compound layer 77.

  In FIG. 16C, the surface of the first conductive layer 75 is oxidized to form a treatment region 76 in contact with the organic compound layer 77, and the second conductive layer 78 has a relatively low solubility parameter. Although an example using a metal material is shown, a metal material having a relatively low solubility parameter as used in the second conductive layer 78 is used for the first conductive layer 75, and the second conductive layer 78 and the organic compound layer 77 are used. A region subjected to oxidation treatment or the like that lowers the interfacial tension may be formed at the interface.

  Further, in the memory elements in FIGS. 1A and 1B and FIGS. 16A to 16C, at the interface between the first conductive layer and the organic compound layer and at the interface between the second conductive layer and the organic compound layer. If the configuration and the material are not changed, another conductive layer is laminated on the first conductive layer (lower side of the first conductive layer in FIG. 1), and the second conductive layer (upper side of the second conductive layer in FIG. 1). ), Another conductive layer may be formed, and a memory element having the stacked conductive layer may be used.

  As the conductive layer stacked over the first conductive layer and the second conductive layer, a highly conductive element, compound, or the like is used. Typically, gold (Au), silver (Ag), platinum (Pt), nickel (Ni), tungsten (W), chromium (Cr), molybdenum (Mo), iron (Fe), cobalt (Co), From one element selected from copper (Cu), palladium (Pd), carbon (C), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), etc. or an alloy containing a plurality of such elements A single layer or a laminated structure can be used. Examples of the alloy containing a plurality of the above elements include an alloy Al containing Al and Ti, an alloy containing Ti and C, an alloy containing Al and Ni, an alloy containing Al and C, and Al, Ni and C. An alloy containing Al or an alloy containing Al and Mo can be used.

    The organic compound layer 32, the organic compound layer 37, the organic compound layer 57, the organic compound layer 67, and the organic compound layer 77 are formed using an organic compound whose conductivity is changed by an optical action or an electrical action. The organic compound layer 57, the organic compound layer 67, and the organic compound layer 77 may be provided as a single layer or a plurality of stacked layers. Alternatively, a layer formed of an organic compound whose conductivity is changed by an optical action or an electrical action may be stacked.

    Examples of organic compounds that can constitute the organic compound layer 32, the organic compound layer 37, the organic compound layer 57, the organic compound layer 67, and the organic compound layer 77 include polyimide, acrylic, polyamide, benzocyclobutene, and epoxy. An organic resin can be used.

    Further, an organic compound that can constitute the organic compound layer 32, the organic compound layer 37, the organic compound layer 57, the organic compound layer 67, and the organic compound layer 77 and whose conductivity is changed by an optical action or an electric action. For example, an organic compound material having a hole transporting property or an organic compound material having an electron transporting property can be used.

As an organic compound material having a hole-transport property, 4,4′-bis [N- (1-naphthyl) -N-phenyl-amino] -biphenyl (abbreviation: NPB), 4,4′-bis [N— (3-methylphenyl) -N-phenyl-amino] -biphenyl (abbreviation: TPD), 4,4 ′, 4 ″ -tris (N, N-diphenyl-amino) -triphenylamine (abbreviation: TDATA), 4,4 ′, 4 ″ -tris [N- (3-methylphenyl) -N-phenyl-amino] -triphenylamine (abbreviation: MTDATA) and 4,4′-bis (N- (4- (N , N-di-m-tolylamino) phenyl) -N-phenylamino) biphenyl (abbreviation: DNTPD) and other aromatic amine-based compounds (that is, having a benzene ring-nitrogen bond) and phthalocyanines (abbreviation: H _2). Pc), copper phthalo Cyanine (abbreviation: CuPc), or vanadyl phthalocyanine (abbreviation: VOPc), and the phthalocyanine compound and the like can be used. The substances described here are mainly substances having a hole mobility of 10 ⁻⁶ cm ² / Vs or higher.

As an organic compound material having an electron transporting property, tris (8-quinolinolato) aluminum (abbreviation: Alq ₃ ), tris (4-methyl-8-quinolinolato) aluminum (abbreviation: Almq ₃ ), bis (10-hydroxybenzo [ h] -quinolinato) beryllium (abbreviation: BeBq ₂ ), bis (2-methyl-8-quinolinolato) -4-phenylphenolato-aluminum (abbreviation: BAlq), etc., and a metal complex having a quinoline skeleton or a benzoquinoline skeleton Materials can be used. In addition, bis [2- (2-hydroxyphenyl) benzoxazolate] zinc (abbreviation: Zn (BOX) ₂ ), bis [2- (2-hydroxyphenyl) benzothiazolate] zinc (abbreviation: Zn (BTZ) A material such as a metal complex having an oxazole-based or thiazole-based ligand such as ₂ ) can also be used. In addition to metal complexes, 2- (4-biphenylyl) -5- (4-tert-butylphenyl) -1,3,4-oxadiazole (abbreviation: PBD), 1,3-bis [5- (P-tert-butylphenyl) -1,3,4-oxadiazol-2-yl] benzene (abbreviation: OXD-7), 3- (4-tert-butylphenyl) -4-phenyl-5- ( 4-biphenylyl) -1,2,4-triazole (abbreviation: TAZ), 3- (4-tert-butylphenyl) -4- (4-ethylphenyl) -5- (4-biphenylyl) -1,2, 4-triazole (abbreviation: p-EtTAZ), bathophenanthroline (abbreviation: BPhen), bathocuproin (abbreviation: BCP), and the like can be used. The substances mentioned here are mainly substances having an electron mobility of 10 ⁻⁶ cm ² / Vs or higher.

  The organic compound layer 32, the organic compound layer 37, the organic compound layer 57, the organic compound layer 67, and the organic compound layer 77 can be formed by a vapor deposition method, an electron beam vapor deposition method, a sputtering method, a CVD method, or the like. Moreover, when forming an organic compound layer using a plurality of materials, it can be formed by simultaneously forming each material, a co-evaporation method by resistance heating evaporation, a co-evaporation method by electron beam evaporation, It can be formed by a combination of the same or different methods such as co-evaporation by resistance heating evaporation and electron beam evaporation, film formation by resistance heating evaporation and sputtering, and film formation by electron beam evaporation and sputtering.

    Note that the organic compound layer 32, the organic compound layer 37, the organic compound layer 57, the organic compound layer 67, and the organic compound layer 77 are formed with a thickness at which the conductivity of the memory element is changed by an optical action or an electrical action. . Since the conductivity of the memory element having the above configuration changes before and after voltage application, two values corresponding to “initial state” and “after conductivity change” can be stored.

  Alternatively, as illustrated in FIGS. 19A to 19C, an insulating layer may be provided between the organic compound layer and the conductive layer. 19A to 19C, the first conductive layer 50, the first conductive layer 60, the first conductive layer 70, the second conductive layer 53, the second conductive layer 63, and the second conductive layer. Similar to the first conductive layer 55 and the second conductive layer 58 in FIG. 16A, the layer 73 is made of indium (In), tin (Sn), lead (Pb), bismuth (Bi) as a metal material to be used. ), Calcium (Ca), antimony (Sb), or zinc (Zn). In addition, one or more of magnesium (Mg), manganese (Mn), cadmium (Cd), thallium (Tl), tellurium (Te), and barium (Ba) are used. A plurality of the metal materials may be included, or an alloy including one or more of the materials may be used. In particular, indium (In), tin (Sn), lead (Pb), bismuth (Bi), calcium (Ca), manganese (Mn), zinc (Zn), or a metal having a relatively low solubility parameter is included. Alloys are preferred as electrode materials. Examples of alloys that can be used include indium tin alloys (InSn), magnesium indium alloys (InMg), phosphorus indium alloys (InP), arsenic indium alloys (InAs), and chromium indium alloys (InCr).

  Of course, the first conductive layer and the second conductive layer in FIGS. 19A to 19C are formed in the same manner as in FIGS. 1A, 1B, 16B, and 16C. A conductive layer may be used, and an oxidation treatment or the like may be performed on the interface between the conductive layer and the organic compound layer so as to reduce the interfacial tension.

  The organic compound layer 52, the organic compound layer 62, and the organic compound layer 72 may be formed using the same materials as those of the organic compound layer 32 and the organic compound layer 37 in FIG.

  FIG. 19A shows an example in which an insulating layer 51 is provided between the first conductive layer 50 and the organic compound layer 52, and the second conductive layer 53 is provided over the organic compound layer 52. In FIG. 19B, the insulating layer 61 is formed over the organic compound layer 62 provided over the first conductive layer 60, and the second conductive layer 63 is provided over the insulating layer 61. FIG. 19C shows a structure in which a first conductive layer 70, a first insulating layer 71, an organic compound layer 72, a second insulating layer 74, and a second conductive layer 73 are stacked. A first insulating layer 71 is provided between the organic compound layer 72 and the organic compound layer 72, and a second insulating layer 74 is provided between the organic compound layer 72 and the second conductive layer 73.

    In this embodiment mode, the insulating layer 51, the insulating layer 61, the first insulating layer 71, and the second insulating layer 74 have insulating properties and are very thin (the thickness of the insulating layer is 4 nm or less, 1 nm or more). 2 nm or less), and depending on the material and manufacturing method thereof, it may not have a continuous film shape but may have a discontinuous island shape. In other drawings in this specification, the insulating layer is described as a continuous layer. However, the insulating layer includes a case where the insulating layer has a discontinuous island shape.

  The insulating layer present at the interface between the conductive layer and the organic compound layer enables tunnel injection of carriers, and a tunnel current flows. Therefore, when a voltage is applied between the first conductive layer and the second conductive layer, a current flows through the organic compound layer and heat is generated. And when the temperature of an organic compound layer rises to a glass transition temperature, the material which forms an organic compound layer turns into a composition which has fluidity | liquidity. The composition having fluidity flows (moves) without maintaining the solid state shape, and changes its shape. Accordingly, the film thickness of the organic compound layer becomes nonuniform, the organic compound layer is deformed, and a part of the first conductive layer and the second conductive layer are in contact with each other, and the first conductive layer and the second conductive layer are Is short-circuited. In some cases, the electric field concentrates on the thin region of the organic compound layer, and the first conductive layer and the second conductive layer are short-circuited due to the influence of the high electric field. Therefore, the conductivity of the memory element before and after voltage application changes.

  In a semiconductor device, after writing into the semiconductor device, the first conductive layer and the second conductive layer may be in contact with each other or the film thickness of the organic compound layer may change.

    By providing the insulating layer 51, the insulating layer 61, the first insulating layer 71, and the second insulating layer 74, characteristics such as the writing voltage of the memory element are stabilized without variation, and normal writing is performed in each element. Is possible. Further, since the carrier injection property is improved by the tunnel current, the organic compound layer can be thickened. Therefore, it is possible to prevent the memory element from being short-circuited in the initial state before energization.

    Note that the voltage applied to the memory element of the present invention may be higher than the second conductive layer in the first conductive layer, or higher in the second conductive layer than in the first conductive layer. May be. Even when the memory element has a rectifying property, a potential difference may be provided between the first conductive layer and the second conductive layer so that the voltage is applied in the forward bias direction, or the voltage is applied in the reverse bias direction. A potential difference may be provided between the first conductive layer and the second conductive layer so that is applied.

    In the present invention, the insulating layer is formed using an inorganic insulator or organic compound that is thermally and chemically stable and into which carriers are not injected. Specific examples of inorganic insulators and organic compounds that can be used for the insulating layer are described below.

In the present invention, as an inorganic insulator that can be used for the insulating layer, lithium oxide (Li ₂ O), sodium oxide (Na ₂ O), potassium oxide (K ₂ O), rubidium oxide (Rb ₂ O), beryllium oxide (BeO), magnesium oxide (MgO), calcium oxide (CaO), strontium oxide (SrO), barium oxide (BaO), scandium oxide (Sc ₂ O ₃ ), zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ) , Rutherfordium oxide (RfO ₂ ), tantalum oxide (TaO), technetium oxide (TcO), iron oxide (Fe ₂ O ₃ ), cobalt oxide (CoO), palladium oxide (PdO), silver oxide (Ag ₂ O), oxidation aluminum _{(Al 2 O} 3), gallium oxide _{(Ga 2 O} 3), bismuth oxide (Bi O ₃₎ may be an oxide such as.

In the present invention, as other inorganic insulators that can be used for the insulating layer, lithium fluoride (LiF), sodium fluoride (NaF), potassium fluoride (KF), rubidium fluoride (RbF), cesium fluoride ( CsF), beryllium fluoride (BeF ₂ ), magnesium fluoride (MgF ₂ ), calcium fluoride (CaF ₂ ), strontium fluoride (SrF ₂ ), barium fluoride (BaF ₂ ), aluminum fluoride (AlF ₃ ) Fluoride such as nitrogen trifluoride (NF ₃ ), sulfur hexafluoride (SF ₆ ), silver fluoride (AgF), manganese fluoride (MnF ₃ ) can be used.

In the present invention, other inorganic insulators that can be used for the insulating layer include lithium chloride (LiCl), sodium chloride (NaCl), potassium chloride (KCl), beryllium chloride (BeCl ₂ ), calcium chloride (CaCl ₂ ), Barium chloride (BaCl ₂ ), aluminum chloride (AlCl ₃ ), silicon chloride (SiCl ₄ ), germanium chloride (GeCl ₄ ), tin chloride (SnCl ₄ ), silver chloride (AgCl), zinc chloride (ZnCl), titanium tetrachloride (TiCl ₄ ), titanium trichloride (TiCl ₃ ), zirconium chloride (ZrCl ₄ ), iron chloride (FeCl ₃ ), palladium chloride (PdCl ₂ ), antimony trichloride (SbCl ₃ ), antimony dichloride (SbCl ₂ ), chloride Strontium (SrCl ₂ ), thallium chloride (TlCl), Chlorides such as copper chloride (CuCl), manganese chloride (MnCl ₂ ), and ruthenium chloride (RuCl ₂ ) can be used.

In the present invention, other inorganic insulators that can be used for the insulating layer include potassium bromide (KBr), cesium bromide (CsBr), silver bromide (AgBr), barium bromide (BaBr ₂ ), silicon bromide. Bromides such as (SiBr ₄ ) and lithium bromide (LiBr) can be used.

In the present invention, other inorganic insulators that can be used for the insulating layer include sodium iodide (NaI), potassium iodide (KI), barium iodide (BaI ₂ ), thallium iodide (TlI), silver iodide. (AgI), titanium iodide _(TiI 4), calcium iodide _(CaI 2), iodide silicon _(SiI 4), it can be used an iodide such as cesium iodide (CsI).

In the present invention, as other inorganic insulators that can be used for the insulating layer, lithium carbonate (Li ₂ CO ₃ ), potassium carbonate (K ₂ CO ₃ ), sodium carbonate (Na ₂ CO ₃ ), magnesium carbonate (MgCO ₃₎ ), Calcium carbonate (CaCO ₃ ), strontium carbonate (SrCO ₃ ), barium carbonate (BaCO ₃ ), manganese carbonate (MnCO ₃ ), iron carbonate (FeCO ₃ ), cobalt carbonate (CoCO ₃ ), nickel carbonate (NiCO ₃ ) Carbonates such as copper carbonate (CuCO ₃ ), silver carbonate (Ag ₂ CO ₃ ), and zinc carbonate (ZnCO ₃ ) can be used.

In the present invention, other inorganic insulators that can be used for the insulating layer include lithium sulfate (Li ₂ SO ₄ ), potassium sulfate (K ₂ SO ₄ ), sodium sulfate (Na ₂ SO ₄ ), magnesium sulfate (MgSO ₄ ). ), Calcium sulfate (CaSO ₄ ), strontium sulfate (SrSO ₄ ), barium sulfate (BaSO ₄ ), titanium sulfate (Ti ₂ (SO ₄ ) ₃ ), zirconium sulfate (Zr (SO ₄ ) ₂ ), manganese sulfate (MnSO ₄ ), iron sulfate (FeSO ₄ ), diferric trisulfate (Fe ₂ (SO ₄ ) ₃ ), cobalt sulfate (CoSO ₄ ), cobalt sulfate (Co ₂ (SO ₄ ) ₃ ), nickel sulfate (NiSO ₄ ), Copper sulfate (CuSO ₄ ), silver sulfate (Ag ₂ SO ₄ ), zinc sulfate (ZnSO ₄ ), aluminum sulfate (Al ₂ (SO ₂ ) ₄ ) ₃ ), indium sulfate (In ₂ (SO ₄ ) ₃ ), tin sulfate (SnSO ₄ ), tin sulfate (Sn (SO ₄ ) ₂ ), antimony sulfate (Sb ₂ (SO ₄ ) ₃ ), bismuth sulfate ( Sulfates such as Bi ₂ (SO ₄ ) ₃ ) can be used.

In the present invention, as other inorganic insulators that can be used for the insulating layer, lithium nitrate (LiNO ₃ ), potassium nitrate (KNO ₃ ), sodium nitrate (NaNO ₃ ), magnesium nitrate (Mg (NO ₃ ) ₂ ), nitric acid Calcium (Ca (NO ₃ ) ₂ ), strontium nitrate (Sr (NO ₃ ) ₂ ), barium nitrate (Ba (NO ₃ ) ₂ ), titanium nitrate (Ti (NO ₃ ) ₄ ), strontium nitrate Sr (NO ₃ ) ₂ ), barium nitrate (Ba (NO ₃ ) ₂ ), zirconium nitrate (Zr (NO ₃ ) ₄ ), manganese nitrate (Mn (NO ₃ ) ₂ ), iron nitrate (Fe (NO ₃ ) ₂ ), iron nitrate ( Fe _{(NO 3) 3),} cobalt nitrate _{(Co (NO 3) 2)} , nickel nitrate _{(Ni (NO 3) 2)} , copper nitrate _{(Cu (NO 3) 2)} , Silver (AgNO _3), zinc nitrate _{(Zn (NO 3) 2)} , aluminum nitrate _{(Al (NO 3) 3)} , indium nitrate _{(In (NO 3) 3)} , tin nitrate _(Sn (NO _{3) 2)} Nitrate such as bismuth nitrate (Bi (NO ₃ ) ₃ ) can be used.

In the present invention, other inorganic insulators that can be used for the insulating layer include nitrides such as aluminum nitride (AlN) and silicon nitride (SiN), lithium carboxylate (LiCOOCH ₃ ), potassium acetate (KCOOCH ₃ ), and acetic acid. Sodium (NaCOOCH ₃ ), magnesium acetate (Mg (COOCH ₃ ) ₂ ), calcium acetate (Ca (COOCH ₃ ) ₂ ), strontium acetate (Sr (COOCH ₃ ) ₂ ), barium acetate (Ba (COOCH ₃ ) ₂ ), etc. Can be used.

    In the present invention, as the inorganic insulator that can be used for the insulating layer, one or more of the above inorganic insulators can be used.

    In the present invention, as an organic compound that can be used for the insulating layer, polyimide, acrylic, polyamide, benzocyclobutene, polyester, novolac resin, melamine resin, phenol resin, epoxy resin, silicon resin, furan resin, diallyl phthalate resin, siloxane Resin can be used.

In the present invention, as another organic compound that can be used for the insulating layer, 4,4′-bis [N- (1-naphthyl) -N-phenyl-amino] -biphenyl (abbreviation: NPB) or 4,4 ′ -Bis [N- (3-methylphenyl) -N-phenyl-amino] -biphenyl (abbreviation: TPD), 4,4 ′, 4 ″ -tris (N, N-diphenyl-amino) -triphenylamine ( Abbreviation: TDATA), 4,4 ′, 4 ″ -tris [N- (3-methylphenyl) -N-phenyl-amino] -triphenylamine (abbreviation: MTDATA) and 4,4′-bis (N— (4- (N, N-di-m-tolylamino) phenyl) -N-phenylamino) biphenyl (abbreviation: DNTPD) and other aromatic amine-based compounds (that is, having a benzene ring-nitrogen bond), phthalocyanines (abbreviation: ₂ Pc), copper phthalocyanine (abbreviation: CuPc), or vanadyl phthalocyanine (abbreviation: VOPc), and phthalocyanine compounds such as, 2Me-TPD, FTPD, TPAC , OTPAC, Diamine, PDA, triphenylmethane (abbreviation: TPM), STB and the like Can be used.

In the present invention, as another organic compound that can be used for the insulating layer, tris (8-quinolinolato) aluminum (abbreviation: Alq ₃ ), tris (4-methyl-8-quinolinolato) aluminum (abbreviation: Almq ₃ ), bis (10-hydroxybenzo [h] -quinolinato) beryllium (abbreviation: BeBq ₂ ), bis (2-methyl-8-quinolinolato) -4-phenylphenolato-aluminum (abbreviation: BAlq), etc. A material composed of a metal complex or the like, bis [2- (2-hydroxyphenyl) benzoxazolate] zinc (abbreviation: Zn (BOX) ₂ ), bis [2- (2-hydroxyphenyl) benzothiazolate] zinc (abbreviation: Metals having an oxazole or thiazole ligand such as Zn (BTZ) ₂ ) Materials such as complexes, 2- (4-biphenylyl) -5- (4-tert-butylphenyl) -1,3,4-oxadiazole (abbreviation: PBD), 1,3-bis [5- (p- tert-butylphenyl) -1,3,4-oxadiazol-2-yl] benzene (abbreviation: OXD-7), 3- (4-tert-butylphenyl) -4-phenyl-5- (4-biphenylyl) ) -1,2,4-triazole (abbreviation: TAZ), 3- (4-tert-butylphenyl) -4- (4-ethylphenyl) -5- (4-biphenylyl) -1,2,4-triazole (Abbreviation: p-EtTAZ), bathophenanthroline (abbreviation: BPhen), bathocuproin (abbreviation: BCP), 5,6,11,12-tetraphenyltetracene (abbreviation: rubrene), hexaphenylbenzene Zen, t-butylperylene, 9,10-di (phenyl) anthracene, coumarin 545T, etc., dendrimer, 4-dicyanomethylene-2-methyl-6- [2- (1,1,7,7-tetramethyl-9 -Jurolidyl) ethenyl] -4H-pyran (abbreviation: DCJT), 4-dicyanomethylene-2-t-butyl-6- [2- (1,1,7,7-tetramethyljulolidin-9-yl) ethenyl ] -4H-pyran (abbreviation: DCJTB), periflanthene, 2,5-dicyano-1,4-bis [2- (10-methoxy-1,1,7,7-tetramethyljulolidin-9-yl) ethenyl ] benzene, N, N'-dimethyl quinacridone (abbreviation: DMQd), coumarin 6, coumarin 545T, tris (8-quinolinolato) aluminum (abbreviation: _Alq 3), , 9′-bianthryl, 9,10-diphenylanthracene (abbreviation: DPA), 9,10-bis (2-naphthyl) anthracene (abbreviation: DNA), 2,5,8,11-tetra-t-butylperylene ( (Abbreviation: TBP), BMD, BDD, 2,5-bis (1-naphthyl) -1,3,4-oxadiazole (abbreviation: BND), BAPD, BBOT, TPQ1, TPQ2, MBDQ, and the like can be used. .

    In the present invention, polyacetylenes, polyphenylene vinylenes, polythiophenes, polyanilines, polyphenylene ethynylenes, and the like can be used as other organic compounds that can be used for the insulating layer. Examples of the polyparaphenylene vinylene include poly (paraphenylene vinylene) [PPV] derivatives, poly (2,5-dialkoxy-1,4-phenylene vinylene) [RO-PPV], poly (2- (2′- Ethyl-hexoxy) -5-methoxy-1,4-phenylenevinylene) [MEH-PPV], poly (2- (dialkoxyphenyl) -1,4-phenylenevinylene) [ROPh-PPV] and the like. Examples of polyparaphenylene include derivatives of polyparaphenylene [PPP], poly (2,5-dialkoxy-1,4-phenylene) [RO-PPP], poly (2,5-dihexoxy-1,4-phenylene). ) And the like. The polythiophene series includes polythiophene [PT] derivatives, poly (3-alkylthiophene) [PAT], poly (3-hexylthiophene) [PHT], poly (3-cyclohexylthiophene) [PCHT], poly (3-cyclohexyl). -4-methylthiophene) [PCHMT], poly (3,4-dicyclohexylthiophene) [PDCHT], poly [3- (4-octylphenyl) -thiophene] [POPT], poly [3- (4-octylphenyl) -2,2 bithiophene] [PTOPT] and the like. Examples of the polyfluorene series include polyfluorene [PF] derivatives, poly (9,9-dialkylfluorene) [PDAF], poly (9,9-dioctylfluorene) [PDOF], and the like.

    In the present invention, PFBT, a carbazole derivative, anthracene, coronene, perylene, PPCP, BPPC, Boryl Anthracene, DCM, QD, Eu (TTA) 3phen, or the like can be used as another organic compound that can be used for the insulating layer. .

    In the present invention, as the organic compound that can be used for the insulating layer, one or more of the above organic compounds can be used.

    In the present invention, the insulating layer can be formed using one or more of the above inorganic insulators and the above organic compounds. In the present invention, the insulating layer has an insulating property.

  For the insulating layer, a vapor deposition method such as co-evaporation, a coating method such as a spin coating method, or a sol-gel method can be used. In addition, a droplet discharge (ejection) method (an ink jet method depending on the method) that can selectively eject (eject) droplets of a composition prepared for a specific purpose to form a predetermined pattern. ), A method by which an object can be transferred or drawn in a desired pattern, such as various printing methods (screen (stencil) printing, offset (lithographic) printing, relief printing or gravure (intaglio printing), etc. Method) can also be used.

  Since the semiconductor device including the memory element manufactured in this embodiment has favorable adhesion inside the memory element, the separation and transfer process can be performed in a favorable state. Therefore, since it can be freely transferred to various substrates, the range of substrate material selectivity is widened. In addition, an inexpensive material can be selected as the substrate, so that not only a wide function can be provided depending on the application, but also a semiconductor device can be manufactured at low cost.

  According to the present invention, a semiconductor device having a memory element with good adhesion inside a memory element that can perform a transposition process in a favorable state can be manufactured. Therefore, a highly reliable semiconductor device can be manufactured with high yield without complicating the device and the process.

(Embodiment 2)
In this embodiment, a structural example of a memory element included in a semiconductor device of the present invention will be described with reference to drawings. More specifically, the case where the structure of the semiconductor device is a passive matrix type will be described.

    The memory element of the present invention and its operation mechanism will be described with reference to FIGS. The memory element in this embodiment can be manufactured using the same material and structure as those in Embodiment 1. Therefore, detailed description of materials and the like is omitted.

  FIG. 3 shows a structural example of the semiconductor device of the present invention. A memory cell array 722 in which memory cells 721 are provided in a matrix, a circuit 726 having a reading circuit and a writing circuit, a decoder 724, and a decoder 723 are shown. Have. Note that the structure of the semiconductor device 716 shown here is merely an example, and other circuits such as a sense amplifier, an output circuit, and a buffer may be included, and a writing circuit may be provided in the bit line driver circuit.

  The memory cell 721 includes a first conductive layer connected to the bit line Bx (1 ≦ x ≦ m), a second conductive layer connected to the word line Wy (1 ≦ y ≦ n), and an organic compound layer And have. The organic compound layer is provided as a single layer or a stacked layer between the first conductive layer and the second conductive layer.

  2A is a top view of the memory cell array 722, and FIGS. 2B and 2C are cross-sectional views taken along line AB in FIG. 2A. In FIG. 2A, the insulating layer 754 is omitted and not shown, but is provided as shown in FIG. 2B.

  The memory cell array 722 includes a first conductive layer 751a, a first conductive layer 751b, a first conductive layer 751c, a first conductive layer 751a, a first conductive layer 751b, and a first layer extending in the first direction. An organic compound layer 752 provided to cover the conductive layer 751c; a second conductive layer 753a extending in a second direction perpendicular to the first direction; a second conductive layer 753b; a second conductive layer 753a; (See FIG. 2A). An organic compound layer 752 is provided between the first conductive layer 751a, the first conductive layer 751b, the first conductive layer 751c, the second conductive layer 753a, the second conductive layer 753b, and the second conductive layer 753a. Is provided. Further, an insulating layer 754 serving as a protective film is provided so as to cover the second conductive layer 753a, the second conductive layer 753b, and the second conductive layer 753a (see FIG. 2B). Note that when there is a concern about the influence of a horizontal electric field between adjacent memory cells, the organic compound layer 752 provided in each memory cell may be separated.

  FIG. 2C is a modification example of FIG. 2B, in which a first conductive layer 791a, a first conductive layer 791b, a first conductive layer 791c, an organic compound layer 792, and a first conductive layer 792 are formed over a substrate 790. 2 conductive layers 793b and an insulating layer 794 which is a protective layer. As in the first conductive layer 791a, the first conductive layer 791b, and the first conductive layer 791c in FIG. 2C, the first conductive layer may have a tapered shape, and the curvature radius may be continuous. The shape may change. Shapes such as the first conductive layer 791a, the first conductive layer 791b, and the first conductive layer 791c can be formed by a droplet discharge method or the like. When the curved surface has such a curvature, the coverage of the organic compound layer and the conductive layer to be stacked is good.

  In addition, a partition wall (insulating layer) may be formed so as to cover an end portion of the first conductive layer. The partition (insulating layer) functions like a wall separating other memory elements. 6A and 6B illustrate a structure in which the end portion of the first conductive layer is covered with a partition wall (insulating layer).

  As shown in FIG. 6B in FIG. 6A, the treatment region 776a, the treatment region 776b, and the treatment region 776c that have been subjected to the treatment for reducing the interfacial tension are respectively formed into the first conductive layer 771a and the first conductive layer 771a. A second conductive layer having a treatment region 777 formed on the surface of the conductive layer 771b and the first conductive layer 771c so as to be in contact with the organic compound layer 772 and subjected to treatment for reducing the interfacial tension via the organic compound layer. An example of forming 773b is shown. In this embodiment, a partition wall (insulating layer) 775 to be a partition wall is formed in a tapered shape so as to cover end portions of the first conductive layer 771a, the first conductive layer 771b, and the first conductive layer 771c. Is done. A partition (insulating layer) 775 is formed over the first conductive layer 771a, the first conductive layer 771b, the first conductive layer 771c, and the insulating layer 776 provided over the substrate 770, and the organic compound layer 772 Two conductive layers 773b and an insulating layer 774 are formed.

    In the semiconductor device illustrated in FIG. 6B, the partition wall (insulating layer) 765 has a curvature, and the curvature radius thereof is continuously changed. As shown in FIG. 16C, a treatment region 766a, a treatment region 766b, and a treatment region 766c, which have been subjected to a treatment for reducing the interfacial tension on the surface of the first conductive layer, are formed into a first conductive layer 761a and a first conductive layer, respectively. The layer 761b is formed on the surface of the first conductive layer 761c so as to be in contact with the organic compound layer 762, and the second conductive layer 763b is formed over the organic compound layer 762. An insulating layer 764 serving as a protective layer is formed over the second conductive layer 763b. The insulating layer 764 is not necessarily formed.

  The second conductive layer 763b is formed using one or more of indium (In), tin (Sn), lead (Pb), bismuth (Bi), calcium (Ca), antimony (Sb), and zinc (Zn). Is formed. In addition, one or more of magnesium (Mg), manganese (Mn), cadmium (Cd), thallium (Tl), tellurium (Te), and barium (Ba) are used. A plurality of the metal materials may be included, or an alloy including one or more of the materials may be used. In particular, indium (In), tin (Sn), lead (Pb), bismuth (Bi), calcium (Ca), manganese (Mn), zinc (Zn), or a metal having a relatively low solubility parameter is included. Alloys are preferred as electrode materials. Examples of alloys that can be used include indium tin alloys (InSn), magnesium indium alloys (InMg), phosphorus indium alloys (InP), arsenic indium alloys (InAs), chromium indium alloys (InCr), and the like. .

  Needless to say, the first conductive layer and the second conductive layer shown in FIGS. 2, 6A, and 6B are the same as those in FIGS. 1A, 1B, and 16A to 16C. A conductive layer formed in the above may be used. A conductive layer containing a metal material having a low solubility parameter is used for at least one of the first conductive layer and the second conductive layer, or at least one organic compound layer of the first conductive layer and the second conductive layer An oxidation treatment or the like that lowers the interfacial tension may be applied to the interface. The first conductive layer and the second conductive layer may be formed using a metal material having a small solubility parameter as shown in FIG. 16A, and the organic compound layer as shown in FIG. A region having a low surface tension may be formed at both interfaces between the first conductive layer and the second conductive layer, and the first conductive layer and the second conductive layer may be formed as shown in FIG. One of the layers may be formed using a metal material having a small solubility parameter, and a region having a low surface tension may be formed at the interface with the other organic compound layer.

In the structure of the memory cell, as the substrate 750, the substrate 760, the substrate 770, and the substrate 780, a glass substrate, a flexible substrate, a quartz substrate, a silicon substrate, a metal substrate, a stainless steel substrate, or the like can be used. The flexible substrate is a substrate that can be bent (flexible), and examples thereof include a plastic substrate made of polycarbonate, polyarylate, polyethersulfone, or the like. It is also possible to use films (made of polypropylene, polyester, vinyl, polyvinyl fluoride, vinyl chloride, etc.), paper made of fibrous materials, substrate films (polyester, polyamide, inorganic vapor deposition film, papers, etc.), etc. it can. In addition, a memory cell array 722 may be provided above a field effect transistor (FET) formed on a semiconductor substrate such as Si or above a thin film transistor (TFT) formed on a substrate such as glass. it can.

  Since the semiconductor device including the memory element manufactured in this embodiment has favorable adhesion inside the memory element, the separation and transfer process can be performed in a favorable state. Therefore, since it can be freely transferred to various substrates, the range of substrate material selectivity is widened. In addition, an inexpensive material can be selected as the substrate, so that not only a wide function can be provided depending on the application, but also a semiconductor device can be manufactured at low cost.

  As the partition wall (insulating layer) 765 and the partition wall (insulating layer) 775, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, and other inorganic insulating materials, acrylic acid, methacrylic acid, and the like Or a heat resistant polymer such as polyimide, aromatic polyamide, polybenzimidazole, or a siloxane resin. Note that a siloxane resin corresponds to a resin including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent. Further, a resin material such as a vinyl resin such as polyvinyl alcohol or polyvinyl butyral, an epoxy resin, a phenol resin, a novolac resin, an acrylic resin, a melamine resin, or a urethane resin is used. Alternatively, an organic material such as benzocyclobutene, parylene, fluorinated arylene ether, or polyimide, a composition material containing a water-soluble homopolymer and a water-soluble copolymer, or the like may be used. As a manufacturing method, a vapor deposition method such as a plasma CVD method or a thermal CVD method, or a sputtering method can be used. Alternatively, a droplet discharge method or a printing method (a method for forming a pattern such as screen printing or offset printing) can be used. A coating film obtained by a coating method can also be used.

  Further, after a conductive layer, an insulating layer, or the like is formed by discharging a composition by a droplet discharge method, the surface may be flattened by pressing with a pressure in order to improve the flatness. As a pressing method, unevenness may be reduced by scanning a roller-shaped object on the surface, or the surface may be pressed with a flat plate-like object. A heating step may be performed when pressing. Alternatively, the surface may be softened or dissolved with a solvent or the like, and the surface irregularities may be removed with an air knife. Further, polishing may be performed using a CMP method. This step can be applied when the surface is flattened when unevenness is generated by the droplet discharge method.

  Further, as shown in FIG. 19 of Embodiment 1, the organic compound layer and the first conductive layer, or the organic compound layer and the second conductive layer, or both the first conductive layer and the second conductive layer, and the organic compound. An insulating layer may be provided between each of the layers. By providing the insulating layer, characteristics such as a writing voltage of the memory element are stabilized without variation, and normal writing can be performed in each element.

  In the above structure of this embodiment, the first conductive layers 751a to 751c, the first conductive layers 761a to 761c, the first conductive layers 771a to 771c, the first conductive layers 791a to 791c, and the organic compound A rectifying element may be provided between the layer 752, the organic compound layer 762, the organic compound layer 772, and the organic compound layer 792. The element having a rectifying property is a transistor or a diode in which a gate electrode and a drain electrode are connected. In this way, by providing a rectifying diode, current flows only in one direction, so that errors are reduced and reading reliability is improved. Note that the rectifying element includes an organic compound layer 752, an organic compound layer 762, an organic compound layer 772, an organic compound layer 792, second conductive layers 753a to 753c, second conductive layers 763a to 763c, second The conductive layers 773a to 773c and the second conductive layers 793a to 793c may be provided.

  Even when the element having the rectifying property is provided, at least one of the first and second conductive layers in contact with the organic compound layer is formed using a metal material having a low solubility parameter shown in FIG. It is necessary to have a structure in which the conductive layer is formed or a conductive layer which has been subjected to an oxidation treatment or the like on the surface of the conductive layer shown in FIG.

  According to the present invention, a semiconductor device having a memory element with good adhesion inside a memory element that can perform a transposition process in a favorable state can be manufactured. Therefore, a highly reliable semiconductor device can be manufactured with high yield without complicating the device and the process.

(Embodiment 3)
In this embodiment mode, a semiconductor device having a structure different from that of Embodiment Mode 2 will be described. Specifically, the case where the structure of the semiconductor device is an active matrix type is described. The memory element in this embodiment can be manufactured using the same material and structure as those in Embodiment 1. Therefore, detailed description of materials and the like is omitted.

  FIG. 5 illustrates a structural example of the semiconductor device described in this embodiment. The semiconductor device includes a memory cell array 232 in which memory cells 231 are provided in a matrix, a circuit 226, a decoder 224, and a decoder 223. The circuit 226 includes a reading circuit and a writing circuit. Note that the structure of the semiconductor device 217 shown here is merely an example, and other circuits such as a sense amplifier, an output circuit, and a buffer may be included, and a writing circuit may be provided in the bit line driver circuit.

  The memory cell 231 includes a first conductive layer connected to the bit line Bx (1 ≦ x ≦ m), a second conductive layer connected to the word line Wy (1 ≦ y ≦ n), a transistor 210a, and a memory An element 215b and a memory cell 231 are included. The memory element 215b has a structure in which an organic compound layer is sandwiched between a pair of conductive layers. The gate electrode of the transistor is connected to the word line, either the source electrode or the drain electrode is connected to the bit line, and the other is connected to one of the two terminals of the memory element. The remaining one terminal of the memory element is connected to a common electrode (potential Vcom).

  4A is a top view of the memory cell array 232, and FIG. 4B is a cross-sectional view taken along line EF in FIG. 4A. In FIG. 4A, the insulating layer 216, the organic compound layer 212, the second conductive layer 213, and the insulating layer 214 are omitted and not shown, but are provided as shown in FIG. 4B. ing.

  The memory cell array 232 includes a first wiring 205a and a first wiring 205b extending in a first direction and a second wiring 202 extending in a second direction perpendicular to the first direction in a matrix. It has been. The first wiring is connected to the source electrode or the drain electrode of the transistors 210a and 210b, and the second wiring is connected to the gate electrodes of the transistors 210a and 210b. Further, the first conductive layer 206a and the first conductive layer 206b are connected to the source electrode or the drain electrode of the transistor 210a and the transistor 210b which are not connected to the first wiring, respectively. A memory element 215a and a memory element 215b are provided by a stacked structure of the first conductive layer 206b, the organic compound layer 212, and the second conductive layer 213. A partition wall (insulating layer) 207 is provided between adjacent memory cells 231, and an organic compound layer 212 and a second conductive layer 213 are stacked over the first conductive layer and the partition wall (insulating layer) 207. ing. An insulating layer 214 serving as a protective layer is provided over the second conductive layer 213. Thin film transistors are used as the transistors 210a and 210b (see FIG. 4B).

  The region where the first conductive layer 206a and the first conductive layer 206b are stacked with the organic compound layer 212 is subjected to a treatment for reducing the interfacial tension, so that a treatment region 203a and a treatment region 203b are formed.

Examples of the treatment for reducing the interfacial tension include exposing the conductive layer to an oxygen atmosphere, and irradiating ultraviolet light in an oxygen atmosphere to generate ozone (O ₃ ) to oxidize the surface of the conductive layer. Alternatively, oxygen plasma may be contacted, or the conductive layer may be oxidized by an organic compound material contained in the organic compound at the layer interface. Alternatively, the conductive layer may be formed in an oxygen atmosphere. In addition to the oxidation treatment, nitridation treatment may be performed. For example, the nitridation treatment may be performed and then the oxidation treatment may be performed.

  A treatment region 203a that reduces the interfacial tension at the interface (surface) in contact with the organic compound layer 212 of the first conductive layer 206a and the interface (surface) in contact with the first conductive layer 206b and the organic compound layer 212; By forming the treatment region 203b, adhesion between the first conductive layer 206a and the first conductive layer 206b and the organic compound layer 212 can be improved.

  As the metal material used for the second conductive layer 213, one or more of indium (In), tin (Sn), lead (Pb), bismuth (Bi), calcium (Ca), antimony (Sb), and zinc (Zn) Use seeds. In addition, one or more of magnesium (Mg), manganese (Mn), cadmium (Cd), thallium (Tl), tellurium (Te), and barium (Ba) are used. A plurality of the metal materials may be included, or an alloy including one or more of the materials may be used. In particular, indium (In), tin (Sn), lead (Pb), bismuth (Bi), calcium (Ca), manganese (Mn), zinc (Zn), or a metal having a relatively low solubility parameter is included. Alloys are preferred as electrode materials. Examples of alloys that can be used include indium tin alloys (InSn), magnesium indium alloys (InMg), phosphorus indium alloys (InP), arsenic indium alloys (InAs), and chromium indium alloys (InCr).

  By using the material having a small solubility parameter for the second conductive layer 213, adhesion between the second conductive layer 213 and the organic compound layer 212 can be improved. Therefore, defects such as film peeling at the layer interface are less likely to occur due to the force applied in the process of being transferred to the second substrate after being formed on the first substrate. Even when a glass substrate that can withstand manufacturing conditions such as temperature is used in the element manufacturing process, a flexible substrate such as a film can be used for the substrate 200 by being transferred to the second substrate after that. Therefore, the memory element can be peeled and transferred with a favorable shape, so that a semiconductor device can be manufactured.

  Needless to say, in the semiconductor device shown in FIG. 4, the first conductive layer and the second conductive layer are formed in the same manner as in FIGS. 1A, 1B, 16A, and 16B. May be used. A conductive layer containing a metal material having a low solubility parameter is used for at least one of the first conductive layer and the second conductive layer, or at least one organic compound layer of the first conductive layer and the second conductive layer An oxidation treatment or the like that lowers the interfacial tension may be applied to the interface. As shown in FIG. 16A, both the first conductive layer and the second conductive layer may be formed using a metal material having a low solubility parameter, as shown in FIG. A configuration may be employed in which regions having low surface tension are formed at both interfaces between the organic compound layer and the first conductive layer and the second conductive layer.

  Since the semiconductor device including the memory element manufactured in this embodiment has favorable adhesion inside the memory element, the separation and transfer process can be performed in a favorable state. Therefore, since it can be freely transferred to various substrates, the range of substrate material selectivity is widened. In addition, an inexpensive material can be selected as the substrate, so that not only a wide function can be provided depending on the application, but also a semiconductor device can be manufactured at low cost.

  The semiconductor device in FIG. 4B is provided over a substrate 200, and includes an insulating layer 201a, an insulating layer 201b, an insulating layer 208, an insulating layer 209, an insulating layer 211, a semiconductor layer 204a included in the transistor 210a, and a gate electrode layer. 202a, a wiring 205a also serving as a source electrode layer or a drain electrode layer, a semiconductor layer 204b included in the transistor 210b, and a gate electrode layer 202b.

  Further, as shown in FIG. 19 of Embodiment 1, the organic compound layer and the first conductive layer, or the organic compound layer and the second conductive layer, or both the first conductive layer and the second conductive layer, and the organic compound. An insulating layer may be provided between each of the layers. By providing the insulating layer, characteristics such as a writing voltage of the memory element are stabilized without variation, and normal writing can be performed in each element.

  An interlayer insulating layer may be provided over the transistors 210a and 210b. In the structure of FIG. 4B, the storage element 215a and the storage element 215b need to be provided in a region avoiding the source electrode layer or the drain electrode layer of the transistor 210a and the transistor 210b, but by providing an interlayer insulating layer, For example, the memory element 215a and the memory element 215b can be formed above the transistors 210a and 210b. As a result, the semiconductor device 217 can be more highly integrated.

  The transistors 210a and 210b may have any structure as long as they can function as switching elements. As the semiconductor layer, various semiconductors such as an amorphous semiconductor, a crystalline semiconductor, a polycrystalline semiconductor, and a microcrystalline semiconductor can be used, and an organic transistor may be formed using an organic compound. FIG. 4B illustrates an example in which a planar thin film transistor is provided over an insulating substrate; however, a transistor can be formed with a staggered structure, an inverted staggered structure, or the like.

  FIG. 7 shows an example using a thin film transistor having an inverted staggered structure. Over the substrate 280, transistors 290a and 290b which are thin film transistors having an inverted staggered structure are provided. The transistor 290a includes an insulating layer 288, a gate electrode layer 281, an amorphous semiconductor layer 282, a semiconductor layer 283a having one conductivity type, a semiconductor layer 283b having one conductivity type, a source or drain electrode layer 285, The source electrode layer or the drain electrode layer is the first conductive layer 286 that forms the memory element. A partition wall (insulating layer) 287 is stacked so as to cover end portions of the first conductive layer 286a and the first conductive layer 286b, and the first conductive layer 286a, the first conductive layer 286b, and the partition wall (insulating layer) 287 are stacked. An organic compound layer 292, a second conductive layer 293, and an insulating layer 294 which is a protective layer are formed over the storage layer 295a and the storage element 295b.

  A region where the organic compound layer 292 of the first conductive layer 286a and the first conductive layer 286b is stacked is subjected to a treatment for reducing interfacial tension, so that a treatment region 296a and a treatment region 296b are formed.

Examples of the treatment for reducing the interfacial tension include exposing the conductive layer to an oxygen atmosphere, and irradiating ultraviolet light in an oxygen atmosphere to generate ozone (O ₃ ) to oxidize the surface of the conductive layer. Alternatively, oxygen plasma may be contacted, or the conductive layer may be oxidized by an organic compound material contained in the organic compound at the layer interface. Alternatively, the conductive layer may be formed in an oxygen atmosphere. In addition to the oxidation treatment, nitridation treatment may be performed. For example, the nitridation treatment may be performed and then the oxidation treatment may be performed.

  A treatment region 296a for reducing interfacial tension at the interface (surface) in contact with the organic compound layer 292 of the first conductive layer 286a and the interface (surface) in contact with the first conductive layer 286b and the organic compound layer 292; By forming the treatment region 296b, adhesion between the first conductive layer 286a and the first conductive layer 286b and the organic compound layer 292 can be improved.

  As the metal material used for the second conductive layer 293, one or more of indium (In), tin (Sn), lead (Pb), bismuth (Bi), calcium (Ca), antimony (Sb), and zinc (Zn) Use seeds. In addition, one or more of magnesium (Mg), manganese (Mn), cadmium (Cd), thallium (Tl), tellurium (Te), and barium (Ba) are used. A plurality of the metal materials may be included, or an alloy including one or more of the materials may be used. In particular, indium (In), tin (Sn), lead (Pb), bismuth (Bi), calcium (Ca), manganese (Mn), zinc (Zn), or a metal having a relatively low solubility parameter is included. Alloys are preferred as electrode materials. Examples of alloys that can be used include indium tin alloys (InSn), magnesium indium alloys (InMg), phosphorus indium alloys (InP), arsenic indium alloys (InAs), and chromium indium alloys (InCr).

  By using the material having a low solubility parameter for the second conductive layer 293, adhesion between the second conductive layer 293 and the organic compound layer 292 can be improved. Therefore, defects such as film peeling at the layer interface are less likely to occur due to the force applied in the process of being transferred to the second substrate after being formed on the first substrate. Even when a glass substrate that can withstand manufacturing conditions such as temperature is used in the element manufacturing process, a flexible substrate such as a film can be used for the substrate 280 by being subsequently transferred to the second substrate. Therefore, the memory element can be peeled and transferred with a favorable shape, so that a semiconductor device can be manufactured.

  In the semiconductor device illustrated in FIG. 7, the gate electrode layer 281, the source or drain electrode layer 285, the first conductive layer 286a, the first conductive layer 286b, and the partition wall (insulating layer) 287 are formed by a droplet discharge method. It may be formed. The droplet discharge method is a method in which a composition containing a composition forming material that is a fluid is discharged (jetted) as droplets to form a desired pattern shape. A droplet containing a component forming material is discharged onto a region where the component is to be formed, and fixed by firing, drying, or the like to form a component having a desired pattern.

    In the case of forming a conductive layer by using a droplet discharge method, a conductive layer is formed by discharging a composition containing a conductive material processed into a particulate form and fusing or fusion-bonding and solidifying by firing. In such a conductive layer (or insulating layer) formed by discharging and baking a composition containing a conductive material, the conductive layer (or insulating layer) formed by sputtering or the like is mostly a columnar structure. In many cases, a polycrystalline state having many grain boundaries is exhibited.

  Further, any structure of a semiconductor layer included in the transistor may be used. For example, an impurity region (including a source region, a drain region, and an LDD region) may be formed, or a p-channel type or an n-channel may be formed. You may form with either type | mold. Further, an insulating layer (side wall) may be formed so as to be in contact with the side surface of the gate electrode, or a silicide layer may be formed on one or both of the source region, the drain region, and the gate electrode. As a material for the silicide layer, nickel, tungsten, molybdenum, cobalt, platinum, or the like can be used.

  The materials and formation methods of the first conductive layers 206a, 206b, 286a, and 286b and the second conductive layers 213, 263, and 293 shown in this embodiment mode are the same as the materials and formation methods described in Embodiment Mode 1. It can carry out similarly using either.

  Further, the organic compound layers 212 and 292 can be provided using a material and a formation method similar to those of the organic compound layer described in Embodiment Mode 1.

  Further, a rectifying element may be provided between the first conductive layers 206a, 206b, 286a, and 286b and the organic compound layers 212 and 292. The element having a rectifying property is a transistor or a diode in which a gate electrode and a drain electrode are connected. For example, a PN junction diode provided by stacking an N-type semiconductor layer and a P-type semiconductor layer can be used. In this way, by providing a rectifying diode, current flows only in one direction, so that errors are reduced and reading reliability is improved. Note that when a diode is provided, a diode having another structure such as a diode having a PIN junction or an avalanche diode may be used instead of a diode having a PN junction. Note that the organic compound layers 212 and 292 may be provided between the second conductive layers 213 and 293.

  Even when the element having the rectifying property is provided, at least one of the first and second conductive layers in contact with the organic compound layer is formed using a metal material having a low solubility parameter shown in FIG. It is necessary to have a structure in which the conductive layer is formed or a conductive layer which has been subjected to an oxidation treatment or the like on the surface of the conductive layer shown in FIG.

  According to the present invention, a semiconductor device having a memory element with good adhesion inside a memory element that can perform a transposition process in a favorable state can be manufactured. Therefore, a highly reliable semiconductor device can be manufactured with high yield without complicating the device and the process.

(Embodiment 4)
In this embodiment, a method for manufacturing a semiconductor device will be described with reference to FIGS. The memory element in this embodiment can be manufactured using the same material and structure as those in Embodiment 1. Therefore, detailed description of materials and the like is omitted.

  As shown in FIG. 8, a peeling layer 268 and an insulating layer 251 are formed over the substrate 250. A transistor 260 a and a transistor 260 b are formed over the insulating layer 251. The transistors 260a and 260b in FIGS. 8A and 8B are top-gate planar thin film transistors and have a sidewall at the end portion of the gate electrode layer; however, the present invention is not limited to this structure. An insulating layer 269 and an insulating layer 261 are stacked over the transistor 260a and the transistor 260b. The insulating layer 269 and the insulating layer 261 are provided with openings reaching impurity regions which serve as a source region or a drain region in the semiconductor layers of the transistors 260a and 260b. The openings have a wiring layer 255a, a wiring layer 255b, and a wiring, respectively. A layer 255c and a wiring layer 255d are formed.

  An insulating layer 270 is formed over the wiring layer 255a, the wiring layer 255b, the wiring layer 255c, and the wiring layer 255d, and openings that reach the wiring layer 255a and the wiring layer 255c are provided in the insulating layer 270. A first conductive layer 256a and a first conductive layer 256b are formed in the opening, and are electrically connected to the transistor 260a and the transistor 260b through the wiring layer 255a and the wiring layer 255b, respectively.

  A partition wall (insulating layer) 267 having openings over the first conductive layer 256a and the first conductive layer 256b and covering end portions of the first conductive layer 256a and the first conductive layer 256b is formed. An organic compound layer 262a is stacked over the first conductive layer 256a, and an organic compound layer 262b is stacked over the first conductive layer 256b. The organic compound layer 262a, the organic compound layer 262b, and the partition wall (insulating layer) 267 are stacked. A second conductive layer 263 is formed (see FIG. 8A). As described above, the memory element 265a including the first conductive layer 256a, the organic compound layer 262a, and the second conductive layer 263, the memory element including the first conductive layer 256b, the organic compound layer 262b, and the second conductive layer 263. 265b is provided on the substrate 250.

The substrate 250 is a glass substrate made of barium borosilicate glass, alumino borosilicate glass, or the like, a quartz substrate, a metal substrate or a stainless steel substrate with an insulating layer formed thereon, or can withstand the processing temperature of this embodiment manufacturing process. A plastic substrate having high heat resistance is used. Further, polishing may be performed by a CMP method or the like so that the surface of the substrate 250 is planarized.

  The release layer 268 is formed by sputtering, plasma CVD, coating, printing, or the like using tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), niobium (Nb), nickel (Ni), An element selected from cobalt (Co), zirconium (Zr), zinc (Zn), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), silicon (Si), Alternatively, an alloy material containing an element as a main component or a layer made of a compound material containing the element as a main component is formed as a single layer or a stacked layer. The crystal structure of the layer containing silicon may be any of amorphous, microcrystalline, and polycrystalline. Here, the coating method includes a spin coating method, a droplet discharge method, and a dispensing method.

  In the case where the separation layer 268 has a single-layer structure, a tungsten layer, a molybdenum layer, or a layer containing a mixture of tungsten and molybdenum is preferably formed. Alternatively, a layer containing tungsten oxide or oxynitride, a layer containing molybdenum oxide or oxynitride, or a layer containing an oxide or oxynitride of a mixture of tungsten and molybdenum is formed. Note that the mixture of tungsten and molybdenum corresponds to, for example, an alloy of tungsten and molybdenum.

  In the case where the separation layer 268 has a stacked structure, preferably, a tungsten layer, a molybdenum layer, or a layer containing a mixture of tungsten and molybdenum is formed as the first layer, and tungsten, molybdenum, or a mixture of tungsten and molybdenum is formed as the second layer. An oxide, nitride, oxynitride, or nitride oxide is formed.

  In the case where a layered structure of a layer containing tungsten and a layer containing an oxide of tungsten is formed as the separation layer 268, a layer containing tungsten is formed, and an insulating layer formed of an oxide is formed thereover. The fact that a layer containing an oxide of tungsten is formed at the interface between the tungsten layer and the insulating layer may be utilized. Further, the layer containing tungsten oxide may be formed by performing thermal oxidation treatment, oxygen plasma treatment, treatment with a strong oxidizing power such as ozone water, or the like on the surface of the layer containing tungsten. The plasma treatment and the heat treatment may be performed in an atmosphere of oxygen, nitrogen, dinitrogen monoxide, dinitrogen monoxide alone, or a mixed gas atmosphere of the above gas and other gas. The same applies to the case where a layer containing tungsten nitride, oxynitride, and nitride oxide is formed. After a layer containing tungsten is formed, a silicon nitride layer, a silicon oxynitride layer, and a silicon nitride oxide layer are formed thereon. A layer may be formed.

The oxide of tungsten is represented by WOx. X is in the range of 2 to 3, when x is 2 (WO ₂ ), x is 2.5 (W ₂ O ₅ ), x is 2.75 (W ₄ O ₁₁ ), x Is 3 (WO ₃ ).

  Further, according to the above process, the release layer 268 is formed so as to be in contact with the substrate 250, but the present invention is not limited to this process. An insulating layer serving as a base may be formed so as to be in contact with the substrate 250, and the peeling layer 268 may be provided so as to be in contact with the insulating layer.

  The insulating layer 251 is formed as a single layer or a stack using an inorganic compound by a sputtering method, a plasma CVD method, a coating method, a printing method, or the like. As a typical example of the inorganic compound, silicon oxide or silicon nitride can be given. Typical examples of silicon oxide include silicon oxide, silicon oxynitride, silicon nitride oxide, and the like. Typical examples of silicon nitride include silicon nitride, silicon oxynitride, silicon nitride oxide, and the like.

  Furthermore, the insulating layer 251 may have a stacked structure. For example, the layers may be stacked using an inorganic compound, and typically, silicon oxide, silicon nitride oxide, and silicon oxynitride may be stacked.

  A material for forming a semiconductor layer included in the transistor 260a and the transistor 260b is an amorphous semiconductor (hereinafter also referred to as “AS”) manufactured by a vapor deposition method or a sputtering method using a semiconductor material gas typified by silane or germane. A polycrystalline semiconductor obtained by crystallizing the amorphous semiconductor using light energy or thermal energy, or a semi-amorphous (also referred to as microcrystal or microcrystal; hereinafter also referred to as “SAS”) semiconductor can be used. . The semiconductor layer can be formed by a known means (such as sputtering, LPCVD, or plasma CVD).

SAS is a semiconductor having an intermediate structure between amorphous and crystalline structures (including single crystal and polycrystal) and having a third state that is stable in terms of free energy and has a short-range order and a lattice. It includes a crystalline region with strain. SAS is formed by glow discharge decomposition (plasma CVD) of a gas containing silicon. As a gas containing silicon, SiH ₄ , Si ₂ H ₆ , SiH ₂ Cl ₂ , SiHCl ₃ , SiCl ₄ , SiF _4, or the like can be used. Further, F ₂ and GeF ₄ may be mixed in the gas containing silicon. The gas containing silicon may be diluted with H ₂ , or H ₂ and one or more kinds of rare gas elements selected from He, Ar, Kr, and Ne. In addition, a SAS layer formed of a hydrogen-based gas may be stacked on a SAS layer formed of a fluorine-based gas as a semiconductor layer.

    A typical example of an amorphous semiconductor is hydrogenated amorphous silicon, and a typical example of a crystalline semiconductor is polysilicon. Polysilicon (polycrystalline silicon) is mainly made of so-called high-temperature polysilicon using polysilicon formed through a process temperature of 800 ° C. or higher as a main material, or polysilicon formed at a process temperature of 600 ° C. or lower. And so-called low-temperature polysilicon, and polysilicon crystallized by adding an element that promotes crystallization. Of course, as described above, a semi-amorphous semiconductor or a semiconductor including a crystal phase in a part of the semiconductor layer can also be used.

As a semiconductor material, a compound semiconductor such as GaAs, InP, SiC, ZnSe, GaN, or SiGe can be used in addition to a simple substance such as silicon (Si) or germanium (Ge). Alternatively, zinc oxide (ZnO), tin oxide (SnO ₂ ), or the like which is an oxide semiconductor can be used. When ZnO is used for the semiconductor layer, the gate insulating layer is formed of Y ₂ O ₃ , Al ₂ O ₃ , TiO ₂ , A stacked layer of them is preferably used, and ITO, Au, Ti, or the like is preferably used for the gate electrode layer, the source electrode layer, and the drain electrode layer. In addition, In, Ga, or the like can be added to ZnO.

In the case where a crystalline semiconductor layer is used for the semiconductor layer, a method for manufacturing the crystalline semiconductor layer can be a known method (laser crystallization method, thermal crystallization method, or heat using an element that promotes crystallization such as nickel. A crystallization method or the like may be used. In addition, a microcrystalline semiconductor that is a SAS can be crystallized by laser irradiation to improve crystallinity. In the case where an element for promoting crystallization is not introduced, the amorphous silicon film is heated at 500 ° C. for 1 hour in a nitrogen atmosphere before irradiating the amorphous silicon film with laser light, whereby the concentration of hydrogen contained in the amorphous silicon film is set to 1 ×. Release to 10 ²⁰ atoms / cm ³ or less. This is because the film is destroyed when the amorphous silicon film containing a large amount of hydrogen is irradiated with laser light.

The method of introducing the metal element into the amorphous semiconductor layer is not particularly limited as long as the metal element can be present on the surface of the amorphous semiconductor layer or inside the amorphous semiconductor layer. For example, sputtering, CVD, A plasma treatment method (including a plasma CVD method), an adsorption method, or a method of applying a metal salt solution can be used. Among these, the method using a solution is simple and useful in that the concentration of the metal element can be easily adjusted. At this time, in order to improve the wettability of the surface of the amorphous semiconductor layer and to spread the aqueous solution over the entire surface of the amorphous semiconductor layer, irradiation with UV light in an oxygen atmosphere, thermal oxidation method, hydroxy radical It is desirable to form an oxide film by treatment with ozone water or hydrogen peroxide.

Further, in the crystallization step of crystallizing the amorphous semiconductor layer to form the crystalline semiconductor layer, an element for promoting crystallization (also referred to as a catalyst element or a metal element) is added to the amorphous semiconductor layer, and heat treatment ( Crystallization may be carried out at 550 ° C. to 750 ° C. for 3 minutes to 24 hours. As elements for promoting crystallization, metal elements for promoting crystallization of silicon include iron (Fe), nickel (Ni), cobalt (Co), ruthenium (Ru), rhodium (Rh), palladium (Pd). One or a plurality of types selected from osmium (Os), iridium (Ir), platinum (Pt), copper (Cu), and gold (Au) can be used.

In order to remove or reduce an element that promotes crystallization from the crystalline semiconductor layer, a semiconductor layer containing an impurity element is formed in contact with the crystalline semiconductor layer and functions as a gettering sink. As the impurity element, an impurity element imparting n-type conductivity, an impurity element imparting p-type conductivity, a rare gas element, or the like can be used. For example, phosphorus (P), nitrogen (N), arsenic (As), antimony (Sb ), Bismuth (Bi), boron (B), helium (He), neon (Ne), argon (Ar), Kr (krypton), and Xe (xenon) can be used. A semiconductor layer containing a rare gas element is formed over the crystalline semiconductor layer containing an element that promotes crystallization, and heat treatment (at 550 ° C. to 750 ° C. for 3 minutes to 24 hours) is performed. The element that promotes crystallization contained in the crystalline semiconductor layer moves into the semiconductor layer containing a rare gas element, and the element that promotes crystallization in the crystalline semiconductor layer is removed or reduced. After that, the semiconductor layer containing a rare gas element that has become a gettering sink is removed.

The crystallization of the amorphous semiconductor layer may be a combination of heat treatment and crystallization by laser light irradiation, or may be performed multiple times by heat treatment or laser light irradiation alone.

Alternatively, the crystalline semiconductor layer may be directly formed over the substrate by a plasma method. Alternatively, the crystalline semiconductor layer may be selectively formed over the substrate by a plasma method.

As a semiconductor, an organic semiconductor material can be used and formed by a printing method, a spray method, a spin coating method, a droplet discharge method, or the like. In this case, the number of processes can be reduced because the etching process is not necessary. As the organic semiconductor, a low molecular material, a polymer material, or the like is used, and materials such as an organic dye or a conductive polymer material can also be used. As the organic semiconductor material, a π-electron conjugated polymer material whose skeleton is composed of conjugated double bonds is desirable. Typically, a soluble polymer material such as polythiophene, polyfluorene, poly (3-alkylthiophene), a polythiophene derivative, or pentacene can be used.

In addition, as an organic semiconductor material that can be used in the present invention, there is a material that can form a semiconductor layer by processing after forming a soluble precursor. Examples of such an organic semiconductor material include polythienylene vinylene, poly (2,5-thienylene vinylene), polyacetylene, a polyacetylene derivative, and polyarylene vinylene.

When converting the precursor into an organic semiconductor, a reaction catalyst such as hydrogen chloride gas is added as well as heat treatment. Typical solvents for dissolving these soluble organic semiconductor materials include toluene, xylene, chlorobenzene, dichlorobenzene, anisole, chloroform, dichloromethane, γ-butyllactone, butyl cellosolve, cyclohexane, NMP (N-methyl-2) -Pyrrolidone), cyclohexanone, 2-butanone, dioxane, dimethylformamide (DMF), THF (tetrahydrofuran), or the like can be applied.

  The gate electrode layer can be formed by a CVD method, a sputtering method, a droplet discharge method, or the like. The gate electrode layer is an element selected from Ag, Au, Cu, Ni, Pt, Pd, Ir, Rh, W, Al, Ta, Mo, Cd, Zn, Fe, Ti, Si, Ge, Zr, Ba, Alternatively, an alloy material or a compound material containing the element as a main component may be used. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus, or an AgPdCu alloy may be used. Alternatively, a single-layer structure or a multi-layer structure may be employed, for example, a two-layer structure of a tungsten nitride film and a molybdenum film, a tungsten film with a thickness of 50 nm, an alloy of aluminum and silicon with a thickness of 500 nm (Al- A three-layer structure in which a Si) film and a titanium nitride film with a thickness of 30 nm are sequentially stacked may be employed. In the case of a three-layer structure, tungsten nitride may be used instead of tungsten of the first conductive film, or aluminum instead of the aluminum and silicon alloy (Al-Si) film of the second conductive film. A titanium alloy film (Al—Ti) may be used, or a titanium film may be used instead of the titanium nitride film of the third conductive film.

A light-transmitting material having a light-transmitting property with respect to visible light can also be used for the gate electrode layer. As the light-transmitting conductive material, indium tin oxide (ITO), indium tin oxide containing silicon oxide (ITSO), organic indium, organic tin, zinc oxide, or the like can be used. Further, indium zinc oxide (IZO) containing zinc oxide (ZnO), zinc oxide (ZnO), ZnO doped with gallium (Ga), tin oxide (SnO ₂ ), tungsten oxide is included. Indium oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, or the like may also be used.

In the case where processing is required by etching to form the gate electrode layer, a mask may be formed and processed by dry etching or dry etching. Using an ICP (Inductively Coupled Plasma) etching method, the etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the substrate-side electrode, the electrode temperature on the substrate side, etc.) are appropriately set. By adjusting, the electrode layer can be etched into a tapered shape. As an etching gas, a chlorine-based gas typified by Cl ₂ , BCl ₃ , SiCl _4, CCl _4, etc., a fluorine-based gas typified by CF ₄ , SF _6, NF _3, etc., or O ₂ is appropriately used. be able to.

Although the single gate structure is described in this embodiment mode, a multi-gate structure such as a double gate structure may be used. In this case, a gate electrode layer may be provided above and below the semiconductor layer, or a plurality of gate electrode layers may be provided only on one side (above or below) of the semiconductor layer. The semiconductor layer may have impurity regions with different concentrations. For example, the vicinity of the channel region of the semiconductor layer and the region stacked with the gate electrode layer may be a low concentration impurity region, and the region outside the channel region may be a high concentration impurity region.

  The wiring layer 255a, the wiring layer 255b, the wiring layer 255c, and the wiring layer 255d can be formed by forming a conductive film by a PVD method, a CVD method, an evaporation method, or the like, and then etching into a desired shape. Further, the source electrode layer or the drain electrode layer can be selectively formed at a predetermined place by a printing method, an electroplating method, or the like. Furthermore, a reflow method or a damascene method may be used. The source electrode layer or drain electrode layer is made of Ag, Au, Cu, Ni, Pt, Pd, Ir, Rh, W, Al, Ta, Mo, Cd, Zn, Fe, Ti, Zr, Ba or other metals, A semiconductor such as Si or Ge, an alloy thereof, or a nitride thereof may be used. A light-transmitting material can also be used.

Further, in the case of a light-transmitting conductive material, indium tin oxide (ITO), indium tin oxide containing silicon oxide (ITSO), indium zinc oxide containing zinc oxide (ZnO) (IZO (indium zinc oxide) )), Zinc oxide (ZnO), ZnO doped with gallium (Ga), tin oxide (SnO ₂ ), indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide Indium tin oxide containing titanium oxide or the like can be used.

  The insulating layer 261, the insulating layer 270, and the partition wall (insulating layer) 267 are formed using silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, or other inorganic insulating materials, or acrylic acid, methacrylic acid, and the like. Or heat-resistant polymers such as polyimide, aromatic polyamide, polybenzimidazole, vinyl resins such as polyvinyl alcohol and polyvinyl butyral, epoxy resins, phenol resins, novolac resins, acrylic resins, A resin material such as a melamine resin, a urethane resin, or a siloxane resin may be used. Acrylic, polyimide, or the like may be formed using either a photosensitive material or a non-photosensitive material. In particular, the partition wall (insulating layer) 267 preferably has a shape in which the radius of curvature continuously changes, and the coverage of the organic compound layer 262a, the organic compound layer 262b, and the second conductive layer 263 formed thereon is improved. Insulating layers include CVD, plasma CVD, sputtering, spin coating, droplet discharge, printing (screen printing, offset printing, relief printing, gravure (intaglio) printing, etc.), spin coating, etc. It can be formed using a coating method, a dipping method, or the like.

  In this embodiment, as a metal material used for the first conductive layer 256a, the first conductive layer 256b, and the second conductive layer 263, indium (In), tin (Sn), lead (Pb), bismuth ( Bi), calcium (Ca), antimony (Sb), or one or more of zinc (Zn) are used. In addition, one or more of magnesium (Mg), manganese (Mn), cadmium (Cd), thallium (Tl), tellurium (Te), and barium (Ba) are used. A plurality of the metal materials may be included, or an alloy including one or more of the materials may be used. In particular, indium (In), tin (Sn), lead (Pb), bismuth (Bi), calcium (Ca), manganese (Mn), zinc (Zn), or a metal having a relatively low solubility parameter is included. Alloys are preferred as electrode materials. Examples of alloys that can be used include indium tin alloys (InSn), magnesium indium alloys (InMg), phosphorus indium alloys (InP), arsenic indium alloys (InAs), and chromium indium alloys (InCr).

  Of course, the first conductive layer and the second conductive layer shown in FIGS. 8 and 9 are formed in the same manner as in FIGS. 1A, 1B, and 16A to 16C. It may be used. A conductive layer containing a metal material having a low solubility parameter is used for at least one of the first conductive layer and the second conductive layer, or at least one organic compound layer of the first conductive layer and the second conductive layer An oxidation treatment or the like that lowers the interfacial tension may be applied to the interface. The first conductive layer and the second conductive layer may be formed using a metal material having a small solubility parameter as shown in FIG. 16A, and the organic compound layer as shown in FIG. A region having a low surface tension may be formed at both interfaces between the first conductive layer and the second conductive layer, and the first conductive layer and the second conductive layer may be formed as shown in FIG. One of the layers may be formed using a metal material having a small solubility parameter, and a region having a low surface tension may be formed at the interface with the other organic compound layer.

  Also in this embodiment (the semiconductor device shown in FIGS. 8 and 9), as shown in FIG. 19 of Embodiment 1, the organic compound layer and the first conductive layer, or the organic compound layer and the second conductive layer are used. An insulating layer may be provided between each of the layers, or both the first conductive layer and the second conductive layer, and the organic compound layer. By providing the insulating layer, characteristics such as a writing voltage of the memory element are stabilized without variation, and normal writing can be performed in each element.

  The organic compound layer 262a and the organic compound layer 262b may be formed using the same material as the organic compound layer 57, the organic compound layer 67, and the organic compound layer 77 in FIG.

Next, as illustrated in FIG. 8B, the insulating layer 264 is formed over the second conductive layer 263. Next, the substrate 266 is attached to the surface of the insulating layer 264.

  The insulating layer 264 is preferably formed by applying the composition using a coating method and then drying and heating. Such an insulating layer 264 is preferably an insulating layer with less surface unevenness because it is provided as a protective layer in a subsequent peeling step. Such an insulating layer can be formed by a coating method. Alternatively, the insulating layer 264 may be formed by a thin film formation method such as a CVD method or a sputtering method, and then the surface is polished by a CMP method. The insulating layer 264 formed using a coating method is an acrylic resin, polyimide resin, melamine resin, polyester resin, polycarbonate resin, phenol resin, epoxy resin, polyacetal, polyether, polyurethane, polyamide (nylon), furan resin, diallyl Organic compounds such as phthalate resins, inorganic siloxane polymers containing Si-O-Si bonds, or alkylsiloxane polymers among compounds consisting of silicon, oxygen, and hydrogen formed from siloxane polymer materials typified by silica glass , Alkyl silsesquioxane polymer, hydrogenated silsesquioxane polymer, organic siloxax in which hydrogen bonded to silicon represented by hydrogenated alkyl silsesquioxane polymer is substituted with an organic group such as methyl or phenyl It is formed of a polymer. The insulating layer formed by forming the insulating film by the above-described thin film forming method and then polishing the surface by the CMP method is formed of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or the like. Alternatively, the insulating layer 264 is not formed, and the substrate 266 may be directly attached to the second conductive layer 263.

  As the substrate 266, a flexible substrate is preferably used, and a thin and light substrate is preferable. Typically, it consists of PET (polyethylene terephthalate), PEN (polyethylene naphthalate), PES (polyethersulfone), polypropylene, polypropylene sulfide, polycarbonate, polyetherimide, polyphenylene sulfide, polyphenylene oxide, polysulfone, polyphthalamide, etc. A substrate can be used. Also, paper made of a fibrous material, a laminated film of a base film (polyester, polyamide, inorganic vapor deposition film, paper, etc.) and an adhesive organic resin film (acrylic organic resin, epoxy organic resin, etc.) are used. You can also. In the case where the above substrate is used, although not illustrated, an adhesive layer may be provided between the insulating layer 264 and the substrate 266 and the insulating layer 264 and the substrate 266 may be attached to each other.

  Further, as the substrate 266, a film (made of polypropylene, polyester, vinyl, polyvinyl fluoride, vinyl chloride, or the like) having an adhesive layer that adheres to an object to be processed by thermocompression bonding may be used. Such a film is obtained by dissolving the adhesive layer provided on the outermost surface or the layer provided on the outermost layer (not the adhesive layer) by heat treatment and adhering it by pressurization. It is possible to adhere. In this case, it is not necessary to provide an adhesive layer between the insulating layer 264 and the substrate 266.

  Here, the insulating layer 264 is formed using an epoxy resin by applying a composition by a coating method, drying and baking the composition. Next, a film is thermocompression bonded to the surface of the insulating layer 264 so that the substrate 266 is attached to the insulating layer 264.

  Next, as illustrated in FIG. 9A, the separation between the separation layer 268 and the insulating layer 251 is separated. In this manner, the element formation layer including the memory element and the circuit portion is separated from the substrate 250 and transferred to the insulating layer 264 and the substrate 266.

Note that in this embodiment, a peeling layer and an insulating layer are formed between the substrate and the element formation layer, a metal oxide film is provided between the peeling layer and the insulating layer, and the metal oxide film is weakened by crystallization. The method for peeling the element formation layer is used, but the method is not limited thereto. (1) An amorphous silicon film containing hydrogen is provided between a substrate having high heat resistance and an element formation layer, and the element formation layer is removed by removing the amorphous silicon film by laser light irradiation or etching. (2) A peeling layer and an insulating layer are formed between the substrate and the element formation layer, a metal oxide film is provided between the peeling layer and the insulating layer, the metal oxide film is weakened by crystallization, and then peeled off. A part of the layer is removed by etching with a solution or halogen fluoride gas such as NF ₃ , BrF ₃ , ClF ₃ , and then peeled off at the weakened metal oxide film, (3) An element type layer is formed A method of removing the substrate mechanically or removing it by etching with a solution or halogen fluoride gas such as NF ₃ , BrF ₃ , or ClF ₃ can be appropriately used. In addition, a film containing nitrogen, oxygen, hydrogen, or the like (for example, an amorphous silicon film containing hydrogen, a hydrogen-containing alloy film, an oxygen-containing alloy film, or the like) is used as the separation layer, and the separation layer is irradiated with laser light for separation. A method of releasing nitrogen, oxygen, or hydrogen contained in the layer as a gas and promoting separation between the element formation layer and the substrate may be used.

  A transposition step can be performed more easily by combining the above peeling methods. In other words, laser irradiation, etching of the release layer with gas or solution, mechanical deletion with a sharp knife or scalpel, etc. to make the release layer and the element formation layer easy to peel off, Separation can also be performed by force (by human hand or machine). Moreover, the said peeling method is an example and this invention is not limited to the said peeling method. When the present invention is applied, the element can be transposed in a good state because the element is not destroyed by the force applied in the peeling step.

  Next, as illustrated in FIG. 9B, a substrate 275 is attached to the surface of the insulating layer 251. As the substrate 275, a substrate similar to the substrate 266 can be used as appropriate. Here, the substrate 275 is attached to the insulating layer 251 by thermocompression bonding.

  Note that the element formation layer including the memory element may be transferred to the substrate 266 and then peeled off from the substrate 266 again. For example, the element formation layer is peeled from the substrate 250 which is the first substrate, transferred to the substrate 266 which is the second substrate, and then transferred to the substrate 275 which is the third substrate. 266 may be peeled off from the element formation layer.

  The memory element 265a including the first conductive layer 256a, the organic compound layer 262a, and the second conductive layer 263 described in this embodiment, the first conductive layer 256b, the organic compound layer 262b, and the second conductive layer 263 The memory element 265b having good adhesion inside the memory element has a layer interface due to the force applied in the process of being transferred to the substrate 266 which is the second substrate after being formed on the substrate 250 which is the first substrate. It is difficult to cause defects such as film peeling. Therefore, the memory element can be peeled and transferred with a favorable shape, so that a semiconductor device can be manufactured.

  Since the semiconductor device including the memory element manufactured in this embodiment has favorable adhesion inside the memory element, the separation and transfer process can be performed in a favorable state. Therefore, since it can be freely transferred to various substrates, the range of substrate material selectivity is widened. In addition, an inexpensive material can be selected as the substrate, so that not only a wide function can be provided depending on the application, but also a semiconductor device can be manufactured at low cost.

  According to the present invention, a semiconductor device having a memory element with good adhesion inside a memory element that can perform a transposition process in a favorable state can be manufactured. Therefore, a highly reliable semiconductor device can be manufactured with high yield without complicating the device and the process.

(Embodiment 5)
In this embodiment, an example of the semiconductor device described in the above embodiment will be described with reference to drawings.

  The semiconductor device described in this embodiment is characterized in that data can be read and written in a non-contact manner. A data transmission format is an electromagnetic which performs communication by mutual induction with a pair of coils arranged opposite to each other. There are roughly divided into a coupling system, an electromagnetic induction system that communicates using an induction electromagnetic field, and a radio system that communicates using radio waves, but any system may be used. In addition, there are two types of antennas used for data transmission. When one antenna is provided on a substrate on which a plurality of elements and memory elements are provided, the other is provided with a plurality of elements and memory elements. In some cases, a terminal portion is provided over the substrate, and an antenna provided over another substrate is connected to the terminal portion.

  First, a structure example of a semiconductor device in the case where an antenna is provided over a substrate provided with a plurality of elements and memory elements will be described with reference to FIGS.

  FIG. 10 illustrates a semiconductor device including an active matrix type. A transistor portion 330 including transistors 310a and 310b on a substrate 300, a transistor portion 340 including transistors 320a and 320b, insulating layers 301a, 301b, 308, and An element formation layer 335 including 311, 316, and 314 is provided, and a storage element portion 325 and a conductive layer 343 functioning as an antenna are provided above the element formation layer 335.

  Note that here, the case where the memory element portion 325 or the conductive layer 343 functioning as an antenna is provided above the element formation layer 335 is shown; however, the structure is not limited thereto, and the memory element portion 325 or the conductive layer 343 functioning as an antenna is provided. Can be provided below the element formation layer 335 or in the same layer.

  The memory element portion 325 includes memory elements 315a and 315b. The memory element 315a has a partition wall (insulating layer) 307a, a partition wall (insulating layer) 307b, an organic compound layer 312 and a second conductive layer on the first conductive layer 306a. The memory element 315b includes a partition wall (insulating layer) 307b, a partition wall (insulating layer) 307c, an insulating layer 326, an organic compound layer 312 and a second layer over the first conductive layer 306b. A conductive layer 313 is stacked. In addition, an insulating layer 314 that covers the second conductive layer 313 and functions as a protective film is formed. The first conductive layer 306a and the first conductive layer 306b in which the plurality of memory elements 315a and 315b are formed are connected to the source electrode layer or the drain electrode layer of each of the transistors 310a and 310b. That is, each memory element is connected to one transistor. Further, the organic compound layer 312 is formed over the entire surface so as to cover the first conductive layers 306a and 306b and the partition walls (insulating layers) 307a, 307b, and 307c, but may be selectively formed in each memory cell. Good. Note that the memory elements 315a and 315b can be formed using any of the materials and manufacturing methods described in the above embodiment modes.

  The region where the first conductive layer 306a and the organic compound layer 312 of the first conductive layer 306b are stacked is subjected to a treatment for reducing the interfacial tension, so that a treatment region 317a and a treatment region 317b are formed.

Examples of the treatment for reducing the interfacial tension include exposing the conductive layer to an oxygen atmosphere, and irradiating ultraviolet light in an oxygen atmosphere to generate ozone (O ₃ ) to oxidize the surface of the conductive layer. Alternatively, oxygen plasma may be contacted, or the conductive layer may be oxidized by an organic compound material contained in the organic compound at the layer interface. Alternatively, the conductive layer may be formed in an oxygen atmosphere. In addition to the oxidation treatment, nitridation treatment may be performed. For example, the nitridation treatment may be performed and then the oxidation treatment may be performed.

  A treatment region 317a that reduces interfacial tension to an interface (surface) in contact with the organic compound layer 312 of the first conductive layer 306a and an interface (surface) in contact with the first conductive layer 306b and the organic compound layer 312; By forming the treatment region 317b, adhesion between the first conductive layer 306a and the first conductive layer 306b and the organic compound layer 312 can be improved.

  As a metal material used for the second conductive layer 313, one or more of indium (In), tin (Sn), lead (Pb), bismuth (Bi), calcium (Ca), antimony (Sb), and zinc (Zn) Use seeds. In addition, one or more of magnesium (Mg), manganese (Mn), cadmium (Cd), thallium (Tl), tellurium (Te), and barium (Ba) are used. A plurality of the metal materials may be included, or an alloy including one or more of the materials may be used. In particular, indium (In), tin (Sn), lead (Pb), bismuth (Bi), calcium (Ca), manganese (Mn), zinc (Zn), or a metal having a relatively low solubility parameter is included. Alloys are preferred as electrode materials. Examples of alloys that can be used include indium tin alloys (InSn), magnesium indium alloys (InMg), phosphorus indium alloys (InP), arsenic indium alloys (InAs), and chromium indium alloys (InCr).

  By using the material having a low solubility parameter for the second conductive layer 313, adhesion between the second conductive layer 313 and the organic compound layer 312 can be improved. Therefore, defects such as film peeling at the layer interface are less likely to occur due to the force applied in the process of being transferred to the second substrate after being formed on the first substrate. Even when a glass substrate that can withstand manufacturing conditions such as temperature is used in the element manufacturing process, a flexible substrate such as a film can be used for the substrate 300 by being subsequently transferred to the second substrate. Therefore, the memory element can be peeled and transferred with a favorable shape, so that a semiconductor device can be manufactured.

  Further, in the memory element 315a, as described in the above embodiment, rectification is performed between the first conductive layer 306a and the organic compound layer 312 or between the organic compound layer 312 and the second conductive layer 313. You may provide the element which has. The above-described elements having a rectifying property can also be used. The same applies to the memory element 315b.

  Even when the element having the rectifying property is provided, at least one of the first and second conductive layers in contact with the organic compound layer is formed using a metal material having a low solubility parameter shown in FIG. It is necessary to have a structure in which the conductive layer is formed or a conductive layer which has been subjected to an oxidation treatment or the like on the surface of the conductive layer shown in FIG.

  Here, the conductive layer 343 functioning as an antenna is provided over the conductive layer 342 formed using the same layer as the second conductive layer 313. Note that a conductive layer functioning as an antenna may be formed using the same layer as the second conductive layer 313.

  As a material of the conductive layer 343 functioning as an antenna, gold (Au), platinum (Pt), nickel (Ni), tungsten (W), molybdenum (Mo), cobalt (Co), copper (Cu), aluminum (Al ), Manganese (Mn), titanium (Ti), or the like, or an alloy containing a plurality of such elements can be used. As a method for forming the conductive layer 343 functioning as an antenna, various printing methods such as vapor deposition, sputtering, CVD, screen printing, and gravure printing, a droplet discharge method, or the like can be used.

  The transistors 310a, 310b, 310c, and 310d included in the element formation layer 335 can be provided using a p-channel TFT, an n-channel TFT, or a combination of these. Further, any structure of the semiconductor layer included in the transistors 310a, 310b, 310c, and 310d may be used. For example, an impurity region (including a source region, a drain region, and an LDD region) may be formed. The p channel type or the n channel type may be used. Further, an insulating layer (side wall) may be formed so as to be in contact with the side surface of the gate electrode, or a silicide layer may be formed on one or both of the source region, the drain region, and the gate electrode. As a material for the silicide layer, nickel, tungsten, molybdenum, cobalt, platinum, or the like can be used.

  Alternatively, the transistors 310a, 310b, 310c, and 310d included in the element formation layer 335 may be organic transistors in which a semiconductor layer included in the transistor is formed using an organic compound. The element formation layer 335 including an organic transistor can be formed using a printing method, a droplet discharge method, or the like. By using a printing method, a droplet discharge method, or the like, a semiconductor device can be manufactured at lower cost.

  The element formation layer 335, the memory elements 315a and 315b, and the conductive layer 343 functioning as an antenna can be formed by vapor deposition, sputtering, CVD, printing, droplet discharge, or the like as described above. . Note that a different method may be used depending on each place. For example, a transistor that requires high-speed operation is provided by forming a semiconductor layer made of Si or the like on a substrate and then crystallizing it by heat treatment, and then forming a transistor that functions as a switching element above the element formation layer by printing or An organic transistor can be provided by a droplet discharge method.

  Note that a sensor connected to the transistor may be provided. Examples of the sensor include an element that detects temperature, humidity, illuminance, gas (gas), gravity, pressure, sound (vibration), acceleration, and other characteristics by physical or chemical means. The sensor is typically formed of a semiconductor element such as a resistance element, a capacitive coupling element, an inductive coupling element, a photovoltaic element, a photoelectric conversion element, a thermoelectric element, a transistor, a thermistor, or a diode.

    Next, a structure example of a semiconductor device in the case where a terminal portion is provided over a substrate provided with a plurality of elements and memory elements and an antenna provided over another terminal is connected to the terminal portion is described with reference to FIG. I will explain.

  FIG. 11 illustrates a passive matrix semiconductor device, in which an element formation layer 385 is provided over a substrate 350, a memory element portion 375 is provided above the element formation layer 385, and functions as an antenna provided over the substrate 396. A conductive layer 393 is provided so as to be connected to the element formation layer 385. Note that here, the case where the memory element portion 375 or the conductive layer 393 functioning as an antenna is provided above the element formation layer 385 is shown; however, the present invention is not limited to this structure, and the memory element portion 375 is provided below the element formation layer 385. A conductive layer 393 functioning as an antenna can be provided below the element formation layer 385 in the same layer.

  The memory element portion 375 includes memory elements 365a and 365b. The memory element 365a includes a partition wall (insulating layer) 357a, a partition wall (insulating layer) 357b, an organic compound layer 362a, and a second conductive layer 356 over the first conductive layer 356. A conductive layer 363a is stacked, and the memory element 365b includes a partition wall (insulating layer) 357b, a partition wall (insulating layer) 357c, an organic compound layer 362b, and a second conductive layer 363b over the first conductive layer 356. Laminated and provided. In addition, an insulating layer 364 that functions as a protective film is formed so as to cover the second conductive layers 363a and 363b. In addition, the first conductive layer 356 in which the plurality of memory elements 365a and 365b are formed is connected to one source electrode layer or drain electrode layer of the transistor 360b. That is, the memory element is connected to the same single transistor. In addition, partition walls (insulating layers) 357a, 357b, and 357c for separating the organic compound layer 362a, the organic compound layer 362b, the second conductive layer 363a, and the second conductive layer 363b for each memory cell are provided. In the case where there is no concern about the influence of the electric field in the lateral direction in adjacent memory cells, it may be formed on the entire surface. Note that the memory elements 365a and 365b can be formed using the material or the manufacturing method described in the above embodiment modes.

  A region where the first conductive layer 356 is stacked with the organic compound layer 362a and the organic compound layer 362b is subjected to a treatment for reducing the interfacial tension, so that a treatment region 376 is formed.

  A treatment region 376 for reducing interfacial tension is formed on the interface (surface) in contact with the organic compound layer 362a of the first conductive layer 356 and the interface (surface) in contact with the first conductive layer 356 and the organic compound layer 362. By forming, the adhesiveness between the first conductive layer 356, the organic compound layer 362a, and the organic compound layer 632b can be improved.

  As a metal material used for the second conductive layer 363a and the second conductive layer 363b, indium (In), tin (Sn), lead (Pb), bismuth (Bi), calcium (Ca), antimony (Sb), zinc One or more of (Zn) are used. In addition, one or more of magnesium (Mg), manganese (Mn), cadmium (Cd), thallium (Tl), tellurium (Te), and barium (Ba) are used. A plurality of the metal materials may be included, or an alloy including one or more of the materials may be used. In particular, indium (In), tin (Sn), lead (Pb), bismuth (Bi), calcium (Ca), manganese (Mn), zinc (Zn), or a metal having a relatively low solubility parameter is included. Alloys are preferred as electrode materials. Examples of alloys that can be used include indium tin alloys (InSn), magnesium indium alloys (InMg), phosphorus indium alloys (InP), arsenic indium alloys (InAs), and chromium indium alloys (InCr).

  By using the material having a small solubility parameter for the second conductive layer 363a and the second conductive layer 363b, the second conductive layer 363a and the second conductive layer 363b, the organic compound layer 362a, and the organic compound layer 362b Adhesion can be improved. Therefore, defects such as film peeling at the layer interface are less likely to occur due to the force applied in the process of being transferred to the second substrate after being formed on the first substrate. Even when a glass substrate that can withstand manufacturing conditions such as temperature is used in the element manufacturing process, a flexible substrate such as a film can be used for the substrate 300 by being subsequently transferred to the second substrate. Therefore, the memory element can be peeled and transferred with a favorable shape, so that a semiconductor device can be manufactured.

  Needless to say, in the semiconductor device illustrated in FIGS. 10 and 11, the first conductive layer and the second conductive layer are formed in the same manner as in FIGS. 1A, 1B, 16A, and 16B. Alternatively, a conductive layer may be used. A conductive layer containing a metal material having a low solubility parameter is used for at least one of the first conductive layer and the second conductive layer, or at least one organic compound layer of the first conductive layer and the second conductive layer An oxidation treatment or the like that lowers the interfacial tension may be applied to the interface. The first conductive layer and the second conductive layer may be formed using a metal material having a small solubility parameter as shown in FIG. 16A, and the organic compound layer as shown in FIG. A region where the surface tension is low may be formed at both interfaces between the first conductive layer and the second conductive layer.

  Also in this embodiment (the semiconductor device shown in FIGS. 10 and 11), as shown in FIG. 19 of Embodiment 1, the organic compound layer and the first conductive layer, or the organic compound layer and the second conductive layer are used. An insulating layer may be provided between each of the layers, or both the first conductive layer and the second conductive layer, and the organic compound layer. By providing the insulating layer, characteristics such as a writing voltage of the memory element are stabilized without variation, and normal writing can be performed in each element.

  A substrate including the element formation layer 385 and the memory element portion 375 and a substrate 396 provided with a conductive layer 393 functioning as an antenna are attached to each other with a resin 395 having adhesiveness. The element formation layer 385 and the conductive layer 393 are electrically connected through conductive fine particles 394 contained in the resin 395. In addition, a conductive layer such as a silver paste, a copper paste, or a carbon paste or a method of performing solder bonding is used to provide a substrate including the element formation layer 385 and the memory element portion 375, and a conductive layer 393 that functions as an antenna. The substrate 396 may be attached.

  In this manner, a semiconductor device including a memory element and an antenna can be formed. In this embodiment mode, an element formation layer can be provided by forming a thin film transistor over a substrate, or by forming a field effect transistor over a substrate using a semiconductor substrate such as Si as the substrate. A layer may be provided. Alternatively, an SOI substrate may be used as a substrate, and an element formation layer may be provided thereover. In this case, the SOI substrate may be formed by using a method of bonding wafers or a method called SIMOX in which an insulating layer is formed inside by implanting oxygen ions into the Si substrate.

  Further, the memory element portion may be provided on a substrate provided with a conductive layer functioning as an antenna. A sensor connected to the transistor may be provided.

  Note that this embodiment can be freely combined with the above embodiment. In addition, the semiconductor device manufactured in this embodiment can be provided over a flexible substrate by being separated from the substrate by a separation process and bonded to a flexible substrate, so that the semiconductor device has flexibility. Can do. Flexible substrate means film made of polypropylene, polyester, vinyl, polyvinyl fluoride, vinyl chloride, paper made of fibrous material, substrate film (polyester, polyamide, inorganic vapor deposition film, paper, etc.) and adhesiveness It corresponds to a laminated film with a synthetic resin film (acrylic synthetic resin, epoxy synthetic resin, etc.). The film is subjected to heat treatment and pressure treatment, and when the heat treatment and pressure treatment are performed, the film is provided on the adhesive layer provided on the outermost surface of the film or on the outermost layer. The layer (not the adhesive layer) is melted by heat treatment and bonded by pressure. Further, an adhesive layer may be provided on the substrate, or an adhesive layer may not be provided. The adhesive layer corresponds to a layer containing an adhesive such as a thermosetting resin, an ultraviolet curable resin, an epoxy resin adhesive, or a resin additive.

  According to the present invention, a semiconductor device having a memory element with good adhesion inside a memory element that can perform a transposition process in a favorable state can be manufactured. Therefore, a highly reliable semiconductor device can be manufactured with high yield without complicating the device and the process.

(Embodiment 6)
In this embodiment, an example of a semiconductor device including the memory element described in the above embodiment will be described with reference to drawings. A top view of the semiconductor device of this embodiment is shown in FIG. 14A, and a cross-sectional view taken along line XY in FIG. 14A is shown in FIG.

  As shown in FIG. 14A, a memory element portion 404 which is a semiconductor device having a memory element, a circuit portion 421, and an antenna 431 are formed over a substrate 400. 14A and 14B show a state in which a memory element portion, a circuit portion, and an antenna are formed over a substrate 400 that can withstand the manufacturing conditions in the middle of the manufacturing process. Materials and manufacturing steps may be selected and manufactured in the same manner as in Embodiment Mode 4.

  A transistor 441 is provided in the memory element portion 404 and a transistor 442 is provided in the circuit portion 421 with a separation layer 452 and an insulating layer 453 provided over a substrate 400. An insulating layer 461, an insulating layer 454, and an insulating layer 455 are formed over the transistors 441 and 442. From the stack of the first conductive layer 457d, the organic compound layer 458, and the second conductive layer 459 over the insulating layer 455. A memory element 443 is formed. The organic compound layers 458 are individually separated by an insulating layer 460b functioning as a partition wall. The first conductive layer 457 d is connected to the wiring layer of the transistor 441, and the memory element 443 is electrically connected to the transistor 441.

  In the semiconductor device in FIG. 14B, the second conductive layer 459 is stacked and electrically connected to the wiring layer 456a and the conductive layer 457c. Over the insulating layer 455, a conductive layer 457a and an antenna 431a, a conductive layer 457b and an antenna 431b, a conductive layer 457e and an antenna 431c, and a conductive layer 457f and an antenna 431d are stacked. The conductive layer 457e is formed in contact with the wiring layer 456b in an opening reaching the wiring layer 456b formed in the insulating layer 455, and electrically connects the antenna to the memory element portion 404 and the circuit portion 421. The conductive layer 457a, the conductive layer 457b, the conductive layer 457e, and the conductive layer 457f under the antenna 431a, the antenna 431b, and the antennas 431c and 431d provide adhesion between the insulating layer 455 and the antenna 431a, the antenna 431b, the antenna 431c, and 431d. There is also an effect to improve. In this embodiment, a polyimide film is used for the insulating layer 455, a titanium film is used for the conductive layer 457a, the conductive layer 457b, the conductive layer 457e, and the conductive layer 457f, and an aluminum film is used for the antenna 431a, the antenna 431b, the antenna 431c, and 431d. ing.

  An opening (also referred to as a contact hole) is formed in the insulating layer 455 so that the first conductive layer 457d and the transistor 441, the conductive layer 457c and the wiring layer 456a, and the conductive layer 457e and the wiring layer 456b are connected to each other. When the opening is increased and the contact area between the conductive layers is increased, the resistance becomes lower. Therefore, in this embodiment, the opening where the first conductive layer 457d and the transistor 441 are connected is the smallest, and the next However, the openings are set in order so that the opening connecting the conductive layer 457c and the wiring layer 456a and the opening connecting the conductive layer 457e and the wiring layer 456b are the largest. In this embodiment, an opening connecting the first conductive layer 457d and the transistor 441 is 5 μm × 5 μm, an opening connecting the conductive layer 457c and the wiring layer 456a is 50 μm × 50 μm, and the conductive layer 457e and the wiring layer 456b are connected. The opening for connecting is set to 500 μm × 500 μm.

  In this embodiment, the distance a from the insulating layer 460a to the antenna 431b is 500 μm or more, the distance b from the end of the second conductive layer 459 to the end of the insulating layer 460a is 250 μm or more, and the second conductive layer 459 is used. The distance c from the end of the insulating layer 460c to the end of the insulating layer 460c is 500 μm or more, and the distance d from the end of the insulating layer 460c to the antenna 431c is 250 μm or more. In the circuit portion 421, the insulating layer 460c is partially formed, and the transistor 442 includes a region not covered with the insulating layer 460c and a region covered with the insulating layer 460c.

  17A and 17B are top views of the semiconductor device in this embodiment. FIG. 17B is an enlarged view of the memory element portion 404 in FIG. 17A, and a memory element 451 is formed as shown in FIG.

The RF input unit 401 includes a high-potential-side power supply (VDD) terminal, a low-potential-side power supply terminal, and a clock signal (CLK) terminal. In this embodiment, a ground potential (GND) is used as the low potential side power source. The RF input unit 401 rectifies radio waves received from an antenna (not shown) to generate VDD, and divides the received radio waves to generate CLK. The logic circuit unit 402 is connected to the high potential side power supply and the ground potential, and receives the clock signal.

  The external input unit 403 is provided with a plurality of pads, for example, a signal output (DATAOUT) pad, a write signal input (WEB) pad, a read signal input (REB) pad, a clock signal (CLK) pad, It has a ground potential (GND) pad, a high potential side power supply (VDD) pad, and a write power supply (VDDH) pad.

  The memory element unit 404 includes a VDDH terminal to which a signal is input via a VDDH pad, a VDD terminal to which a signal is input via a VDD pad, and a GND terminal to which a signal is input via a GND pad. , A CLK terminal for receiving a signal via the CLK pad, a REB terminal for receiving a signal via the REB pad, and a WEB terminal for receiving a signal via the WEB pad are provided. Yes. Further, the high-potential-side power supply (VDD) terminal of the RF input unit 401 and the VDDH terminal of the storage element unit 404 are connected via a diode 406. By connecting through the diode in this way, when writing to the memory element portion, the power supply connected to the tip of the high potential side power supply (VDD) terminal and the VDDH terminal are short-circuited. Can be prevented. 18A and 18B, a protection circuit is provided between the CLK pad and the CLK terminal, between the REB pad and the REB terminal, or between the WEB pad and the WEB terminal. Is preferably provided.

  The adjustment circuit unit 405 has a plurality of resistors. The CLK terminal of the memory element portion 404 and the logic circuit portion 402 are connected via any one of the resistors. In addition, the REB terminal of the memory element portion 404 and the logic circuit portion 402 are connected to each other through any resistor different from the resistor. Such an adjustment circuit unit 405 performs adjustment so that an unnecessary control signal is not input to the storage element unit 404 from the logic circuit unit 402 when data is written to or read from the storage element unit 404 using an external signal. . Similarly, the resistor 407 is also adjusted so that no signal is input from the logic circuit portion 402 to the memory element portion 404 when data is written to the memory element portion 404. That is, the resistor 407 functions as an adjustment circuit.

  By using such a semiconductor device, data (corresponding to information) is written to the memory element unit 404 by directly inputting a power supply voltage or a signal from the external input unit 403 to the memory element unit 404, or the memory element unit Data can be read from 404.

  In addition, when a signal is not directly input to the external input unit 403, it is possible to generate a power source or a signal inside the radio wave received by the antenna unit through the RF input unit and read data from the storage element unit 404.

  In the circuit configuration of the present invention, when data is written to the memory element unit 404, the signal from the external input unit 403 is blocked by the diode 406, but when data is read from the memory element unit 404 by a signal from the antenna. The VDDH of the memory element unit 404 can be fixed to the VDD of the RF input unit 401 and stabilized.

  Next, FIG. 18B illustrates a structure of a semiconductor device in which the structure of the adjustment circuit portion 405 is different from that in FIG. A semiconductor device illustrated in FIG. 18B includes an RF input portion 411, a logic circuit portion 412, an external input portion 413, a memory element portion 414, an adjustment circuit portion 415, a diode 416, and a resistor 417. The adjustment circuit portion 415 in the semiconductor device in FIG. 18B includes a switch. As the switch, an inverter, an analog switch, or the like can be used. In this embodiment, an inverter or an analog switch is used, and the input terminal and the analog switch of the inverter are connected between the resistor 417 and the WEB terminal, and the output terminal and the analog switch of the inverter are connected to each other. Resistor 417 is installed in order to prioritize the input of VDD when there is no external input to WEB, but VDD enters WEB. The adjustment circuit unit 415 receives a low signal in the WEB with an external input, that is, when external input is performed, the unnecessary signal from the logic circuit unit 412 is cut off, and conversely, a high signal is input into the WEB, or the external input is When there is no signal, a stable signal is supplied to the memory element portion 414 by blocking the externally input signals REB and CLK.

Such a semiconductor device can also be operated similarly to the semiconductor device described with reference to the block diagram of FIG. However, since the adjustment circuit portion 415 including an inverter and an analog switch can be dedicated to power generation, the problem that the potential of VDDH decreases by the threshold voltage of the diode 416 hardly occurs.

  FIG. 22 is a schematic diagram corresponding to FIG. 18A of the circuit of the semiconductor device shown in FIG. In the semiconductor device, a logic circuit portion 402 occupying the largest area is provided, and an RF input portion 401 and a storage element portion 404 are provided adjacent thereto. An adjustment circuit portion 405 and a resistor 407 are provided in one area of the memory element portion 404, and these are provided adjacent to each other. An external input unit 403 is provided adjacent to the RF input unit 401. Since the external input portion 403 includes a pad, the external input portion 403 is preferably provided in a region in contact with one side of the semiconductor device. This is because the bonding can be performed using one side of the semiconductor device as a reference at the time of bad connection. These circuits and the like can be formed by the manufacturing methods described in the above embodiment modes. FIG. 18 is a block diagram relating to the circuit of the semiconductor device shown in FIG. The block diagram of the semiconductor device in FIG. 18A includes an RF input portion 401, a logic circuit portion 402, an external input portion 403, a memory element portion 404, an adjustment circuit portion 405, a diode 406, and a resistor 407. The block diagram in FIG. 18B includes an RF input portion 411, a logic circuit portion 412, an external input portion 413, a memory element portion 414, an adjustment circuit portion 415, a diode 416, and a resistor 417. FIG. 22 is a schematic diagram corresponding to FIG. 18A of the circuit of the semiconductor device shown in FIG.

  The voltage and signal input from the external input terminal are input to the memory element portion 404, and data (information) is written to the memory element portion 404. The written data is received by the RF input unit 401 by an antenna and an AC signal is input to the logic circuit unit 402. The signal becomes a control signal through the logic circuit portion 402, and the control signal is input to the storage element portion 404 and is read again from the storage element portion 404.

  In the semiconductor devices in FIGS. 18A and 18B, the structure of the adjustment circuit portion 405 is different. The adjustment circuit portion 405 is a resistor, and the adjustment circuit portion 415 is a switch. The resistors 407 and 417 are pull-up circuits and function as an adjustment circuit unit. The adjustment circuit unit 405 performs adjustment so that unnecessary control signals are not input to the storage element unit 404 from the logic circuit unit 402 when data is written to the storage element unit 404. Similarly, the resistor 407 is also adjusted so that no signal is input from the logic circuit portion 402 to the memory element portion 404 when data is written to the memory element portion 404. When writing data to the storage element unit 404, the signal from the external input unit 403 is cut off by the diode 406, but when reading data from the storage element unit 404, VDDH of the storage element unit 404 is set from the RF input unit 401. Fix to the applied VDD and stabilize. Although described based on the block diagram of FIG. 18A, the same applies to FIG. 18B.

  Further, the antenna may be provided so as to overlap with the memory element portion, or may be provided around the memory element portion without overlapping. When overlapping, the entire surface may overlap, or a structure where a part overlaps may be used. When the antenna unit and the memory element unit overlap each other, the malfunction of the semiconductor device due to the influence of noise, etc. on the signal when the antenna communicates or fluctuations in electromotive force generated by electromagnetic induction is reduced. Is possible, and reliability is improved. In addition, the semiconductor device can be reduced in size.

  As a signal transmission method in the semiconductor device capable of inputting / outputting non-contact data described above, an electromagnetic coupling method, an electromagnetic induction method, a microwave method, or the like can be used. The transmission method may be appropriately selected by the practitioner in consideration of the intended use, and an optimal antenna may be provided according to the transmission method.

  For example, when an electromagnetic coupling method or an electromagnetic induction method (for example, 13.56 MHz band) is applied as a signal transmission method in a semiconductor device, an electromagnetic induction due to a change in magnetic field density is used, and thus a conductive layer that functions as an antenna. Are formed in a ring shape (for example, a loop antenna) or a spiral shape (for example, a spiral antenna). FIGS. 21A to 21C illustrate an example of a chip-shaped semiconductor device 503 including a conductive layer 502 functioning as an antenna and an integrated circuit, which are formed over a substrate 501.

  In addition, when a microwave method (for example, UHF band (860 to 960 MHz band), 2.45 GHz band, or the like) is applied as a signal transmission method in a semiconductor device, the wavelength of an electromagnetic wave used for signal transmission is considered. The length of the conductive layer functioning as an antenna may be set as appropriate. For example, the conductive layer functioning as an antenna is linear (for example, a dipole antenna (see FIG. 21A)) or a flat shape ( For example, it can be formed in a patch antenna (see FIG. 21B)) or a ribbon shape (see FIGS. 21C and 21D). Further, the shape of the conductive layer functioning as an antenna is not limited to a linear shape, and may be provided in a curved shape, a meandering shape, or a combination thereof in consideration of the wavelength of electromagnetic waves.

  The conductive layer functioning as an antenna is formed using a conductive material by a CVD method, a sputtering method, a printing method such as screen printing or gravure printing, a droplet discharge method, a dispenser method, a plating method, or the like. Conductive materials are aluminum (Al), titanium (Ti), silver (Ag), copper (Cu), gold (Au), platinum (Pt) nickel (Ni), palladium (Pd), tantalum (Ta), molybdenum An element selected from (Mo) or an alloy material or a compound material containing these elements as a main component is formed in a single layer structure or a laminated structure.

  For example, when a conductive layer that functions as an antenna is formed using a screen printing method, a conductive paste in which conductive particles having a particle size of several nanometers to several tens of micrometers are dissolved or dispersed in an organic resin is selectively used. Can be provided by printing. Conductor particles include silver (Ag), gold (Au), copper (Cu), nickel (Ni), platinum (Pt), palladium (Pd), tantalum (Ta), molybdenum (Mo) and titanium (Ti). Any one or more metal particles, silver halide fine particles, or dispersible nanoparticles can be used. In addition, as the organic resin contained in the conductive paste, one or more selected from organic resins that function as a binder of metal particles, a solvent, a dispersant, and a coating material can be used. Typically, an organic resin such as an epoxy resin or a silicon resin can be given. In forming the conductive layer, it is preferable to fire after extruding the conductive paste. For example, in the case where fine particles containing silver as a main component (for example, a particle size of 1 nm or more and 100 nm or less) is used as the material of the conductive paste, the conductive layer is obtained by being cured by baking in a temperature range of 150 to 300 ° C. Can do. Further, fine particles mainly composed of solder or lead-free solder may be used. In this case, it is preferable to use fine particles having a particle diameter of 20 μm or less. Solder and lead-free solder have the advantage of low cost.

  In addition to the materials described above, ceramic, ferrite, or the like may be applied to the antenna.

  Further, in the case where an electromagnetic coupling method or an electromagnetic induction method is applied and a semiconductor device provided with an antenna is provided in contact with a metal, a magnetic material having a permeability between the semiconductor device and the metal is used. It is preferable to provide it. When a semiconductor device provided with an antenna is provided in contact with a metal, an eddy current flows in the metal as the magnetic field changes, and the change in the magnetic field is weakened by the demagnetizing field generated by the eddy current, thereby reducing the communication distance. . Therefore, by providing a material having magnetic permeability between the semiconductor device and the metal, it is possible to suppress the eddy current of the metal and suppress the decrease in the communication distance. As the magnetic material, a metal thin film or ferrite having high magnetic permeability and low high-frequency loss can be used.

  In the case of providing an antenna, a semiconductor element such as a transistor and a conductive layer functioning as an antenna may be directly formed over one substrate, or the semiconductor element and the conductive layer functioning as an antenna may be provided separately. After being provided on the substrate, it may be provided by bonding so as to be electrically connected.

  The memory element 443 including the first conductive layer 457d, the organic compound layer 458, and the second conductive layer 459 described in this embodiment has good adhesion inside the memory element; thus, the substrate 400 which is a first substrate Due to the force applied in the process of being transferred to the second substrate after being formed, defects such as film peeling are unlikely to occur at the layer interface. Therefore, the memory element can be peeled and transferred with a favorable shape, so that a semiconductor device can be manufactured.

  Since the semiconductor device including the memory element manufactured in this embodiment has favorable adhesion inside the memory element, the separation and transfer process can be performed in a favorable state. Therefore, since it can be freely transferred to various substrates, the range of substrate material selectivity is widened. In addition, an inexpensive material can be selected as the substrate, so that not only a wide function can be provided depending on the application, but also a semiconductor device can be manufactured at low cost.

  According to the present invention, a semiconductor device having a memory element with good adhesion inside a memory element that can perform a transposition process in a favorable state can be manufactured. Therefore, a highly reliable semiconductor device can be manufactured with high yield without complicating the device and the process.

(Embodiment 7)
In this embodiment mode, reading or writing of data in the semiconductor device having the above structure is described.

  First, operation when data is written to a memory element in a passive matrix semiconductor device will be described with reference to FIGS. Data writing is performed by optical action or electrical action. First, the case of writing data by electrical action will be described (see FIG. 3). Writing is performed by changing the electrical characteristics of the memory cell. The initial state of the memory cell (the state where no electrical action is applied) is data “0”, and the state where the electrical characteristic is changed is “1”. To do.

  When data “1” is written in the memory cell 721, first, the memory cell 721 is selected by the decoders 723 and 724 and the selector 725. Specifically, the decoder 724 applies a predetermined voltage V2 to the word line W3 connected to the memory cell 721. In addition, the bit line B 3 connected to the memory cell 721 is connected to the circuit 726 by the decoder 723 and the selector 725. Then, the write voltage V1 is output from the circuit 726 to the bit line B3. In this way, the voltage Vw = V1−V2 is applied between the first conductive layer and the second conductive layer constituting the memory cell 721. By appropriately selecting the potential Vw, the organic compound layer provided between the conductive layers is changed physically or electrically, and data “1” is written. Specifically, at the read operation voltage, the electrical resistance between the first conductive layer and the second conductive layer in the data “1” state is significantly smaller than that in the data “0” state. It is good to change as follows. For example, it may be appropriately selected from the range of (V1, V2) = (0V, 5-15V), or (3-5V, -12--2V). The voltage Vw may be 5 to 15V, or -5 to -15V.

  Note that data “1” is controlled not to be written in the memory cell connected to the non-selected word line and the non-selected bit line. For example, unselected word lines and unselected bit lines may be set in a floating state. The first conductive layer and the second conductive layer constituting the memory cell must have characteristics such as diode characteristics that can ensure selectivity.

  On the other hand, when data “0” is written in the memory cell 721, it is not necessary to apply an electrical action to the memory cell 721. In the circuit operation, for example, as in the case of writing “1”, the memory cell 721 is selected by the decoders 723 and 724 and the selector 725, but the output potential from the circuit 726 to the bit line B3 is set to the selected word line. A voltage (for example, a voltage that does not change the electrical characteristics of the memory cell 721 between the first conductive layer and the second conductive layer constituting the memory cell 721) is set to the same level as the potential of W3 or the potential of the unselected word line. −5 to 5 V) may be applied.

  Next, a case where data is written by optical action will be described (see FIG. 20). In this case, the second conductive layer 753a needs to transmit laser light. This is performed by irradiating the organic compound layer 752 with laser light from the side of the light-transmitting conductive layer (herein, the second conductive layer 753a). Here, the organic compound layer 752 is destroyed by selectively irradiating a desired portion of the organic compound layer 752 with laser light. Since the destroyed organic compound layer is insulated, the electric resistance is significantly increased as compared with other portions. In this manner, data is written by utilizing the change in electrical resistance between two conductive films provided with the organic compound layer 752 interposed therebetween by laser light irradiation. For example, when an organic compound layer not irradiated with laser light is set to “0” data, when writing “1” data, a desired portion of the organic compound layer is selectively irradiated with laser light for destruction. To increase the electrical resistance.

  When a conjugated polymer doped with a compound that generates acid by absorbing light (a photoacid generator) is used as the organic compound layer 752, when irradiated with laser light, only the irradiated portion is conductive. Increases, and the unirradiated portion has no conductivity. Therefore, data is written by utilizing the change in the electrical resistance of the organic compound layer by selectively irradiating the organic compound layer in a desired portion with laser light. For example, in a case where an organic compound layer not irradiated with laser light is set to “0” data, when writing “1” data, a desired portion of the organic compound layer is selectively irradiated with laser light to be conductive. Increase sex.

In the case of irradiation with laser light, the change in the electrical resistance of the organic compound layer 752 depends on the size of the memory cell 721, but is realized by laser light irradiation with a diameter on the order of μm. For example, when a laser beam having a diameter of 1 μm passes at a linear velocity of 10 m / sec, the time during which the layer containing an organic compound included in one memory cell is irradiated with laser light is 100 nsec. In order to change the phase within a short time of 100 nsec, the laser power is preferably 10 mW and the power density is 10 kW / mm ² . In the case of selectively irradiating laser light, it is preferable to use a pulsed laser irradiation apparatus.

  Here, an example of a laser irradiation apparatus will be briefly described with reference to FIG. A laser irradiation apparatus 1001 includes a computer (hereinafter, referred to as a PC) 1002 that executes various controls when irradiating laser light, a laser oscillator 1003 that outputs laser light, a power source 1004 of the laser oscillator 1003, and laser light. An optical system (ND filter) 1005 for attenuating light, an acousto-optic modulator (AOM) 1006 for modulating the intensity of the laser light, and a lens and an optical path for reducing the cross section of the laser light An optical system 1007 composed of a mirror for changing the angle, a moving mechanism 1009 having an X-axis stage and a Y-axis stage, a D / A conversion unit 1010 for digital-analog conversion of control data output from the PC, Acousto-optic modulator 10 according to the analog voltage output from the D / A converter 6, a driver 1012 that outputs a drive signal for driving the moving mechanism 1009, and an autofocus mechanism 1013 for focusing the laser beam on the irradiated object (FIG. 20 ( See C).

As the laser oscillator 1003, a laser oscillator that can oscillate ultraviolet light, visible light, or infrared light can be used. As the laser oscillator, excimer laser oscillators such as KrF, ArF, KrF, XeCl, and Xe, gas laser oscillators such as He, He—Cd, Ar, He—Ne, and HF, YAG, GdVO ₄ , YVO ₄ , YLF, and YAlO Cr crystal such as _{3, Nd, Er, Ho,} Ce, Co, solid-state laser oscillator using a crystal doped with Ti or Tm, can be used GaN, GaAs, GaAlAs, a semiconductor laser oscillator of InGaAsP or the like. In the solid-state laser oscillator, it is preferable to apply the fundamental wave or the second to fifth harmonics.

  Next, an irradiation method using a laser irradiation apparatus will be described. When the substrate provided with the organic compound layer is mounted on the moving mechanism 1009, the PC 1002 detects the position of the organic compound layer to be irradiated with the laser light by a camera (not shown). Next, the PC 1002 generates movement data for moving the movement mechanism 1009 based on the detected position data.

  Thereafter, the PC 1002 controls the output light amount of the acousto-optic modulator 1006 via the driver 1011, so that the laser light output from the laser oscillator 1003 is attenuated by the optical system 1005 and then the acousto-optic modulator 1006. The light amount is controlled so as to be a predetermined light amount. On the other hand, the laser light output from the acousto-optic modulator 1006 is changed in optical path and beam spot shape by the optical system 1007, condensed by a lens, and then irradiated onto the substrate 750.

  At this time, according to the movement data generated by the PC 1002, the movement mechanism 1009 is controlled to move in the X direction and the Y direction. As a result, laser light is irradiated to a predetermined place, the light energy density of the laser light is converted into thermal energy, and the organic compound layer provided over the substrate 750 can be selectively irradiated with the laser light. Note that, here, an example in which the moving mechanism 1009 is moved and laser light irradiation is performed is shown; however, the laser light may be moved in the X direction and the Y direction by adjusting the optical system 1007.

  As described above, the structure of the present invention in which data is written by laser light irradiation can easily manufacture a large number of semiconductor devices. Therefore, an inexpensive semiconductor device can be provided.

  Next, an operation of reading data from a memory element in a passive matrix semiconductor device will be described (see FIG. 3). In reading data, the electrical characteristics between the first conductive layer and the second conductive layer constituting the memory cell are different between the memory cell having data “0” and the memory cell having data “1”. Use it. For example, the effective electrical resistance between the first conductive layer and the second conductive layer constituting the memory cell having data “0” (hereinafter simply referred to as the electrical resistance of the memory cell) is R0 at the read voltage. A method of reading data by using the difference in electric resistance when the electric resistance of the memory cell having data “1” is R1 in the read voltage will be described. Note that R1 << R0. As the structure of the reading / writing circuit, for example, a circuit 726 using a resistance element 746 and a differential amplifier 747 shown in FIG. 3B can be considered. The resistance element 746 has a resistance value Rr, and R1 <Rr <R0. A transistor 748 may be used instead of the resistance element 746, and a clocked inverter 749 may be used instead of the differential amplifier (FIG. 3C). The clocked inverter 749 receives a signal φ or an inverted signal φ that is High when reading is performed and is Low when the reading is not performed. Of course, the circuit configuration is not limited to FIG.

  When reading data from the memory cell 721, first, the memory cell 721 is selected by the decoders 723 and 724 and the selector 725. Specifically, the decoder 724 applies a predetermined voltage Vy to the word line Wy connected to the memory cell 721. In addition, the bit line Bx connected to the memory cell 721 is connected to the terminal P of the circuit 726 by the decoder 723 and the selector 725. As a result, the potential Vp of the terminal P becomes a value determined by resistance division by the resistance element 246 (resistance value Rr) and the memory cell 721 (resistance value R0 or R1). Therefore, when the memory cell 721 has data “0”, Vp0 = Vy + (V0−Vy) × R0 / (R0 + Rr). When the memory cell 721 has data “1”, Vp1 = Vy + (V0−Vy) × R1 / (R1 + Rr). As a result, in FIG. 3B, Vref is selected to be between Vp0 and Vp1, and in FIG. 3C, the change point of the clocked inverter is selected to be between Vp0 and Vp1. Thus, Low / High (or High / Low) is output as the output potential Vout according to the data “0” / “1”, and reading can be performed.

  For example, the differential amplifier is operated at Vdd = 3V, and Vy = 0V, V0 = 3V, and Vref = 1.5V. Assuming that R0 / Rr = Rr / R1 = 9, if the memory cell data is “0”, Vp0 = 2.7 V and Vout is High, and if the memory cell data is “1”, Vp1 = 0.3V and Low is output as Vout. Thus, the memory cell can be read.

  According to the above method, the state of the electric resistance of the organic compound layer 752 is read as a voltage value by utilizing the difference in resistance value and resistance division. Of course, the reading method is not limited to this method. For example, in addition to using the difference in electrical resistance, reading may be performed using the difference in current value. In addition, when the electrical characteristics of the memory cell have data “0” and “1” and diode characteristics with different threshold voltages, reading may be performed using the threshold voltage difference.

  Next, operation when data is written to the memory element in the active matrix semiconductor device is described (see FIGS. 4 and 5).

  First, an operation when data is written by electrical action will be described. Writing is performed by changing the electrical characteristics of the memory cell. The initial state of the memory cell (the state where no electrical action is applied) is data “0”, and the state where the electrical characteristic is changed is “1”. To do.

  Here, a case where data is written to the memory cell 231 in the nth row and the mth column will be described. When data “1” is written to the memory cell 231, first, the memory cell 231 is selected by the decoders 223 and 224 and the selector 225. Specifically, the decoder 224 applies a predetermined voltage V22 to the word line Wn connected to the memory cell 231. The decoder 223 and the selector 225 connect the bit line Bm connected to the memory cell 231 to a circuit 226 having a reading circuit and a writing circuit. Then, the write voltage V21 is output from the circuit 226 to the bit line B3.

  Thus, the transistor 210a included in the memory cell is turned on, the bit line is electrically connected to the memory element 215b, and a voltage of approximately Vw = Vcom−V21 is applied. Note that one electrode of the memory element 30 is connected to a common electrode having the potential Vcom. By appropriately selecting the potential Vw, the organic compound layer provided between the conductive layers is changed physically or electrically, and data “1” is written. Specifically, at the read operation voltage, the electrical resistance between the first conductive layer and the second conductive layer in the data “1” state is significantly smaller than that in the data “0” state. It may be changed as described above, or it may be simply short-circuited. The potential may be appropriately selected from the range of (V21, V22, Vcom) = (5-15V, 5-15V, 0V), or (-12 to 0V, -12 to 0V, 3 to 5V). The voltage Vw may be 5 to 15V, or -5 to -15V.

  Note that data “1” is controlled not to be written in the memory cell connected to the non-selected word line and the non-selected bit line. Specifically, a potential (for example, 0 V) for turning off the transistor of the memory cell to be connected is applied to the non-selected word line, and the non-selected bit line is in a floating state or approximately equal to Vcom. A potential may be applied.

  On the other hand, when data “0” is written in the memory cell 231, it is not necessary to apply an electrical action to the memory cell 231. In the circuit operation, for example, as in the case of writing “1”, the memory cell 231 is selected by the decoders 223 and 224 and the selector 225, but the output potential from the circuit 226 to the bit line B3 is set to the same level as Vcom. Alternatively, the bit line B3 is brought into a floating state. As a result, a small voltage (for example, −5 to 5 V) is applied to the memory element 215b or no voltage is applied, so that the electrical characteristics do not change and data “0” writing is realized.

  Next, a case where data is written by optical action will be described. In this case, the laser irradiation is performed by irradiating the organic compound layer with laser light from the light-transmitting conductive layer side. As the laser irradiation apparatus, a passive matrix semiconductor device similar to that described with reference to FIG. 20 may be used.

  In the case where an organic compound material is used as the organic compound layer, the organic compound layer is oxidized or carbonized and insulated by laser light irradiation. Then, the resistance value of the memory element irradiated with the laser light increases, and the resistance value of the memory element not irradiated with the laser light does not change. When a conjugated polymer material doped with a photoacid generator is used, conductivity is imparted to the organic compound layer by irradiation with laser light. That is, conductivity is given to the memory element irradiated with the laser beam, and conductivity is not given to the memory element not irradiated with the laser beam.

  Next, an operation when data is read by electrical action will be described. Here, the circuit 226 includes a resistance element 246 and a differential amplifier 247. However, the configuration of the circuit 226 is not limited to the above configuration, and may have any configuration.

  Next, an operation in reading data by an electrical action in an active matrix semiconductor device will be described. Data is read by utilizing the fact that the electrical characteristics of the memory element 215b are different between the memory cell having data “0” and the memory cell having data “1”. For example, the electrical resistance of the memory element constituting the memory cell having data “0” is R0 at the read voltage, and the electrical resistance of the memory element constituting the memory cell having data “1” is R1 at the read voltage. A method of reading using the difference will be described. Note that R1 << R0. As the reading / writing circuit, for example, a circuit 226 using a resistance element 246 and a differential amplifier 247 shown in FIG. The resistance element has a resistance value Rr, and R1 <Rr <R0. A transistor 249 may be used instead of the resistance element 246, and a clocked inverter 248 may be used instead of the differential amplifier (FIG. 5C). Of course, the circuit configuration is not limited to FIG.

  When data is read from the memory cell 231 in the xth row and the yth column, first, the memory cell 231 is selected by the decoders 223 and 224 and the selector 225. Specifically, the decoder 224 applies a predetermined voltage V24 to the word line Wy connected to the memory cell 231 to turn on the transistor 210a. In addition, the bit line Bx connected to the memory cell 231 is connected to the terminal P of the circuit 226 by the decoder 223 and the selector 225. As a result, the potential Vp of the terminal P becomes a value determined by resistance division of Vcom and V0 by the resistance element 246 (resistance value Rr) and the memory element 215b (resistance value R0 or R1). Therefore, when the memory cell 231 has data “0”, Vp0 = Vcom + (V0−Vcom) × R0 / (R0 + Rr). When the memory cell 231 has data “1”, Vp1 = Vcom + (V0−Vcom) × R1 / (R1 + Rr). As a result, in FIG. 5B, Vref is selected to be between Vp0 and Vp1, and in FIG. 5C, the change point of the clocked inverter is selected to be between Vp0 and Vp1. Thus, the output potential Vout is Low / High (or High / Low) according to the data “0” / “1”, and reading can be performed.

  For example, the differential amplifier is operated at Vdd = 3V, and Vcom = 0V, V0 = 3V, and Vref = 1.5V. Assuming that R0 / Rr = Rr / R1 = 9 and the on-resistance of the transistor 210a is negligible, when the data of the memory cell is “0”, Vp0 = 2.7V and Vout is output as High, When the data of “1” is “1”, Vp1 = 0.3V and Vout is output as Low. Thus, the memory cell can be read.

  According to the above method, the voltage value is read by utilizing the difference in resistance value of the memory element 215b and the resistance division. Of course, the reading method is not limited to this method. For example, in addition to using the difference in electrical resistance, reading may be performed using the difference in current value. In addition, when the electrical characteristics of the memory cell have data “0” and “1” and diode characteristics with different threshold voltages, reading may be performed using the threshold voltage difference.

  Since a memory element having the above structure and a semiconductor device including the memory element are nonvolatile memories, a small, thin, and lightweight semiconductor device is provided without the need to incorporate a battery for holding data. Can do. In addition, data can be written (added) by using the insulating material used in the above embodiment as an organic compound layer, but data cannot be rewritten. Therefore, it is possible to provide a semiconductor device that prevents forgery and ensures security.

Note that this embodiment can be freely combined with the structures of the memory element and the semiconductor device including the memory element described in the above embodiment.
(Embodiment 8)

The configuration of the semiconductor device of this embodiment will be described with reference to FIG. As shown in FIG. 12, the semiconductor device 20 of the present invention has a function of communicating data without contact, and controls the power supply circuit 11, the clock generation circuit 12, the data demodulation / modulation circuit 13, and other circuits. A circuit 14, an interface circuit 15, a memory circuit 16, a data bus 17, an antenna (antenna coil) 18, a sensor 21, and a sensor circuit 22 are included.

The power supply circuit 11 is a circuit that generates various power supplies to be supplied to each circuit inside the semiconductor device 20 based on the AC signal input from the antenna 18. The clock generation circuit 12 is a circuit that generates various clock signals to be supplied to each circuit inside the semiconductor device 20 based on the AC signal input from the antenna 18. The data demodulation / modulation circuit 13 has a function of demodulating / modulating data communicated with the reader / writer 19. The control circuit 14 has a function of controlling the memory circuit 16. The antenna 18 has a function of transmitting / receiving electromagnetic waves or radio waves. The reader / writer 19 controls communication and control with the semiconductor device and processing related to the data. The semiconductor device is not limited to the above-described configuration, and may be a configuration in which other elements such as a power supply voltage limiter circuit and hardware dedicated to cryptographic processing are added.

The memory circuit 16 includes a memory element in which an organic compound layer or a phase change layer is sandwiched between a pair of conductive layers. Note that the memory circuit 16 may include only a memory element in which an organic compound layer or a phase change layer is sandwiched between a pair of conductive layers, or may include a memory circuit having another structure. The memory circuit having another configuration corresponds to, for example, one or more selected from DRAM, SRAM, FeRAM, mask ROM, PROM, EPROM, EEPROM, and flash memory.

The sensor 21 is formed of a semiconductor element such as a resistance element, a capacitive coupling element, an inductive coupling element, a photovoltaic element, a photoelectric conversion element, a thermoelectric element, a transistor, a thermistor, or a diode. The sensor circuit 22 detects a change in impedance, reactance, inductance, voltage or current, performs analog / digital conversion (A / D conversion), and outputs a signal to the control circuit 14.

(Embodiment 9)
According to the present invention, a semiconductor device that functions as a chip having a processor circuit (hereinafter also referred to as a processor chip, a wireless chip, a wireless processor, a wireless memory, or a wireless tag) can be formed. The semiconductor device of the present invention has a wide range of uses, such as banknotes, coins, securities, certificates, bearer bonds, packaging containers, books, recording media, personal items, vehicles, foods, clothing It can be used in health supplies, daily necessities, medicines and electronic devices.

  Since a semiconductor device having a memory element using the present invention has good adhesion inside the memory element, the peeling and transposing steps can be performed in a good state. Therefore, since it can be freely transferred to various substrates, an inexpensive material can be selected as the substrate, and not only can a wide range of functions be provided depending on the application, but also a semiconductor device can be manufactured at low cost. be able to. Therefore, the chip having a processor circuit according to the present invention also has features such as low cost, small size, thinness, and light weight, so it is suitable for a large amount of money, coins, etc., books that are often carried, personal items, clothes, etc. is there.

  Banknotes and coins are money that circulates in the market, and include those that are used in the same way as money in a specific area (cash vouchers), commemorative coins, and the like. Securities refer to checks, securities, promissory notes, and the like, and can be provided with a chip 90 having a processor circuit (see FIG. 13A). The certificate refers to a driver's license, a resident's card, and the like, and can be provided with a chip 91 having a processor circuit (see FIG. 13B). The vehicles refer to vehicles such as bicycles, ships, and the like, and can be provided with a chip 97 including a processor circuit (see FIG. 13C). Bearer bonds refer to stamps, gift cards, and various gift certificates. Packaging containers refer to wrapping paper for lunch boxes, plastic bottles, and the like, and can be provided with a chip 93 having a processor circuit (see FIG. 13D). Books refer to books, books, and the like, and can be provided with a chip 94 including a processor circuit (see FIG. 13E). The recording medium refers to DVD software, video tape, or the like, and can be provided with a chip 95 including a processor circuit (see FIG. 13F). Personal belongings refer to bags, glasses, and the like, and can be provided with a chip 96 including a processor circuit (see FIG. 13G). Foods refer to food products, beverages, and the like. Clothing refers to clothing, footwear, and the like. Health supplies refer to medical equipment, health equipment, and the like. Livingware refers to furniture, lighting equipment, and the like. Chemicals refer to pharmaceuticals, agricultural chemicals, and the like. Electronic devices refer to liquid crystal display devices, EL display devices, television devices (TV receivers, flat-screen TV receivers), mobile phones, and the like.

The semiconductor device of the present invention is fixed to an article by being mounted on a printed board, pasted on a surface, or embedded. For example, a book is embedded in paper, and a package made of an organic resin is embedded in the organic resin, and is fixed to each article. Since the semiconductor device of the present invention realizes a small size, a thin shape, and a light weight, the design of the article itself is not impaired even after being fixed to the article. In addition, by providing the semiconductor device of the present invention in bills, coins, securities, bearer bonds, certificates, etc., an authentication function can be provided, and if this authentication function is utilized, counterfeiting can be prevented. it can. In addition, by providing the semiconductor device of the present invention in packaging containers, recording media, personal items, foods, clothing, daily necessities, electronic devices, etc., the efficiency of a system such as an inspection system can be improved.

Next, one mode of an electronic device in which the semiconductor device of the present invention is mounted will be described with reference to the drawings. An electronic device illustrated here is a mobile phone, which includes housings 2700 and 2706, a panel 2701, a housing 2702, a printed wiring board 2703, operation buttons 2704, and a battery 2705 (see FIG. 12B). The panel 2701 is detachably incorporated in the housing 2702, and the housing 2702 is fitted on the printed wiring board 2703. The shape and dimensions of the housing 2702 are changed as appropriate in accordance with the electronic device in which the panel 2701 is incorporated. A plurality of packaged semiconductor devices are mounted on the printed wiring board 2703, and the semiconductor device of the present invention can be used as one of them. The plurality of semiconductor devices mounted on the printed wiring board 2703 have any one function of a controller, a central processing unit (CPU), a memory, a power supply circuit, a sound processing circuit, a transmission / reception circuit, and the like.

The panel 2701 is connected to the printed wiring board 2703 through the connection film 2708. The panel 2701, the housing 2702, and the printed wiring board 2703 are housed in the housings 2700 and 2706 together with the operation buttons 2704 and the battery 2705. A pixel region 2709 included in the panel 2701 is arranged so as to be visible from an opening window provided in the housing 2700.

As described above, the semiconductor device of the present invention is characterized in that it is small, thin, and lightweight, and the limited space inside the housings 2700 and 2706 of the electronic device can be effectively used due to the above characteristics. .

In addition, since the semiconductor device of the present invention includes a memory element having a simple structure in which an organic compound layer is sandwiched between a pair of conductive layers, an electronic device using an inexpensive semiconductor device can be provided. In addition, since the semiconductor device of the present invention can be easily integrated, an electronic device using the semiconductor device including a large-capacity memory circuit can be provided.

In addition, a memory element included in the semiconductor device of the present invention writes data by an optical action or an electrical action, is nonvolatile, and can additionally write data. With the above feature, forgery due to rewriting can be prevented, and new data can be added and written. Therefore, an electronic device using a semiconductor device that achieves high functionality and high added value can be provided.

Note that the housings 2700 and 2706 are examples of the appearance of a mobile phone, and the electronic device according to this embodiment can be modified into various modes depending on functions and uses.

  The results of manufacturing a memory element using the present invention and performing a transposition step are shown in this embodiment.

On a glass substrate, a titanium film as a first conductive layer, a polyimide film with a thickness of 1.5 μm covering a part of the first conductive layer as a partition, and a calcium fluoride film (CaF ₂ ) with a thickness of 1 nm as an insulating layer Samples 1 to 7 were manufactured by stacking an NPB film having a thickness of 10 nm as the organic compound layer and changing the material and the manufacturing method as the second conductive layer. As a comparative example, a sample using an aluminum film for the second conductive layer was manufactured. In this example, after forming a polyimide film on the first conductive layer so as to have an opening, oxygen (O ₂ ) ashing was performed to remove the polyimide residue on the first conductive layer.

As the second conductive layer, sample 1 is an indium film (thickness 200 nm), sample 2 is a laminate of an indium film (thickness 100 nm) and an aluminum film (thickness 200 nm), and sample 3 is an indium tin alloy of 10 wt% tin. Film 4 (thickness 200 nm), Sample 4 is an indium tin alloy film (thickness 200 nm) of 1 wt% tin, Sample 5 is an indium tin alloy film (thickness 100 nm) of tin 10 wt% and an aluminum film (thickness 200 nm). The laminated sample 6 is a magnesium indium alloy film (film thickness 150 nm) of 10 wt% magnesium, and the sample 7 is a manganese film (film thickness 80 nm). Samples 1, 2 and 7 are films formed by vapor deposition. The indium tin alloy films of Samples 3 to 5 are films formed by co-evaporation of indium and tin, and the magnesium indium alloy film of Sample 6 is a film of co-evaporation of indium and magnesium. The aluminum film of the comparative example was also formed by the vapor deposition method, and the film thickness was 200 nm. The area of the organic compound layer is about 100 mm ² in the sample. The area of the second conductive layer is about 170 mm ² . Note that in the indium tin alloy film, it is preferable that 0.1 wt% or more of tin is added to indium to reduce electrical resistance and to easily maintain conduction with an external terminal.

  An epoxy resin is applied by stencil printing on samples 1 to 7 prepared on a glass substrate and the memory element of the comparative example, and heated at 110 ° C. in a nitrogen atmosphere for 60 minutes to have a thickness of 100 to 200 μm. A layer was formed. Thereafter, samples 1 to 7 and the memory element of the comparative example were peeled off and transferred to the epoxy resin layer. The respective transposition states are shown in Table 1.

  In all of Samples 1 to 7 in the present example produced using the present invention, it was possible to peel in a good state with no film peeling and no peeling residue in visual recognition. On the other hand, in the memory element in which the aluminum film as the comparative example was produced as the second conductive layer, only the aluminum film was transferred to the epoxy resin layer, and the entire memory element could not be peeled from the glass substrate.

  Thus, since the memory element manufactured using this invention has favorable adhesiveness inside a memory element, it has confirmed that a peeling and transposition process can be performed in a favorable state. Therefore, since it can be freely transferred to various substrates, the range of substrate material selectivity is widened. In addition, an inexpensive material can be selected as the substrate, so that not only a wide function can be provided depending on the application, but also a semiconductor device can be manufactured at low cost.

  According to the present invention, a semiconductor device having a memory element with good adhesion inside a memory element that can perform a transposition process in a favorable state can be manufactured. Thus, a highly reliable semiconductor device can be manufactured with high yield without complicating the process.

  The results of manufacturing a memory element using the present invention and performing a transposition step are shown in this embodiment.

As in Example 1, a titanium film as a first conductive layer, a calcium fluoride (CaF ₂ ) film with a thickness of 1 nm as an insulating layer, and an NPB film with a thickness of 10 nm as an organic compound layer are stacked on a glass substrate, A second conductive layer was formed. In this example, an indium tin alloy film was formed as the second conductive layer by vapor deposition with a thickness of 200 nm using an indium tin alloy containing 5 wt% tin as a deposition source. The area of the organic compound layer is about 1 mm ² . The area of the second conductive layer is about 170 mm ² . In this example, after forming a polyimide film on the first conductive layer so as to have an opening, oxygen (O ₂ ) ashing was performed to remove the polyimide residue on the first conductive layer.

  An epoxy resin was applied to the memory element of this example formed on a glass substrate by stencil printing and heated at 110 ° C. for 60 minutes in a nitrogen atmosphere to form an epoxy resin layer having a thickness of 100 μm to 200 μm. Thereafter, the memory element of this example was peeled off and transferred to the epoxy resin layer.

  The memory element of this example manufactured using the present invention was able to be peeled off in a good state with no film peeling and no peeling residue.

  Thus, since the memory element manufactured using this invention has favorable adhesiveness inside a memory element, it has confirmed that a peeling and transposition process can be performed in a favorable state. Therefore, since it can be freely transferred to various substrates, the range of substrate material selectivity is widened. In addition, an inexpensive material can be selected as the substrate, so that not only a wide function can be provided depending on the application, but also a semiconductor device can be manufactured at low cost.

  According to the present invention, a semiconductor device having a memory element with good adhesion inside a memory element that can perform a transposition process in a favorable state can be manufactured. Thus, a highly reliable semiconductor device can be manufactured with high yield without complicating the process.

The figure explaining this invention. 6A and 6B illustrate a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. FIG. 10 illustrates a conventional semiconductor device. The figure explaining this invention. 6A and 6B illustrate a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention.

Claims (3)

Forming a first conductive layer on the substrate;
Oxidizing the surface of the first conductive layer;
Forming an organic compound layer on the first conductive layer subjected to the oxidation treatment;
Forming a second conductive layer on the organic compound layer to form a memory element including the first conductive layer, the organic compound layer, and the second conductive layer;
At least one of the first conductive layer and the second conductive layer includes one or more selected from indium, tin, lead, bismuth, calcium, manganese, and zinc .
A method for manufacturing a semiconductor device, wherein the second conductive layer is formed in an oxygen atmosphere . Forming a first conductive layer on a first substrate;
Oxidizing the surface of the first conductive layer;
Forming an organic compound layer on the first conductive layer subjected to the oxidation treatment;
Forming a second conductive layer on the organic compound layer to form a memory element including the first conductive layer, the organic compound layer, and the second conductive layer;
Bonding a flexible second substrate to the second conductive layer;
Peeling the memory element from the first substrate;
Bonding the memory element to a third substrate by an adhesive layer;
At least one of the first conductive layer and the second conductive layer includes one or more selected from indium, tin, lead, bismuth, calcium, manganese, and zinc .
A method for manufacturing a semiconductor device, wherein the second conductive layer is formed in an oxygen atmosphere . In claim 1 or claim 2 ,
The method for manufacturing a semiconductor device, wherein the first conductive layer is formed over the first substrate with a peeling layer interposed therebetween.

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