JP5121119B2 - Chip loading - Google Patents

Description

The present invention relates to a thin film integrated circuit formed on an insulating surface and a chip incorporating the thin film integrated circuit. In particular, the present invention relates to securities mounting the chip, other mounted items, and methods for manufacturing them.

In recent years, there is an increasing need for IC cards and IC tags that can exchange data without contact in all fields that require automatic recognition, such as securities and merchandise management. These IC cards and IC tags are small in size in terms of impact resistance, but are inexpensive for disposable applications, especially with a view to managing securities, the compatibility with paper, or the amount of information The increase in memory capacity is required due to the increase, and various technologies are being used on silicon substrates to develop IC chips that meet these requirements.

Proposal is made for a method of using such an IC chip, in which a fine IC chip is mounted on valuable securities to prevent unauthorized use, and it can be reused if it can be returned to a legitimate management source. (See Patent Document 1).
JP 2001-260580 A

However, an IC chip formed from a silicon wafer is more expensive than a magnetic card. As a result, it is limited to applications where added value is important, and is a factor that hinders its spread.

Further, when an IC card having an IC chip is provided with a function such as security, a CPU and a memory having a certain capacity are required, and the area of the IC chip is increased. Since an IC chip formed on a silicon wafer is thinly used for a card, there is a problem that the impact resistance is low. In particular, when the area of the IC chip is large, the reliability of the IC card is seriously affected.

In addition, since the chip formed on the silicon wafer is thick, when it is mounted on a product or a product, particularly a paper such as a banknote, or a label attached to the product or the product itself, the surface is uneven. As a result, the design of products and products has been degraded.

In view of the above, an object of the present invention is to provide an ID chip that realizes cost reduction and improvement in impact resistance and is excellent in design, a product on which the ID chip is mounted, and a manufacturing method thereof.

In view of the above-mentioned problems, the present invention has a thickness of 0.2 μm or less, typically 40 nm to 170 nm, preferably in containers such as securities including banknotes, belongings, food and drink (hereinafter referred to as products). Is equipped with an integrated circuit having a semiconductor film with a thickness of 50 nm to 150 nm (hereinafter referred to as a thin film integrated circuit). Since the thin film integrated circuit of the present invention is an extremely thin integrated circuit compared to a chip manufactured using a silicon wafer, the design is not impaired even when the thin film integrated circuit is mounted on a product or the like. The thickness of a thin film integrated circuit having such a semiconductor film is 0.3 to 3 μm as a whole, typically about 2 μm.

In addition, such a thin thin film integrated circuit has a light-transmitting property unlike a chip made of a silicon wafer. Therefore, it is preferable to mount a thin film integrated circuit on the surface of a product or the like without disturbing the display.

Since the thin film integrated circuit of the present invention is provided over an insulating surface, it can receive a highly sensitive signal without worrying about radio wave absorption as compared with a chip manufactured using a silicon wafer.

Examples of the substrate having an insulating surface include glass substrates such as barium borosilicate glass and alumino borosilicate glass, quartz substrates, and stainless steel substrates. Other substrates having an insulating surface include plastics typified by polyethylene-terephthalate (PET), polyethylene naphthalate (PEN), and polyethersulfone (PES), and flexible synthetic resins such as acrylic. There is a substrate that becomes. In the case where a thin film integrated circuit is formed over a substrate having such an insulating surface, the shape of the base substrate is not limited as compared with a chip manufactured using a silicon wafer in which the chip is extracted from a circular silicon wafer. Therefore, productivity of the thin film integrated circuit of the present invention can be improved and mass production can be performed. As a result, cost reduction of the thin film integrated circuit can be expected. A thin film integrated circuit having a very low unit price can generate a great profit by reducing the unit cost.

Note that securities include banknotes, stock certificates, checks, and the like. The chips of the present invention can be mounted on these securities. In addition, the chip of the present invention can be mounted on a certificate such as a driver's license, a family register copy, or a resident's card. As a result, unauthorized use of these can be prevented. In addition to securities, a thin film integrated circuit may be mounted on a container such as a food or drink. Containers such as food and drink include PET bottles, lunch boxes, medicine bottles, other containers, or labels attached to the containers. A thin film integrated circuit may be mounted on the property. There are bicycles, automobiles, etc. as belongings, and it is possible to prevent theft or to know the location after theft. Furthermore, a thin film integrated circuit may be mounted on a book, CD, video, or the like, and in particular, it may be mounted on a product to be lent. Lending procedures can be performed more quickly than barcode processing, and smooth information management can be performed. A thin film integrated circuit may be mounted on a wrapping paper for wrapping such products. In addition, information input to such a thin film integrated circuit, such as a message, can be read by a reader and displayed on a display device.

The chip of the present invention having such a thin film integrated circuit of the present invention is called an ID chip or a semiconductor device. In addition, the present invention can provide a chip having an antenna electrically connected to a thin film integrated circuit. An ID chip on which an antenna is mounted is also called a non-contact type ID chip (wireless chip). In particular, when used as a tag, it can also be called a wireless tag. Further, it can be called a hybrid ID chip in which a contact ID chip in which a terminal connected to an external power source is formed without mounting an antenna, and a non-contact type and a contact type. The chip of the present invention is characterized by having an integrated circuit having a semiconductor film having a thickness of 0.2 μm or less, and the effect of the present invention can be applied to any of a contact type, a non-contact type, and a hybrid type chip. Play.

In addition, the above-mentioned products and other products on which the chip of the present invention is mounted are referred to as chip-mounted products. A product on which an ID chip is mounted can be called an ID chip mounted product.

The specific present invention is characterized by a securities equipped with a chip including an integrated circuit having a semiconductor film having a thickness of 0.2 μm or less, and other chip mounted products.

Another embodiment of the present invention is a securities having a chip including an integrated circuit having a semiconductor film having a thickness of 0.2 μm or less, and other chip-mounted products, wherein the integrated circuit is formed by a droplet discharge method. Alternatively, it is characterized by securities having a ROM having a memory cell selected by a circuit connection formed by a laser cut method (connection by a wiring formed by these), and other chip mounted products. Note that the droplet discharge method is a method capable of selectively forming a pattern, and selectively discharges a droplet (also referred to as a dot) of a composition mixed with a material such as a conductive film or an insulating film (also referred to as a dot). This is a method of forming a pattern by jetting. Therefore, depending on the method, the droplet discharge method is called an ink jet drawing method, screen printing, or offset printing.

Another embodiment of the present invention is a securities having a chip including an integrated circuit having a semiconductor film having a thickness of 0.2 μm or less, and other chip-mounted products, wherein the integrated circuit is formed by a droplet discharge method. Or a securities having a first ROM having a memory cell selected by circuit connection formed by a laser cut method and a second ROM having a memory cell selected by circuit connection formed by a photolithography method, And other chip mounting features.

Another embodiment of the present invention is a securities equipped with a chip including an integrated circuit having a semiconductor film having a thickness of 0.2 μm or less, and other chip mounted objects, wherein the integrated circuit has characteristics of the semiconductor film. It is characterized by securities having a non-rewritable nonvolatile memory storing unique data based on variations, and other chip-mounted items. In this embodiment mode, the semiconductor film is formed of a crystalline semiconductor film, and unique data based on variation in characteristics of the crystalline semiconductor film can be stored.

Another embodiment of the present invention includes an integrated circuit including a semiconductor film having a thickness of 0.2 μm or less and an antenna provided over the integrated circuit, and the antenna is electrically connected to the integrated circuit. It features securities with other chips and other chips.

Another embodiment of the present invention includes an integrated circuit provided over a first substrate and having a semiconductor film having a thickness of 0.2 μm or less, and an antenna provided over the second substrate. Is characterized by securities carrying chips that are electrically connected to the integrated circuit, and other chip-mounted items.

In the present invention, the semiconductor film is provided on any insulating surface of a glass substrate, a quartz substrate, a stainless steel substrate, and a substrate made of a synthetic resin having flexibility.

In the present invention, the integrated circuit includes a thin film transistor including a semiconductor film.

A specific form of the present invention is a method for manufacturing securities and other chip-mounted products, in which a semiconductor film having a thickness of 0.2 μm or less is formed, and the semiconductor film is crystallized to form a crystalline semiconductor film. An integrated circuit having a crystalline semiconductor film is formed, and a chip having the integrated circuit is mounted.

The manufacturing method of the securities of the present invention having another form, and other chip-mounted objects includes forming a semiconductor film having a thickness of 0.2 μm or less, crystallizing the semiconductor film to form a crystalline semiconductor film, A metal wiring is formed on the crystalline semiconductor film using a photolithography method, a first memory cell selected by circuit connection using the metal wiring is formed, and a droplet discharge method or a laser is formed on the crystalline semiconductor film. A metal wiring is formed using a cutting method, and a second memory cell selected by circuit connection using the metal wiring is formed to form an integrated circuit, and a chip having the integrated circuit is mounted.

In another method of manufacturing the securities of the present invention and other chip-mounted products, a semiconductor film having a thickness of 0.2 μm or less is formed, and the semiconductor film is crystallized by a laser to form a crystalline semiconductor film Then, an integrated circuit having a crystalline semiconductor film is formed, and a chip having the integrated circuit is mounted.

According to another method of manufacturing the securities of the present invention and other chip-mounted products, a semiconductor film having a thickness of 0.2 μm or less is formed, a metal element is added so as to be in contact with the semiconductor film, and heating is performed. The first crystalline semiconductor film is crystallized to form a first crystalline semiconductor film, and the first crystalline semiconductor film is crystallized with a laser to form a second crystalline semiconductor film, and the second crystalline semiconductor film is integrated. A circuit is formed and a chip having an integrated circuit is mounted.

In such a manufacturing method of securities and other chip-mounted objects, a channel formation region of the semiconductor film is formed so that the laser irradiation direction and the carrier movement direction are aligned, and the direction perpendicular to the laser irradiation direction The chip may be mounted by being fixed so as to be bent. As a result, peeling and destruction of the thin film transistor can be prevented.

In such a manufacturing method of securities and other chip-mounted objects, an antenna electrically connected to the integrated circuit can be formed. The antennas may be formed symmetrically via an integrated circuit. Still further, the antenna may be formed on a second substrate, the second substrate may be folded so as to sandwich the integrated circuit, and the antenna may be formed symmetrically via the integrated circuit.

Since it is formed on the insulating surface, the cost of the chip, that is, the chip can be reduced as compared with the conventional silicon wafer. In particular, a chip made of a silicon wafer takes out the chip from a circular silicon wafer, so the shape of the base substrate is limited. On the other hand, in the chip of the present invention, the base substrate is an insulating substrate such as glass, and the shape is limited. There is no. Therefore, productivity can be increased and mass production can be performed. As a result, further cost reduction can be expected. An integrated circuit with a very low unit price, such as a chip, can generate very large profits by reducing unit cost.

Further, since a thin film integrated circuit can be formed on a substrate made of a synthetic resin having flexibility, an improvement in impact resistance of the chip can be expected.

Further, unlike the conventional silicon wafer, the thin film integrated circuit of the present invention is a very thin integrated circuit and can further have translucency, so that the design is not impaired even when it is attached to a product or the like. .

Such a thin film integrated circuit of the present invention can perform information transactions or information management in a short time compared to information providing means such as a barcode, and can provide a wide variety of information.

Embodiments of the present invention will be described below with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of this embodiment mode. Note that in all the drawings for describing the embodiments, the same portions or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted. In the following embodiment, in order to emphasize the chip, it is described in a shape that is much larger than the actual size.

(Embodiment 1)
In this embodiment, a product that is an ID chip mounted product will be described. Further, the position and shape for mounting the ID chip and the number of ID chips to be mounted are not limited to the present embodiment.

If a memory such as a ROM that cannot rewrite data is formed in the thin film integrated circuit of the ID chip, such as securities such as banknotes, checks, family register copies, residence cards, traveler's checks, passports Counterfeiting can be prevented. Further, for example, the use of the wireless tag of the present invention for food products whose merchandise value is greatly influenced by the production area, the producer, etc. is useful for preventing impersonation of the production area, the producer, and the like. Note that the wireless tag of the present invention can be provided at a lower cost than an IC chip formed from a silicon wafer.

Below, the case where ID chip is mounted in various goods is demonstrated.

FIG. 1A shows a bill 101 on which an ID chip is mounted. In FIG. 1A, the ID chip 102 is attached to the inside of the bill 101, but may be exposed to the front.

Moreover, you may print a banknote using the ink containing the ID chip of this invention. Still further, when the bill material and the medicine are mixed, the ID chip may be dispersed to form a bill having a plurality of ID chips. Since the ID chip of the present invention is low in cost, even if a plurality of ID chips are mounted, the production cost of banknotes can be reduced.

Moreover, you may mount ID chip in coins other than a banknote.

FIG. 1B shows a check 111 on which an ID chip is mounted. In FIG. 1B, the ID chip 112 is exposed on the surface of the check 111. Since the ID chip of the present invention has translucency, it may be provided exposed on the surface of the check 111. Of course, the ID chip 112 may be attached inside the check 111.

A check may be printed using ink containing the ID chip of the present invention. Furthermore, when the check material and the medicine are mixed, the ID chip may be dispersed to be a check having a plurality of ID chips. Since the ID chip of the present invention is low-cost, even if a plurality of ID chips are mounted, the manufacturing cost of the check is less affected.

FIG. 1C shows a stock certificate 121 on which an ID chip is mounted. In FIG. 1C, the ID chip 122 is attached to the inside of the stock certificate 121, but may be exposed to the front. Further, the size and shape of the ID chip (the shape together) and the mounting position are not limited. However, when the amount of information is large, the shape of the ID chip may be increased.

In addition, stock certificates may be printed using ink containing the ID chip of the present invention. Furthermore, when the stock certificate material and the medicine are mixed, the ID chip may be dispersed to provide a stock certificate having a plurality of ID chips. Since the ID chip of the present invention is low-cost, even if a plurality of ID chips are mounted, the production cost of stock certificates can be reduced.

As described above, since the ID chip is formed using a very thin thin film integrated circuit, the ID chip can be mounted on a very thin paper-like product. For this reason, the design of the product is not impaired. Further, since the ID chip has translucency, it may be mounted on the product surface.

FIG. 2A shows a license 131 on which an ID chip is mounted. In FIG. 2A, the ID chip 132 is attached to the inside of the license 131, and the ID chip can also be attached under the laminate covering the license 131. Since the ID chip of the present invention has translucency, it may be provided on the printing surface of the license 131.

FIG. 2B shows an insurance card 141 equipped with an ID chip. In FIG. 2B, the ID chip 142 is attached to the inside of the insurance card 141. However, the ID chip may be attached to the surface of the insurance card 141. Since the ID chip of the present invention has translucency, it may be provided on the printed surface of the insurance card 141.

FIG. 2C shows a passport 151 on which an ID chip is mounted. Although the ID chip 152 is attached to the cover of the passport 151 in FIG. 2C, it may be attached to another page. Further, the ID chip may be attached to the inside of the cover or the like or attached to the surface. Since the ID chip of the present invention has translucency, it may be provided on the printing surface of the passport 151.

Unauthorized use can be prevented by mounting an ID chip on the product as described above. Moreover, management of goods can be simplified by the ID chip. Furthermore, since information or the like can be stored in the ID chip without directly filling in a product (passport), privacy can be protected. Of course, since a very thin thin film integrated circuit is used, the design of the product (passport) is not impaired. Further, since the ID chip has translucency, it may be mounted on the surface of a product (passport).

FIG. 3A shows a display label 163 on which an ID chip is mounted and a meat pack 161 to which the display label 163 is attached. The ID chip 162 may be exposed on the surface of the display label 163 or may be attached inside. In the case of fresh food such as vegetables, an ID chip may be attached to a wrap that covers the fresh food. If the price of the product is written as data on the ID chip, the product can be settled more easily and in a shorter time than the conventional method using a barcode. That is, unlike a conventional barcode, in the case of a product on which an ID chip is mounted, a plurality of products can be settled at once. Furthermore, the ID chip enables the payment of the product even if the distance between the register and the product is long, and also helps prevent shoplifting. Of course, the ID chip can be written with basic information about the product, such as the product's production location, producer, processing date, expiration date, and other information such as cooking examples using the product. When the ID chip and the barcode are used in combination, information that does not need to be rewritten, such as the basic information, is input to the barcode, and the rewritable information is written to the ID chip.

FIG. 3B shows a display label 173 on which an ID chip is mounted and a PET bottle 171 to which the display label is attached. The ID chip 172 may be exposed on the surface of the display label 173 or may be attached inside. The ID chip 172 may be attached to the lid of the plastic bottle 171. Furthermore, the ID chip 172 may be provided inside the PET bottle 171. For example, in the case of a plastic bottle composed of a plurality of layers, the ID chip 172 can be attached between the layers.

FIG. 3C illustrates a display label 183 on which an ID chip is mounted and a medicine bottle 181 on which the display label is attached. The ID chip 182 may be exposed on the surface of the display label 183 or may be attached inside. Further, the ID chip 182 may be attached to the lid of the medicine bottle 181. In the case where the product is a medicine, the ID chip 182 may be written with the medicine taking method, effects, side effects, allergy information, and the like as data.

Since consumers want to obtain information regarding such products at the time of purchase, it is preferable to install a reader and a display device at the store. Further, an electronic device carried by a consumer may have a reader function and a display device function. For example, a mobile phone or PDA may have a reader function and information may be displayed on the screen.

Further, since the ID chip of the present invention is inexpensive, it is also suitable for applications that are eventually discarded by consumers. In particular, the inexpensive ID chip of the present invention is very useful for a product in which a difference in price in units of several yen or several tens of yen greatly affects sales.

FIG. 4A shows a stuffed animal 191 equipped with an ID chip. The ID chip 192 can be attached inside the stuffed animal. The ID chip 192 may be attached to the surface of the stuffed animal 191 pupil or nose. Since the ID chip of the present invention has translucency, it can be provided on the surface of the stuffed animal 191. If the stuffed animal is lost or stolen by the ID chip, the location can be confirmed.

FIG. 4B illustrates a bicycle 1201 as an example of a vehicle on which an ID chip is mounted. The ID chip 1202 can be attached inside the saddle. The ID chip can also be attached to a handle, pedal or tire. With the ID chip, if the bicycle is lost or stolen, the location can be confirmed.

FIG. 4C illustrates an umbrella 211 on which an ID chip is mounted. The ID chip 212 can be mounted inside a branch or cloth. The ID chip can also be attached to the surface of a branch or cloth.

As shown in FIG. 24, an ID chip 1702 is mounted on a bag 1701. For example, the ID chip 1702 can be mounted on the bottom or part of the side surface of the bag 1701. Since the ID chip is very thin and small, it can be mounted without deteriorating the design of the bag. In addition, since the ID chip can have translucency, it is difficult for a thief to determine whether the ID chip is mounted. Therefore, there is little possibility that the ID chip is removed by the theft.

When such an ID chip-mounted product is stolen, information on the current position of the mounted product can be obtained using, for example, GPS (Global Positioning System). GPS is a system that captures a signal sent from a GPS satellite, obtains a time difference thereof, and performs positioning based on the time difference.

In addition to stolen merchandise, it is possible to obtain information on the current position of forgotten or lost items using GPS.

By mounting the ID chip on such personal property, the location at the time of loss or theft can be confirmed.

Moreover, you may attach an ID chip to the wrapping paper which wraps such a property. Further, a message can be written as voice data in the ID chip. In this case, information can be read by a reader and a message can be heard by a playback device.

FIG. 5A shows a book 221 mounted with an ID chip. The ID chip 222 can be provided on the surface or inside of the book cover. An ID chip may be mounted on other pages of the book.

FIG. 5B shows a DVD 231 mounted with an ID chip. The ID chip 232 can be provided on the surface of or inside the DVD package. Needless to say, an ID chip may be mounted on a product such as a CD or a video instead of the DVD.

By mounting an ID chip on a product for which such rental business is actively carried out, the lending process and the return process can be performed easily and in a short time. In addition, information such as product contents, advertisements, and performers can be written in the ID chip as data.

Moreover, the shape of the ID chip of the present invention can be changed to some extent in accordance with the shape of the object to be attached. Therefore, the wireless tag of the present invention is not limited to the application shown in this embodiment mode and can be used for various other applications. Further, since it is more flexible than a wireless tag using an IC chip formed from a silicon wafer, the mechanical strength can be increased.

Next, a case where an ID chip is mounted on a product such as a beer bottle for distribution management will be described. As shown in FIG. 25A, an ID chip 712 is mounted on a beer bottle 711. For example, an ID chip can be mounted using the label 713.

In the ID chip 712, basic items such as a manufacturing date, a manufacturing place, and a material used are recorded. Such basic matters do not need to be rewritten, and are preferably recorded using a non-rewritable memory such as a mask ROM. In addition, individual items such as the delivery destination and delivery date and time of each beer bottle are recorded in the ID chip. For example, as shown in FIG. 25B, when each beer bottle flows by the belt conveyor 714 and passes through the writer device 715, each delivery destination and delivery date and time can be recorded. Such individual items may be recorded using a rewritable and erasable memory such as an EEPROM.

When product information purchased from a delivery destination is transmitted to the distribution management center through the network, based on this product information, the writer device or a personal computer that controls the writer device calculates the delivery destination and delivery date and time. A system that records on a chip should be constructed.

Moreover, since delivery is performed for each case, an ID chip may be mounted for each case or for each of a plurality of cases, and individual items may be recorded.

By installing an ID chip in such a beverage product in which a plurality of delivery destinations can be recorded, the time required for manual input can be reduced, and input errors caused by the time can be reduced. In addition, labor costs that are the most expensive in the field of logistics management can be reduced. Therefore, by mounting the ID chip, it is possible to carry out low-cost logistics management with few mistakes.

Furthermore, application items such as foods suitable for beer and cooking methods using beer may be recorded at the delivery destination. As a result, it can serve as an advertisement for foods and the like, and the consumer's willingness to purchase can be enhanced. Such application items may be recorded using a rewritable and erasable memory such as an EEPROM. By mounting the ID chip in this way, information that can be provided to the consumer can be increased, so that the consumer can purchase the product with peace of mind.

Next, in order to perform manufacturing management, a manufactured product on which an ID chip is mounted and a manufacturing apparatus (manufacturing robot) controlled based on information on the ID chip will be described.

Currently, there are many scenes where original products are produced, and production is performed on the production line based on the original information of the products. For example, in an automobile production line in which a door paint color can be freely selected, an ID chip is mounted on a part of the automobile, and the coating apparatus is controlled based on information from the ID chip. And it is possible to produce cars with originality.

As a result of mounting the ID chip, it is not necessary to adjust the order of the cars to be put on the production line or the number having the same color in advance. For this reason, it is not necessary to set a program for controlling the painting apparatus to match the order and number of cars. That is, the manufacturing apparatus can operate individually based on the information of the ID chip mounted on the automobile.

Thus, the ID chip can be used in various places. And the specific information regarding manufacture can be obtained from the information recorded on the ID chip, and the manufacturing apparatus can be controlled based on the information.

FIG. 6 shows a cross-sectional view of a product on which an ID chip is mounted.

FIG. 6A shows a cross-sectional view of the banknote 101 on which the ID chip shown in FIG. In this state, the ID chip 102 is attached to the inside of the bill 101.

FIG. 6B shows a cross-sectional view of the check 111 on which the ID chip shown in FIG. 1B is mounted. The ID chip 112 is attached to the surface of the check 111. More preferably, an insulating film 115 is provided so as to cover the check 111.

FIG. 6C shows a cross-sectional view of the license 131 on which the ID chip shown in FIG. The ID chip 132 is attached so as to be sandwiched between 131 license boards. An insulating film 135 is provided so as to cover the license 131.

When an ID chip is mounted on such a sheet-like product, the ID chip is arranged at the center of the product to be mounted (mounting product), and the periphery of the ID chip is formed so as to be covered with the product material. Good. As a result, the mechanical strength of the ID chip can be increased. Specifically, the position where the ID chip is sandwiched (the center of the ID chip): X satisfies (1/2) · D−30 μm <X <(1/2) · D + 30 μm where D is the thickness of the mounted product. It is good to arrange like this.

In this way, a wide variety of information can be provided by an ID chip on which a very thin thin film integrated circuit is mounted. In addition, information transactions or information management can be performed easily and in a short time by the ID chip. Furthermore, even when an ID chip is attached to a product container together with a label, the design is not impaired because it is very thin.

Further, the thin film integrated circuit of the present invention does not need to be subjected to a back grinding process that causes cracks or polishing marks unlike an integrated circuit manufactured using a silicon wafer. Furthermore, since the thickness variation of the thin film integrated circuit according to the present invention also depends on variations in the film formation of the semiconductor film or the like, it is about several hundred nm at the maximum, and several to several by the back grinding process. Compared with the variation of 10 μm, it can be remarkably reduced.

In addition, the ID chip of the present invention can be formed at a lower cost than a chip made of a silicon wafer. This is because it can be formed on an inexpensive base substrate such as a glass substrate. In addition, since a chip made of a silicon wafer takes out the chip from a circular silicon wafer, the shape of the base substrate is limited. On the other hand, in the ID chip of the present invention, the base substrate is an insulating substrate such as glass, and the shape is There are no restrictions. Therefore, productivity can be improved and cost reduction can be achieved, and the shape and size of the ID chip can be set freely.

In view of the material for forming the ID chip, a low-cost and safe material is used as compared with a chip formed from a silicon wafer. Therefore, the need for collecting used ID chips is low and it is environmentally friendly. Further, when the ID chip is discarded, it has a certain area, so that it can be cut with scissors or the like, and unauthorized use can be prevented.

In addition, an IC chip manufactured using a silicon wafer may cause radio wave absorption by the silicon wafer, and signal sensitivity may be a problem. In particular, there is a concern about radio wave absorption for the commonly used radio wave of 13.56 MHz or 2.45 GHz. On the other hand, since the ID chip of the present invention is formed on an insulating substrate such as glass, radio wave absorption does not occur. As a result, a highly sensitive ID chip can be formed. If it is strong, the area of the antenna which the ID chip of this invention has can be made small, and size reduction of an ID chip can be expected.

In addition, a chip formed on a silicon wafer has a semiconducting property, so that the junction is likely to be forward-biased with respect to AC radio waves, and it is necessary to take measures against latch-up. On the other hand, since the ID chip of the present invention forms a thin film integrated circuit on an insulating substrate, there is no such concern.

The contactless ID chip on which the antenna is mounted has been described above. However, only a thin film integrated circuit may be mounted on a product and a contact ID chip on which a terminal connected to an external power source is formed may be mounted. A hybrid type ID chip in which a non-contact type and a contact type are mixed may be mounted. This is because the present invention is characterized by a thin thin film integrated circuit formed on an insulating surface, and the above-described effects are exhibited even in a contact type, a non-contact type, and a hybrid type.

(Embodiment 2)
In order to function as a non-contact type ID chip, a thin film integrated circuit and an antenna are required as described above. The antenna can have various arrangements, and a connection terminal for connecting to the thin film integrated circuit is preferably provided at the tip of the antenna. In this embodiment mode, an antenna shape, an antenna manufacturing method, and a mounting mode in the case of mounting an antenna on an ID chip will be described.

First, the shape of the antenna will be described.

For example, an antenna 515 provided over a substrate (hereinafter referred to as an antenna substrate) 516 for providing an antenna is provided so as to be wound, and a connection terminal 517 is provided at each end. The connection terminal 517 may be provided anywhere, and the arrangement of each connection terminal can be determined in accordance with the connection terminal on the thin film integrated circuit side.

The antenna 515 may be provided so as to meander on a rectangle. A connection terminal 517 is preferably provided at the tip of the antenna 515. The connection terminal 517 may be provided anywhere, and the arrangement of each connection terminal can be determined in accordance with the connection terminal on the thin film integrated circuit side. The connection terminals may be provided so as to be separated from each other or close to each other.

The antenna 515 may be arranged in a circular shape without being arranged in a rectangular shape.

Next, a method for manufacturing the antenna will be described.

The antenna 515 is formed on the antenna substrate 516 so as to be arranged as described above. As the antenna material, a conductive material such as Ag (silver), Al (aluminum), Au (gold), Cu (copper), or Pt (platinum) can be used. When using Al or Au having relatively high resistance, there is a concern about wiring resistance. However, when the antenna 515 is thick or the antenna formation area is large, the wiring resistance can be reduced by increasing the width of the antenna 515. For a conductive material such as Cu that is likely to be diffused, an insulating film functioning as a protective film may be formed so as to cover the surface on which the antenna 515 is formed or the periphery of Cu. The antenna 515 can be formed by any one of a sputtering method, a droplet discharge method, a printing method, a plating method, a photolithography method, and a vapor deposition method using a metal mask. In particular, when an antenna is formed by a droplet discharge method, a printing method, or a plating method, the manufacturing process can be reduced because the conductive film does not need to be patterned.

More preferably, pressure is applied to the antenna 515 to improve flatness. As a result, the antenna 515 can be thinned. In addition to the pressurizing means, a heating means may be provided, and the pressurization process and the heat treatment can be performed simultaneously.

Alternatively, an opening may be formed in the antenna substrate 516, and the antenna 515 may be formed in the opening. Since the antenna 515 can be formed in the opening, the antenna substrate 516 can be thinned.

Next, a specific method for mounting the antenna and the thin film integrated circuit will be described.

The antenna substrate formed based on the above embodiment and a thin film integrated circuit are mounted. As shown in FIG. 7A, a set of antenna substrates 516 provided with an antenna 515 is prepared. The thin film integrated circuit 501 is disposed between the antenna substrates 516, that is, the antenna substrate 516 is disposed so as to be symmetrical via the thin film integrated circuit 501. Note that the direction of the current flowing through the antenna is the same among the plurality of antennas. Therefore, the direction in which the antenna is wound is preferably symmetric with respect to the thin film integrated circuit 501. Thereafter, the connection terminals 517 for the antenna 515 and the thin film integrated circuit 501 are fixed so as to be connected to each other. You may use the wire bonding method for the means to connect. The ID chip is completed.

FIG. 7B shows a method for mounting a thin film integrated circuit by a method different from that shown in FIG.

As shown in FIG. 7B, an antenna substrate 516 provided with a pair of antennas 515 is prepared. As the antenna substrate 516, a flexible substrate that can be folded from the center, for example, a substrate such as polyethylene terephthalate (PET), vinylidene chloride, or vinyl chloride resin is used.

After that, the antenna substrate 516 is folded so that the thin film integrated circuit 501 is interposed therebetween. In order to facilitate folding, it is preferable to form a cut or a recess in the fold of the antenna substrate. Thereafter, the connection terminals 517 for the antenna 515 and the thin film integrated circuit 501 are fixed so as to be connected. You may use the wire bonding method for the means to connect. Then, the ID chip 522 is completed.

By providing a set of antennas, one antenna can be used for the power generation circuit and the other antenna can be used for the modulation circuit. As a result, an antenna can be set for each circuit, and the communication distance and sensitivity can be increased.

Further, in order to connect the thin film integrated circuit to a set of antennas in this way, it is necessary to form connection terminal portions on both surfaces (upper surface and lower surface) of the thin film integrated circuit. It is necessary to provide an insulating film that functions as a protective film so that the antennas do not short-circuit. An organic material or an inorganic material can be used for the insulating film. As the organic material, polyimide, acrylic, polyamide, polyimide amide, resist, benzocyclobutene, siloxane, or polysilazane can be used. Siloxane has a skeletal structure with a bond of silicon (Si) and oxygen (O), and the substituent contains at least hydrogen, or the substituent has at least one of fluorine, alkyl groups, and aromatic hydrocarbons. A polymeric material having a starting material. Polysilazane is formed using a polymer material having a bond of silicon (Si) and nitrogen (N), that is, a liquid material containing so-called polysilazane as a starting material. As the inorganic material, silicon oxide or silicon nitride can be used. The insulating film can be formed by a plasma CVD method, a low pressure CVD method, a droplet discharge method, a spin coating method, or a dip method. In the case of using a highly viscous raw material, it is preferable to use a droplet discharge method, a spin coating method, or a dip method. Further, a conductive resin may be applied between the connection terminal portions, and an insulating resin may be applied to other regions.

Alternatively, by opening a contact in the antenna substrate and forming the connection terminal portion of the antenna on the back surface (the surface where no antenna is provided) of the antenna substrate, the antennas can be prevented from short-circuiting.

In this embodiment mode, the case where a thin film integrated circuit is mounted between a pair of antenna substrates has been described. However, a thin film integrated circuit may be mounted on one antenna substrate.

Unlike this embodiment, an antenna may be formed over a thin film circuit through an insulating film provided over the thin film integrated circuit without using an antenna substrate.

Next, so-called multi-chamfering, in which a plurality of ID chips are produced from a large substrate will be described.

For example, a plurality of (for example, 25) thin film integrated circuits are formed on a large substrate. A large substrate is placed between the antenna substrates and fixed so that the connection terminals of each thin film integrated circuit and the connection terminals of each antenna are connected.

Thereafter, a plurality of ID chips are formed on a large substrate and separated by scribing or dicing to complete one ID chip. A laser may be used for separating the ID chip. In particular, when cutting an ID chip, it is considered that it is less susceptible to damage at the time of cutting than a chip formed on a silicon wafer. Therefore, the cutting area of the ID chip can be made smaller than the cutting area of the chip formed on the silicon wafer. As a result, the antenna formation area can be increased. Thereafter, the ID chip may be further sealed with an insulating film functioning as a sealing film.

Thus, by obtaining a plurality of ID chips from a large substrate, the cost of the ID chip can be reduced. An integrated circuit with a very low unit price, such as a chip, can make a huge profit by reducing costs.

For example, the number of picks and the like are compared between when a silicon wafer having a diameter of 12 inches is used and when a glass substrate of 7300 × 9200 mm ² is used. The area of the former silicon substrate is about 73000 mm ² , while the area of the latter glass substrate is about 672000 mm ² , and the glass substrate corresponds to about 9.2 times the silicon substrate. When the area of the latter glass substrate is about 672000 mm ² , ignoring the area consumed by dividing the substrate, it is calculated that about 672,000 1 mm square ID chips can be formed, and the number is about 9.2 times that of the silicon substrate. It is equivalent to the number of The capital investment for mass production of ID chips requires fewer steps when a 7300 × 9200 mm ² glass substrate is used than when a silicon substrate having a diameter of 12 inches is used. Can be done in a third.

Next, a completed form of the ID chip will be described. Further, the case where the antenna substrate is provided over the thin film integrated circuit without using the antenna substrate will be described.

As shown in FIG. 8A, a region (thin film integrated circuit region) 501 including a thin film integrated circuit or the like is formed over a substrate 500 having an insulating surface. An antenna 515 is formed over the thin film integrated circuit region with an insulating film 518 interposed therebetween. The antenna 515 can be formed by, for example, a droplet discharge method. The insulating film 518 can be formed in a manner similar to that of the insulating film functioning as a protective film so that the antennas 515 are not short-circuited. The antenna connection terminal and the thin film integrated circuit connection terminal must be connected. Therefore, for example, a contact hole is formed in the insulating film 518, and a connection terminal provided in the antenna 515 and a connection terminal of the thin film integrated circuit 501 are connected. At this time, you may connect via a conductive resin.

After that, as shown in FIG. 8B, an insulating film 519 functioning as a protective film is formed so as to cover the thin film integrated circuit 501 and the antenna 515. The insulating film 519 can be formed in a manner similar to the insulating film functioning as a protective film so that the antennas are not short-circuited. As a result of providing the insulating film 519, the thin film integrated circuit 501 can be protected from the outside, and an ID chip having a form that is easy to carry can be completed. Further, the function of the thin film integrated circuit 501 can be assisted by covering with an insulating film 519.

FIG. 9A is a cross-sectional view taken along a line AB in FIG. A thin film integrated circuit 501 provided over a substrate 500 having an insulating surface, an insulating film 518 provided over the thin film integrated circuit 501, an antenna 515 provided over the insulating film 518, and a protection provided so as to cover the antenna 515 An insulating film 530 functioning as a film is sequentially formed, and an insulating film 519 is provided to cover these films. Although not shown, a contact hole is formed in the insulating film 518 as described above, and the antenna 515 and the thin film integrated circuit 501 are electrically connected by connecting the connection terminal of the antenna 515 and the connection terminal of the thin film integrated circuit 501. Can be connected to.

By forming the antenna on the thin film integrated circuit, the ID chip can be miniaturized.

In addition, an ID chip having a form other than those shown in FIGS. 8 and 9A can be completed.

For example, as illustrated in FIG. 9B, an antenna 515b may be provided on the insulating film 519 side. The antenna 515 b is covered with an insulating film 530 b that functions as a protective film, and a contact hole is provided in a region connected to the thin film integrated circuit 501. Further, a pad is provided as the connection terminal 517 on the thin film integrated circuit 501 side, and the antenna 515 can be connected through a conductive resin 532.

In this manner, by forming the antenna 515 on the insulating film 519 side and forming it separately from the thin film integrated circuit 501, the yield is improved.

As shown in FIG. 9C, an antenna 515 provided over the thin film integrated circuit 501 and an antenna 515b provided on the insulating film 519 side may be formed together. In this case, in the insulating film 530 covering the antenna 515, a contact hole is provided in a region connected to the antenna 515b, and in the insulating film 530b covering the antenna 515b, a contact hole is provided in a region connected to the antenna 515. Then, the antenna 515 and the antenna 515b can be connected to each other through the conductive resin 532. Note that the conductive resin 532 may be provided at a plurality of positions or in a wide range between the antenna 515 and the antenna 515b. As a result, the resistance of the antenna can be lowered.

When antennas are provided on a plurality of surfaces in this way, the directions of currents flowing through the antennas are directions that do not cancel each other's magnetic field.

When a plurality of antennas are provided, they can be connected in series or in parallel. When connected in series, the inductance of the antenna can be increased. Further, when connected in parallel, the resistance of the antenna can be lowered.

With such a structure in which the antenna is formed in many regions, a highly sensitive ID chip can be formed.

Note that in FIG. 9, a space is formed in the thin film integrated circuit 501 and the insulating film 519, but the insulating film 530 functions as a protective film filled so as to cover the antenna in the space. Or resin may be provided. As a result, the strength of the thin film integrated circuit 501 can be increased.

Further, even a thin film integrated circuit which is integrally formed an antenna, 5 mm square (25 mm ²⁾ or less, preferably to a 0.3mm square (0.09 mm ²⁾ to 4 mm square (16 mm ^2). Since a very small thin film integrated circuit can be formed in this way, it can be mounted in a minute recess or the like.

As described above, the ID chip can have various configurations.

(Embodiment 3)
In this embodiment, a case where an ID chip is mounted on a curved surface of a product will be described.

FIG. 10A illustrates a plurality of thin film integrated circuits 501 provided over a large substrate 500 having an insulating surface. The cost of a thin film integrated circuit, that is, an ID chip can be reduced by so-called multi-sided drawing of a plurality of thin film integrated circuits.

The semiconductor film included in the thin film integrated circuit has any state selected from an amorphous semiconductor, a semi-amorphous semiconductor in which an amorphous state and a crystalline state are mixed (also referred to as SAS), and a crystalline semiconductor. May be. SAS includes a microcrystalline semiconductor capable of observing a crystal grain of 0.5 nm to 20 nm in an amorphous semiconductor, and in particular, a microcrystal capable of observing a crystal of 0.5 nm to 20 nm. The state is called a so-called microcrystal (μc).

In this embodiment, an amorphous semiconductor film is formed and a crystalline semiconductor film crystallized by heat treatment is formed. The heat treatment can be a heating furnace, laser irradiation, irradiation of light emitted from a lamp instead of laser light (hereinafter referred to as lamp annealing), or a combination thereof.

In the case of using a heating furnace, the amorphous semiconductor film is heated at 500 to 550 ° C. for 2 to 20 hours. At this time, the temperature may be set in multiple stages in the range of 500 to 550 ° C. so that the temperature gradually increases. In the first low-temperature heating step, hydrogen or the like of the amorphous semiconductor film comes out, so that so-called hydrogen dipping that reduces film roughness during crystallization can be performed. Furthermore, it is preferable to form a metal element that promotes crystallization, such as Ni, on the amorphous semiconductor film because the heating temperature can be reduced. Even when a metal element is used, high-temperature heating at 600 to 950 ° C. may be performed.

However, when a metal element is formed, there is a concern that the electrical characteristics of the semiconductor element may be adversely affected. Therefore, it is necessary to perform a gettering step for reducing or removing the metal element. For example, a process may be performed so as to capture a metal element using an amorphous semiconductor film as a gettering sink.

When laser irradiation is used, a continuous wave laser (CW laser) or a pulsed laser (pulse laser) can be used. Lasers include Ar laser, Kr laser, excimer laser, YAG laser, Y ₂ O ₃ laser, YVO ₄ laser, YLF laser, YAlO ₃ laser, glass laser, ruby laser, alexandride laser, Ti: sapphire laser, copper vapor One or a plurality of lasers or gold vapor lasers can be used. The beam shape of the laser is preferably linear, and the length of the long axis may be 200 to 350 μm. Further, the laser may have an incident angle θ (0 ° <θ <90 °) with respect to the semiconductor film.

Note that continuous wave fundamental laser light and continuous wave harmonic laser light may be emitted, or continuous wave fundamental laser light and pulsed harmonic laser light are emitted. You may do it.

In addition, it is a pulse oscillation type laser that oscillates laser light at an oscillation frequency that can irradiate the laser light of the next pulse after the semiconductor film is melted by the laser light and solidifies in the scanning direction. Crystal grains grown continuously can be obtained. That is, a pulse beam that defines a lower limit of the oscillation frequency may be used so that the period of pulse oscillation is shorter than the time from when the semiconductor film is melted until it is completely solidified.

The oscillation frequency of the pulse beam that can be actually used is 10 MHz or more, and a frequency band that is significantly higher than the frequency band of several tens to several hundreds Hz that is normally used is used.

Note that laser light may be irradiated in an inert gas atmosphere such as a rare gas or nitrogen. Thereby, roughness of the semiconductor surface due to laser light irradiation can be suppressed, and variation in threshold value caused by variation in interface state density can be suppressed.

Alternatively, a crystalline semiconductor film may be formed directly on the surface to be formed. In this case, a crystalline semiconductor film is directly formed on the surface to be formed using heat or plasma using a fluorine-based gas such as GeF ₄ or F ₂ and a silane-based gas such as SiH ₄ or Si ₂ H _6. Can be formed. At this time, when the heating temperature is high, a quartz substrate with high heat resistance is preferably used.

Alternatively, a microcrystalline semiconductor film may be formed using SiH ₄ and F ₂ , or SiH ₄ and H ₂ , and then crystallized by performing laser irradiation as described above.

In this embodiment mode, heat treatment is performed using laser irradiation. As shown in FIG. 10A, by scanning a laser irradiation region 502 in a rectangular shape 503, the amorphous semiconductor film on the entire surface can be crystallized to form a crystalline semiconductor film.

As shown in FIG. 10B, in the thin film integrated circuit 501, a thin film transistor 510 including a plurality of crystalline semiconductor films is formed. The thin film transistor includes a source and drain electrode 511, a channel formation region 512, a gate electrode 514, and a crystalline semiconductor film, and the crystalline semiconductor film includes an impurity region and a gate electrode 514 provided below the source and drain electrodes 511. A channel formation region 512 is provided below. At this time, it is preferable to form the source and drain electrodes 511 and the gate electrode 514 so that the carrier moving direction 513 is aligned with the laser beam scanning direction (irradiation direction) 503 in the channel formation region.

As shown in FIG. 10C, an antenna 515 and an antenna connection terminal 517 are formed over a thin film integrated circuit 501, and an ID chip 522 is formed. At this time, the contactless ID chip on which the antenna is mounted is obtained.

When the ID chip 522 is bent, it may be bent in a direction perpendicular to the laser scanning direction 503. That is, the ID chip 522 is bent in a direction perpendicular to the carrier moving direction 513. By bending the ID chip 522 in such a direction, the thin film integrated circuit, in particular, the thin film transistor is not destroyed.

Thereafter, as shown in FIG. 10D, the ID chip 522 is fixed to the product 521 having a curved surface. At this time, the ID chip can be fixed by the adhesive of the label 523.

In addition, the semiconductor film used in the integrated circuit of the present invention differs from a chip formed from a silicon wafer in that hydrogen is 1 × 10 ¹⁹ to 1 × 10 ²² , preferably 1 × 10 ^{19 to} 5 × 10 ²⁰ / cm ^3. It is characterized by having. Hydrogen can alleviate defects in the semiconductor film, and has a so-called defect termination effect. In addition, the flexibility of the ID chip can be increased by hydrogen. Further, halogen may be added instead of hydrogen.

Therefore, when a thin film integrated circuit is formed on a flexible substrate or bent, the integrated circuit can be prevented from being broken.

Furthermore, in the ID chip, the proportion of the area occupied by the patterned semiconductor film in the thin film integrated circuit is 1 to 30%, so that the thin film transistor can be prevented from being broken or peeled off due to bending stress.

In this embodiment, the case of mounting a non-contact type ID chip on which an antenna is mounted has been described, but either a contact type ID chip or a hybrid type ID chip may be used. Further, as a method for mounting an antenna, for example, a label may be used as an antenna substrate, and a thin film integrated circuit may be transferred to the label and then mounted on a product.

(Embodiment 4)
In this embodiment mode, a specific method for manufacturing a thin film integrated circuit including a TFT will be described with reference to FIGS. Here, for the sake of simplicity, a manufacturing method will be described by showing a cross-sectional structure of a CPU and a memory portion using n-type TFTs and p-type TFTs.

First, as illustrated in FIG. 21A, a separation layer 61 is formed over a substrate 60. Here, an a-Si film (amorphous silicon film) having a thickness of 50 nm is formed on a glass substrate (for example, a 1737 substrate manufactured by Corning) by a low pressure CVD method. In addition to the glass substrate, the substrate 60 may be a quartz substrate, a substrate formed of an insulating material such as alumina, a plastic substrate having heat resistance that can withstand a processing temperature in a subsequent process, or the like.

As the separation layer 61, it is desirable to use a film containing silicon as a main component, such as polycrystalline silicon, single crystal silicon, and SAS (including microcrystalline silicon and microcrystalline silicon) in addition to amorphous silicon. However, it is not limited to these. The peeling layer 61 may be formed by a plasma CVD method, a sputtering method, or the like in addition to the low pressure CVD method. Alternatively, a film doped with an impurity such as phosphorus may be used. The release layer may have a thickness of 30 nm to 1 μm, and may be 30 nm or less if the thin film formation limit of the release layer 1 is allowed.

Next, a protective film 55 (also referred to as a base film or a base insulating film) is formed over the peeling layer 61. Here, the three-layer structure is formed in the order of SiON film (100 nm) / SiNO film (50 nm) / SiON film (100 nm), but the material, film thickness, and number of layers are not limited thereto. For example, instead of the lower SiON film, an organic material such as siloxane having a film thickness of 0.5 to 3 μm may be formed by a spin coat method, a slit coater method, a droplet discharge method, or the like. Further, a silicon nitride film (SiN, Si ₃ N ₄ or the like) may be used. Each film thickness is preferably 0.05 to 3 μm, and can be freely selected from the range.

In addition, when using the material which has silicon as main components, such as a-Si, as the peeling layer 61 and the island-like semiconductor film 57, it is good to use SiOxNy for the protective film which touches them from the point of ensuring adhesiveness. .

Here, the silicon oxide film can be formed by a method such as thermal CVD, plasma CVD, atmospheric pressure CVD, or bias ECRCVD, using a mixed gas such as SiH ₄ and O ₂ , TEOS (tetraethoxysilane), and O _2. it can. The silicon nitride film can be typically formed by plasma CVD using a mixed gas of SiH ₄ and NH ₃ . The SiON film or SiNO film can be typically formed by plasma CVD using a mixed gas of SiH ₄ and N ₂ O.

After that, as illustrated in FIG. 21B, an island-shaped semiconductor film 57 is formed over the protective film 55. The island-shaped semiconductor film 57 is formed using an amorphous semiconductor, a crystalline semiconductor, or SAS (including microcrystalline silicon and microcrystalline silicon). In any case, a semiconductor film containing silicon, silicon germanium (SiGe), or the like as a main component can be used.

In this embodiment, an amorphous semiconductor film is formed and a crystalline semiconductor film crystallized by heat treatment is formed. Embodiment 3 can be referred to for other methods for manufacturing a semiconductor film.

In addition, it is considered that the peeling layer is affected by the process of heating the semiconductor film. For example, when heat treatment is performed using a furnace, or when laser irradiation is performed using a wavelength of 532 nm, energy may reach the release layer. As a result, the release layer may be crystallized at the same time. The reaction rate can be improved by the crystallization state of the release layer.

On the other hand, in order to crystallize the semiconductor film efficiently, the structure of the protective film can be selected so that the energy from the laser does not reach the release layer. For example, the material of the protective film, the film thickness, and the stacking order are selected.

Note that hydrogen or halogen of 1 × 10 ¹⁹ to 1 × 10 ²² cm ⁻³ , preferably 1 × 10 ^{19 to} 5 × 10 ²⁰ cm ⁻³ is preferably added to the channel region in the TFT. . Regarding SAS, it is desirable to set it as 1 * 10 < ¹⁹ > -2 * 10 < ²¹ > cm < ^-3 >. In any case, it is desirable to contain more than the content of hydrogen or halogen contained in an IC chip formed from a silicon wafer. Thereby, even if a local crack occurs in the TFT portion, it can be terminated (terminated) by hydrogen or halogen.

Next, as illustrated in FIG. 21B, a gate insulating film 58 is formed over the island-shaped semiconductor film 57. The gate insulating film is formed by a single layer or a stack of films containing silicon nitride, silicon oxide, silicon nitride oxide, or silicon oxynitride by a plasma CVD method, a sputtering method, or the like. In the case of stacking, for example, a three-layer structure of a silicon oxide film, a silicon nitride film, and a silicon oxide film is preferable from the substrate side.

Next, as shown in FIG. 21C, a gate electrode 56 is formed. Here, after the Si and W (tungsten) layers are formed by sputtering, the gate electrode 56 is formed by etching using the resist 62 as a mask. Of course, the material, structure, and manufacturing method of the gate electrode 56 are not limited to this, and can be selected as appropriate. For example, a stacked structure of Si and NiSi (nickel silicide) doped with an n-type impurity or a stacked structure of TaN (tantalum nitride) and W (tungsten) may be used. Alternatively, a single layer structure may be formed using various conductive materials.

In place of the resist mask, a mask containing an inorganic material such as SiOx (referred to as a hard mask) may be used. In this case, a patterning process is added to a hard mask such as SiOx, SiON, etc. However, since the film thickness of the mask during etching is less than that of the resist, a gate electrode layer having a desired width can be formed. Alternatively, the gate electrode 56 may be selectively formed by using a droplet discharge method without using the resist 62.

Further, the gate electrode 56 and the antenna can be formed at the same time. In that case, the material is selected in consideration of the functions of the gate electrode 56 and the antenna.

As an etching gas for forming the gate electrode 56 by etching, a mixed gas of CF ₄ , Cl ₂ , O ₂ or Cl ₂ gas can be used, but is not limited thereto.

Next, as shown in FIG. 21D, the portions to be the p-type TFTs 70 and 72 are covered with a resist 63, and n-type is imparted to the island-shaped semiconductor films of the n-type TFTs 69 and 71 using the gate electrode as a mask. Impurity element 64 (typically P (phosphorus) or As (arsenic)) is doped at a low concentration (first doping step). The conditions of the first doping step are a dose of 1 × 10 ^{13 to} 6 × 10 ¹³ / cm ² and an acceleration voltage of 50 to 70 keV, but are not limited thereto. By this first doping step, doping (through doping) is performed through the gate insulating film 58, and a pair of low-concentration impurity regions 65 is formed. The first doping step may be performed on the entire surface without covering the p-type TFT region with the resist.

Next, as shown in FIG. 21E, after removing the resist 63 by ashing or the like, a resist 66 covering the n-type TFT region is newly formed, and the islands of the p-type TFTs 70 and 72 are formed using the gate electrode as a mask. An impurity element 67 imparting p-type (typically B (boron)) is doped at a high concentration in the semiconductor film (second doping step). The conditions of the second doping step are a dose amount: 1 × 10 ^{16 to} 3 × 10 ¹⁶ / cm ² and an acceleration voltage: 20 to 40 keV. Through this second doping step, through doping is performed through the gate insulating film 58, and a pair of p-type high concentration impurity regions 68 are formed.

Next, as shown in FIG. 22A, after the resist 66 is removed by ashing or the like, an insulating film 75 is formed so as to cover the gate electrode and the like. Here, a SiO ₂ film having a thickness of 100 nm is formed by a plasma CVD method.

Thereafter, as shown in FIG. 22B, the entire surface of the substrate is covered with a resist 84, and the resist 84, the insulating film 75, and the gate insulating film 58 are removed by etching by an etch back method, and the side wall (side wall) 76 is self-aligned. (Self-aligned). As the etching gas, a mixed gas of CHF ₃ and He was used. Note that the step of forming the sidewall is not limited to these.

Note that in the case where an insulating film is also formed on the back surface of the substrate when the insulating film 75 is formed, the back surface insulating film may be removed by etching using the resist 84 as a mask (back surface processing).

The method for forming the sidewall 76 is not limited to the above. For example, the method shown in FIG. 23 can be used. FIG. 23A illustrates an example in which the insulating film 75 has a two-layer structure or more. The insulating film 75 has a two-layer structure of, for example, a 100 nm thick SiON (silicon oxynitride) film and a 200 nm thick LTO film (Low Temperature Oxide). Here, the SiON film is formed by a plasma CVD method, and the SiO ₂ film is formed by a low pressure CVD method as the LTO film. Thereafter, by performing etch back using the resist 84 as a mask, the sidewall 76 having an L shape and an arc shape can be formed.

FIG. 23B shows an example in which etching is performed so as to leave the gate insulating film 58 during etch back. In this case, the insulating film 75 may have a single layer structure or a laminated structure.

The sidewall 76 functions as a mask when a high-concentration n-type impurity is doped later and a low-concentration impurity region or a non-doped offset region is formed below the sidewall 76. In any of these formation methods, the etch-back conditions may be appropriately changed depending on the width of the low concentration impurity region or the offset region.

Next, as shown in FIG. 22C, a resist 77 covering the p-type TFT region is newly formed, and an n-type impurity element 78 (typically, using the gate electrode 56 and the sidewall 76 as a mask) Is doped with P or As) at a high concentration (third doping step). The conditions of the third doping step are a dose amount: 1 × 10 ^{13 to} 5 × 10 ¹⁵ / cm ² and an acceleration voltage: 60 to 100 keV. Through the third doping step, through doping is performed through the gate insulating film 57, and a pair of n-type high concentration impurity regions 79 are formed.

The impurity region may be thermally activated after removing the resist 77 by ashing or the like. For example, after a 50 nm SiON film is formed, heat treatment may be performed in a nitrogen atmosphere at 550 ° C. for 4 hours. In addition, after the SiNx film containing hydrogen is formed to a thickness of 100 nm, defects in the crystalline semiconductor film can be improved by performing heat treatment at 410 ° C. for 1 hour in a nitrogen atmosphere. This terminates dangling bonds existing in the crystalline semiconductor film, for example, and is called a hydrogenation process. Thereafter, a SiON film having a film thickness of 600 nm is formed as a cap insulating film for protecting the TFT. Note that the hydrogenation process may be performed after the formation of the SiON film. In this case, the SiNx film and the SiON film can be continuously formed. As described above, a three-layer insulating film is formed on the TFT in the order of SiON / SiNx / SiON, but the structure and material are not limited to these. In addition, these insulating films have a function of protecting the TFTs, so it is desirable to form them as much as possible.

Next, as illustrated in FIG. 22D, an interlayer film 53 is formed over the TFT. As the interlayer film 53, a heat-resistant organic resin such as polyimide, acrylic, polyamide, or siloxane can be used. As a forming method, depending on the material, a liquid such as a spin coating method, a dip method, a spray coating method, a doctor knife, a roll coater, a curtain coater, a knife coater, an ink jet drawing method, a screen printing method, or an offset printing method. A droplet discharge method or the like can be employed. In addition, an inorganic material may be used. In that case, silicon oxide, silicon nitride, silicon oxynitride, PSG (phosphorus glass), BPSG (phosphorus boron glass), an alumina film, or the like can be used. Note that the interlayer film 53 may be formed by stacking these insulating films.

Further, a protective film 54 may be formed on the interlayer film 53. As the protective film 54, a film containing carbon such as DLC (diamond-like carbon) or carbon nitride (CN), a silicon oxide film, a silicon nitride film, a silicon nitride oxide film, or the like can be used. As a formation method, a plasma CVD method, an atmospheric pressure plasma, or the like can be used. Alternatively, a photosensitive or non-photosensitive organic material such as polyimide, acrylic, polyamide, resist, or benzocyclobutene, or a heat-resistant organic resin such as siloxane may be used.

In order to prevent the film from peeling or cracking of these films due to the stress caused by the difference in thermal expansion coefficient between the interlayer film 53 or the protective film 54 and a conductive material or the like constituting the wiring to be formed later, A filler may be mixed in the film 53 or the protective film 54.

Next, after forming a resist, a contact hole is formed by etching, and a wiring 51 for connecting TFTs and a connection wiring 82 for connecting to an external antenna are formed.
At this time, the connection wiring of the memory portion can be formed according to the application by using an ink jet drawing method or a laser cut method described in Embodiment 6 below.

A gas used for etching when opening the contact hole is a mixed gas of CHF ₃ and He, but is not limited to this. Further, the wiring 51 and the connection wiring 82 may be formed simultaneously using the same material, or may be formed separately. Here, the wiring 51 connected to the TFT has a five-layer structure in which Ti / TiN / Al—Si / Ti / TiN are stacked in this order, and is formed by a sputtering method and then patterned.

In addition, by mixing Si in the Al layer, generation of hillocks in resist baking during wiring patterning can be prevented. Moreover, you may mix about 0.5% of Cu instead of Si. Further, the hillock resistance is further improved by sandwiching the Al—Si layer with Ti or TiN. In the patterning, it is desirable to use the hard mask made of SiON or the like. Note that the wiring material and the formation method are not limited to these, and the material used for the gate electrode described above may be employed.

In the present embodiment, the case where only the TFT region constituting the CPU 73, the memory 74, etc. and the terminal portion 80 connected to the antenna are integrally formed has been shown. However, even when the TFT region and the antenna are integrally formed, The TFT structure or the like of this embodiment mode can be applied. In this case, an antenna is preferably formed on the interlayer film 53 or the protective film 54 and further covered with another protective film. As the conductive material of the antenna, Ag, Au, Al, Cu, Zn, Sn, Ni, Cr, Fe, Co, or Ti, or an alloy containing them can be used, but is not limited thereto. Further, the material may be different between the wiring and the antenna. Note that the wiring and the antenna are preferably formed so as to have a metal material having excellent malleability and ductility, and more preferably, the wiring and the antenna are made thick to withstand stress due to deformation.

As a method for forming the antenna, after forming a film on the entire surface by a sputtering method, patterning may be performed using a resist mask, or selective formation may be performed from a nozzle by a droplet discharge method or the like. In addition, the wiring and the antenna may be formed at the same time, or may be formed so that the other rides on after forming one first.

Through the above steps, a thin film integrated circuit composed of TFTs is completed. Although the top gate structure is used in this embodiment mode, a bottom gate structure (reverse stagger structure) may be used.

Further, as shown in FIG. _22D , the distance (t _under ) from the semiconductor film of the TFT to the lower protective film in the thin film integrated circuit device and the upper interlayer film (protective film is formed from the semiconductor film). In some cases, it is desirable to adjust the thickness of the upper and lower protective films or interlayer films so that the distance (t _over ) to the protective film is equal or approximately equal. In this manner, by placing the semiconductor film in the center of the thin film integrated circuit device, the stress on the semiconductor film can be relaxed and the occurrence of cracks can be prevented.

Thereafter, the release layer is removed, and the substrate is peeled off. At this time, as an etchant for removing the peeling layer, a gas or liquid containing halogenated fluorine is used as the etchant. Specifically, ClF ₃ (chlorine trifluoride) can be used as the halogenated fluorine. In this way, an ID chip can be formed. Furthermore, you may transfer to a flexible substrate after that. This is because the breaking strength of the ID chip can be increased.

(Embodiment 5)
In the present embodiment, a usage pattern for a product equipped with an ID chip, particularly a securities, will be described.

One ID chip may be provided for each product, or a plurality of ID chips may be provided. When a plurality of ID chips are provided, high security can be provided. FIG. 19A shows a securities 241 on which ten ID chips 242 are mounted. The information that each ID chip has may be the same or different. In the case of ID chips having the same information, even if a certain ID chip is damaged, regular information can be continuously provided. Further, in the case of ID chips having different information, they can be handled as regular products, that is, securities only when the information of each ID chip matches. That is, as the number of mounted ID chips increases, high security can be provided. In addition, by specifying the arrangement of the ID chips, it is possible to determine whether or not all the ID chips are aligned.

For example, as shown in FIG. 19B, it is assumed that the user of the securities pays with the securities equipped with the ID chip. Then, at the store, the securities are received and passed through, for example, a register. Then, the information of the ID chip is sent to the manager of the securities, specifically, the management server via the Internet. The management server determines whether or not the information of the ID chip is legitimate and notifies that fact. For example, if it is notified that it is legitimate, at the store, the securities can be used, and the user's payment is terminated.

A procedure for determining whether the information of the ID chip performed by the administrator, specifically the management server at this time, is authentic will be described with reference to the flowchart shown in FIG.

The management server first determines whether the ID chip is a proper ID chip. It is determined whether the information of each ID chip is correct with respect to the ID chip determined to be legitimate. For the ID chip determined to be correct, it is determined whether the number and arrangement of each ID chip are correct. As a result, the use permission information is notified to the store for the product such as the securities with the ID chip determined to be correct. For other securities and other commodities, the dealer is notified of unavailable information.

In this way, unauthorized use of products such as securities can be prevented by the ID chip.

In addition to the Internet, it is possible to determine whether or not the ID chip information is authentic by an electronic device to which the ID chip information is input. By using the electronic equipment of the store, the usage status of the securities can be determined in a short time.

In addition, for example, when using a bill equipped with an ID chip in a vending machine or the like, a means for determining whether or not the information of the ID chip is legitimate may be installed in the vending machine. Current vending machines may not accept regular banknotes if the banknotes are in poor condition, since it cannot be determined whether or not they are legitimate banknotes. If it is a banknote mounted with an ID chip, it can be expected that it can be determined whether or not it is a regular banknote regardless of the state of the banknote.

Note that the number and arrangement of ID chips mounted on the product are not limited. For example, a plurality of ID chips may be randomly arranged.

Next, a mode in which a card using the ID chip of the present invention is used as electronic money will be described. FIG. 26 shows how payment is performed using the card 721. The card 721 has the ID chip 722 of the present invention. A register 723 and a reader / writer device 724 are included. The ID chip 722 holds information on the amount of money deposited in the card 721, and the reader / writer device 724 can read the information on the amount of money without contact and transmit it to the register 723. In the register 723, it is confirmed that the amount deposited in the card 721 is equal to or greater than the amount to be settled, and settlement is performed. Then, information on the balance after settlement is transmitted to the reader / writer device 724. The reader / writer device 724 can write the remaining amount information into the ID chip 722 of the card 721.

Note that a key 725 capable of inputting a personal identification number or the like may be added to the reader / writer device 724 so that payment using the card 721 by a third party can be restricted without permission.

(Embodiment 6)
In this embodiment mode, a circuit configuration of an ID chip having a non-rewritable nonvolatile ROM as a memory and a manufacturing method thereof will be described.

For example, as the simplest ID chip circuit configuration, only a high-frequency circuit, a power supply circuit, a clock generation circuit, and a ROM storing authentication data are mounted, the function is limited to individual identification, and the lack of functions is the Internet. Complementary using network technology. Conversely, as a complicated example, a CPU and a congestion control circuit that individually recognizes a plurality of ID chips in the same radio wave area are added to the above circuit, and a security function and an arithmetic function are added. Etc.

FIG. 11 is a typical block diagram of an ID chip having a non-rewritable nonvolatile ROM as a memory, and shows a configuration having a simple function of reading only fixed data such as authentication data. In the figure, an ID chip 522 includes an antenna 515, a high frequency circuit 103, a power supply circuit 104, a reset circuit 105, a clock generation circuit 106, a data demodulation circuit 107, a data demodulation / modulation circuit 108, a control circuit 109, a first ROM 110a, and a first ROM 110a. 2 ROM 110b.

The circuit and the ROM can be formed as a thin film integrated circuit 501 integrally formed on an insulating surface. The antenna 515 can be formed over a thin film integrated circuit 501 provided over an insulating surface or formed over another substrate, that is, an antenna substrate.

As the substrate having an insulating surface, for example, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a quartz substrate, a stainless steel substrate, or the like can be used. Preferably, a substrate made of a plastic represented by polyethylene-terephthalate (PET), polyethylene naphthalate (PEN), or polyethersulfone (PES) or a synthetic resin such as acrylic is used. A substrate made of such a synthetic resin has flexibility and is lighter.

Further, in order to improve the flatness of such a substrate, it is preferable to use after polishing the surface by a chemical or mechanical polishing method, so-called CMP (Chemical-Mechanical Polishing) method. As the CMP abrasive (slurry), for example, fumed silica particles obtained by thermally decomposing silicon chloride gas dispersed in a KOH-added aqueous solution can be used.

It is also possible to form a thin film integrated circuit on an insulating surface such as a glass substrate and transfer it onto a substrate made of a synthetic resin. Therefore, a thin film integrated circuit can be formed without considering the heat resistance of the substrate made of synthetic resin. At this time, the thin film integrated circuit may be transferred to the antenna substrate. Note that as a method for peeling the thin film integrated circuit, a peeling method using stress, a peeling method for removing a peeling layer using a laser or an etching solution, a peeling method for removing a substrate, and other peeling methods can be used. Further, it can be transferred to a substrate made of a synthetic resin or an antenna substrate with an ultraviolet curable resin, specifically, an adhesive such as an epoxy resin adhesive or a resin additive, or an adhesive such as a double-sided tape. As a result, an ID chip that is highly flexible, lightweight, and thin can be formed. Since such an ID chip is resistant to stress, the width of products to be mounted can be widened.

In particular, sheet-like products such as banknotes are often touched by hand, and there is concern about the diffusion of alkali metals such as Na. Therefore, in order to prevent diffusion of impurities into the thin film integrated circuit, the thin film integrated circuit is preferably covered with an insulating film containing resin or nitrogen. For example, an insulating film containing nitrogen (SiN, SiON, or SiNO, or a laminate of these and SiO ₂ ) may be used for the base film of the thin film integrated circuit. In addition, an insulating film containing nitrogen may be formed so as to cover the wiring and the like. That is, a structure in which the thin film transistor is sandwiched between insulating films containing nitrogen is preferable.

The first ROM 110a is a mask ROM composed of first memory cells, and stores “data common between substrates”. The second ROM 110b is a ROM constituted by the second memory cells, and stores “data different between substrates”.

Thus, the data to be stored may be different, and the first memory cell and the second memory cell often have different design rules. Therefore, each ROM is preferably formed by a different manufacturing process.

For example, it can be manufactured using an ink jet drawing method or a laser cut method in combination with a process using a photomask.

Specifically, the first memory cell is manufactured by a photolithography method, and the second memory cell is manufactured by an ink jet drawing method or a laser cut method in order to realize a different layout for each substrate. In particular, an ink jet drawing method can be used in a metal wiring forming process for connecting a circuit in the second memory cell, or a laser cutting method can be used in a metal wiring dividing process.

As described above, as a result of applying different manufacturing methods, a memory cell excellent in frequency characteristics and operation margin can be formed.

Note that although the case where the first memory cell and the second memory cell are separately configured has been described in this embodiment mode, the present invention is not limited to this. If either one of the first and second memory cells requires a small number of memory cells, it may be advantageous in terms of area to be configured with a ROM formed by a similar manufacturing process. It is.

Next, each circuit will be described. The high frequency circuit 103 is a circuit that receives an analog signal from the antenna 515 and outputs the analog signal received from the data demodulation / modulation circuit 108 from the antenna 515. The power supply circuit 104 is a circuit that generates a constant power supply from the received signal. The reset circuit 105 is a circuit that generates a reset signal. The clock generation circuit 106 is a circuit that generates a clock signal. The data demodulation circuit 107 is a circuit that extracts data from the received signal. The data demodulation / modulation circuit 108 is a circuit that generates an analog signal to be output to the antenna 515 based on the digital signal received from the control circuit 1019 or changes the antenna characteristics. And the analog part is comprised from the above circuit.

The control circuit 109 receives data extracted from the received signal and performs data reading. Specifically, the address signal and the ROM selection signal of the first ROM 110a and the second ROM 110b are generated, the data is read, and the read data is sent to the data demodulation / modulation circuit. The control unit 109, the first ROM 110a, and the second ROM 110b constitute a digital unit.

The first ROM 110a may be formed by photolithography in order to store data that does not depend on the substrate. For example, when wiring is connected through a contact hole formed in an insulating film by a photolithography method to determine data, a memory cell layout example as shown in FIG. 12A can be given.

FIG. 12A shows four memory cells. One memory cell includes a bit line 201, a VDD 202, a GND 203, a word line 204, and a semiconductor film 206. In the layout of the mask ROM in which wiring is connected through a contact hole formed in an insulating film by photolithography to determine data, the high concentration of one of the thin film transistors (TFT) in which the bit line 201 forms a memory cell Overlapping the impurity region, VDD 202 and GND 203 overlap the other high concentration impurity region. Since the bit line 201 is a data read path, it is short-circuited to the semiconductor film 206 through the contact hole 205.

For example, when the read potential is GND and the data when VDD is “1” and “1”, both the VDD 202 and GND 203 lines are formed in one high concentration impurity region of the TFT. Therefore, the data content can be determined to be “0” or “1” depending on whether the site where the contact hole 205 is drilled is VDD 202 or GND 203. That is, when “0” is recorded as data, the contact hole 205 is formed under the GND 203, and when “1” is recorded, the contact hole 205 is formed under the VDD 202 and short-circuited with the semiconductor film 206.

Of course, the data may be determined in the wiring process or the semiconductor film patterning process. However, in the first ROM 110a, the photolithography method is used in the process of determining the data contents.

On the other hand, the second ROM 110b may use an ink jet drawing method or a laser cut method instead of using a photolithography method in a manufacturing process for different circuit connections of memory cells for each substrate. When the inkjet drawing method is used, for example, a drawing program may be prepared assuming a layout as shown in FIG.

In FIG. 12B, a memory cell for the ink jet drawing method includes a bit line 301, a VDD 302, a GND 303, a word line 304, and a semiconductor film 305. In the layout when data is determined by the ink jet drawing method, the bit line 301 connected to one high-concentration impurity region of the TFT is a data reading path. Therefore, the contact hole 306 is formed and the semiconductor film 305 is short-circuited. Is doing. On the other hand, although the contact hole 308 is formed in the other high-concentration impurity region of the TFT, the VDD 302 and the GND 303 are not short-circuited with the semiconductor film 305.

For example, assuming that the data when the read potential is GND is “0” and the data when the potential is VDD is “1”, as shown in FIG. Among them, one that is not short-circuited with the bit line 301 and the metal wiring of the GND 303 are short-circuited with the metal wiring 307 using the ink jet drawing method. As a result, the data can be set to “0”.

On the other hand, when the data of the memory cell is set to “1”, an inkjet drawing method is used to connect one of the high concentration impurity regions of the TFT forming the memory cell that is not short-circuited with the bit line 301 and the wiring of the VDD 302. Then, the metal wiring 307 is short-circuited. As a result, the data can be set to “1”.

Where the metal wiring is to be drawn by the ink jet drawing method may be input in advance to the drawing program. In this way, it becomes possible to store desired data for each substrate only by local modification of the drawing program, and it is possible to avoid the disposable use of a photomask used in the photolithography method. In designing, it is important to design the whole so as to satisfy the design rules and restrictions in accordance with the ink jet drawing process.

In the case of using the ink jet drawing method, a metal wiring can be selectively drawn without forming an insulating film, so that a contact hole is not necessarily provided.

Further, in the manufacturing process for different circuit connections of the memory cells for each substrate, contact holes may be formed by an ink jet drawing method.

Further, when the laser cut method is used, for example, a layout as shown in FIG. One memory cell includes a bit line 401, VDD 402, GND 403, word line 404, and semiconductor film 405. In the layout when data is determined by the laser cut method, the bit line 401 connected to one of the high concentration impurity regions of the TFT is a data read path, so that a contact hole 406 is formed and short-circuited with the semiconductor film. It is. The VDD 402 and GND 403 are both short-circuited in the other high concentration impurity region of the TFT.

For example, in order to set the data in the memory cell to “0” when the read potential is GND and the data in the case of VDD is “1”, the TFT of the TFT that forms the memory cell A part of the metal wiring of VDD 402 connected to one high concentration impurity region is separated by a laser cut method. As a result, one high-concentration impurity region of the TFT is short-circuited only with the GND 403, so that the memory content becomes “0”.

On the other hand, when the data of the memory cell is set to “1”, a part of the metal wiring of the GND 403 connected to the other high-concentration impurity region of the TFT forming the memory cell is cut using laser cutting. As a result, the other high-concentration impurity region of the TFT is short-circuited with only VDD 402, so that the content of the memory can be “1”.

Moreover, what metal wiring is to be cut off by the laser cutting method may be input to the program in advance. In this manner, the laser cut method after TFT fabrication makes it possible to store desired data for each substrate, and avoid the disposable use of a photomask used for the photolithography method. Of course, in designing, it is important to design the whole so as to satisfy the design rules and constraints in accordance with the laser cutting method.

Note that, in the manufacturing process of the second ROM, both the ink jet drawing method and the laser cutting method may be used as a manufacturing process for changing the circuit connection of the memory cell for each substrate.

By determining the data in the ROM as described above, it is possible to avoid disposable photomasks and achieve further cost reduction of the ID chip.

FIG. 13A shows an example in which a total of 2 ^{m + n} ID chips 702 are manufactured on one glass substrate 701 with 2 ^m in length and 2 ⁿ in width. (M and n are positive integers) Individual numbers such as 702 (1), 702 (2),... 702 (2 ^{m + n} ) are assigned to the ID chips in order.

As shown in FIG. 13B, when the serial data for authentication in one ID chip is L bits, the lower m + n bits are stored in the first ROM that determines the data contents by a process using a photomask. The first data common between the substrates is stored in a second ROM in which the upper L- (m + n) bits determine the data contents by the ink jet drawing method or the laser cut method. Data.

FIG. 13C illustrates the first lower data content. This common data between the substrates must also be different for the chips in the substrate, so an area of m + n bits is required. If the content of the first data of the Nth chip is represented as ID {702 (N)}, ID {702 (N)} = N−1, which is a binary number corresponding to the data content of the ROM. This is as shown in FIG.

In the present embodiment, the number of ID chips 702 on one substrate is 2 ^{m + n} , but is not limited to this.

(Embodiment 7)
In this embodiment mode, a circuit configuration of an ID chip using a fingerprint and a manufacturing method thereof will be described. Fingerprinting realizes a memory that stores random fixed data by using characteristic variations of TFTs to be manufactured. Note that variations in TFT characteristics include variations due to the grain pattern of the crystalline semiconductor film constituting the active layer of the TFT, and various variations (film thickness, film quality, impurity concentration, etc.) due to the process. A non-volatile memory having a common circuit configuration and layout and storing random fixed data every time it is manufactured even if the same manufacturing process is used is called a random number ROM.

As a simple configuration example of an ID chip using a fingerprint, a block diagram as shown in FIG. 14 can be given. FIG. 14 shows a non-contact type ID chip with a built-in antenna, which has a function of reading fixed data such as an identification number. Even if the function of the ID chip is limited to reading fixed data such as an identification number, it can be applied to various applications by supplementing the lacking function using network technology such as the Internet. It is possible.

As shown in FIG. 14, the ID chip 522 includes an antenna 515, an RF circuit 13, a power / clock signal / reset signal generation circuit 14, a data demodulation / modulation circuit 15, a control circuit 16, a mask ROM 17, and a random number ROM 18. .

The circuit and the ROM shown in FIG. 14A can be formed as a thin film integrated circuit 501 integrally formed over an insulating surface. For the substrate having an insulating surface, the above embodiment mode can be referred to. The antenna 515 can be formed over the thin film integrated circuit 501 provided over the insulating surface or can be formed over another substrate, that is, an antenna substrate, as in the above embodiment mode. The method for peeling and transposing the thin film integrated circuit described in the above embodiment can be used in combination with this embodiment.

Next, each circuit will be described. The RF circuit 13 is a circuit that receives an analog signal from the antenna 515 and outputs the analog signal received from the data demodulation / modulation circuit 15 from the antenna 515. The power supply / clock signal / reset signal generation circuit 14 is a circuit that generates a constant power supply, a reset signal, and a clock signal based on the received signal. The data demodulation / modulation circuit 15 extracts data from the received signal, and also controls the control circuit. 16 is a circuit that converts the digital signal received from 16 into an analog signal to be output to the antenna 515.

On the other hand, the control circuit 16 controls the mask ROM 17 and the random number ROM 18 and reads data according to the demodulated received signal. Specifically, an address signal and an enable signal for the mask ROM 17 and the random number ROM 18 are generated, data is read, and the read data is sent to the data demodulation / modulation circuit 15.

The random number ROM 18 is a memory circuit that has a common circuit configuration and layout, and stores random fixed data every time it is manufactured even if the same manufacturing process is used. ) Can be used as a ROM. Hereinafter, the form of the random number ROM will be described with reference to FIGS.

FIG. 15A shows a typical configuration example of a random number ROM. In the figure, the random number ROM includes a decoder 21, a memory cell array 22, and a read circuit 23. The decoder 21 receives the address signal and selects the word line of the corresponding address. The memory cell array 22 includes memory cells 24 arranged in a matrix. Memory cells in the same row are connected to the same word line, and memory cells in the same column are connected to the same bit line. A memory cell is selected through a word line, and data is read out through a bit line. The read circuit 23 inputs a bit line, amplifies the bit line potential, and reads data.

FIG. 15B shows an example of a memory cell constituting a random number memory. The memory cell is composed of one TFT 25. One of the source electrode and the drain electrode of the TFT is connected to the bit line, and the remaining one and the gate electrode are connected to the word line. In this memory cell, when a voltage Vword higher than the threshold voltage Vth of the TFT 25 is applied to the word line, the bit line is charged with a potential of (Vword−Vth). Since the threshold voltage of the TFT has variations due to grain patterns and process variations, assuming that the variation is δVth, an analog potential according to the distribution shown in FIG. 15C is charged to the bit line. become. As a result, this memory cell outputs a random potential based on variations in the threshold voltage of the TFT.

FIG. 16 shows a configuration example of a read circuit, and shows a read circuit corresponding to one column of memory cells. The read circuit 31 includes a reference memory cell 32, a differential amplifier circuit 33, and a latch circuit 34. When the word line is selected, the memory cell 35 of the memory cell array 36 charges the bit line with the potential Vbit. On the other hand, a reference potential Vref is output from the reference memory cell 32, and these two potentials are compared and amplified by the differential amplifier circuit 33 and stored in the latch circuit 34.

Note that the reference potential Vref is preferably close to the average value of the bit line potential charged by the memory cell. By doing so, also in each memory cell column, the memory cell data is assigned to 0 or 1 with a probability of almost ½, and a uniform random number is generated. For example, this can be realized by increasing the channel width of the TFT constituting the reference memory cell.

As described above, a 1-bit random number is determined and latched based on the difference between the threshold voltage of the TFT constituting the reference memory cell 32 and the threshold voltage of the TFT constituting the selected memory cell 35. It is stored in the circuit 34. More precisely, the random number is determined including variations in TFTs constituting the differential amplifier circuit 33, but in any case, the random numbers are determined by variations in TFT characteristics. In this way, it is possible to configure a random number ROM that stores random fixed data using the same manufacturing process.

Note that the random number ROM described above can be manufactured by using a normal TFT manufacturing technique, and can be manufactured by the same process as that for manufacturing other integrated circuits.

Therefore, there is no increase in the process cost associated with the production of the random number ROM, and the process cost can be kept low compared with the case of producing a flash memory.

Since the value stored in the random number memory circuit is random, the probability that the same ID is stored in different ID chips is not zero. However, even if a capacity of, for example, about 128 bits is considered, there are 2 ¹²⁸ random numbers that can exist, and the probability of matching the random numbers is substantially 0, so this is not a problem.

By using the random number ROM as described above and using that data as data (identification number etc.) unique to the ID chip, it is possible to avoid disposable photomasks and increase process costs when manufacturing mask ROMs. It is possible to manufacture a low-cost ID chip without accompanying.

FIGS. 15 and 16 show a random number ROM that determines data by comparing each memory cell with a reference memory cell. However, the random number ROM performs data determination by comparing potentials between adjacent memory cells. You can also. For example, when a memory cell in a memory cell array is selected, a potential reflecting the threshold voltage of the TFT constituting each memory cell is charged to the corresponding bit line, and the potential difference between both bit lines is amplified by a differential amplifier circuit. Then, the data is stored in the latch circuit. Such a random number ROM has a circuit configuration that is advantageous in terms of area, although biased random numbers may be generated depending on the process.

If the ID chip has only a function of reading fixed data such as an authentication number, a small amount of data is sufficient. For example, 128 bits is sufficient as an identification number unique to the ID chip. In such a case, it is possible to adopt a configuration in which the initial value of the shift register is given instead of arranging the memory cells constituting the random number ROM in a matrix.

Such an example will be described with reference to FIG. FIG. 17A is a block diagram, FIG. 17B is a circuit diagram in which a part is extracted, and FIG. 17C is a timing chart. In FIG. 17A, a shift register 41 receives a clock signal and a load signal, and a random number ROM 42 receives a load signal and an address signal. The circuit shown in the figure loads random number data from the random number ROM 42 to the shift register 41 by the load signal, and then serially outputs the random number data from the shift register 41 according to the clock signal.

FIG. 17B shows an example of a circuit configuration related to one bit of random numbers in the block diagram shown in FIG. In the figure, a shift register 41 using a clocked inverter and memory cells 46 and 47 connected to both ends of a flip-flop 43 constituting the shift register 41 via selection TFTs 44 and 45 are shown.

FIG. 17C shows a timing chart. First, with the clock signal stopped, the initial value is loaded from the random number ROM 42 into the shift register 41. When the load signal is asserted, the power supply potential of the shift register 41 is grounded and the information stored in the register is erased, and a random potential is read from the memory cells 46 and 47 to the bit lines B1 and B2. The signal is applied to both ends P1 and P2 of the flip-flop 43 through the selection TFTs 44 and 45. Thereafter, when the load signal is deasserted, the selection transistors 44 and 45 are turned off, and the shift register 41 and the memory cells 46 and 47 are disconnected. At the same time, the flip-flop 43 stores data with the analog potential charged by the memory cells 46 and 47 as an initial value, and loading of the random number into the shift register 41 is completed. Thereafter, by operating the clock signal, data unique to the chip is serially output.

As described above, it is possible to realize a simple circuit having a function of storing and reading data unique to the ID chip.

The ID chip can also be used as a high-function circuit having a logic portion including a CPU and the like. FIG. 18 shows such a configuration example. In the figure, an ID chip 522 includes an antenna 515, an RF circuit 603, a power / clock signal / reset signal generation circuit 604, a data demodulation / modulation circuit 605, and a logic unit 606. The logic unit 606 further includes a control circuit 607, a CPU 608, a program ROM 609, a work RAM 610, and a random number ROM 611.

The circuit, the ROM, and the RAM shown in FIG. 18 can be formed as a thin film integrated circuit 501 integrally formed on an insulating surface. For the substrate having an insulating surface, the above embodiment mode can be referred to. The antenna 515 can be formed over the thin film integrated circuit 501 provided over the insulating surface or can be formed over another substrate, that is, an antenna substrate, as in the above embodiment mode. The method for peeling and transposing the thin film integrated circuit described in the above embodiment can be used in combination with this embodiment.

The ID chip 522 shown in FIG. 18 is not limited to the function of simply reading the identification number assigned to the ID chip, but has various functions when the CPU 608 executes the program stored in the program ROM 609 and performs processing. sell.

Typically, it is a security function, and it is possible to perform processing such as password verification, memory divided into segments, and access authority controlled for each segment. It is also possible to perform encryption / decryption processing. For the encryption / decryption processing, dedicated hardware may be provided to improve the processing speed.

Note that when such a complicated thin film integrated circuit is realized using a silicon wafer, the circuit area becomes large, and the impact resistance performance becomes a problem. On the other hand, by forming the ID chip of the present invention on a flexible substrate, it can have high impact resistance even if the circuit area is somewhat increased.

It is the figure which showed the goods carrying an ID chip It is the figure which showed the goods carrying an ID chip It is the figure which showed the goods carrying an ID chip It is the figure which showed the goods carrying an ID chip It is the figure which showed the goods carrying an ID chip It is sectional drawing which showed the goods carrying an ID chip. It is the figure which showed the form of ID chip It is the figure which showed the form of ID chip It is sectional drawing which showed the form of ID chip It is the figure which showed the mounting method of ID chip It is the figure which showed the circuit structure of ID chip | tip. It is the figure which showed the structure of ID chip It is the figure which showed the process of forming a several ID chip. It is the figure which showed the circuit structure of ID chip | tip. It is the figure which showed the structure of ID chip It is the figure which showed the structure of ID chip It is the figure which showed the structure of ID chip It is the figure which showed the circuit structure of ID chip | tip. It is the figure which showed the usage form of the goods which mount ID chip | tip. It is the figure which showed the flowchart which judges whether the goods carrying an ID chip can be used. It is sectional drawing which showed the manufacturing process of ID chip | tip. It is sectional drawing which showed the manufacturing process of ID chip | tip. It is sectional drawing which showed the manufacturing process of ID chip | tip. It is the figure which showed the goods carrying an ID chip It is the figure which showed the goods carrying an ID chip It is the figure which showed the goods carrying an ID chip

Claims (1)

A chip-mounted object on which a chip including an integrated circuit having first to third memory cells is mounted,
The first memory cell includes a first transistor,
The first transistor has a first impurity region and a second impurity region having the same conductivity type, and the first impurity region and the second impurity region are disposed through a channel formation region,
A first bit line is provided on the first impurity region of the first transistor;
A first wiring and a second wiring having a potential higher than that of the first wiring are provided over the second impurity region of the first transistor;
A first contact hole for connecting the first bit line and the first impurity region is provided;
A second contact hole for connecting the first wiring and the second impurity region is provided;
A third contact hole is provided for connecting the second wiring and the second impurity region;
A part of the second wiring is cut by a laser cutting method, and the first wiring and the second impurity region are electrically connected to each other through the second contact hole. The data of the first memory cell is in accordance with the potential of the first wiring,
The second memory cell includes a second transistor,
The third memory cell has a third transistor,
The second transistor has a third impurity region and a fourth impurity region having the same conductivity type, and the third impurity region and the fourth impurity region are disposed through a channel formation region,
The third transistor has a fifth impurity region and a sixth impurity region having the same conductivity type, and the fifth impurity region and the sixth impurity region are disposed via a channel formation region,
A second bit line is provided over the third impurity region of the second transistor and the fifth impurity region of the third transistor;
A fourth contact hole for connecting the second bit line and the third impurity region of the second transistor is formed by photolithography,
A fifth contact hole for connecting the second bit line and the fifth impurity region of the third transistor is formed by a photolithography method,
A third wiring and a fourth wiring having a potential higher than that of the third wiring over the fourth impurity region of the second transistor and the sixth impurity region of the third transistor; Is provided,
A sixth contact hole for connecting the third wiring and the fourth impurity region of the second transistor is formed by a photolithography method, and data of the second memory cell is stored in the third memory cell. According to the potential of the wiring,
A seventh contact hole for connecting the fourth wiring and the sixth impurity region of the third transistor is formed by a photolithography method, and data of the third memory cell is stored in the fourth memory cell. According to the potential of the wiring,
A chip-mounted object, wherein the semiconductor film included in each of the first to third transistors is a crystalline semiconductor film having a thickness of 0.2 μm or less.

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