JP5193503B2 - 貫通電極付き基板及びその製造方法 - Google Patents
貫通電極付き基板及びその製造方法 Download PDFInfo
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- 239000000758 substrate Substances 0.000 title claims description 183
- 238000004519 manufacturing process Methods 0.000 title claims description 55
- 238000000034 method Methods 0.000 title description 31
- 239000011347 resin Substances 0.000 claims description 55
- 229920005989 resin Polymers 0.000 claims description 55
- 230000035515 penetration Effects 0.000 claims description 33
- 238000007747 plating Methods 0.000 claims description 23
- 239000000463 material Substances 0.000 claims description 18
- 238000009713 electroplating Methods 0.000 claims description 11
- 239000003822 epoxy resin Substances 0.000 claims description 9
- 229920000647 polyepoxide Polymers 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 description 26
- 230000002265 prevention Effects 0.000 description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 239000004020 conductor Substances 0.000 description 8
- 238000005498 polishing Methods 0.000 description 8
- 229910000679 solder Inorganic materials 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 239000000654 additive Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 239000004850 liquid epoxy resins (LERs) Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
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- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
- H05K3/4605—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated made from inorganic insulating material
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/147—Semiconductor insulating substrates
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/0979—Redundant conductors or connections, i.e. more than one current path between two points
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/03—Metal processing
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/06—Lamination
- H05K2203/063—Lamination of preperforated insulating layer
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- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0703—Plating
- H05K2203/0733—Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
- H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4647—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Inorganic Chemistry (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Electrostatic, Electromagnetic, Magneto- Strictive, And Variable-Resistance Transducers (AREA)
- Pressure Sensors (AREA)
- Printers Or Recording Devices Using Electromagnetic And Radiation Means (AREA)
Description
本発明の他の観点によれば、貫通孔を有した基板と、前記貫通孔に収容された柱状の貫通電極と、を備えた貫通電極付き基板において、前記貫通孔の内壁と前記貫通電極の側面との隙間に充填された樹脂と、前記貫通電極の上面の一部と前記貫通孔を有した基板の上面とを覆う配線層用樹脂層の母材と、が一体形成の樹脂であることを特徴とする貫通電極付き基板が提供される。
図13は、本発明の第1の実施の形態に係る貫通電極付き基板の断面図である。
図30は、本発明の第2の実施の形態に係る貫通電極付き基板の断面図である。図30において、第1の実施の形態の貫通電極付き基板10と同一構成部分には同一符号を付す。
図31は、本発明の第3の実施の形態に係る貫通電極付き基板の断面図である。図31において、第1の実施の形態の貫通電極付き基板10と同一構成部分には同一符号を付す。
11 基板
11A,14A,25A,28A,45A 上面
11B,21A 下面
12 樹脂
13,33 拡散防止膜
14 貫通電極
16,72 ビルドアップ構造体
17 外部接続端子
18 貫通孔
22,38 Ni層
21,39 Au層
25,28 樹脂層
26,29,73 配線パターン
32 ソルダーレジスト
32A,35,37,48A 開口部
45 支持板
46 シード層
48 レジスト膜
71 導体層
L1 長さ
M1〜M2 厚さ
R1〜R2 直径
Claims (4)
- 貫通孔を有した基板と、前記貫通孔に収容された柱状の貫通電極と、を備えた貫通電極付き基板の製造方法であって、
支持板上に前記貫通電極を形成する貫通電極形成工程と、
前記貫通孔を有した基板を形成する貫通孔を有した基板の形成工程と、
前記支持板と前記貫通孔を有した基板とを重ね合わせて、前記貫通孔に前記貫通電極を収容する貫通電極収容工程と、
前記貫通電極収容工程の後に、フィルム状のエポキシ系樹脂を軟化させて、前記貫通孔を有した基板の前記貫通孔の内壁と前記貫通電極の側面との隙間に充填し、同時に、前記貫通電極の上面の一部と前記貫通孔を有した基板の上面とを覆うように配線層用樹脂層の母材を形成する樹脂充填工程と、
前記樹脂充填工程後に、前記支持板を除去する支持板除去工程と、を含み、
前記貫通電極形成工程では、前記貫通電極を電解めっきにより形成し、
前記樹脂充填工程と前記支持板除去工程との間に、前記支持板が設けられた側とは反対側に位置する前記貫通孔を有した基板の面に前記貫通電極と電気的に接続された配線層を形成する配線層形成工程を有することを特徴とする貫通電極付き基板の製造方法。 - 前記貫通電極形成工程では、前記支持板上に開口部を有したレジスト膜を形成し、その後、前記電解めっきにより、前記開口部の底部に露出された前記支持体上から前記開口部の開口端部に向けてめっき膜を析出させて前記貫通電極を形成し、前記貫通電極を形成後に前記レジスト膜を除去することを特徴とする請求項1記載の貫通電極付き基板の製造方法。
- 貫通孔を有した基板と、前記貫通孔に収容された柱状の貫通電極と、を備えた貫通電極付き基板において、
前記貫通孔の内壁と前記貫通電極の側面との隙間に充填された樹脂と、前記貫通電極の上面の一部と前記貫通孔を有した基板の上面とを覆う配線層用樹脂層の母材と、が一体形成の樹脂であることを特徴とする貫通電極付き基板。 - 前記樹脂層上に、前記貫通電極と接続された配線パターンが設けられていることを特徴とする請求項3記載の貫通電極付き基板。
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007148182A JP5193503B2 (ja) | 2007-06-04 | 2007-06-04 | 貫通電極付き基板及びその製造方法 |
KR1020080051603A KR20080106844A (ko) | 2007-06-04 | 2008-06-02 | 관통 전극을 갖는 기판의 제조 방법 |
US12/132,187 US8349733B2 (en) | 2007-06-04 | 2008-06-03 | Manufacturing method of substrate with through electrode |
TW097120562A TW200850096A (en) | 2007-06-04 | 2008-06-03 | Manufacturing method of substrate with through electrode |
EP08157592A EP2001274A3 (en) | 2007-06-04 | 2008-06-04 | Manufacturing method of substrate with through electrodes |
CNA2008101086822A CN101320695A (zh) | 2007-06-04 | 2008-06-04 | 带穿通电极的基板的制造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007148182A JP5193503B2 (ja) | 2007-06-04 | 2007-06-04 | 貫通電極付き基板及びその製造方法 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2008300782A JP2008300782A (ja) | 2008-12-11 |
JP2008300782A5 JP2008300782A5 (ja) | 2010-05-20 |
JP5193503B2 true JP5193503B2 (ja) | 2013-05-08 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007148182A Active JP5193503B2 (ja) | 2007-06-04 | 2007-06-04 | 貫通電極付き基板及びその製造方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US8349733B2 (ja) |
EP (1) | EP2001274A3 (ja) |
JP (1) | JP5193503B2 (ja) |
KR (1) | KR20080106844A (ja) |
CN (1) | CN101320695A (ja) |
TW (1) | TW200850096A (ja) |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
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US8288872B2 (en) * | 2008-08-05 | 2012-10-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through silicon via layout |
US8294240B2 (en) * | 2009-06-08 | 2012-10-23 | Qualcomm Incorporated | Through silicon via with embedded decoupling capacitor |
KR101095373B1 (ko) * | 2010-04-22 | 2011-12-16 | 재단법인 서울테크노파크 | 장벽층을 갖는 범프를 포함하는 반도체칩 및 그 제조방법 |
JP5485818B2 (ja) * | 2010-06-29 | 2014-05-07 | 株式会社アドバンテスト | 貫通配線基板および製造方法 |
JP5547566B2 (ja) * | 2010-06-29 | 2014-07-16 | 株式会社アドバンテスト | 貫通配線基板の製造方法 |
KR20120012602A (ko) * | 2010-08-02 | 2012-02-10 | 삼성전자주식회사 | 반도체 장치, 그 제조 방법 및 반도체 패키지의 제조 방법 |
US8472207B2 (en) * | 2011-01-14 | 2013-06-25 | Harris Corporation | Electronic device having liquid crystal polymer solder mask and outer sealing layers, and associated methods |
US8693203B2 (en) | 2011-01-14 | 2014-04-08 | Harris Corporation | Method of making an electronic device having a liquid crystal polymer solder mask laminated to an interconnect layer stack and related devices |
JP2012156327A (ja) | 2011-01-26 | 2012-08-16 | Elpida Memory Inc | 半導体装置、及び積層型半導体装置 |
KR101806806B1 (ko) | 2011-12-20 | 2017-12-11 | 삼성전자주식회사 | 전자 소자 탑재용 기판의 제조방법 |
JP5878362B2 (ja) * | 2011-12-22 | 2016-03-08 | 新光電気工業株式会社 | 半導体装置、半導体パッケージ及び半導体装置の製造方法 |
TWI475623B (zh) * | 2011-12-27 | 2015-03-01 | Ind Tech Res Inst | 堆疊式半導體結構的接合結構及其形成方法 |
CN104051369A (zh) * | 2014-07-02 | 2014-09-17 | 上海朕芯微电子科技有限公司 | 一种用于2.5d封装的中间互联层及其制备方法 |
JP2016039512A (ja) | 2014-08-08 | 2016-03-22 | キヤノン株式会社 | 電極が貫通配線と繋がったデバイス、及びその製造方法 |
US10431533B2 (en) * | 2014-10-31 | 2019-10-01 | Ati Technologies Ulc | Circuit board with constrained solder interconnect pads |
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JP6424297B2 (ja) * | 2016-03-25 | 2018-11-14 | 住友精密工業株式会社 | 充填方法 |
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JP2006165112A (ja) * | 2004-12-03 | 2006-06-22 | Sharp Corp | 貫通電極形成方法およびそれを用いる半導体装置の製造方法、ならびに該方法によって得られる半導体装置 |
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JP2007148182A (ja) | 2005-11-30 | 2007-06-14 | Ricoh Co Ltd | 現像装置及び画像形成装置 |
US7863189B2 (en) * | 2007-01-05 | 2011-01-04 | International Business Machines Corporation | Methods for fabricating silicon carriers with conductive through-vias with low stress and low defect density |
JP5302522B2 (ja) * | 2007-07-02 | 2013-10-02 | スパンション エルエルシー | 半導体装置及びその製造方法 |
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CN101320695A (zh) | 2008-12-10 |
KR20080106844A (ko) | 2008-12-09 |
EP2001274A3 (en) | 2009-11-11 |
TW200850096A (en) | 2008-12-16 |
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JP2008300782A (ja) | 2008-12-11 |
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