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JP5003955B2 - IC tester - Google Patents

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JP5003955B2
JP5003955B2 JP2007301089A JP2007301089A JP5003955B2 JP 5003955 B2 JP5003955 B2 JP 5003955B2 JP 2007301089 A JP2007301089 A JP 2007301089A JP 2007301089 A JP2007301089 A JP 2007301089A JP 5003955 B2 JP5003955 B2 JP 5003955B2
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voltage
pin
switch
resistance
liquid crystal
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JP2009128082A (en
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英樹 永沼
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Yokogawa Electric Corp
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Description

本発明は、多階調電圧を出力する液晶駆動ドライバを試験するICテスタに関し、電流測定部をピンごとに設けることなく、液晶駆動ドライバのピン間抵抗試験の短縮を図れるICテスタに関するものである。 The present invention relates to an IC tester for testing a liquid crystal driver for outputting a multi-tone voltage, without providing a current measuring unit for each pin, it relates to an IC tester which attained a reduction of pin-to-pin resistance test of the liquid crystal driver .

液晶駆動ドライバは、TCP(Tape Carrier Package)(TCPは総称で、COF(Chip On Film)も含まれる)で構成され、図3に示すように、TAB(Tape Automated Bonding)テープ11に、チップ12が搭載され、チップ12が複数のピン13に配線(図示せず)を介して接続される構成をとっている。このため、ピン13間のピッチが狭いため、ICテスタにより、ピン13間の電流を測定し、ピン間の抵抗値の試験を行っている。ピン間抵抗値の試験は、下記特許文献1のように行えるが、液晶駆動ドライバのピンは、非常に多く、隣接ピンごとに電流測定部を設けると、ICテスタが高価になってしまうので、図4に示すように試験を行っている。   The liquid crystal drive driver is composed of TCP (Tape Carrier Package) (TCP is a generic name and includes COF (Chip On Film)), and as shown in FIG. 3, a TAB (Tape Automated Bonding) tape 11 and a chip 12 And the chip 12 is connected to the plurality of pins 13 via wiring (not shown). For this reason, since the pitch between the pins 13 is narrow, the current between the pins 13 is measured by an IC tester to test the resistance value between the pins. Although the resistance test between pins can be performed as in Patent Document 1 below, the number of pins of the liquid crystal drive driver is very large, and if a current measuring unit is provided for each adjacent pin, the IC tester becomes expensive. The test is performed as shown in FIG.

特開平5−190637号公報JP 5-190637 A

図4において、液晶駆動ドライバ(以下DUTと略す)10は、図3に示されるようなTCPで構成され、複数ピンから多階調電圧を出力する。電圧発生部20は、ICテスタに設けられ、DUT10の複数ピンに電圧を与える。マルチプレクサ30は、電圧発生部20に電圧が与えられるピンに隣接する複数ピンに接続し、切り替える。電流測定部40は、マルチプレクサ30が切り替えたピンの電流を測定する。制御部50は、電圧発生部20、マルチプレクサ30を制御し、電流測定部40の測定結果により、ピン間抵抗試験の判定を行う。ピン間抵抗Rは、DUT10のピン間の抵抗成分を示す。なお、ピン間抵抗以外の試験のための構成は省略している。   In FIG. 4, a liquid crystal drive driver (hereinafter abbreviated as DUT) 10 is composed of TCP as shown in FIG. 3, and outputs a multi-gradation voltage from a plurality of pins. The voltage generator 20 is provided in the IC tester and applies a voltage to a plurality of pins of the DUT 10. The multiplexer 30 is connected to and switched to a plurality of pins adjacent to a pin to which a voltage is applied to the voltage generator 20. The current measuring unit 40 measures the current of the pin switched by the multiplexer 30. The control unit 50 controls the voltage generation unit 20 and the multiplexer 30 and determines the inter-pin resistance test based on the measurement result of the current measurement unit 40. The inter-pin resistance R indicates a resistance component between the pins of the DUT 10. Note that configurations for tests other than inter-pin resistance are omitted.

このような装置のピン間抵抗試験動作を説明する。電圧発生部20が、制御部50の指示により、DUT10の所望の複数ピンに電圧出力する。これら所望ピンの隣接するDUT10のピンを、制御部50の指示により、マルチプレクサ30が切り替える。このマルチプレクサ30で切り替えられたピンの電流を電流測定部40が測定する。この測定結果(電流値)により、制御部50が、ピン間抵抗Rの抵抗値を求め、DUT10の良否の判定を行っている。   The inter-pin resistance test operation of such an apparatus will be described. The voltage generator 20 outputs a voltage to a desired plurality of pins of the DUT 10 according to an instruction from the controller 50. The multiplexer 30 switches the pins of the DUT 10 adjacent to these desired pins according to an instruction from the control unit 50. The current measuring unit 40 measures the current of the pin switched by the multiplexer 30. Based on the measurement result (current value), the control unit 50 obtains the resistance value of the inter-pin resistance R and determines whether the DUT 10 is good or bad.

近年、液晶ディスプレイの大型化、画素数の上昇により、液晶駆動ドライバが約700ピンと多ピン化し、ピン間ピッチが約30μmで、ピン間の隙間は約10μmと狭くなってきている。これにより、ピン間ショートが起きやすくなるため、従来、ピン間抵抗値が200MΩ程度だったものが、750MΩを越える判定値が要求されてきている。この結果、ピン間に流れる電流のセトリング時間が10〜100nsから数十msになり、測定開始までの待ち時間が長くなってしまった。従って、セトリングを待って、マルチプレクサで切替を行い、試験を行っていたのでは、試験時間がかかってしまう。一方、電流測定部をピンごとに設けると、ICテスタが高価になってしまうという問題点があった。   In recent years, the liquid crystal display driver has increased in size and the number of pixels, so that the liquid crystal driving driver has about 700 pins, the pin-to-pin pitch is about 30 μm, and the gap between pins is narrowed to about 10 μm. As a result, a short-circuit between pins is likely to occur, so that a determination value exceeding 750 MΩ has been required for a conventional pin resistance value of about 200 MΩ. As a result, the settling time of the current flowing between the pins is changed from 10 to 100 ns to several tens of ms, and the waiting time until the measurement is started is increased. Therefore, if the test is performed after the settling is performed and the multiplexer is used for switching, the test time is required. On the other hand, if a current measuring unit is provided for each pin, there is a problem that the IC tester becomes expensive.

そこで、本発明の目的は、電流測定部をピンごとに設けることなく、液晶駆動ドライバのピン間抵抗試験の短縮を図れるICテスタを実現することにある。 Accordingly, an object of the present invention is to realize an IC tester capable of shortening the resistance test between pins of a liquid crystal drive driver without providing a current measuring unit for each pin.

このような課題を達成するために、本発明のうち請求項1記載の発明は、
多階調電圧を出力する液晶駆動ドライバを試験するICテスタにおいて、
前記液晶駆動ドライバの複数ピンに電圧を与える電圧発生部と、
前記液晶駆動ドライバの多階調電圧を出力するピンごとに設けられ、入力を抵抗分圧によるアッテネータにより減衰が行え、電圧を測定する電圧測定部と、
階調電圧試験時に、前記電圧発生部をオフにし、前記電圧測定部が測定した電圧値により階調電圧試験を行い、ピン間抵抗試験時に、前記電圧発生部に電圧を与えさせ、前記電圧発生部が電圧を与えるピンの隣接ピンに対応する前記電圧測定部のアッテネータの抵抗による電圧を、前記電圧測定部に測定させ、この測定結果によりピン間抵抗試験の判定を行う制御部と
を有することを特徴とするものである。
請求項2記載の発明は、請求項1記載の発明であって、
電圧測定部は、ピン間抵抗試験時に、アッテネータの2つの分圧抵抗を1つの抵抗として、電流を電圧に変換し、電圧を測定することを特徴とするものである。
請求項3記載の発明は、請求項1または2記載の発明であって、
電圧測定部は、
液晶駆動ドライバのピンに一端を電気的に接続する第1のスイッチと、
液晶駆動ドライバのピンに一端を電気的に接続する第2のスイッチと、
この第2のスイッチの他端に一端を接続する第1の抵抗と、
この第1の抵抗の他端に一端を接続し、他端を接地する第2の抵抗と、
前記第1のスイッチの他端に一端を接続する第3のスイッチと、
前記第1の抵抗の他端に一端を接続する第4のスイッチと、
前記第3、第4のスイッチの他端に入力端を接続するA/D変換部と
を設けたことを特徴とするものである
In order to achieve such a problem, the invention according to claim 1 of the present invention is:
In an IC tester for testing a liquid crystal drive driver that outputs a multi-gradation voltage,
A voltage generator for applying a voltage to a plurality of pins of the liquid crystal drive driver;
A voltage measuring unit that is provided for each pin that outputs a multi-gradation voltage of the liquid crystal drive driver, the input can be attenuated by an attenuator by resistance voltage division, and the voltage is measured;
The voltage generator is turned off during a grayscale voltage test, a grayscale voltage test is performed based on the voltage value measured by the voltage measurement unit, and a voltage is applied to the voltage generator during a pin-to-pin resistance test. A control unit that causes the voltage measurement unit to measure a voltage due to the resistance of the attenuator of the voltage measurement unit corresponding to the pin adjacent to the pin to which the voltage is applied, and to determine a resistance test between the pins based on the measurement result It is characterized by.
Invention of Claim 2 is invention of Claim 1, Comprising:
The voltage measuring unit is characterized in that, during the inter-pin resistance test, the two voltage dividing resistors of the attenuator are used as one resistor, the current is converted into a voltage, and the voltage is measured.
Invention of Claim 3 is invention of Claim 1 or 2, Comprising:
The voltage measurement unit
A first switch electrically connecting one end to a pin of the liquid crystal drive driver;
A second switch for electrically connecting one end to the pin of the liquid crystal drive driver;
A first resistor connecting one end to the other end of the second switch;
A second resistor for connecting one end to the other end of the first resistor and grounding the other end;
A third switch connecting one end to the other end of the first switch;
A fourth switch connecting one end to the other end of the first resistor;
An A / D conversion unit for connecting an input end to the other end of the third and fourth switches is provided .

本発明によれば、ピン間抵抗試験の電流を電圧測定部のアッテネータの抵抗により電圧に変換し、液晶駆動ドライバのピンを同時に測定するので、電流測定部をピンごとに設けることなく、液晶駆動ドライバのピン間抵抗試験の短縮を図ることができる。   According to the present invention, the current of the inter-pin resistance test is converted into a voltage by the resistance of the attenuator of the voltage measurement unit, and the pins of the liquid crystal drive driver are measured at the same time. The driver pin-to-pin resistance test can be shortened.

また、請求項によれば、アッテネータの2つの分圧抵抗を1つの抵抗として用い、電流を電圧に変換したので、微小電流を電圧測定部で感度よく試験することができる。
Further, according to claim 2, using two voltage dividing resistors of the attenuator as a single resistor, since converts the current into a voltage, it can be sensitively tested low current at the voltage measuring unit.

以下本発明を、図面を用いて詳細に説明する。図1は本発明の一実施例を示した構成図である。   Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention.

図1において、液晶駆動ドライバ(以下DUTと略す)1は、図3に示されるようなTCPで構成され、複数ピンから多階調電圧を出力する。電圧発生部2は、DUT1の複数ピン、つまり、1つ飛びのピンごとに電圧を与える。電圧測定部3は、DUT1の多階調電圧を出力するピンごとに設けられ、入力を抵抗分圧によるアッテネータにより減衰が行え、電圧を測定する。制御部4は、階調電圧試験時に、電圧発生部2をオフにし、電圧測定部3が測定した電圧値により階調電圧試験を行い、ピン間抵抗試験時に、電圧発生部2に電圧を与えさせ、電圧発生部2が電圧を与えるピンの隣接ピンに対応する電圧測定部3のアッテネータによる電圧を、電圧測定部3に測定させ、この測定結果によりピン間抵抗試験の判定を行う。ピン間抵抗Rは、DUT1のピン間の抵抗成分を示す。   In FIG. 1, a liquid crystal drive driver (hereinafter abbreviated as DUT) 1 is composed of TCP as shown in FIG. 3, and outputs a multi-gradation voltage from a plurality of pins. The voltage generation unit 2 applies a voltage to each of a plurality of pins of the DUT 1, that is, one skipped pin. The voltage measuring unit 3 is provided for each pin that outputs the multi-tone voltage of the DUT 1, and the input can be attenuated by an attenuator based on resistance voltage division to measure the voltage. The control unit 4 turns off the voltage generation unit 2 during the grayscale voltage test, performs a grayscale voltage test based on the voltage value measured by the voltage measurement unit 3, and gives a voltage to the voltage generation unit 2 during the inter-pin resistance test. The voltage measurement unit 3 measures the voltage by the attenuator of the voltage measurement unit 3 corresponding to the pin adjacent to the pin to which the voltage is applied by the voltage generation unit 2, and the inter-pin resistance test is determined based on the measurement result. The inter-pin resistance R indicates a resistance component between the pins of the DUT 1.

次に、電圧測定部2の具体例を図2に示し説明する。
図2において、スイッチSW1,SW2はDUTのピンに一端を電気的に接続する。抵抗r1は、スイッチSW2の他端に一端を接続する。抵抗r2は、抵抗r1の他端に一端を接続し、他端を接地する。そして、抵抗r1,r2はアッテネータを構成する。スイッチSW3は、スイッチSW1の他端に一端を接続する。スイッチSW4は、抵抗r1の他端に一端を接続する。A/D変換器31は、スイッチSW3,SW4の他端に入力端を接続する。
Next, a specific example of the voltage measuring unit 2 will be described with reference to FIG.
In FIG. 2, switches SW1 and SW2 are electrically connected at one end to the pins of the DUT. The resistor r1 has one end connected to the other end of the switch SW2. The resistor r2 has one end connected to the other end of the resistor r1 and the other end grounded. The resistors r1 and r2 constitute an attenuator. The switch SW3 has one end connected to the other end of the switch SW1. The switch SW4 has one end connected to the other end of the resistor r1. The A / D converter 31 has an input terminal connected to the other ends of the switches SW3 and SW4.

このような装置の動作を説明する。
まず、階調電圧試験を行う場合、制御部4がスイッチSW1,SW3をオンし、スイッチSW2,SW4をオフし、電圧発生部2をオフとする。そして、図示しない信号発生部からDUT1に対して信号が与えられ、DUT1が階調電圧を出力する。この階調電圧を、スイッチSW1,SW3を介して、A/D変換器31でデジタルデータに変換し、制御部4に出力する。制御部4は、デジタルデータにより、階調電圧が期待値電圧になっているか判定し、DUT1の良否の判定を行う。なお、DUT1がソースドライバの場合は、階調電圧は0〜20Vの出力範囲で、ライン経路を選択したが、ゲートドライバの場合0〜40Vの出力範囲なので、抵抗r1,r2によるアッテネータ経路が選択される。
The operation of such an apparatus will be described.
First, when performing the gradation voltage test, the control unit 4 turns on the switches SW1 and SW3, turns off the switches SW2 and SW4, and turns off the voltage generation unit 2. A signal is supplied from a signal generator (not shown) to the DUT 1, and the DUT 1 outputs a gradation voltage. This gradation voltage is converted into digital data by the A / D converter 31 via the switches SW1 and SW3, and is output to the control unit 4. The control unit 4 determines whether the gradation voltage is an expected value voltage based on the digital data, and determines whether the DUT 1 is good or bad. When DUT1 is a source driver, the line path is selected with an output range of 0 to 20 V for the gradation voltage, but when the gate driver is an output range of 0 to 40 V, the attenuator path with resistors r1 and r2 is selected. Is done.

次に、ピン間抵抗試験の場合、制御部4がスイッチSW1〜SW3をオンし、スイッチSW4をオフする。そして、制御部4が電圧発生部2に電圧を発生させ、ピン間抵抗Rに電流が流れる。そして、スイッチSW2、抵抗r1,r2に電流が流れ、抵抗r1,r2による電圧を、A/D変換器31でデジタルデータに変換し、制御部4に出力する。制御部4は、デジタルデータにより、DUT1の良否の判定を行う。   Next, in the case of the inter-pin resistance test, the control unit 4 turns on the switches SW1 to SW3 and turns off the switch SW4. Then, the control unit 4 causes the voltage generation unit 2 to generate a voltage, and a current flows through the inter-pin resistance R. Then, current flows through the switch SW2 and the resistors r1 and r2, and the voltage generated by the resistors r1 and r2 is converted into digital data by the A / D converter 31 and output to the control unit 4. The control unit 4 determines whether the DUT 1 is good or bad based on the digital data.

ここで、ピン間抵抗試験の良否の判定方法について説明する。電圧発生部2が出力する電圧を”V”、ピン間抵抗Rの抵抗値”R”、抵抗r1,r2の抵抗値をそれぞれ”r1”,”r2”、ピン間抵抗Rに流れる電流を”i”、電圧測定部3が測定する電圧を”v”とする。これらの関係を式に表すと、V=i・(R+r1+r2)、v=i・(r1+r2)となる。そして、v=(r1+r2)・V/(R+r1+r2)となる。判定値の条件として、Rが大きければ、ピン間に電流が流れ難くなるので、v<(r1+r2)・V/(R+r1+r2)により判定がなされる。従って、vだけを求めることにより、DUT1の良否の判定を行うことができる。   Here, the quality determination method of the inter-pin resistance test will be described. The voltage output from the voltage generator 2 is “V”, the resistance value “R” of the inter-pin resistor R, the resistance values of the resistors r1 and r2 are “r1” and “r2”, respectively, and the current flowing through the inter-pin resistor R is “ i ”and the voltage measured by the voltage measuring unit 3 is“ v ”. When these relationships are expressed in equations, V = i · (R + r1 + r2) and v = i · (r1 + r2). Then, v = (r1 + r2) · V / (R + r1 + r2). As a condition for the determination value, if R is large, it is difficult for current to flow between the pins. Therefore, determination is made by v <(r1 + r2) · V / (R + r1 + r2). Therefore, it is possible to determine whether the DUT 1 is good or bad by obtaining only v.

このように、ピン間抵抗試験の電流を電圧測定部3のアッテネータの抵抗により電圧に変換し、DUT1のピンを同時に測定するので、電流測定部をピンごとに設けることなく、DUT1のピン間抵抗試験の短縮を図ることができる。   In this way, the current of the inter-pin resistance test is converted into a voltage by the resistance of the attenuator of the voltage measuring unit 3, and the pins of the DUT 1 are measured at the same time. Therefore, the inter-pin resistance of the DUT 1 is not provided for each pin. Tests can be shortened.

また、ピン間抵抗試験時に、抵抗r1,r2を1つの抵抗として用い、電流を電圧に変換し、微小電流を感度よく、電圧測定部3で試験することができる。   Further, during the inter-pin resistance test, the resistors r1 and r2 are used as one resistor, the current is converted into a voltage, and a minute current can be tested with the voltage measuring unit 3 with high sensitivity.

なお、本発明はこれに限定されるものではなく、DUT1と電圧発生部2との接続した状態の例を示したが、DUT1と電圧発生部2との経路上にスイッチを設け、切り離し可能に構成してもよい。   Note that the present invention is not limited to this, and an example in which the DUT 1 and the voltage generator 2 are connected is shown. However, a switch is provided on the path between the DUT 1 and the voltage generator 2 so that the switch can be disconnected. It may be configured.

また、電圧測定部3のアッテネータが1つの場合の例を示したが、複数あってもよい。そして、ピン間抵抗試験時に、抵抗r1,r2を1つの抵抗として、電圧を求める構成を示したが、スイッチSW1,SW3をオフとし、スイッチSW2,SW4をオンとして、A/D変換器31は、抵抗r1,r2により分圧した電圧を測定する構成でもよい。   Moreover, although the example in case the voltage measurement part 3 has one attenuator was shown, there may be multiple. In the inter-pin resistance test, the configuration is shown in which the voltage is obtained by using the resistors r1 and r2 as one resistor. However, the switches SW1 and SW3 are turned off, the switches SW2 and SW4 are turned on, and the A / D converter 31 is The voltage divided by the resistors r1 and r2 may be measured.

また、制御部4は、電圧値により、ピン間抵抗試験におけるDUT1の良否の判定を行っているが、抵抗値を求めて判定を行ってもよい。   Moreover, although the control part 4 is determining the quality of DUT1 in the inter-pin resistance test with a voltage value, you may determine by determining resistance value.

そして、階調電圧試験とピン間抵抗試験との順番は逆でもよい。   The order of the gradation voltage test and the inter-pin resistance test may be reversed.

本発明の一実施例を示した構成図である。It is the block diagram which showed one Example of this invention. 電圧測定部3の具体的構成を示した図である。FIG. 4 is a diagram showing a specific configuration of a voltage measurement unit 3. 液晶駆動ドライバの具体的構成を示した図である。It is the figure which showed the specific structure of the liquid crystal drive driver. 従来のICテスタの構成を示した図である。It is the figure which showed the structure of the conventional IC tester.

符号の説明Explanation of symbols

1 DUT
2 電圧発生部
3 電圧測定部
SW1〜SW4 スイッチ
r1,r2 抵抗
31 A/D変換器
4 制御部
R ピン間抵抗
1 DUT
2 Voltage generation unit 3 Voltage measurement unit SW1 to SW4 switch r1, r2 resistance 31 A / D converter 4 control unit R resistance between pins

Claims (3)

多階調電圧を出力する液晶駆動ドライバを試験するICテスタにおいて、
前記液晶駆動ドライバの複数ピンに電圧を与える電圧発生部と、
前記液晶駆動ドライバの多階調電圧を出力するピンごとに設けられ、入力を抵抗分圧によるアッテネータにより減衰が行え、電圧を測定する電圧測定部と、
階調電圧試験時に、前記電圧発生部をオフにし、前記電圧測定部が測定した電圧値により階調電圧試験を行い、ピン間抵抗試験時に、前記電圧発生部に電圧を与えさせ、前記電圧発生部が電圧を与えるピンの隣接ピンに対応する前記電圧測定部のアッテネータの抵抗による電圧を、前記電圧測定部に測定させ、この測定結果によりピン間抵抗試験の判定を行う制御部と
を有することを特徴とするICテスタ。
In an IC tester for testing a liquid crystal drive driver that outputs a multi-gradation voltage,
A voltage generator for applying a voltage to a plurality of pins of the liquid crystal drive driver;
A voltage measuring unit that is provided for each pin that outputs a multi-gradation voltage of the liquid crystal drive driver, the input can be attenuated by an attenuator by resistance voltage division, and the voltage is measured;
The voltage generator is turned off during a grayscale voltage test, a grayscale voltage test is performed based on the voltage value measured by the voltage measurement unit, and a voltage is applied to the voltage generator during a pin-to-pin resistance test. A control unit that causes the voltage measurement unit to measure a voltage due to the resistance of the attenuator of the voltage measurement unit corresponding to the pin adjacent to the pin to which the voltage is applied, and to determine a resistance test between the pins based on the measurement result IC tester characterized by
電圧測定部は、ピン間抵抗試験時に、アッテネータの2つの分圧抵抗を1つの抵抗として、電流を電圧に変換し、電圧を測定することを特徴とする請求項1記載のICテスタ。   2. The IC tester according to claim 1, wherein the voltage measuring unit measures the voltage by converting the current into the voltage by using the two voltage dividing resistors of the attenuator as one resistance during the inter-pin resistance test. 電圧測定部は、
液晶駆動ドライバのピンに一端を電気的に接続する第1のスイッチと、
液晶駆動ドライバのピンに一端を電気的に接続する第2のスイッチと、
この第2のスイッチの他端に一端を接続する第1の抵抗と、
この第1の抵抗の他端に一端を接続し、他端を接地する第2の抵抗と、
前記第1のスイッチの他端に一端を接続する第3のスイッチと、
前記第1の抵抗の他端に一端を接続する第4のスイッチと、
前記第3、第4のスイッチの他端に入力端を接続するA/D変換部と
を設けたことを特徴とする請求項1または2記載のICテスタ。
The voltage measurement unit
A first switch electrically connecting one end to a pin of the liquid crystal drive driver;
A second switch for electrically connecting one end to the pin of the liquid crystal drive driver;
A first resistor connecting one end to the other end of the second switch;
A second resistor for connecting one end to the other end of the first resistor and grounding the other end;
A third switch connecting one end to the other end of the first switch;
A fourth switch connecting one end to the other end of the first resistor;
3. The IC tester according to claim 1, further comprising an A / D converter that connects an input terminal to the other end of each of the third and fourth switches.
JP2007301089A 2007-11-21 2007-11-21 IC tester Expired - Fee Related JP5003955B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6371669A (en) * 1986-09-16 1988-04-01 Matsushita Electronics Corp Inspecting method for electronic circuit device
JP2919147B2 (en) * 1992-01-13 1999-07-12 九州日本電気株式会社 Test method for semiconductor integrated circuit
JP3594136B2 (en) * 2001-11-15 2004-11-24 横河電機株式会社 IC tester and DUT card
JP2003240807A (en) * 2002-02-19 2003-08-27 Mitsubishi Electric Corp Voltage measurement device
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