JP4923527B2 - Display device and driving method thereof - Google Patents

Description

  The present invention relates to a flat panel display device that displays an image with a light emitting element arranged for each pixel. More specifically, the present invention relates to a so-called active matrix display device that controls the amount of current supplied to a light emitting element such as an organic EL by an insulated gate field effect transistor provided in each pixel, and a driving method thereof.

  In an image display device such as a liquid crystal display, an image is displayed by arranging a large number of liquid crystal pixels in a matrix and controlling the transmission intensity or reflection intensity of incident light for each pixel in accordance with image information to be displayed. This also applies to an organic EL display using an organic EL element as a pixel, but unlike a liquid crystal pixel, the organic EL element is a self-luminous element. Therefore, the organic EL display has advantages such as higher image visibility than the liquid crystal display, no backlight, and high response speed. Further, the luminance level (gradation) of each light emitting element can be controlled by the value of the current flowing therethrough, and is greatly different from a voltage control type such as a liquid crystal display in that it is a so-called current control type.

In the organic EL display, similarly to the liquid crystal display, there are a simple matrix method and an active matrix method as driving methods. Although the former has a simple structure, there is a problem that it is difficult to realize a large-sized and high-definition display. Therefore, the active matrix method is actively developed at present. In this method, a current flowing through a light emitting element in each pixel circuit is controlled by an active element (generally a thin film transistor or TFT) provided in the pixel circuit, and is described in the following patent documents.
JP 2003-255856 A JP 2003-271095 A JP 2004-133240 A JP 2004-029791 A JP 2004-093682 A

  A conventional pixel circuit is arranged at a portion where a row scanning line for supplying a control signal and a column signal line for supplying a video signal intersect, and includes at least a sampling transistor, a capacitor, a drive transistor, and a light emitting element. . The sampling transistor conducts in response to the control signal supplied from the scanning line and samples the video signal supplied from the signal line. The capacitor unit holds an input voltage corresponding to the sampled video signal. The drive transistor supplies an output current during a predetermined light emission period in accordance with the input voltage held in the capacitor unit. In general, the output current depends on the carrier mobility and threshold voltage of the channel region of the drive transistor. The light emitting element emits light with luminance according to the video signal by the output current supplied from the drive transistor.

  The drive transistor receives the input voltage held in the capacitor portion at the gate, causes an output current to flow between the source and the drain, and energizes the light emitting element. In general, the light emission luminance of a light emitting element is proportional to the amount of current applied. Further, the output current supply amount of the drive transistor is controlled by the gate voltage, that is, the input voltage written in the capacitor. The conventional pixel circuit controls the amount of current supplied to the light emitting element by changing the input voltage applied to the gate of the drive transistor in accordance with the input video signal.

Here, the operating characteristic of the drive transistor is expressed by the following Equation 1.
Ids = (1/2) μ (W / L) Cox (Vgs−Vth) ² Formula 1
In the transistor characteristic formula 1, Ids represents a drain current flowing between the source and the drain, and is an output current supplied to the light emitting element in the pixel circuit. Vgs represents a gate voltage applied to the gate with reference to the source, and is the above-described input voltage in the pixel circuit. Vth is the threshold voltage of the transistor. Μ represents the mobility of the semiconductor thin film constituting the channel of the transistor. In addition, W represents the channel width, L represents the channel length, and Cox represents the gate capacitance. As is apparent from the transistor characteristic equation 1, when the thin film transistor operates in the saturation region, if the gate voltage Vgs increases beyond the threshold voltage Vth, the thin film transistor is turned on and the drain current Ids flows. In principle, as shown in the above transistor characteristic equation 1, if the gate voltage Vgs is constant, the same amount of drain current Ids is always supplied to the light emitting element. Therefore, if video signals of the same level are supplied to all the pixels constituting the screen, all the pixels should emit light with the same luminance, and the uniformity of the screen should be obtained.

  However, in reality, thin film transistors (TFTs) composed of semiconductor thin films such as polysilicon have variations in individual device characteristics. In particular, the threshold voltage Vth is not constant and varies from pixel to pixel. As apparent from the transistor characteristic equation 1 described above, if the threshold voltage Vth of each drive transistor varies, even if the gate voltage Vgs is constant, the drain current Ids varies and the luminance varies from pixel to pixel. , Damage the screen uniformity. Conventionally, a pixel circuit incorporating a function for canceling variations in threshold voltages of drive transistors has been developed, and is disclosed in, for example, Patent Document 3 described above.

  A pixel circuit incorporating a function for canceling variations in threshold voltage (threshold voltage correction function) generally operates before sampling a video signal in a pixel capacitor, writes a voltage corresponding to the threshold voltage Vth into the pixel capacitor, The voltage Vth is canceled. For this reason, the threshold voltage correcting operation requires a certain amount of time to charge the pixel capacitance to a voltage corresponding to the threshold voltage. However, the threshold voltage correction time allocated to each pixel has become shorter due to the higher definition of pixels and the resulting increase in the number of pixels, and further the increase in the operation speed of the panel. The threshold voltage correction function cannot be achieved.

  In view of the above-described problems of the conventional technology, an object of the present invention is to provide a display device having a threshold voltage correction function that can cope with an increase in the number of pixels and an increase in operating speed, and a driving method thereof. In order to achieve this purpose, the following measures were taken. That is, the present invention includes a pixel array section, a scanner section, and a signal section, and the pixel array section is disposed at a portion where the scanning lines arranged in rows and the signal lines arranged in columns intersect with each other. The signal unit supplies a video signal to the signal line, the scanner unit supplies a control signal to the scanning line, and sequentially scans the pixels for each row. At least a sampling transistor, a pixel capacitor connected thereto, a drive transistor connected thereto, and a light emitting element connected thereto, wherein the sampling transistor is turned on in response to a control signal supplied from a scanning line The signal potential of the video signal supplied from the line is sampled in the pixel capacitor, and the pixel capacitor enters the gate of the drive transistor in accordance with the signal potential of the sampled video signal. A voltage is applied, and the drive transistor supplies an output current corresponding to the input voltage to the light emitting element, and the output current has a dependency on a threshold voltage of the drive transistor, and the light emitting element A display device that emits light with a luminance corresponding to the signal potential of the video signal by an output current supplied from the drive transistor during a light emission period, wherein the scanner unit outputs a control signal to a scanning line within a horizontal scanning period. To control the pixel and to correct the pixel capacitance to correct the dependency of the output current on the threshold voltage, and to perform the operation of sampling the signal potential of the video signal in the corrected pixel capacitance Further, the scanner unit performs an operation for correcting the pixel capacity in a time-sharing manner in each horizontal scanning period by using the previous horizontal scanning period assigned to the row preceding the pixel of the row. And performing.

  Specifically, each pixel includes a switching transistor for connecting the drive transistor to a power supply, and the switching transistor is supplied from a second scanning line separately from the first scanning line connected to the sampling transistor. And the drive transistor is connected to the power source during the light emission period, and becomes non-conductive during the non-light emission period to disconnect the drive transistor from the power source, and the scanner unit performs the first scanning line during the horizontal scanning period. And a control signal is output to each of the second scanning lines, the sampling transistor and the switching transistor are controlled to be turned on and off, and the pixel capacitance is corrected to correct the dependency of the output current on the threshold voltage. The threshold voltage is applied to the preparatory operation for resetting the pixel capacitance and the reset pixel capacitance. A correction operation for writing a voltage for cell, and then performing a sampling operation for sampling the signal potential of the video signal in the corrected pixel capacity, and the scanner unit further performs a row preceding the pixel in the row. The preparation operation and the correction operation or both of them are performed in a time-sharing manner in each horizontal scanning period using the previous horizontal scanning period assigned to. In this case, the signal unit switches the video signal between the first fixed potential, the second fixed potential, and the signal potential in each horizontal scanning period, and thus the preparation operation, the correction operation, and the A potential necessary for the sampling operation is supplied to each pixel through a signal line. The signal unit supplies a first fixed potential at a high level according to the preparation operation, supplies a second fixed potential at a low level according to the correction operation, and applies the signal potential according to the sampling operation. Supply. Further, the drive transistor has an output current dependent on the carrier mobility of the channel region in addition to the threshold voltage, and the scanner unit outputs a control signal to the second scanning line during a horizontal scanning period. In order to further control the switching transistor and cancel the dependence of the output current on the carrier mobility, the output current is taken out from the drive transistor while the signal potential is sampled, and this is negatively applied to the pixel capacitance. An operation of correcting the input voltage by performing feedback is performed.

  The present invention also includes a pixel array section, a scanner section, and a signal section, and the pixel array section is disposed at a portion where the scanning lines arranged in rows and the signal lines arranged in columns intersect with each other. The signal unit supplies a video signal to the signal line, the scanner unit supplies a control signal to the scanning line, and sequentially scans the pixels for each row. A driving method of a display device including at least a sampling transistor, a pixel capacitor connected thereto, a drive transistor connected thereto, and a light emitting element connected thereto, wherein the sampling transistor is supplied from a scanning line The signal potential of the video signal that is conducted in response to the control signal and supplied from the signal line is sampled in the pixel capacitor, and the pixel capacitor is driven in accordance with the signal potential of the sampled video signal. An input voltage is applied to the gate of the transistor, and the drive transistor supplies an output current corresponding to the input voltage to the light emitting element, and the output current is dependent on a threshold voltage of the drive transistor, The light emitting element emits light with a luminance corresponding to the signal potential of the video signal by an output current supplied from the drive transistor during a light emission period, and the scanner unit outputs a control signal to a scanning line within a horizontal scanning period. To control the pixel and to correct the pixel capacitance to correct the dependency of the output current on the threshold voltage, and to perform the operation of sampling the signal potential of the video signal in the corrected pixel capacitance Further, the scanner unit performs an operation for correcting the pixel capacity in each horizontal scanning period by using the previous horizontal scanning period assigned to the row preceding the pixel of the row. And performing a split manner.

  According to the present invention, the scanner unit of the display device outputs a control signal to the scanning line within the horizontal scanning period to control the pixel, and corrects the pixel capacitance to correct the dependency of the output current on the threshold voltage. The operation and the operation of sampling the signal potential of the video signal in the corrected pixel capacity are executed. At that time, the scanner unit performs an operation for correcting the pixel capacity in a time-sharing manner using the previous horizontal scanning period assigned to the row preceding the pixel in the row. A total correction time is secured by dividing the threshold voltage correction operation into a plurality of horizontal scanning periods. When accumulating correction operations performed in a time-sharing manner in each horizontal scanning period and finally sampling a video signal in the horizontal scanning period, a voltage corresponding to a sufficient threshold voltage is written in the pixel capacitance. I can do it. For this reason, even if the drive frequency of the display device is increased and the horizontal scanning period is shortened, the threshold voltage correction operation can be sufficiently performed.

  According to the present invention, the preparatory operation for canceling the threshold voltage and the actual correction operation are performed within the horizontal scanning period, and further the signal potential sampling operation is performed. By performing necessary operations within the horizontal scanning period in this way, necessary control voltages and signal voltages can be supplied from the signal lines to the pixels, so that the number of elements constituting the pixel circuit can be reduced. Incidentally, the pixel circuit of the present invention can be composed of three transistors, one pixel capacitor, and one light emitting element, and the number of elements can be greatly reduced as compared with a conventional pixel circuit with a threshold voltage correction function. . However, since the correction operation and the sampling operation are performed within the horizontal scanning period, the required operation time cannot be ensured if the horizontal scanning period becomes shorter as the drive frequency increases. Therefore, in the present invention, the correction operation is performed in a time-sharing manner in a plurality of horizontal scanning periods, and the results are accumulated to ensure a substantially sufficient operation time.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. First, in order to clarify the background of the present invention, a reference example of a display device will be described with reference to FIG. This reference example is the basis for developing the display device according to the present invention and is useful for understanding the present invention. Therefore, the reference example will be described here as a reference example.

As shown in the figure, this active matrix display device is composed of a pixel array 1 as a main part and a peripheral circuit part. The peripheral circuit section includes a horizontal selector 3, a write scanner 4, a drive scanner 5, a first correction scanner 71, a second correction scanner 72, and the like. The pixel array 1 is composed of row-like scanning lines WS and column-like signal lines SL, and pixel circuits 2 arranged in a matrix at portions where they intersect. In the figure, only one pixel circuit 2 is enlarged for easy understanding. The signal line SL is driven by the horizontal selector 3. The horizontal selector 3 forms a signal unit and supplies a video signal to the signal line SL. The scanning line WS is scanned by the write scanner 4. In addition, other scanning lines DS, AZ1, and AZ2 are also wired in parallel with the scanning line WS. The scanning line DS is scanned by the drive scanner 5. The scanning line AZ1 is scanned by the first correction scanner 71. The scanning line AZ2 is scanned by the second correction scanner 72. The write scanner 4, the drive scanner 5, the first correction scanner 71, and the second correction scanner 72 constitute a scanner unit, which sequentially scans a row of pixels every horizontal scanning period. Each pixel circuit 2 samples a video signal from the signal line SL when selected by the scanning line WS. Further, when selected by the scanning line DS, the light emitting element EL included in the pixel circuit 2 is driven in accordance with the sampled video signal. In addition, the pixel circuit 2 performs a predetermined correction operation when scanned by the scanning lines AZ1 and AZ2.

  The pixel circuit 2 includes five thin film transistors Tr1 to Tr4 and Trd, one capacitor element (pixel capacitor) Cs, and one light emitting element EL. The transistors Tr1 to Tr3 and Trd are N channel type polysilicon TFTs. Only the transistor Tr4 is a P-channel type polysilicon TFT. One capacitive element Cs constitutes a capacitive part of the pixel circuit 2. The light emitting element EL is, for example, a diode type organic EL element having an anode and a cathode. However, the present invention is not limited to this, and the light emitting element generally includes all devices that emit light by current drive.

  The drive transistor Trd which is the center of the pixel circuit 2 has a gate G connected to one end of the pixel capacitor Cs and a source S connected to the other end of the pixel capacitor Cs. The gate G of the drive transistor Trd is connected to another reference potential Vss1 via the switching transistor Tr2. The drain of the drive transistor Trd is connected to the power source Vcc via the switching transistor Tr4. The gate of the switching transistor Tr2 is connected to the scanning line AZ1. The gate of the switching transistor Tr4 is connected to the scanning line DS. The anode of the light emitting element EL is connected to the source S of the drive transistor Trd, and the cathode is grounded. This ground potential may be represented by Vcath. Further, the switching transistor Tr3 is interposed between the source S of the drive transistor Trd and a predetermined reference potential Vss2. The gate of the transistor Tr3 is connected to the scanning line AZ2. On the other hand, the sampling transistor Tr1 is connected between the signal line SL and the gate G of the drive transistor Trd. The gate of the sampling transistor Tr1 is connected to the scanning line WS.

  In such a configuration, the sampling transistor Tr1 conducts in response to the control signal WS supplied from the scanning line WS during a predetermined sampling period, and samples the video signal Sig supplied from the signal line SL in the capacitor Cs. The capacitor Cs applies an input voltage Vgs between the gate G and the source S of the drive transistor in accordance with the sampled video signal Sig. The drive transistor Trd supplies an output current Ids corresponding to the input voltage Vgs to the light emitting element EL during a predetermined light emission period. The output current (drain current) Ids has dependency on the carrier mobility μ and the threshold voltage Vth in the channel region of the drive transistor Trd. The light emitting element EL emits light with luminance according to the video signal Sig by the output current Ids supplied from the drive transistor Trd.

  As a feature of this reference example, the pixel circuit 2 is provided with a correction unit including switching transistors Tr2 to Tr4, and in order to cancel the dependency of the output current Ids on the carrier mobility μ, the capacitance is previously set at the head of the light emission period. The input voltage Vgs held in the part Cs is corrected. Specifically, the correction means (Tr2 to Tr4) operate in a part of the sampling period according to the control signals WS and DS supplied from the scanning lines WS and DS, and the video signal Sig is sampled. Thus, the output current Ids is extracted from the drive transistor Trd and negatively fed back to the capacitor Cs to correct the input voltage Vgs. Further, the correction means (Tr2 to Tr4) detects the threshold voltage Vth of the drive transistor Trd in advance of the sampling period in order to cancel the dependence of the output current Ids on the threshold voltage Vth, and detects the detected threshold voltage Vth. Is added to the input voltage Vgs.

  In the case of this reference example, the drive transistor Trd is an N-channel transistor, and the drain is connected to the power supply Vcc side, while the source S is connected to the light emitting element EL side. In this case, the correction means described above takes out the output current Ids from the drive transistor Trd at the beginning of the light emission period that overlaps the latter part of the sampling period, and negatively feeds back to the capacitor Cs side. At this time, the present correcting means causes the output current Ids extracted from the source S side of the drive transistor Trd at the head of the light emission period to flow into the capacitance of the light emitting element EL. Specifically, the light emitting element EL is composed of a diode type light emitting element having an anode and a cathode. The anode side is connected to the source S of the drive transistor Trd, and the cathode side is grounded. With this configuration, the correction means (Tr2 to Tr4) sets the anode / cathode of the light emitting element EL in a reverse bias state in advance, and the output current Ids extracted from the source S side of the drive transistor Trd is the light emitting element EL. This diode-type light emitting element EL functions as a capacitive element. The correction means can adjust the time width t for extracting the output current Ids from the drive transistor Trd within the sampling period, and thereby optimizes the negative feedback amount of the output current Ids with respect to the capacitor Cs.

  FIG. 2 is a schematic view of a pixel circuit portion extracted from the display device shown in FIG. For easy understanding, the video signal Sig sampled by the sampling transistor Tr1, the input voltage Vgs and output current Ids of the drive transistor Trd, and the capacitance component Coled of the light emitting element EL are added. The operation of the pixel circuit 2 according to the reference example will be described below with reference to FIG.

  FIG. 3 is a timing chart of the pixel circuit shown in FIG. With reference to FIG. 3, the operation of the pixel circuit according to the reference example shown in FIG. 2 will be described more specifically. FIG. 3 shows waveforms of control signals applied to the scanning lines WS, AZ1, AZ2, and DS along the time axis T. In order to simplify the notation, the control signals are also represented by the same reference numerals as the corresponding scanning lines. Since the transistors Tr1, Tr2 and Tr3 are N-channel type, they are turned on when the scanning lines WS, AZ1 and AZ2 are at a high level and turned off when the scanning lines are at a low level. On the other hand, since the transistor Tr4 is a P-channel type, it is turned off when the scanning line DS is at a high level and turned on when it is at a low level. This timing chart also shows the change in the potential of the gate G and the change in the potential of the source S of the drive transistor Trd, along with the waveforms of the control signals WS, AZ1, AZ2, and DS.

  In the timing chart of FIG. 3, timings T1 to T8 are defined as one field (1f). Each row of the pixel array is sequentially scanned once during one field. The timing chart shows the waveforms of the control signals WS, AZ1, AZ2, DS applied to the pixels for one row.

  At timing T0 before the field starts, all control line numbers WS, AZ1, AZ2, DS are at a low level. Therefore, the N-channel transistors Tr1, Tr2, Tr3 are in the off state, while only the P-channel transistor Tr4 is in the on state. Therefore, since the drive transistor Trd is connected to the power supply Vcc via the transistor Tr4 in the on state, the output current Ids is supplied to the light emitting element EL according to the predetermined input voltage Vgs. Therefore, the light emitting element EL emits light at the timing T0. At this time, the input voltage Vgs applied to the drive transistor Trd is expressed by the difference between the gate potential (G) and the source potential (S).

  At the timing T1 when the field starts, the control signal DS is switched from the low level to the high level. As a result, the transistor Tr4 is turned off and the drive transistor Trd is disconnected from the power supply Vcc, so that the light emission stops and the non-light emission period starts. Therefore, at the timing T1, all the transistors Tr1 to Tr4 are turned off.

  Subsequently, at timing T2, since the control signals AZ1 and AZ2 are at a high level, the switching transistors Tr2 and Tr3 are turned on. As a result, the gate G of the drive transistor Trd is connected to the reference potential Vss1, and the source S is connected to the reference potential Vss2. Here, Vss1−Vss2> Vth is satisfied, and by setting Vss1−Vss2 = Vgs> Vth, preparation for Vth correction performed at timing T3 is performed. In other words, the period T2-T3 corresponds to a reset period of the drive transistor Trd. Further, when the threshold voltage of the light emitting element EL is VthEL, VthEL> Vss2 is set. Thereby, a minus bias is applied to the light emitting element EL, and a so-called reverse bias state is obtained. This reverse bias state is necessary for normally performing the Vth correction operation and the mobility correction operation to be performed later.

  At timing T3, the control signal AZ2 is set to the low level, and the control signal DS is also set to the low level. As a result, the transistor Tr3 is turned off while the transistor Tr4 is turned on. As a result, the drain current Ids flows into the pixel capacitor Cs, and the Vth correction operation is started. At this time, the gate G of the drive transistor Trd is held at Vss1, and the current Ids flows until the drive transistor Trd is cut off. When cut off, the source potential (S) of the drive transistor Trd becomes Vss1-Vth. At timing T4 after the drain current is cut off, the control signal DS is returned to the high level again, and the switching transistor Tr4 is turned off. Further, the control signal AZ1 is also returned to the low level, and the switching transistor Tr2 is also turned off. As a result, Vth is held and fixed in the pixel capacitor Cs. Thus, the timing T3-T4 is a period for detecting the threshold voltage Vth of the drive transistor Trd. Here, this detection period T3-T4 is called a Vth correction period.

  After performing the Vth correction in this way, the control signal WS is switched to the high level at timing T5, the sampling transistor Tr1 is turned on, and the signal potential Vsig of the video signal Sig is written into the pixel capacitor Cs. The pixel capacitance Cs is sufficiently smaller than the equivalent capacitance Coled of the light emitting element EL. As a result, most of the video signal Sig is written into the pixel capacitor Cs. To be precise, for Vss1. A difference Vsig−Vss1 of the signal voltage Vsig is written into the pixel capacitor Cs. Therefore, the voltage Vgs between the gate G and the source S of the drive transistor Trd becomes a level (Vsig−Vss1 + Vth) obtained by adding Vth previously detected and held and Vsig−Vss1 sampled this time. Hereinafter, if Vss1 = 0V for simplification of explanation, the gate / source voltage Vgs becomes Vsig + Vth as shown in the timing chart of FIG. The sampling of the video signal Sig is performed until timing T7 when the control signal WS returns to the low level. That is, the timing T5-T7 corresponds to the sampling period.

  At timing T6 before the end of the sampling period T7, the control signal DS becomes low level and the switching transistor Tr4 is turned on. As a result, the drive transistor Trd is connected to the power supply Vcc, so that the pixel circuit proceeds from the non-light emitting period to the light emitting period. In this manner, the mobility correction of the drive transistor Trd is performed in the period T6-T7 in which the sampling transistor Tr1 is still on and the switching transistor Tr4 is on. That is, in this reference example, the mobility correction is performed in the period T6-T7 in which the latter part of the sampling period and the head part of the light emission period overlap. Note that, at the beginning of the light emission period in which the mobility correction is performed, the light emitting element EL is actually in a reverse bias state, and thus does not emit light. In the mobility correction period T6-T7, the drain current Ids flows through the drive transistor Trd while the gate G of the drive transistor Trd is fixed to the level Vsig of the video signal Sig. Here, by setting Vss1−Vth <VthEL, the light emitting element EL is placed in a reverse bias state, so that it exhibits simple capacitance characteristics instead of diode characteristics. Therefore, the current Ids flowing through the drive transistor Trd is written into a capacitor C = Cs + Coled obtained by combining both the pixel capacitor Cs and the equivalent capacitor Coled of the light emitting element EL. As a result, the source potential (S) of the drive transistor Trd increases. In the timing chart of FIG. 3, this increase is represented by ΔV. Since this increase ΔV is eventually subtracted from the gate / source voltage Vgs held in the pixel capacitor Cs, negative feedback is applied. In this way, the mobility μ can be corrected by negatively feeding back the output current Ids of the drive transistor Trd to the input voltage Vgs of the drive transistor Trd. The negative feedback amount ΔV can be optimized by adjusting the time width t of the mobility correction period T6-T7.

At timing T7, the control signal WS becomes low level and the sampling transistor Tr1 is turned off. As a result, the gate G of the drive transistor Trd is disconnected from the signal line SL. Since the application of the video signal Sig is cancelled, the gate potential (G) of the drive transistor Trd can be increased and increases with the source potential (S). Meanwhile, the gate / source voltage Vgs held in the pixel capacitor Cs maintains a value of (Vsig−ΔV + Vth). As the source potential (S) rises, the reverse bias state of the light emitting element EL is canceled, so that the light emitting element EL actually starts to emit light by the inflow of the output current Ids. The relationship between the drain current Ids and the gate voltage Vgs at this time is given by the following equation 2 by substituting Vsig−ΔV + Vth into Vgs of the previous transistor characteristic equation 1.
Ids = kμ (Vgs−Vth) ² = kμ (Vsig−ΔV) ² Equation 2
In the above formula 2, k = (1/2) (W / L) Cox. It can be seen from the characteristic formula 2 that the term Vth is canceled and the output current Ids supplied to the light emitting element EL does not depend on the threshold voltage Vth of the drive transistor Trd. Basically, the drain current Ids is determined by the signal voltage Vsig of the video signal. In other words, the light emitting element EL emits light with a luminance corresponding to the potential level Vsig of the video signal Sig. At that time, Vsig is corrected by the feedback amount ΔV. This correction amount ΔV acts so as to cancel the effect of the mobility μ located in the coefficient part of the characteristic formula 2 just. Therefore, the drain current Ids substantially depends only on the video signal potential Vsig.

  Finally, when the timing T8 is reached, the control signal DS becomes high level, the switching transistor Tr4 is turned off, the light emission ends, and the field ends. Thereafter, the operation proceeds to the next field, and the Vth correction operation, the mobility correction operation, and the light emission operation are repeated again.

  However, in the pixel circuit according to this reference example, five types of transistors Tr1, Tr2, Tr3, Tr4, Trd, three types of power supply lines Vss1, Vss2, Vcc, and four types of gate lines (scanning lines) WS, DS, AZ1. , AZ2 need to be formed, and the crossover with the power line and the signal line increases. This causes a decrease in yield. Furthermore, it becomes difficult to achieve high definition in terms of layout. In a high-definition panel, it is necessary to reduce the number of elements in order to increase the yield.

  FIG. 4 shows the overall configuration of the display device according to the present invention, which is an active matrix type having a threshold voltage (Vth) correction function. As shown in the figure, this active matrix display device is composed of a pixel array 1 as a main part and a peripheral circuit part. The peripheral circuit unit includes a horizontal selector 3, a write scanner 4, a drive scanner 5, and the like. The pixel array 1 includes row-like scanning lines WS and column-like signal lines SL, and pixels R, G, and B arranged in a matrix at the intersection of the two. In order to enable color display, RGB three primary color pixels are prepared, but the present invention is not limited to this. Each pixel R, G, B is composed of a pixel circuit 2. The signal line SL is driven by the horizontal selector 3. The horizontal selector 3 constitutes a signal unit, and generally a driver IC is used to supply a video signal to the signal line SL. The scanning line WS is scanned by the write scanner 4. Note that a second scanning line DS is also wired in parallel with the first scanning line WS. The scanning line DS is scanned by the drive scanner 5. The write scanner 4 and the drive scanner 5 constitute a scanner unit, and sequentially scan the pixel rows every horizontal scanning period. Each pixel circuit 2 samples a video signal from the signal line SL when selected by the scanning line WS. Further, when selected by the scanning line DS, the light emitting element included in the pixel circuit 2 is driven in accordance with the sampled video signal. In addition, the pixel circuit 2 performs a predetermined correction operation when controlled by the scanning lines WS and DS within the horizontal scanning period.

  The pixel array 1 described above is usually formed on an insulating substrate such as glass and is a flat panel. Each pixel circuit 2 is formed of an amorphous silicon thin film transistor (TFT) or a low temperature polysilicon TFT. In the case of an amorphous silicon TFT, the scanner part is composed of TAB or the like different from the panel, and is connected to the flat panel with a flexible cable. Similarly, the signal section is also composed of an external driver IC, and is connected to the flat panel with a flexible cable. In the case of the low-temperature polysilicon TFT, the signal portion and the scanner portion can be formed of the same low-temperature polysilicon TFT, so that the pixel array portion, the signal portion, and the scanner portion can be integrally formed on the flat panel.

  FIG. 5 shows an embodiment of a pixel circuit incorporated in the display device shown in FIG. This pixel circuit 2 includes a sampling transistor Tr1, a pixel capacitor Cs connected thereto, a drive transistor Trd connected thereto, a light emitting element EL connected thereto, and a switching transistor Tr4 connecting the drive transistor Trd to a power supply Vcc. Including.

The sampling transistor Tr1 conducts according to the control signal WS supplied from the first scanning line WS and samples the signal potential Vsig of the video signal supplied from the signal line SL into the pixel capacitor Cs. The pixel capacitor Cs applies the input voltage Vgs to the gate G of the drive transistor Trd in accordance with the signal potential Vsig of the sampled video signal. The drive transistor Trd supplies an output current Ids corresponding to the input voltage Vgs to the light emitting element EL. The output current Ids has a dependency on the threshold voltage Vth of the drive transistor Trd. The light emitting element EL emits light with luminance corresponding to the signal potential Vsig of the video signal by the output current Ids supplied from the drive transistor Trd during the light emission period. The switching transistor Tr4 is turned on in response to the control signal DS supplied from the second scanning line DS, connects the drive transistor Trd to the power source Vcc during the light emission period, and becomes non-conductive during the non-light emission period, and powers the drive transistor Trd. Disconnect from Vcc.

  As a characteristic matter, the scanner unit composed of the write scanner 4 and the drive scanner 5 outputs control signals WS and DS to the first scanning line WS and the second scanning line DS in the horizontal scanning period (1H), respectively, and the sampling transistor A preparatory operation for resetting the pixel capacitor Cs in order to correct the dependency of the output current Ids on the threshold voltage Vth by controlling the Tr1 and the switching transistor Tr4, and canceling the threshold voltage Vth to the reset pixel capacitor Cs. A correction operation for writing the voltage and a sampling operation for sampling the signal potential Vsig of the video signal Sig in the corrected pixel capacitance Cs are executed. On the other hand, the signal section composed of the horizontal selector (driver IC) 3 switches the video signal between the first fixed potential VssH, the second fixed potential VssL, and the signal potential Vsig during the horizontal scanning period (1H). Thus, the potentials necessary for the above-described preparation operation, correction operation, and sampling operation are supplied to each pixel through the signal line SL.

  Specifically, the horizontal selector 3 first supplies a high-level first fixed potential VssH, then switches to a low-level second fixed potential VssL to enable a preparatory operation, and further applies a low-level second fixed potential VssL. The correction operation is executed in the maintained state, and then the sampling operation is executed by switching to the signal potential Vsig. As described above, the horizontal selector 3 includes a driver IC, and inserts the first fixed potential VssH and the second fixed potential VssL into the signal generation circuit that generates the signal potential Vsig and the signal potential Vsig output from the signal generation circuit. Therefore, an output circuit that synthesizes a video signal for switching between the first fixed potential VssH, the second fixed potential VssL, and the signal potential Vsig and outputs the synthesized video signal to each signal line SL is included. Preferably, the driver IC constituting the horizontal selector 3 outputs a video signal obtained by synthesizing the signal potential Vsig not exceeding the normal rating and the first fixed potential VssH exceeding the rating. In this case, the signal generation circuit included in the driver IC has a normal breakdown voltage to generate the signal potential Vsig that does not exceed the rating, while the output circuit has a high breakdown voltage to cope with the first fixed potential VssH that exceeds the rating. .

  In the drive transistor Trd, the output current Ids depends on the carrier mobility μ in the channel region in addition to the threshold voltage Vth. In this case, the scanner unit composed of the write scanner 4 and the drive scanner 5 outputs a control signal to the second scanning line DS in the horizontal scanning period (1H), further controls the switching transistor Tr4, and moves the carrier of the output current Ids. In order to cancel the dependence on the degree μ, an output current is taken out from the drive transistor Trd in a state where the signal potential Vsig is sampled, and this is negatively fed back to the pixel capacitor Cs to correct the input voltage Vgs.

  FIG. 6 is a schematic diagram in which a portion of the pixel circuit 2 is taken out from the display device shown in FIG. In order to facilitate understanding, the video signal Sig sampled by the sampling transistor Tr1, the input voltage Vgs and output current Ids of the drive transistor Trd, and the capacitance component Coled of the light emitting element EL are added. The scanning lines WS and DS connected to the gates of the transistors are also written. The pixel circuit 2 performs a Vth correction preparation operation, an actual correction operation, and a signal potential sampling operation within the horizontal scanning period (1H). Accordingly, the pixel circuit 2 can be configured with three transistors Tr1, Tr4, Trd, one pixel capacitor Cs, and one light emitting element EL. Compared to the pixel circuit incorporating the Vth correction function according to the reference example shown in FIG. 1, at least two transistors can be reduced. As a result, power lines and gate lines can be reduced, which leads to an improvement in panel yield. Further, high definition can be achieved by simplifying the layout of the pixel circuit.

  FIG. 7 is a timing chart of the pixel circuit shown in FIGS. With reference to FIG. 7, the operation of the pixel circuit shown in FIGS. 5 and 6 will be described specifically and in detail. FIG. 7 shows the waveforms of control signals applied to the scanning lines WS and DS along the time axis T. In order to simplify the notation, the control signals are also denoted by the same reference numerals as the corresponding scanning lines. In addition, the waveform of the video signal Sig applied to the signal line is also shown along the time axis T. As shown in the figure, this video signal is sequentially switched between a high potential VssH, a low potential VssL, and a signal potential Vsig within each horizontal scanning period (1H). Since the transistor Tr1 is an N-channel type, it is turned on when the scanning line WS is at a high level and turned off when it is at a low level. On the other hand, since the transistor Tr4 is a P-channel type, it is turned off when the scanning line DS is at a high level and turned on when it is at a low level. This timing chart also shows the change in the potential of the gate G and the change in the potential of the source S of the drive transistor Trd, along with the waveforms of the control signals WS and DS and the waveform of the video signal.

  In the timing chart of FIG. 7, timings T1 to T8 are defined as one field (1f). Each row of the pixel array is sequentially scanned once during one field. The timing chart shows the waveforms of the control signals WS and DS applied to the pixels for one row.

  First, at the timing T1, the switching transistor Tr4 is turned off to emit no light. At this time, since the source potential of the drive transistor Trd is not supplied from Vcc, it is lowered to the cut-off voltage VthEL of the light emitting element EL.

  Next, at timing T2, the sampling transistor Tr1 is turned on. However, it is preferable to increase the signal line voltage to VssH before this because the writing time can be shortened. By turning on the sampling transistor Tr1, VssH is written as the gate potential of the drive transistor Trd. At this time, coupling enters the source potential via the pixel capacitor Cs, and the source potential rises. Although the potential of the source S rises once, it is discharged through the light emitting element EL, so that the source voltage becomes VthEL again. At this time, the gate voltage remains VssH.

  Next, at timing Ta, the signal voltage is changed to VssL while the sampling transistor Tr1 is kept on. This potential change is coupled to the source potential via the pixel capacitor Cs. The amount of coupling at this time is determined by Cs / (Cs + Coled) × (VssH−VssL). At this time, the gate potential is represented by VssL, and the source potential is represented by VthEL−Cs / (Cs + Coled) × (VssH−VssL). Since a negative bias is applied here, the source voltage becomes lower than VthEL, and the light emitting element EL is cut off. Here, the source potential is desirably set to a potential at which the light emitting element EL continues to be cut off after the subsequent Vth correction or mobility correction. Further, by adding coupling so that Vgs> Vth, preparation for Vth correction can be made. As described above, Vth correction preparation can be performed even in a circuit in which transistors, power supply lines, and gate lines are reduced. That is, the timings T2 to Ta are included in the correction preparation period.

  Thereafter, when the switching transistor Tr4 is turned on with the gate G held at VssL at the timing T3, a current flows through the drive transistor Trd, and Vth correction is performed as in the reference example. A current flows until the drive transistor Trd is cut off. When the drive transistor Trd is cut off, the source potential of the drive transistor Trd becomes VssL−Vth. Here, it is necessary to satisfy VssL−Vth <VthEL.

  Thereafter, at timing T4, the switching transistor Tr4 is turned off and the Vth correction ends. That is, the timings T3 to T4 are Vth correction periods.

  After performing Vth correction at timings T3 to T4 in this way, the potential of the signal line changes from VssL to Vsig at timing T5. As a result, the signal potential Vsig of the video signal is written into the pixel capacitor Cs. The pixel capacitance Cs is sufficiently smaller than the equivalent capacitance Coled of the light emitting element EL. As a result, most of the signal potential Vsig is written into the pixel capacitor Cs. Therefore, the voltage Vgs between the gate G and the source S of the drive transistor Trd becomes a level (Vsig + Vth) obtained by adding Vth previously detected and held and Vsig sampled this time. That is, the input voltage Vgs to the drive transistor Trd is Vsig + Vth. The sampling of the signal voltage Vsig is performed until timing T7 when the control signal WS returns to the low level. That is, timings T5 to T7 correspond to the sampling period.

  The pixel circuit according to the present invention corrects the mobility μ in addition to the correction of the threshold voltage Vth described above. The mobility μ is corrected at timings T6 to T7. This point will be described later in detail. As a conclusion, as shown in the timing chart, the correction amount ΔV is subtracted from the input voltage Vgs.

  At timing T7, the control signal WS becomes low level and the sampling transistor Tr1 is turned off. As a result, the gate G of the drive transistor Trd is disconnected from the signal line SL. Since the application of the video signal Sig is cancelled, the gate potential (G) of the drive transistor Trd can be increased and increases with the source potential (S). Meanwhile, the gate / source voltage Vgs held in the pixel capacitor Cs maintains a value of (Vsig−ΔV + Vth). As the source potential (S) rises, the reverse bias state of the light emitting element EL is canceled, so that the light emitting element EL actually starts to emit light by the inflow of the output current Ids. The relationship between the drain current Ids and the gate voltage Vgs at this time is given by the above-described equation 2. It can be seen from the characteristic formula 2 that the term Vth is canceled and the output current Ids supplied to the light emitting element EL does not depend on the threshold voltage Vth of the drive transistor Trd. Basically, the drain current Ids is determined by the signal voltage Vsig of the video signal. In other words, the light emitting element EL emits light with a luminance corresponding to the video signal Sig. At that time, Vsig is corrected by the feedback amount ΔV. This correction amount ΔV acts so as to cancel the effect of the mobility μ located in the coefficient part of the characteristic formula 2 just. Therefore, the drain current Ids substantially depends only on the signal potential Vsig of the video signal Sig.

  Finally, when the timing T8 is reached, the control signal DS becomes high level, the switching transistor Tr4 is turned off, the light emission ends, and the field ends. Thereafter, the process proceeds to the next field, and the correction preparation operation, the Vth correction operation, the mobility correction operation, and the light emission operation are repeated again.

  As shown in the timing chart of FIG. 7, the preparatory operation for correcting the threshold voltage, the correction operation, and the sampling operation are continuously performed within one horizontal scanning period (1H), so that the pixel circuit as shown in FIG. 2 can be composed of three transistors and one pixel capacitor. As a result, the number of constituent elements of the pixel circuit is significantly reduced compared to the reference example. However, since the number of pixels increases as the panel becomes higher in definition, the horizontal scanning period assigned to each pixel row becomes shorter. In addition, a high-frequency driving method has been proposed to improve the image quality, but the horizontal scanning period is similarly shortened in this high-frequency driving. If the horizontal scanning period is shortened in this way, it may be difficult to complete the Vth correction preparation operation or the actual Vth correction operation within one horizontal scanning period. Therefore, a display device driving method corresponding to a high-definition panel or a high-frequency driving panel is required, and will be described below as the best embodiment of the present invention.

  In the best embodiment of the present invention, the number of elements is reduced by a pixel circuit with a Vth correction function, and a driving method that can be applied to a high-definition panel or a high-frequency driving panel is realized. In the present embodiment, the Vth correction preparation and the Vth correction operation that have been performed within one horizontal scanning period are executed in a time-sharing manner over a plurality of horizontal scanning periods, so that the total operation time is shown in the timing chart shown in FIG. It can be secured to the same extent as the driving method. In this time division method, the preparatory operation period and the correction operation period occupying one horizontal scanning period can be shortened, so that it is possible to secure a sufficient signal potential sampling time.

  FIG. 8 is a timing chart showing the best embodiment of the present invention. For easy understanding, portions corresponding to the timing chart of the previous example shown in FIG. 7 are denoted by corresponding reference numerals.

  As shown in the figure, at the timing T1, the switching transistor Tr4 is turned off to emit no light. At this time, since the source potential of the drive transistor Trd is not supplied from Vcc, it is lowered to the cut-off voltage VthEL of the light emitting element EL.

  Next, the sampling transistor Tr1 is turned on at timings T21 to Tb1 in a time zone in which the video signal Sig becomes the high voltage VssH necessary for Vth correction preparation. By turning on the sampling transistor Tr1, VssH is written to the gate potential of the drive transistor Trd. At this time, coupling enters the source potential via the pixel capacitor Cs, and the source potential rises. Although the source S rises once, it is discharged through the light emitting element EL, so that the source voltage becomes VthEL again. The control signal WS for turning on the sampling transistor Tr1 is a divided pulse, the pulse width (T21 to Tb1) is very short, and the gate voltage is not written up to VssH. Therefore, at the subsequent timings T22 to Tb2, when the video signal Sig becomes the high voltage VssH again, the sampling transistor Tr1 is turned on. If necessary, the same operation is repeated until the gate voltage becomes VssH.

  Next, the sampling transistor Tr1 is turned on while the video signal Sig is changed to the low voltage VssL. With this potential change, Vgs> Vth, and preparation for Vth correction can be completed. With the sampling transistor Tr1 turned on, the switching transistor Tr4 is further turned on at timings T31 to T41, whereby a current flows through the drive transistor Trd and the Vth correction operation is performed. Similarly, since the Vth correction period is also divided and the time width (timing T31 to T41) of each pulse is shortened, it is necessary to repeatedly drive the sampling transistor Tr1 and the switching transistor Tr4 on until the Vth correction is completed. Yes (timing T32 to T42).

  Finally, the signal voltage Vsig is written into the pixel capacitor Cs at timings T5 to T7 when the sampling transistor Tr1 is turned on. Meanwhile, after the mobility correction is performed at timings T6 to T7, the light emission state is entered.

  As described above, in a circuit in which transistors, power supply lines, and gate lines are reduced, Vth correction preparation and Vth correction can be performed even if the operation of the panel is high frequency and the pixels are high definition. In the above embodiment, the mobility correction is performed by turning on the switching transistor Tr4 with the sampling transistor Tr1 turned on. However, the mobility correction is performed by making the sampling transistor Tr1 and the switching transistor Tr4 non-overlapping. Even in a simple Vth correction operation, the number of wirings and transistors can be similarly reduced. In the circuit of this embodiment, the switching transistor Tr4 is an Nch type, but the characteristics of each transistor may be Nch or Pch.

  As described above, the scanner unit of the present invention outputs a control signal to the scanning line within the horizontal scanning period to control the pixel circuit 2 and correct the dependency of the output current Ids of the drive transistor Trd on the threshold voltage Vth. An operation of correcting the capacitance Cs and an operation of sampling the signal potential Vsig of the video signal Sig to the corrected pixel capacitance Cs are executed, and the scanner unit is assigned to a row preceding the pixel circuit of the row. An operation for correcting the pixel capacitance Cs using the previous horizontal scanning period is performed in a time-sharing manner in each horizontal scanning period. Specifically, the scanner unit includes a write scanner 4 and a drive scanner 5, and outputs control signals to the first scanning line WS and the second scanning line DS in the horizontal scanning period, respectively, and the sampling transistor Tr1 and the switching transistor Tr4. Are turned on and off to correct the dependency of the output current Ids on the threshold voltage Vth, and to correct the pixel capacitance Cs, the preparatory operation for resetting the pixel capacitance Cs and the threshold voltage Vth applied to the reset pixel capacitance Cs. A correction operation for writing a voltage for canceling the image signal is performed, and then a sampling operation for sampling the signal potential Vsig of the video signal Sig in the corrected pixel capacitance Cs is executed. Further, the scanner unit precedes the pixel in the row. Preparation and correction operations using the previous horizontal scan period assigned to a row Divisionally performs time at both or one each horizontal scanning period.

  Next, the mobility correction operation performed at the timing T6-T7 will be described in detail. FIG. 9 is a circuit diagram showing a state of the pixel circuit 2 in the mobility correction period T6-T7. As shown in the figure, in the mobility correction period T6-T7, the sampling transistor Tr1 and the switching transistor Tr4 are turned on, while the remaining switching transistors Tr3 are turned off. In this state, the source potential (S) of the drive transistor Tr4 is VssL-Vth. This source potential S is also the anode potential of the light emitting element EL. As described above, by setting VssL−Vth <VthEL, the light emitting element EL is placed in a reverse bias state and exhibits simple capacitance characteristics instead of diode characteristics. Therefore, the current Ids flowing through the drive transistor Trd flows into the combined capacitance C = Cs + Coled of the pixel capacitance Cs and the equivalent capacitance Coled of the light emitting element EL. In other words, a part of the drain current Ids is negatively fed back to the pixel capacitor Cs, and the mobility is corrected.

  FIG. 10 is a graph of the transistor characteristic equation 2 described above, where Ids is plotted on the vertical axis and Vsig is plotted on the horizontal axis. The characteristic formula 2 is also shown below the graph. In the graph of FIG. 10, a characteristic curve is drawn in a state where the pixel 1 and the pixel 2 are compared. The mobility μ of the drive transistor of the pixel 1 is relatively large. Conversely, the mobility μ of the drive transistor included in the pixel 2 is relatively small. Thus, when the drive transistor is composed of a polysilicon thin film transistor or the like, it is inevitable that the mobility μ varies between pixels. For example, when the video signal potential Vsig of the same level is written in both the pixels 1 and 2, the output current Ids 1 ′ flowing through the pixel 1 having a high mobility μ is a pixel having a low mobility μ if no mobility correction is performed. As compared with the output current Ids 2 ′ flowing in the circuit 2, a large difference occurs. In this way, a large difference occurs between the output currents Ids due to the variation in the mobility μ, so that the uniformity of the screen is impaired.

  Therefore, in the present invention, the variation in mobility is canceled by negatively feeding back the output current to the input voltage side. As is clear from the transistor characteristic equation, the drain current Ids increases when the mobility is large. Therefore, the negative feedback amount ΔV increases as the mobility increases. As shown in the graph of FIG. 10, the negative feedback amount ΔV1 of the pixel 1 having a high mobility μ is larger than the negative feedback amount ΔV2 of the pixel 2 having a low mobility. Therefore, the larger the mobility μ is, the more negative feedback is applied, and the variation can be suppressed. As shown in the figure, when ΔV1 is corrected in the pixel 1 having a high mobility μ, the output current greatly decreases from Ids1 ′ to Ids1. On the other hand, since the correction amount ΔV2 of the pixel 2 having the low mobility μ is small, the output current Ids2 ′ does not decrease so much to Ids2. As a result, Ids1 and Ids2 are substantially equal, and the variation in mobility is cancelled. Since the cancellation of the variation in mobility is performed in the entire range of Vsig from the black level to the white level, the uniformity of the screen becomes extremely high. In summary, when there are pixels 1 and 2 having different mobility, the correction amount ΔV1 of the pixel 1 having high mobility is smaller than the correction amount ΔV2 of the pixel 2 having low mobility. That is, as the mobility increases, ΔV increases and the decrease value of Ids increases. As a result, pixel current values having different mobilities are made uniform, and variations in mobility can be corrected.

For reference, a numerical analysis of the mobility correction described above is performed with reference to FIG. As shown in FIG. 11, the analysis is performed by taking the source potential of the drive transistor Trd as a variable V in a state where the transistors Tr1 and Tr4 are turned on. Assuming that the source potential (S) of the drive transistor Trd is V, the drain current Ids flowing through the drive transistor Trd is as shown in Equation 3 below.

Further, Ids = dQ / dt = CdV / dt is established as shown in the following Expression 4 by the relationship between the drain current Ids and the capacitance C (= Cs + Coled).

Both sides are integrated by substituting Equation 3 into Equation 4. Here, the initial state of the source voltage V is -Vth, and the mobility variation correction time (T6-T7) is t. When this differential equation is solved, the pixel current with respect to the mobility correction time t is given as shown in Equation 5 below.

  FIG. 12 is a graph of Equation 5, in which the vertical axis represents the output current Ids and the horizontal axis represents the signal potential Vsig of the video signal Sig. As the parameters, mobility correction periods t = 0 us, 2.5 us, and 5 us are set. Further, when the mobility μ is a relatively large parameter, the parameter is 1.2 μ and the relatively small mobility is 0.8 μ. It can be seen that the mobility variation is sufficiently corrected at t = 2.5 us, compared to the case where the mobility correction is not substantially applied at t = 0 us. Without mobility correction, Ids with 40% variation can be reduced to 10% or less when mobility correction is applied. However, if the correction period is lengthened with t = 5 us, the variation in the output current Ids due to the difference in mobility μ is increased. Thus, in order to apply appropriate mobility correction, it is necessary to set t to an optimal value. In the case of the graph shown in FIG. 12, the optimum value is in the vicinity of t = 2.5 us.

  As described above, in the present invention, the Vth correction preparation by changing the gate voltage from the high voltage to the low voltage and the Vth correction operation are performed within 1H, and then the video signal is written within the same horizontal scanning period. With this operation, the power lines, the switching transistors, and the gate lines can be reduced by sharing the three types of power sources, which have been required in the past, with the signal lines, and a three-transistor one-capacitance pixel circuit can be configured. it can. As described above, the yield of the panel can be improved. In addition, high definition can be achieved by reducing the layout. In this embodiment, the mobility correction is performed by turning on the switching transistor Tr4 with the sampling transistor Tr1 turned on. However, the mobility correction is not performed by making the sampling transistor Tr1 and the switching transistor Tr4 non-overlapping. In the Vth correction operation, the number of wirings and transistors can be similarly reduced.

  Finally, an embodiment of the data driver constituting the signal unit (horizontal selector) of the display device according to the present invention will be described. In the present embodiment, the data driver arranged in the column direction of the image display device and used to display image data can switch and output a signal potential representing image data and a fixed potential for pixel circuit control, When the pixel circuit control fixed potential requires a voltage amplitude higher than the maximum rated voltage of a general data driver, the image data signal potential and the pixel circuit control fixed potential near the output terminal are switched. By increasing the withstand voltage of only the switch function part, it is possible to realize the necessary functions in the driver manufacturing process without changing to a withstand voltage process, changing the circuit size, increasing the terminal pitch, etc. It is.

  FIG. 13 shows an example of a pixel circuit (A) and a drive waveform (B) of an image display device in which a signal potential representing image data and a fixed potential for controlling a pixel circuit are mixed on a data signal line. The pixel circuit shown in FIG. 5A includes three transistors, one pixel capacitor, and one light emitting element EL. The pixel circuit according to the embodiment of the present invention shown in FIG. It is a generalization. The video signal Sig is supplied from the data signal line SL. The drive transistor Trd is driven by the voltage value Vpc of the video signal, and the light emitting element EL emits light with a desired brightness. In this image display apparatus, since the characteristic variation of the drive transistor Trd directly affects the image quality at this time, the pixel capacitance Cs is used to correct this variation during the correction period. When this correction operation is performed, a fixed potential Vst for control is sent from the data signal line SL to the pixel circuit using the drive waveforms of the scan pulse WA and the scan pulse DS. In a normal image display device, the signal line for the image data system and the signal line for the drive control system are separated, and separate wiring and scanning pulses are arranged when the control system signal is input. However, if the number of elements in the pixel circuit increases, the yield deteriorates due to transistor defects, and the area required for one pixel circuit increases. Therefore, adverse effects such as a decrease in physical resolution can be considered. In order to reduce the number of circuit elements as much as possible and correct variations in the drive transistor Trd, the signal potential Vpc corresponding to the image data and the fixed potential Vst for controlling the pixel circuit are separated from the data signal line SL during sampling and during correction. Need to be sent.

  At this time, the fixed voltage Vst for controlling the pixel circuit is not necessarily in the same range as the signal voltage Vpc of the image data. As in the waveform timing chart example of (B), the control signal voltage Vst may be higher than the image signal voltage Vpc, and Vst may be higher than the rated voltage of the data driver IC. The normal driver output is indefinite (high impedance) during the non-display period. In this pixel circuit, Vst and Vpc are separated into the sampling period and the correction period, and the voltage between them is fixed at the ground level GND. Things may be necessary.

  FIG. 14 shows a block configuration of the data driver IC 3 that satisfies such a drive waveform condition. A portion surrounded by a square solid line is a high withstand voltage output circuit unit 32. If only a circuit in this is increased by increasing the wiring film thickness, the image signal generation circuit unit 31 has a normal withstand voltage. And can be made by a process. The output circuit unit 32 includes voltage switching switches SW1 and SW2. However, since the control signal for the switch SW1 and the control signal for the switch SW2 are logic signals for controlling ON / OFF of the switch, there is no need to increase the breakdown voltage.

  The output terminal 31B of the image signal generation circuit unit 31 outputs output voltages Vpc1 to Vpcn having the image display system power supply voltage Vpc as a maximum voltage. This output voltage is sent to the switch SW1 and switched to a fixed voltage for controlling the pixel circuit. The fixed voltage for controlling the pixel circuit is a logic pulse having an amplitude of the control system power supply voltage Vst. The output of the switch SW1 is sent to the switch SW2. The switch SW2 selects a signal or GND in order to fix the output terminal at the GND level when switching between Vpc1 to Vpcn and Vst. As a result, as the final output signal Sig, Vst having the control system power supply voltage as a maximum value, Vpc1 to Vpcn having the maximum value as the image display system power supply voltage, or a GND level voltage is output to the final output terminal 32B.

It is a block diagram which shows the reference example of a display apparatus. It is the schematic diagram which cut out one pixel circuit from the display apparatus of the reference example shown in FIG. 3 is a timing chart for explaining the operation of the pixel circuit shown in FIGS. 1 and 2. 1 is a block diagram showing an overall configuration of a display device according to the present invention. FIG. 5 is a circuit diagram illustrating a configuration example of a pixel circuit incorporated in the display device illustrated in FIG. 4. FIG. 6 is a schematic diagram showing one pixel circuit cut out from the display device shown in FIG. 5. FIG. 7 is a timing chart for explaining the operation of the pixel circuit shown in FIGS. 5 and 6. FIG. It is a timing chart which shows the best embodiment of the display apparatus concerning this invention. It is a circuit diagram with which it uses for operation | movement description of the display apparatus concerning this invention. It is a graph similarly provided for operation | movement description. It is a circuit diagram similarly used for operation | movement description. It is a graph similarly provided for operation | movement description. It is a schematic diagram with which it uses for operation | movement description of the driver IC integrated in the display apparatus concerning this invention. It is a circuit diagram which similarly shows the structural example of driver IC.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Pixel array, 2 ... Pixel circuit, 3 ... Horizontal selector (driver IC), 4 ... Write scanner, 5 ... Drive scanner, Tr1 ... Sampling transistor, Tr4 ... Switching transistor, Trd ... Drive transistor, Cs ... Pixel capacitance, EL ... Light emitting element

Claims (4)

Including a pixel array unit, a scanner unit, and a signal unit,
The pixel array unit includes first and second scanning lines arranged in rows and signal lines arranged in a column and matrix-like pixels arranged in a portion where both intersect.
Each pixel includes at least a sampling transistor having a gate connected to the first scan line, a drive transistor, a switching transistor having a gate connected to the second scan line, a pixel capacitor, and a light emitting element.
In the drive transistor, the gate is connected to the signal line through the sampling transistor, the source is connected to the light emitting element, and the drain is connected to the power supply through the switching transistor,
The pixel capacitor is connected between a gate and a source of the drive transistor,
The sampling transistor conducts according to a first control signal supplied from the first scanning line and samples the signal potential of the video signal supplied from the signal line into the pixel capacitor,
The pixel capacitor applies an input voltage to the gate of the drive transistor according to the signal potential of the sampled video signal,
The drive transistor supplies an output current corresponding to the input voltage to the light emitting element, and the output current has a dependency on a threshold voltage of the drive transistor,
The light emitting element emits light with luminance according to the signal potential of the video signal by an output current supplied from the drive transistor during a light emission period ,
The switching transistor is turned on in response to a second control signal supplied from the second scanning line, connects the drive transistor to the power supply during the light emission period, and becomes non-conductive during the non-light emission period. Disconnect from the power source,
A display device,
The signal unit supplies the video signal to the signal line and switches the video signal between a first fixed potential, a second fixed potential, and a signal potential in each horizontal scanning period,
The scanner unit outputs the first control signal and the second control signal to the first scanning line and the second scanning line, respectively, in a horizontal scanning period to control on / off of the sampling transistor and the switching transistor, and A preparatory operation for resetting the pixel capacitance by turning on the sampling transistor in a time period in which the switching transistor is in an off state and the video signal is in the first fixed potential; and the video signal is in the second fixed potential. A correction operation for writing a voltage for canceling the threshold voltage to the pixel capacitor that has been reset by turning on the sampling transistor and the switching transistor in a state where the video signal is changed to When the signal potential is on Performing the sampling operation for sampling the signal potential of the video signal to the pixel capacitor via a ring transistor,
Further, the scanner unit performs the preparation operation and / or the correction operation in a time-sharing manner in each horizontal scanning period by using the previous horizontal scanning period assigned to the row preceding the pixel of the row. Display device. The signal unit supplies the first fixed potential at a high level according to the preparation operation, supplies the second fixed potential at a low level according to the correction operation, and the signal potential according to the sampling operation. The display device according to claim 1, wherein: The drive transistor has an output current dependent on the carrier mobility of the channel region in addition to the threshold voltage,
The scanner unit extracts an output current flowing through the drive transistor by sampling the signal potential when the switching transistor is on in order to cancel the dependence of the output current on carrier mobility. 2. The display device according to claim 1, wherein the sampling transistor is controlled so as to execute an operation of correcting the input voltage by negatively feeding back to the pixel capacitor. Including a pixel array unit, a scanner unit, and a signal unit,
The pixel array unit includes first and second scanning lines arranged in rows and signal lines arranged in a column and matrix-like pixels arranged in a portion where both intersect.
Each pixel includes at least a sampling transistor having a gate connected to the first scan line, a drive transistor, a switching transistor having a gate connected to the second scan line, a pixel capacitor, and a light emitting element.
In the drive transistor, the gate is connected to the signal line through the sampling transistor, the source is connected to the light emitting element, and the drain is connected to the power supply through the switching transistor,
The pixel capacitor is connected between a gate and a source of the drive transistor,
The sampling transistor conducts according to a first control signal supplied from the first scanning line and samples the signal potential of the video signal supplied from the signal line into the pixel capacitor,
The pixel capacitor applies an input voltage to the gate of the drive transistor according to the signal potential of the sampled video signal,
The drive transistor supplies an output current corresponding to the input voltage to the light emitting element, and the output current has a dependency on a threshold voltage of the drive transistor,
The light emitting element emits light with luminance according to the signal potential of the video signal by an output current supplied from the drive transistor during a light emission period,
The switching transistor is turned on in response to a second control signal supplied from the second scanning line, connects the drive transistor to the power supply during the light emission period, and becomes non-conductive during the non-light emission period. A display device driving method for disconnecting the power supply from the power source,
The signal unit supplies the video signal to the signal line, and switches the video signal between a first fixed potential, a second fixed potential, and a signal potential in each horizontal scanning period,
The scanner unit outputs the first control signal and the second control signal to the first scanning line and the second scanning line, respectively, in a horizontal scanning period to control on / off of the sampling transistor and the switching transistor; A preparatory operation for resetting the pixel capacitance by turning on the sampling transistor in a time period in which the switching transistor is in an off state and the video signal is in the first fixed potential; and the video signal is in the second fixed potential. A correction operation for writing a voltage for canceling the threshold voltage to the pixel capacitor that has been reset by turning on the sampling transistor and the switching transistor in a state where the video signal is changed to When the signal potential is on Performing the sampling operation for sampling the signal potential of the video signal to the pixel capacitor via a ring transistor,
Further, the scanner unit performs the preparation operation and / or the correction operation in a time-sharing manner in each horizontal scanning period by using the previous horizontal scanning period assigned to the row preceding the pixel of the row. A driving method of a display device.

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