JP4954626B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device having a memory element and a method for driving the semiconductor device.

With the miniaturization of wiring due to the development of LSI (Large Scale Integration) manufacturing technology, the problem of leakage current has become prominent. The leak current causes problems such as heat generation of LSI and increase in power consumption. Particularly in mobile devices such as mobile phones and notebook personal computers, the problem of power consumption is directly related to the continuous operation time, which is a big problem. For this reason, various techniques have been proposed for reducing the power consumption of LSIs.

For example, the LSI operation may or may not require the maximum performance. When the operation speed of the LSI is not so required, there is a technique for operating by lowering the clock frequency. In addition, there is a technique for reducing the leakage current by shifting the substrate bias and controlling the threshold when the operation speed is not required to be maximized.

Further, in recent LSIs, a very large capacity memory such as a cache is present inside and is often configured by an SRAM (Static Random Access Memory). The SRAM holds the value by connecting the inverter circuits to each other. Once the value is held, the electrical state does not change, but a leakage current flows from the power supply line connected to the inverter circuit to the ground line.

As an SRAM configuration with reduced power consumption, a switching MOS transistor is provided between the power supply line of the memory cell group selected by each word line of the SRAM row decoder and the power supply line on the voltage supply source side. Some line selection signals open and close switching MOS transistors (see Patent Document 1).
Japanese Patent Laid-Open No. 10-106267

The operation of the SRAM includes writing and reading. When this operation is performed, only a part of the entire memory operates, and the other part only holds a value. A predetermined voltage is required at the time of writing and reading, but the predetermined voltage is not required if only the value is held, and the off-current can be reduced by lowering the power supply voltage.

The SRAM described in Patent Document 1 describes a configuration in which the power supply of an address is changed and the power supply is cut. However, when the power supply is cut off, electricity flows to the ground line due to the off-state current of the transistor applied to the SRAM, and it is considered difficult to maintain the value.

Therefore, an object of the present invention is to control the power supply method in the memory by a method different from Patent Document 1 during LSI operation, and to suppress the power consumption of the LSI by reducing the leakage current of the transistor.

In view of the above problems, the present invention is characterized in that the driving voltage during the holding period is lower than the period during which values are written or the period during which values are read. That is, the first voltage is applied to the power supply line of the memory cell in the period in which the value is written in the memory cell according to the present invention, and the first voltage is applied to the power supply line in the memory cell in the period in which the written value is held. The driving method is characterized in that a lower second voltage is applied.

The specific configuration of the present invention is shown below.

One embodiment of the present invention includes a memory cell including an inverter circuit connected to a power supply line, and a first voltage is supplied to the power supply line during a period in which a value is written to the memory cell. A second voltage lower than the first voltage is supplied to the power supply line during a period for holding the written value, and the first voltage is applied during a period for reading the value written in the memory cell. A semiconductor device supplied to the power line.

Another embodiment of the present invention includes a power supply control circuit and a memory cell, and the power supply control circuit is provided for each of the first word line and the second word line, and the first word line or the second word line. It has two connected input terminals and one output terminal. When a HIGH level is input to one of the input terminals, a HIGH level is output to the output terminal, and a LOW ( When a low level is input, a circuit that outputs a LOW level to the output terminal, a first inverter circuit having an input terminal connected to the output terminal, and the circuit and the first inverter circuit are electrically connected; Means for supplying a first voltage or a second voltage lower than the first voltage to the memory cell, the memory cell having a second inverter circuit, a first word line and a second voltage Connected to other word lines A conductor arrangement.

Another embodiment of the present invention includes a power supply control circuit and a memory cell, and the power supply control circuit is provided for each of the first word line and the second word line, and the first word line or the second word line. It has two connected input terminals and one output terminal. When a HIGH level is input to one of the input terminals, a HIGH level is output to the output terminal, and a LOW level is input to both input terminals. Then, a circuit that outputs a LOW level to the output terminal, a first inverter circuit having the output terminal connected to the input terminal, and the circuit and the first inverter circuit are electrically connected to the memory cell, and Means for supplying a voltage or a second voltage lower than the first voltage, and the memory cell has a second inverter circuit connected to the ground line and the power supply line, and the first word line And the second word A semiconductor device connected to the line.

Another embodiment of the present invention includes a power supply control circuit and a memory cell, and the power supply control circuit is provided for each of the first word line and the second word line, and the first word line or the second word line. It has two connected input terminals and one output terminal. When a HIGH level is input to one of the input terminals, a HIGH level is output to the output terminal, and a LOW level is input to both input terminals. Then, a circuit that outputs a LOW level to the output terminal, a first inverter circuit having the output terminal connected to the input terminal, and the circuit and the first inverter circuit are electrically connected to the memory cell, and Means for supplying a voltage or a second voltage lower than the first voltage, and the memory cell is connected to a second inverter circuit connected to the ground line and the power line, and to the second inverter circuit Is And a transistor, a first word line connected to a gate electrode of the transistor is a semiconductor device that is connected to a first word line and the second word line.

Another embodiment of the present invention includes a power supply control circuit and a memory cell, and the power supply control circuit is provided for each of the first word line and the second word line, and the first word line or the second word line. It has two connected input terminals and one output terminal. When a HIGH level is input to one of the input terminals, a HIGH level is output to the output terminal, and a LOW level is input to both input terminals. Then, a circuit that outputs a LOW level to the output terminal, a first inverter circuit having the output terminal connected to the input terminal, and the circuit and the first inverter circuit are electrically connected to the memory cell, and Means for supplying a voltage or a second voltage lower than the first voltage, and the memory cell is connected to a second inverter circuit connected to the ground line and the power line, and to the second inverter circuit Is First to third transistors, a first word line connected to the gate electrode of the first transistor, and a data line connected to one electrode of the second and third transistors, A semiconductor device is connected to the second word line connected to the gate electrodes of the second and third transistors, and to the first word line and the second word line.

In the present invention, the means for supplying the memory cell with the first voltage or the second voltage lower than the first voltage comprises two transistors.

In the present invention, there are two input terminals and one output terminal. When a HIGH level is input to one of the input terminals, a HIGH level is output, and when a LOW level is input to both input terminals, the LOW level is output. The circuit to which the level is output includes a circuit composed of an OR circuit, a NOR circuit, and an inverter circuit, two inverter circuits, and a NAND circuit.

In the present invention, the word line and the power line can be provided in the same layer as the gate electrode of the thin film transistor.

In the present invention, the data line can be formed using the same material as the source electrode and the drain electrode of the thin film transistor.

Another embodiment of the present invention includes a memory cell having a first inverter circuit connected to a first word line and a second word line, a first word line and a second word line, There are two input terminals and one output terminal respectively connected to the word line or the second word line. When a HIGH level is input to one of the input terminals, a HIGH level is output to the output terminal, When a LOW level is input to both input terminals, a circuit that outputs a LOW level to the output terminal, a second inverter circuit having an input terminal connected to the output terminal, and a gate to the output terminal of the second inverter circuit A power control circuit having a first transistor to which an electrode is connected, a second transistor connected to an output terminal of the circuit, and a power supply line connected to the first and second transistors. In the period during which a value is written to the memory cell, the first word line is set to HIGH level, the second word line is set to LOW level, the first transistor is turned on, and the first voltage is applied to the power supply line. In the period in which the value written in the cell is held, the first word line and the second word line are set to the LOW level, the second transistor is turned on, and the power supply line has a second voltage lower than the first voltage. Is a method for driving a semiconductor device.

Another embodiment of the present invention includes a first inverter circuit connected to a ground line and a power supply line, a memory cell connected to the first word line and the second word line, a first word line, It has a second word line, two input terminals connected to the first word line or the second word line, and one output terminal, respectively, and a HIGH level is input to one of the input terminals. A HIGH level is output to the output terminal, a LOW level is output to the output terminal when a LOW level is input to both input terminals, an inverter circuit in which the input terminal is connected to the output terminal, a circuit and an inverter A power supply control circuit that is connected to the circuit and that supplies a first voltage or a second voltage lower than the first voltage to the memory cell. 1 In the period in which the word line becomes HIGH level, the second word line becomes LOW level, the first transistor is turned on, the first voltage is applied to the power supply line, and the value written in the memory cell is held. In this method, the first word line and the second word line are set to the LOW level, the second transistor is turned on, and the second voltage lower than the first voltage is applied to the power supply line.

Another embodiment of the present invention includes a memory cell having an inverter circuit connected to a first word line and a second word line, a first word line and a second word line, and a first word line or There are two input terminals connected to the second word line and one output terminal. When a HIGH level is input to one of the input terminals, a HIGH level is output to the output terminal, and both input terminals When a LOW level is input to the output terminal, a circuit that outputs a LOW level to the output terminal, an inverter circuit having an input terminal connected to the output terminal, a first transistor having a gate electrode connected to the output terminal of the inverter circuit, And a power supply control circuit having a second transistor connected to the output terminal of the circuit and a power supply line connected to the first and second transistors, and writing a value into the memory cell In the period, the first word line is set to HIGH level, the second word line is set to LOW level, the first transistor is turned on, and the first voltage is applied to the power supply line connected to the first transistor, In a period in which the value written in the memory cell is held, the first word line and the second word line are at a LOW level, the second transistor is turned on, and a voltage lower than the first voltage is applied to the power supply line. In the period for reading the value written in the memory cell, the first word line is at a low level, the second word line is at a high level, the first transistor is turned on, and the first transistor is turned on. This is a method for driving a semiconductor device in which a first voltage is applied to a power supply line connected to.

Another embodiment of the present invention includes an inverter circuit connected to a ground line and a power supply line, a memory cell connected to the first word line and the second word line, the first word line, and the second word line It has a word line, two input terminals connected to the first word line or the second word line, and one output terminal, respectively, and an output terminal when a HIGH level is input to one of the input terminals Is connected to the circuit that outputs the LOW level to the output terminal, the inverter circuit having the input terminal connected to the output terminal, and the circuit and the inverter circuit. And a power supply control circuit having a first voltage or a second voltage lower than the first voltage supplied to the memory cell, and the first word is written in a period in which a value is written in the memory cell. The line becomes HIGH level, the second word line becomes LOW level, the first transistor is turned on, the first voltage is applied to the power supply line connected to the first transistor, and the value is held in the memory cell. In the period, the first word line and the second word line are at a LOW level, the second transistor is turned on, a voltage lower than the first voltage is applied to the power supply line, and the value written in the memory cell In the period during which the first word line is read, the first word line is at a low level, the second word line is at a high level, the first transistor is turned on, and a first power line connected to the first transistor is connected to a first power line. A driving method of a semiconductor device to which a voltage is applied.

According to the present invention, power consumption of a semiconductor device including a memory can be reduced. In particular, as the functions of LSIs become more complex, the memory capacity required for LSIs also increases, and the proportion of the area occupied by the memory in the chip also increases. As the capacity of the memory increases, the ratio of memory cells that require a predetermined voltage to the entire SRAM decreases, so the effect of the present invention increases.

A semiconductor device according to the present invention includes a memory cell array in which a plurality of memory cells are arranged, a read circuit that controls bit lines for writing and reading, and an address decoder that controls word lines. Further, a power supply control circuit is provided between the address decoder and the memory cell array. When outputting a signal from the address decoder to the word line, the power supply control circuit controls the power supply line extending to the memory cell array and connected to the memory cell in synchronization with the signal. At this time, a predetermined power supply voltage is applied to the power supply line.

The memory cell is configured by connecting inverter circuits in series. Specifically, in the two inverter circuits, the output terminal of one inverter circuit is connected to the input terminal of the other inverter circuit, and the input terminal of one inverter circuit is connected to the output terminal of the other inverter circuit. That is, a static RAM is configured.

The power supply control circuit has at least two word lines, two input terminals respectively connected to the word lines, and one output terminal. When a HIGH level is input to one of the input terminals, the power supply control circuit is HIGH. A circuit that outputs a LOW level when a LOW level is input to both input terminals, an inverter circuit connected to the circuit, a circuit and the inverter circuit, and a first voltage applied to the memory cell Or means for supplying a second voltage lower than the first voltage. As a means for supplying a first voltage or a second voltage lower than the first voltage to the memory cell, two transistors connected in series can be applied. When writing or reading a value into the memory cell, a first voltage is supplied, and when a value is stored, a second voltage is supplied. As a result, the driving voltage in the holding period can be lowered compared with the period in which the value is written or the period in which the value is read, and the power consumption of the memory cell can be reduced.

Such a memory array can be used as a cache memory of a CPU (Central Processing Unit) or a microprocessor MPU (Microprocessor). By applying to the CPU and MPU, it is possible to achieve low power consumption of the CPU and MPU.

Embodiments of the present invention will be described below with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention should not be construed as being limited to the description of the following examples. Note that in all the drawings for describing the embodiments, the same portions or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted.

Moreover, the voltage value in the Example shown below is an example, and this invention is not limited to this value.

Example 1
In the present embodiment, the configuration of the SRAM memory of the present invention will be described. A device having a semiconductor element such as the SRAM memory of the present invention can also be called a semiconductor device.

FIG. 1 shows an example of the SRAM memory configuration of the present invention. The memory 103 is a byte address type memory having addresses from 0 to 63, 8 bits of memory cells arranged in the horizontal direction, and 64 lines from address 0 to address 63 in the vertical direction.

The memory cell 104 can hold a 1-bit value, and the memory cell array 102 has 8 bits × 64 lines of memory cells 104.

The write / read circuit 101 performs a process of writing data from the outside of the memory into the memory cell array 102 and a process of reading data from the memory cell array 102 and transmitting the data to the outside of the memory.

The address decoder 105 decodes a 6-bit address from the outside of the memory into 64 word lines.

The address decoder 105 outputs signals to the word lines WR0 to WR63 and WW0 to WW63, which are input to the power supply control circuit 106 to control the power supply lines V0 to V63 of the memory cell array 102. A predetermined power supply voltage is applied to the power supply line.

The word lines WR0 to WR63 and WW0 to WW63 can function as read and write word lines, respectively, according to an output signal from the address decoder 105. That is, at the time of writing, one of WW0 to WW63 is in a high potential state (hereinafter referred to as “HIGH level”), and at the time of reading, one of WR0 to WR63 is at a HIGH level. For example, when the address is 00 and reading, only WR0 is HIGH level, and when the address is 63 and writing, only WW63 is HIGH level.

BR0 to BR7 and BW0 to BW7 are read and write bit lines, respectively. At the time of reading, the value of the 8-bit memory cell selected by the address is input to BR0 to BR7, and at the time of writing, external data is input to BW0 to BW7.

Such SRAM memory can store information of 8 bits × 64 = 512 bits.

Next, a configuration example of the memory cell 104 is shown. Note that in this embodiment, the case where 5 V is supplied as the power supply voltage in the reading period and the writing period and 3 V is supplied as the power supply voltage in the holding period is described.

The memory cell 104 shown in FIG. 2 includes data lines 201 and 202 at writing, a data line 203, a word line 204 at writing, a power line 205, a ground line 206, a word line 207 at reading, an N-channel transistor 208, 209, 210, 212, a node 211, and an inverter circuit 213.

The inverter circuit 213 has two inverter circuits 213a and 213b, and an input terminal and an output terminal are connected to each other. One electrode of the inverter circuits 213 a and 213 b included in the inverter circuit 213 is connected to the power supply line 205, and the other electrode is connected to the ground line 206. A gate electrode of the transistor 208 and a gate electrode of the transistor 209 are connected to the word line 204. One electrode of the transistor 208 is connected to the data line 201, and the other electrode is connected to the output terminal of one inverter circuit 213 a in the inverter circuit 213. A gate electrode of the transistor 209 is connected to the word line 204, one electrode is connected to the data line 202, and the other electrode is connected to an output terminal of one inverter circuit 213 b in the inverter circuit 213. A gate electrode of the transistor 212 is connected to the node 211, one electrode is connected to the ground line 206, and the other electrode is connected to one electrode of the transistor 210. The gate electrode of the transistor 210 is connected to the word line 207, and the other electrode is connected to the data line 203.

A normal value which is a write value is input to the data line 201 at the time of writing, and an inverted value is input to the data line 202 at the time of writing. In the data line 203 at the time of reading, when the memory cell holds 1 except for the time of reading, a normal value is written, and when it is 0, an inverted value is written. , And precharged to 5 V by the read circuit 101.

At the time of writing, the word line 204 is 5 V and the transistors 208 and 209 are turned on, so that a value can be written into the memory cell.

At the time of reading, the word line 207 is at a high level and the transistor 210 is turned on. When the value of the memory cell is 0, the voltage of the node 211 is 5V, the transistor 212 is turned on, and the voltage of the precharged data line 203 is 0V by the transistors 210 and 212. When the value of the memory cell is 1, since the transistor 212 is not turned on, the data line 203 is held at the precharged 5V.

As described above, the memory cell needs the same voltage as the power supply voltage of the entire device at the time of writing and reading, but only the inverter circuit is used for the LSI system during the period for holding the written value except for writing and reading. The value is held in a state where it is electrically disconnected from. That is, in the period for holding the value, there is no signal exchange with the outside of the memory cell, and the two inverter circuits in the inverter circuit 213 may be operated. Once a value is written in the memory cell, of the four transistors of the inverter circuit 213, two transistors are turned on and two transistors are turned off, but the memory flowing from the power line 205 to the ground line 206 The magnitude of the cell leakage current is determined by these two off-state transistors. In the conventional memory cell, a voltage of 5V is supplied during the period of holding the value, but a voltage of 3V is supplied during the holding period according to the present invention. The leakage current of the off-state transistor is reduced by lowering the power supply voltage. As a result, the power consumption of the memory element can be reduced. In order to perform such an operation, a power supply control circuit 106 is provided.

Next, a configuration example and operation of the power supply control circuit 106 will be described. As shown in FIG. 3, the power supply control circuit 106 includes an OR 320, an inverter circuit 321, P-channel transistors 301 and 302, word lines WR0 to WR63, and WW0 to WW63. Instead of the OR 320, NOR and an inverter circuit, or two inverter circuits and a NAND can be used. That is, it has two input terminals and one output terminal. When a high potential side signal is input to one of the input terminals, a HIGH level is output, and a low potential side signal (hereinafter referred to as “low potential side signal”) is input to both input terminals. Any circuit that has a function of outputting a LOW level when it is input). Here, the two input terminals are connected to the word line WR0 or WW0, respectively, and the output terminal is connected to the input terminal of the inverter circuit.

Word lines WR0 to WR63 and WW0 to WW63 are connected to the input terminal of OR320, and the gate electrode of transistor 301 and the input terminal of inverter circuit 321 are connected to the output terminal. The gate electrode of the transistor 302 is connected to the output terminal of the inverter circuit 321. One electrode of the transistor 301 and one electrode of the transistor 302 are connected and further connected to the power supply line V0.

Such a power supply control circuit 106 receives the output from the word line of the address decoder 105 as input, uses the word lines WR and WW of the respective lines as input terminals of OR, and when the corresponding address is read or written by the output of OR. A power supply voltage of 5V is supplied to the line, and 3V is supplied otherwise. For example, when address 00 is read, WR0 is set to 1, node 311 is set to LOW level, and node 310 is set to HIGH level, so that transistor 302 is turned on and 5 V is supplied to power supply line V0. As for the power supply voltage of other addresses, the transistor 301 connected to 3V is turned on, and 3V is supplied to the power supply lines V1 to V63. That is, for example, in a period in which a value is written to a memory cell, the word line WR0 is at a high level, the word line WW0 is at a LOW level, the transistor 302 is turned on, and a first voltage is applied to the power supply line connected to the transistor 302 It is done. In a period in which the value written in the memory cell is held, the word line WR0 and the word line WW0 are at the LOW level, the transistor 301 is turned on, and a voltage lower than the first voltage is applied to the power supply line. Then, in the period of reading the value written in the memory cell, the word line WR0 becomes LOW level, the word line WW0 becomes HIGH level, the transistor 302 is turned on, and the first voltage is applied to the power supply line connected to the transistor 302. Given. Here, the transistors 301 and 302 correspond to means for supplying a first voltage or a second voltage lower than the first voltage to the memory cell.

As described above, since the voltage of 3V is supplied during the holding period by using the present invention, the power consumption of the memory element is reduced as compared with the conventional memory cell in which the voltage of 5V is supplied during the holding period. be able to. That is, according to the present invention, it is possible to reduce the voltage supplied to the power supply line during the period of holding the value compared to the voltage supplied to the power supply line during the writing or reading period. Low power consumption can be achieved.

(Example 2)
In this embodiment, the operation of the SRAM memory of the present invention in the case of Embodiment 1 will be described using a timing chart.

FIG. 4 shows a timing chart of the SRAM memory of the present invention. The SRAM signal of the present invention includes: a signal for indicating a write period: WE (write enable); a signal for indicating a read period: RE (read enable); a data bus signal to be written to the SRAM during the write period: WDATA (write) date), data bus signal from which SRAM data is read during the read period: RDATA (read data), address bus signal for writing or reading: ADDR (read or write address), input to power supply lines V0 to V63 Have a signal. When WE is 1, the memory is determined to be in the writing period, and external write data is written to the address line. When WE is 0, no write operation is performed.

WE is at a HIGH level when a value is written to the SRAM, and is at a LOW level otherwise. RE is HIGH when reading a value from SRAM, and LOW otherwise. Further, RE can be used at the timing of precharging the data line 203 in FIG. 2. Writing is performed at a timing other than the time of reading, and the data line 203 is precharged by the reading circuit 101.

WDATA is an 8-bit bus, and a value written to the SRAM at the time of writing is input. RDATA is an 8-bit bus, and a value read from the SRAM at the time of reading is input. ADDR is a 6-bit bus, and an address for writing or reading is input. The input address is decoded by the decoder 105 into a 64-bit read word line and write word line. Pulse signals shown as power supply lines V0 to V63 are power supply voltages supplied to addresses 0 to 63, respectively.

A period 401 is a period in which WE becomes HIGH level and writing to the SRAM is performed. A period 402 is a period in which RE becomes HIGH level and reading is performed.

In a period 403, an operation of writing the data 00 input to the WDATA bus to the address 00 input to the ADDR bus is performed. At this time, the voltage of the power supply line V0 supplied to the address 00 is 5V, and the voltages of the power supply lines V1 to V63 of other addresses are 3V. Similarly, the period 404 is a period in which data is written to the address 01. 5V is supplied only to the power supply line V1 supplied to the memory cell at the address 01, and 3V is supplied to the other power supply lines V0 and V2 to V63. . Similarly, in the periods 405 and 406, 5V is supplied only to the power supply lines V62 and V63 of the address 62 and address 63, respectively, and 3V is supplied to the other addresses.

In the period 407, data is read from the address 00 input to the ADDR bus, and the value 00 is input to the RDATA bus. At this time, 5V is supplied to the power supply line V0 of the memory cell at address 00, and 3V is supplied to the power supply voltages V1 to V63 of other addresses.

A period 408 is a period during which the SRAM read data bus RDATA is precharged to HIGH level. In the case of the SRAM configuration shown in the first embodiment, the SRAM memory cell cannot set the data bus to the HIGH level. Therefore, it is necessary to write by setting RE to the LOW level and to precharge by the read circuit 101. Therefore, when reading a value from an address in the reading period 402 and then reading data at a different address, a period in which RE is at a LOW level is required. In this way, 3V is supplied to all the power supply lines V0 to V63 supplied to the SRAM memory cells in a period in which WE is at the LOW level and RE is also at the LOW level. This period is a period for holding the written value.

According to the present invention, a voltage of 3V is supplied during a period for holding a value, and a memory cell is supplied with a voltage of 5V during a period for holding a value. Can do.

(Example 3)
In the case of the configuration of the power control circuit 106 shown in the first embodiment, power necessary for the operation is supplied at the same timing as writing or reading from the SRAM memory. However, with this configuration, it is expected that power supply will not be in time, and the operating speed of the SRAM memory will be slow. Therefore, in this embodiment, a configuration of an SRAM memory that supplies a power supply voltage at a timing before a necessary timing is shown.

The configuration of the SRAM memory of this embodiment is shown in FIG.

In the configuration of the SRAM memory of this embodiment, the address is input to the data bus or the like at the previous timing. The address decoder 501 decodes the input address. The power supply control circuit 502 receives the decoded write and read word lines.

FIG. 6 shows the configuration of the power supply control circuit 502 in the SRAM memory of this embodiment.

The power supply control circuit 502 includes read word lines WWP0 to WWP63, write word lines WRP0 to WRP63, an OR 602 having four inputs, an inverter circuit 603, P-channel transistors 604 and 605, and a flip-flop 607.

A clock is input to the flip-flop 607 and each output terminal is connected to the input terminal of the OR 602. The output terminal of the OR 602 is connected to the input terminal of the inverter circuit 603 and the gate electrode of the transistor 604. An output terminal of the inverter circuit 603 is connected to the gate electrode of the transistor 605. One electrode of the transistor 604 and one electrode of the transistor 605 are connected to each other and connected to the power supply line V0.

Such a power supply control circuit 502 delays the read word lines WWP0 to WWP63 and the write word lines WRP0 to WRP63 inputted by the signal from the decoder 501 by one clock through the internal flip-flop 607, and writes the write word line WW0. To WW63 and read word lines WR0 to WR63.

When WWP0 or WRP0 becomes HIGH level, the node 601 becomes HIGH level and 5V is supplied to the power supply line V0 of address 00. WWP0 and WRP0 pass through the flip-flops and become WW0 and WR0. When WWP0 or WRP0 is at the HIGH level, WW0 and WR0 are at the HIGH level at the timing one clock later, the node 601 is at the HIGH level, and the power line of address 00 V0 is supplied with 5V. In this way, 5V power can be supplied from the timing one clock before reading and writing. As a result, the supply of power is not in time, and the operating speed of the SRAM memory does not slow down.

Example 4
In this embodiment, a timing chart of the power supply control circuit 502 is shown in FIG.

A period 701 is a period in which writing is performed, and a period 702 is a period in which reading is performed. In the period 703, 00 is input to the address bus ADDR, 5V is supplied to the power supply line V0, and 3V is supplied to power supply lines other than the power supply line V0. In the period 703, WWP0 passes through the flip-flop in the power supply control circuit. In the period 704, the write word line WW0 becomes HIGH level, and the value 00 of the WDATA bus is written. Further, when WW0 becomes HIGH level, 5V is continuously supplied to the power supply line V0. In the period 704, 01 is input to the address bus ADDR and 5V is supplied to V1.

In the period 705, 3V is supplied to the power supply line V0, and 5V is continuously supplied to V1. Also, the value 01 of the WDATA bus is written to the address 01.

In the period 708, RDATA is written and precharged by the reading circuit, and 5 V is started to be supplied to the power supply line V0 of the address 00. In the period 709, 5V is continuously supplied to the power supply line V0, and the value 00 of the address 00 is input to the RDATA bus. In the period 710, 5 V starts to be supplied to the power supply voltage V1 of the address 01. Even in the period 711, 5V is supplied to V1, and the value 01 of the address 01 is input to the RDATA bus.

(Example 5)
In this embodiment, a configuration example of a top view and a cross-sectional view of a memory cell of the present invention will be described. In this embodiment, a thin film transistor (TFT) is used as a transistor.

FIG. 8 shows a top view of a memory cell corresponding to the circuit diagram of FIG. The memory cell 104 includes data lines 201 and 202 at writing, a data line 203, a word line 204 at writing, a power supply line 205, a ground line 206, a word line 207 at reading, and N-channel TFTs 208, 209, 210, and 212. , Node 211, and inverter circuit 213. The N-channel TFTs 208 and 209 are made of the same semiconductor layer, the N-channel TFTs 210 and 212 are made of the same semiconductor layer, and the P-channel TFT included in the inverter circuit 213 is made of the same semiconductor layer. The N-channel TFTs 210 and 212 are provided so as to have a wide channel width. Since the readout line 203 has a large capacitance, a transistor with a wide channel width is preferably provided in order to reduce the readout line 203 to 0 V at a predetermined operation speed. The P-channel TFT in the inverter circuit 213 is provided so that the channel width is wider than that of the N-channel TFT. This is to increase the mobility of the P-channel TFT.

A gate electrode and a gate wiring are provided on these semiconductor layers. N-channel TFTs 210 and 212 are provided in series. One gate electrode serves as a node 211, and the other gate electrode serves as a word line 207. Since the gate electrode of the N-channel TFT in the inverter circuit 213 and the gate electrode of the P-channel TFT are connected, they are the same gate electrode.

A source electrode, a drain electrode, and a wiring are provided over the gate electrode and the semiconductor layer. Line widths of the source electrode, the drain electrode, and the wiring are wider than those of the gate electrode and the gate wiring. The word line 204 and the power supply line 205 are arranged via the inverter circuit 213. In order to connect the source electrode, the drain electrode, and the wiring to the semiconductor layer, the gate wiring, or the like, a contact hole (shown by a square) is provided in an insulating layer provided therebetween. By increasing the number of contact holes or increasing the area, contact failure can be reduced.

A wiring is provided over the source electrode, the drain electrode, and the wiring. The wiring becomes the ground line 206 and the word line 207, and is provided so as to be wider than the line width of the source electrode, the drain electrode, and the wiring. A voltage drop can be suppressed by the ground line 206 and the word line 207 having a wide line width. In order to connect the wiring to the gate wiring or the wiring, a contact hole (shown by a square) is provided in an insulating layer provided between them.

Next, a manufacturing process of a memory cell will be described with reference to a cross-sectional view taken along a line AB in FIG.

In FIG. 9A, a substrate (insulating substrate) 801 having an insulating surface is prepared. Examples of the insulating substrate include a glass substrate, a quartz substrate, and a plastic substrate. Further, these substrates can be thinned by a technique such as polishing the back surface thereof. Furthermore, it is also possible to use a conductive substrate such as a metal element or a substrate in which a layer is formed using an insulating material on a semiconductor substrate such as silicon. By forming the memory cell on a plastic substrate, for example, a highly flexible, lightweight, and thin device can be manufactured.

A base layer 802 is formed over the insulating substrate 801. The base layer 802 can be formed with a single-layer structure or a stacked structure using an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the case where a two-layer structure is used as the base layer 802 is described. As a first layer of the base layer 802, a silicon oxynitride layer having a thickness of 10 nm to 200 nm (preferably 50 nm to 100 nm) is formed. The silicon oxynitride layer can be formed using SiH ₄ , NH ₃ , N ₂ O, and H ₂ as a reaction gas by a plasma CVD method. Next, a silicon oxynitride layer with a thickness of 50 nm to 200 nm (preferably 100 nm to 150 nm) is formed as the second layer of the base layer 802. The silicon oxynitride layer can be formed using SiH ₄ and N ₂ O as a reaction gas by a plasma CVD method.

A semiconductor layer is formed over the base layer 802. The semiconductor layer can be formed from a material containing silicon. The state of the semiconductor layer can be any of an amorphous state, a crystalline state, and a microcrystalline state. A crystalline state is preferable because the mobility of the TFT can be increased.

In order to form a crystalline semiconductor layer, there is a method in which heat treatment is performed on an amorphous semiconductor layer. Examples of the heat treatment include laser irradiation, a heating furnace, lamp irradiation, and the like, and any one or more of them can be used.

For laser irradiation, a continuous wave laser beam (CW laser) or a pulsed laser beam (pulse laser) can be used. As the laser beam, Ar laser, Kr laser, excimer laser, YAG laser, Y ₂ O ₃ laser, YVO ₄ laser, YLF laser, YAlO ₃ laser, glass laser, ruby laser, alexandrite laser, Ti: sapphire laser, copper vapor A laser or a gold vapor laser oscillated from one or a plurality of types can be used. By irradiating either a fundamental wave of such a laser beam or a harmonic laser beam such as the second harmonic to the fourth harmonic of the fundamental wave, a silicon layer having a crystal with a large grain size is obtained. Can do. As the harmonic, the second harmonic (532 nm) or the third harmonic (355 nm) of an Nd: YVO ₄ laser (fundamental wave 1064 nm) can be used. Energy density of laser irradiation of about 0.01 to 100 MW / cm ² (preferably 0.1 to 10 MW / cm ²⁾ is required. Then, irradiation is performed at a scanning speed of about 10 to 2000 cm / sec.

The fundamental CW laser and the harmonic CW laser may be irradiated, or the fundamental CW laser and the harmonic pulse laser may be irradiated. By irradiating a plurality of laser beams, a wide energy range can be compensated.

In addition, a pulse laser that uses a laser beam that oscillates at an oscillation frequency capable of irradiating a laser of the next pulse before the amorphous silicon layer is melted by the laser and solidified is used. You can also. By oscillating the laser at such a frequency, a silicon layer having crystal grains continuously grown in the scanning direction can be obtained. The oscillation frequency of such a laser is 10 MHz or more, which is significantly higher than a frequency band of several tens to several hundreds Hz that is normally used.

In the case of using a heating furnace as the heat treatment, the semiconductor layer having an amorphous state is heated at 400 to 550 ° C. for 2 to 20 hours. At this time, the temperature may be set in multiple stages in the range of 400 to 550 ° C. so that the temperature gradually increases. In the first low-temperature heating process at about 400 ° C., hydrogen and the like contained in the semiconductor layer having an amorphous state are produced, so that the layer surface can be prevented from being roughened during crystallization.

In the heat treatment step, a metal that promotes crystallization of the semiconductor layer, for example, nickel (Ni) is added. For example, a solution containing nickel can be applied to a silicon layer having an amorphous state, and heat treatment can be performed. By performing heat treatment using a metal in this manner, the heating temperature can be reduced, and a polycrystalline silicon layer having continuous crystal grain boundaries can be obtained. Here, as a metal for promoting crystallization, in addition to Ni, iron (Fe), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), platinum (Pt ), Copper (Cu), silver (Au), or the like can also be used.

Since the metal that promotes crystallization serves as a contamination source for memory cells and the like, it is desirable to perform a gettering step for removing the metal after the semiconductor layer is crystallized. In the gettering step, after the semiconductor layer is crystallized, a layer to be a gettering sink is formed on the semiconductor layer, and the metal is moved to the gettering sink by heating. As the gettering sink, a polycrystalline semiconductor layer or a semiconductor layer to which an impurity is added can be used. For example, a polycrystalline semiconductor layer to which an inert element such as argon is added can be formed on the polycrystalline silicon layer, and this can be used as a gettering sink. By adding an inert element to the gettering sink, distortion can be generated and the metal can be captured more efficiently. In addition, a metal can be captured by adding an element such as phosphorus to a part of the semiconductor layer of the TFT without forming a new gettering sink.

The semiconductor layer thus formed is processed into a predetermined shape, so that an island-shaped semiconductor layer 803 is formed. The processing means is etched using a mask formed by photolithography. A wet etching method or a dry etching method can be applied to the etching.

An insulating layer functioning as the gate insulating layer 804 is formed so as to cover the semiconductor layer 803. The gate insulating layer 804 can be formed using a material and a method similar to those of the base layer 802.

As shown in FIG. 9B, a conductive layer functioning as a gate electrode and a gate wiring is formed over the gate insulating layer 804. As the conductive layer, a film made of aluminum (Al), titanium (Ti), molybdenum (Mo), tantalum (Ta), tungsten (W), or silicon (Si) or an alloy film containing these elements can be used. . The conductive layer can have a single-layer structure or a stacked structure, and a stacked structure of tantalum nitride and tungsten can be used as the stacked structure. The conductive layer can be processed into a predetermined shape, whereby the gate electrode 806 and the gate wiring 813 having a stacked structure can be formed. The processing means is etched using a mask formed by photolithography. A wet etching method or a dry etching method can be applied to the etching.

An insulator called a sidewall 807 is formed on the side surface of the gate electrode 806. The sidewall 807 can be formed using a material and a method similar to those of the base layer 802. In order to make the end portion of the sidewall 807 tapered, isotropic etching may be used. The sidewall can prevent the short channel effect that occurs as the gate length becomes narrower. Since the short channel effect is conspicuous in the N-channel TFT, it is preferable to provide at least the side surface of the gate electrode of the N-channel TFT. Similarly, a side wall may be formed on the gate wiring.

In this state, an impurity element is added to the semiconductor layer 803 using the gate electrode 806 and the sidewalls 807. In the case of an N-channel TFT, phosphorus (P) can be used as the impurity element, and in the case of a P-channel TFT, boron (B) can be used as the impurity element. When the impurity element is added, an impurity region is formed in the semiconductor layer 803. In the impurity region, high-concentration impurity regions 808 and 810 and low-concentration impurity regions 809 and 811 below the sidewall 807 are formed.

After the impurity addition, heat treatment can be performed as necessary to activate the impurity element and improve the surface of the semiconductor layer. For the heat treatment, a method similar to crystallization can be used.

As shown in FIG. 9C, insulating layers 815 and 816 functioning as interlayer films are formed so as to cover the semiconductor layer and the gate electrode. The interlayer film can have a single-layer structure or a stacked structure, and a stacked structure is shown in this embodiment. An inorganic material or an organic material can be used for the interlayer film. As the inorganic material, silicon oxide, silicon nitride, silicon oxynitride, or the like can be used. As the organic material, polyimide, acrylic, polyamide, polyimide amide, resist, benzocyclobutene, siloxane, or polysilazane can be used. Note that siloxane has a skeleton structure of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent. Polysilazane is formed using a polymer material having a bond of silicon (Si) and nitrogen (N) as a starting material. When an inorganic material is used, entry of an impurity element can be prevented, and when an organic material is used, flatness can be improved. Therefore, in this embodiment, an inorganic material is used for the insulating layer 815 and an organic material is used for the insulating layer 816.

As shown in FIG. 9D, a contact hole that penetrates the insulating layers 816 and 815 is formed, and a wiring 818 is formed so as to fill the contact hole. As the wiring 818, a film formed of an element of aluminum (Al), titanium (Ti), molybdenum (Mo), tantalum (Ta), tungsten (W), or silicon (Si) or an alloy film including these elements is used. it can. The wiring 818 can have a single-layer structure or a stacked structure. For example, tungsten, tungsten nitride, or the like is used for the first layer, and an alloy of aluminum and silicon (Al—Si) or an alloy of aluminum and titanium (Al—Si) is used for the second layer. A structure in which a titanium nitride film, a titanium film, and the like are sequentially stacked on the third layer can be applied using (Al—Ti). For the processing of the wiring 818, there is an etching method using a mask formed by a photolithography method. As the etching method, a wet etching method or a dry etching method can be applied. The wiring 818 is connected to the impurity region in the semiconductor layer 803, and such a wiring can be referred to as a source electrode or a drain electrode.

In this manner, a P-channel TFT 820 and an N-channel TFT 821 can be formed. Note that the N-channel TFT 821 corresponds to the transistors 210 and 212, respectively, and part of the wiring 818 corresponds to the data line 201 and the word line 207.

In this manner, the memory cell of the present invention can be formed using TFTs on an insulating substrate. Of course, the memory cell of the present invention is not limited to this, and can also be formed by a transistor using a silicon wafer. However, it is possible to provide an inexpensive memory cell and a device having the same by forming it over an insulating substrate.

(Example 6)
The SRAM of the present invention can be applied to a CPU. In this embodiment, the configuration of a CPU equipped with the SRAM of the present invention will be described. A simple configuration of the CPU is shown in FIG.

The CPU includes a D $ block (data cache) 901, an I $ block (instruction cache) 902, a DU block (data unit) 903, an ALU block (arithmetic logic unit, arithmetic logic circuit) 904, and a PC block (program counter) 905. , An IO (InOut) block 906.

D $ 901 has a function of temporarily holding data at a recently accessed address so that the data at the address can be accessed at high speed. The I $ 902 has a function of temporarily holding an instruction at a recently accessed address so that the instruction at the address can be accessed at high speed. The DU 903 has a function of determining whether to access D $ or IO when a store or load instruction is executed.
The ALU 904 is an arithmetic logic operation circuit and has a function of performing four arithmetic operations, comparison operations, logical operations, and the like. The PC 905 has a function of holding the address of the instruction currently being executed and fetching the next instruction after the end of the execution. Also, it has a function of determining whether to access I $ or IO when fetching the next instruction. The IO 906 has a function of receiving data from the DU and the PC and transmitting / receiving data to / from the outside. Each relationship will be described below.

When the PC 905 fetches an instruction, it first accesses the I $ 902, and accesses the IO 906 when there is no instruction at an address corresponding to the I $ 902. The instruction thus obtained is stored in the I $ 902 and executed. If the instruction to be executed is an arithmetic logic operation, the ALU 904 performs the operation. When the instruction to be executed is a store or load instruction, the DU 903 performs an operation. At this time, the DU 903 first accesses the D $ 901, and accesses the IO 906 when the data at the corresponding address is not in the D $ 901.

In such a CPU, the SRAM of the present invention can be applied to GPRs existing in D $ 901, I $ 902, and ALU904. As a result, a CPU that achieves low power consumption can be provided.

(Example 7)
As a semiconductor device in which the SRAM of the present invention can be mounted, a video camera, a digital camera, a goggle type display (head mounted display), a navigation system, a sound reproduction device (car audio, audio component, etc.), a notebook type personal computer, a game machine, A portable information terminal (mobile computer, cellular phone, portable game machine, electronic book, or the like), an image reproducing apparatus (specifically, a DVD: Digital Versatile Disc, or the like) that reproduces a recording medium and displays the image And a device equipped with a display that can be used. Specific examples of these semiconductor devices are shown in FIGS.

FIG. 11A illustrates a personal digital assistant (so-called PDA: Personal Digital Assistant), which includes a main body 2001, a display portion 2002, operation keys 2003, a modem 2004, and the like. The SRAM memory of the present invention is a memory element included in the main body 2001. Is provided. The SRAM memory of the present invention can reduce the cost of the portable information terminal.

FIG. 11B illustrates a cellular phone, which includes a main body 2101, a display portion 2102, an audio input portion 2103, an audio output portion 2104, operation keys 2105, an external connection port 2106, an antenna 2107, and the like. The SRAM memory of the present invention is provided. The SRAM memory of the present invention can reduce the cost of a mobile phone.

FIG. 11C illustrates an electronic card, which includes a main body 2201, a display portion 2202, a connection terminal 2203, and the like, and the SRAM memory of the present invention is provided as a memory element included in the main body 2201. The SRAM memory of the present invention can reduce the cost of the electronic card. Although FIG. 11C shows a contact-type electronic card, the SRAM memory of the present invention is also used for a non-contact type electronic card and an electronic card having both a contact type and a non-contact type function. be able to.

FIG. 11D illustrates an electronic book which includes a main body 2301, a display portion 2302, an operation key 2303, and the like, and the SRAM memory of the present invention is provided as a memory element included in the main body 2301. In the electronic book, a modem may be built in the main body 2301. The SRAM memory of the present invention can reduce the cost of an electronic book.

FIG. 11E illustrates a computer, which includes a main body 2401, a display portion 2402, a keyboard 2403, a touch pad 2404, an external connection port 2405, a power plug 2406, and the like. The SRAM memory of the present invention is provided as a memory element included in the main body 2401. It has been. The SRAM memory of the present invention can reduce the cost of the computer.

As described above, the applicable range of the present invention is so wide that it can be used for semiconductor devices in various fields. Note that the semiconductor device of this example can be implemented in combination with any structure and manufacturing method shown in the embodiment modes and examples.

It is the figure which showed the SRAM memory constitution of this invention FIG. 3 is a circuit diagram showing a configuration of a memory cell of the present invention. FIG. 3 is a circuit diagram showing a configuration of a power supply control circuit of the present invention. 4 is a timing chart of the SRAM memory of the present invention. It is the figure which showed the SRAM memory constitution of this invention FIG. 3 is a circuit diagram showing a configuration of a power supply control circuit of the present invention. 4 is a timing chart of the power supply control circuit of the present invention. It is a top view corresponding to the memory cell of the present invention. It is sectional drawing corresponding to the memory cell of this invention It is the block diagram which showed CPU which can mount the SRAM memory of this invention It is the figure which showed the electronic device of this invention

Claims (4)

A power control circuit, a memory cell, first to fourth word lines, a ground line, a power line,
First to third data lines,
The power supply control circuit
There are four input terminals and one output terminal. When a high level is input to at least one of the input terminals, a high level is output to the output terminal, and a low level is input to all the input terminals. And a circuit that outputs a low level to the output terminal, a first inverter circuit, first and second transistors, and a flip-flop circuit that receives a clock,
Four input terminals of the circuit having the four input terminals and one output terminal are electrically connected to the first to fourth word lines, respectively.
The first and second word lines are electrically connected to the output terminal of the flip-flop circuit, respectively, and the third and fourth word lines are electrically connected to the input terminal of the flip-flop circuit, respectively. And
The output terminal of the circuit having the four input terminals and one output terminal is electrically connected to the input terminal of the first inverter circuit and the gate electrode of the first transistor;
One electrode of the first transistor is electrically connected to a wiring for supplying a first voltage, and the other electrode of the first transistor is connected to the power supply line and to the second transistor. Electrically connected to one electrode,
The other of the second transistors is electrically connected to a wiring for supplying a second voltage, and a gate electrode of the second transistor is electrically connected to an output terminal of the first inverter circuit,
The memory cell is
Third to sixth transistors, and second and third inverter circuits having an output terminal and an input terminal connected to each other,
The second and third inverter circuits have seventh and eighth transistors in which one electrode is electrically connected to the power line,
The second and third inverter circuits have ninth and tenth transistors in which one electrode is electrically connected to the ground line,
One electrode of the third transistor is electrically connected to the output terminal of the second inverter circuit, and the other electrode of the third transistor is electrically connected to the first data line. The gate electrode of the third transistor is electrically connected to the first word line,
One electrode of the fourth transistor is connected to the second data line, the other electrode of the fourth transistor is electrically connected to an output terminal of the third inverter circuit, and 4 transistor gate electrode is electrically connected to the first word line,
One electrode of the fifth transistor is electrically connected to the other electrode of the tenth transistor, and the other electrode of the fifth transistor is electrically connected to one electrode of the sixth transistor. The gate electrode of the fifth transistor is electrically connected to the input terminal of the second inverter circuit;
The other electrode of the sixth transistor is electrically connected to the third data line, and the gate electrode of the sixth transistor is electrically connected to the second word line. A featured semiconductor device. 2. The circuit according to claim 1 , wherein the circuit having the four input terminals and the one output terminal is an OR circuit,
A semiconductor device comprising either a circuit comprising a NOR circuit and an inverter circuit, or a circuit comprising two inverter circuits and a NAND circuit. 3. The semiconductor device according to claim 1, wherein the first to tenth transistors are thin film transistors formed over an insulating substrate. 4. The semiconductor device according to claim 1 , wherein the first to third data lines are provided in the same layer as a source electrode and a drain electrode of the first to tenth transistors.

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