JP4881337B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP4881337B2 JP4881337B2 JP2008062288A JP2008062288A JP4881337B2 JP 4881337 B2 JP4881337 B2 JP 4881337B2 JP 2008062288 A JP2008062288 A JP 2008062288A JP 2008062288 A JP2008062288 A JP 2008062288A JP 4881337 B2 JP4881337 B2 JP 4881337B2
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- 239000004065 semiconductor Substances 0.000 title claims description 125
- 239000000758 substrate Substances 0.000 claims description 91
- 239000010409 thin film Substances 0.000 claims description 50
- 239000003822 epoxy resin Substances 0.000 claims description 27
- 229920000647 polyepoxide Polymers 0.000 claims description 27
- 229920005989 resin Polymers 0.000 claims description 27
- 239000011347 resin Substances 0.000 claims description 27
- 238000007789 sealing Methods 0.000 claims description 27
- 229910000679 solder Inorganic materials 0.000 claims description 21
- 239000010408 film Substances 0.000 claims 4
- 238000004519 manufacturing process Methods 0.000 description 13
- 230000003287 optical effect Effects 0.000 description 11
- 238000000034 method Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 2
- 230000001678 irradiating effect Effects 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 208000032368 Device malfunction Diseases 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002238 attenuated effect Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
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- H01L2224/05573—Single external layer
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- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
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Description
なお、本発明は、以下の構成についても開示されている。
(1)
パッケージ基板と、
前記パッケージ基板上に設けられた接続部と、
前記接続部と対応して形成され前記接続部と電気的に接続される接続端子が形成された一主面を有するとともに前記一主面と対向する面に薄膜が形成された半導体基板と、
前記接続部、前記半導体基板、及び前記薄膜を封止する封止樹脂と、
を備え、
前記薄膜は、前記封止樹脂が有する屈折率より低い屈折率を有することを特徴とする半導体装置。
(2)
前記薄膜は、第1薄膜および前記第1薄膜の下方に位置し、前記第1薄膜と異なる屈折率を有する第2薄膜を含むことを特徴とする上記(1)に記載の半導体装置。
(3)
前記第2薄膜が有する屈折率は、前記第1薄膜が有する屈折率より低いことを特徴とする上記(2)に記載の半導体装置。
(4)
前記接続部は第1接続部であって、前記第1接続部が設けられた前記パッケージ基板上の面と対向する面に、他の装置と前記パッケージ基板との電気的な接続に用いる第2接続部をさらに有することを特徴とする上記(1)に記載の半導体装置。
(5)
前記第1接続部は、互いに離間して設けられた複数の半田ボールであることを特徴とする上記(4)に記載の半導体装置。
(6)
前記第2接続部は、互いに離間して設けられた複数の半田ボールであることを特徴とする上記(4)に記載の半導体装置。
(7)
前記第2接続部と電気的に接続された実装基板をさらに有することを特徴とする上記(4)に記載の半導体装置。
(8)
前記パッケージ基板と前記半導体基板の間に設けられ、前記複数の半田ボールを覆う樹脂をさらに有することを特徴とする上記(5)に記載の半導体装置。
(9)
前記封止樹脂はエポキシ樹脂であり、前記薄膜は、SIO 2 であることを特徴とする上記(1)に記載の半導体装置。
(10)
パッケージ基板と、
前記パッケージ基板上に設けられた接続部と、
前記接続部と対応して形成され前記接続部と電気的に接続される接続端子が形成された一主面を有するとともに前記一主面と対向する面に薄膜が形成された半導体基板と、
前記接続部、前記半導体基板、及び前記薄膜を封止する封止樹脂と、
を備え、
前記薄膜は、前記封止樹脂に照射されるとともに前記封止樹脂を透過する光の光路長を増加させることを特徴とする半導体装置。
101 実装基板
102 半田ボール
103 パッケージ基板
104 半田ボール
105 樹脂
106 半導体基板
107 薄膜
108 エポキシ樹脂
109 接続端子
110 接続端子
111 接続端子
112 接続端子
500 半導体ウエハ
Claims (7)
- パッケージ基板と、
前記パッケージ基板上に設けられた第1接続部と、
前記第1接続部が設けられた前記パッケージ基板上の面と対向する面に設けられた第2接続部と、
前記第1接続部と対応して形成され前記第1接続部と接続される接続端子が形成された一主面を有するとともに前記一主面と対向する面に第1薄膜及び前記第1薄膜の下方に積層された第2薄膜が形成された半導体基板と、
前記第1接続部、前記半導体基板、及び前記第1及び第2薄膜を封止すると共に、捺印が刻まれている封止樹脂と、
を備え、
前記第1薄膜は、前記封止樹脂が有する屈折率より低い屈折率を有し、前記第2薄膜は前記第1薄膜が有する屈折率より更に低い屈折率を有することを特徴とする半導体装置。 - 前記第2接続部は他の装置と前記パッケージ基板との接続に用いられることを特徴とする請求項1に記載の半導体装置。
- 前記第1接続部は、互いに離間して設けられた複数の半田ボールであることを特徴とする請求項1に記載の半導体装置。
- 前記第2接続部は、互いに離間して設けられた複数の半田ボールであることを特徴とする請求項1に記載の半導体装置。
- 前記第2接続部と接続された実装基板をさらに有することを特徴とする請求項1に記載の半導体装置。
- 前記パッケージ基板と前記半導体基板の間に設けられ、前記複数の半田ボールを覆う樹脂をさらに有することを特徴とする請求項3に記載の半導体装置。
- 前記封止樹脂はエポキシ樹脂であり、前記第1薄膜又は第2薄膜は、SIO2 を含むことを特徴とする請求項1に記載の半導体装置。
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JP2008062288A JP4881337B2 (ja) | 2008-03-12 | 2008-03-12 | 半導体装置 |
US12/370,171 US7956435B2 (en) | 2008-03-12 | 2009-02-12 | Semiconductor device |
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JP2008062288A JP4881337B2 (ja) | 2008-03-12 | 2008-03-12 | 半導体装置 |
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JP2009218467A JP2009218467A (ja) | 2009-09-24 |
JP4881337B2 true JP4881337B2 (ja) | 2012-02-22 |
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WO2014129351A1 (ja) * | 2013-02-21 | 2014-08-28 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置とその製造方法 |
KR20160032958A (ko) | 2014-09-17 | 2016-03-25 | 삼성전자주식회사 | 반도체 패키지 및 이의 제조 방법 |
US9922935B2 (en) | 2014-09-17 | 2018-03-20 | Samsung Electronics Co., Ltd. | Semiconductor package and method of fabricating the same |
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JPH0940756A (ja) | 1995-07-25 | 1997-02-10 | Toshiba Chem Corp | エポキシ樹脂組成物および半導体封止装置 |
JP3538526B2 (ja) * | 1997-07-03 | 2004-06-14 | 三菱電機株式会社 | 半導体集積回路装置 |
JPH11239037A (ja) * | 1998-02-20 | 1999-08-31 | Nec Corp | 弾性表面波装置 |
JP2001060598A (ja) * | 1999-08-23 | 2001-03-06 | Hitachi Ltd | 樹脂封止型半導体装置及びその製造方法 |
DE10100142A1 (de) | 2000-08-21 | 2002-03-07 | Orient Semiconductor Elect Ltd | Kühlanordnung für Flip-Chip-Modul |
JP4370615B2 (ja) * | 2003-10-27 | 2009-11-25 | エプソントヨコム株式会社 | 圧電デバイスとその製造方法 |
JPWO2007074567A1 (ja) * | 2005-12-27 | 2009-06-04 | イビデン株式会社 | 光・電気複合配線板及びその製造方法 |
JP5092251B2 (ja) * | 2006-02-22 | 2012-12-05 | 住友電気工業株式会社 | 光検出装置 |
US7729570B2 (en) * | 2007-05-18 | 2010-06-01 | Ibiden Co., Ltd. | Photoelectric circuit board and device for optical communication |
JP4521015B2 (ja) * | 2007-05-28 | 2010-08-11 | パナソニック電工株式会社 | 半導体装置の製造方法 |
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2008
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US20090230539A1 (en) | 2009-09-17 |
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