JP4877983B2 - Asynchronous synchronous communication network conversion device, method, program, recording medium, and communication system - Google Patents

Description

The present invention relates to an asynchronous synchronous communication network conversion device and method for connecting a legacy multiplex communication device that synchronously transmits multi-frame data in a synchronous communication network to an IP communication network that is an asynchronous communication network to communicate between legacy devices, Asynchronous synchronous communication network conversion apparatus for communicating multi-frame data between legacy multiple communication apparatuses of a synchronous communication network through an asynchronous communication network without taking external network synchronization , Method, program, recording medium, and communication system.

  Conventionally, there is a communication facility consisting of legacy equipment and a synchronous communication network. A synchronous communication network is mainly constructed with optical fibers, and multiple transmission devices such as 2.048 Mbps and 1.544 Mbps used for circuit switching are accommodated. In addition, legacy data communication for transmitting multi-channel data of a plurality of channels in synchronization with a clock signal is performed.

  In the legacy multiplex transmission device of such a synchronous communication network, data communication synchronized with the clock is performed between each other by extracting the synchronous clock from the received data of the counterpart device.

However, it is desired to change a communication facility configured by a conventional legacy device and a synchronous communication network to an Internet protocol network (hereinafter referred to as an “IP communication network”) that is an asynchronous communication network. This is because the optical fiber communication infrastructure is used as an IP communication network rather than a synchronous communication network in which only special legacy equipment, which is expensive due to the end of manufacture and sale of products, can be connected as a terminal. However, since the number of devices that can be connected has increased dramatically and the cost of the devices has decreased, it has become the mainstream in recent years.
JP-A-9-252292 JP 2002-217945 A

  However, in the case of a newly installed optical fiber, there is no problem, but in the case of an existing synchronous communication network in which a large amount of legacy equipment is already connected, for example, a communication facility in which a trunk optical fiber cable is installed along a highway, the synchronous communication network is changed to an asynchronous communication network. It is very difficult to change to the IP communication network, because all legacy multiplex transmission devices used for circuit switching, which are existing synchronous communication terminals, cannot be used.

  In other words, a synchronous clock can be extracted from transmission data in a synchronous communication network. However, in the case of an IP communication network, a synchronous clock cannot be extracted from data because it is a completely asynchronous communication network. Synchronous communication is not possible.

  In the case of an IP communication network, even if data is transmitted at regular intervals, data cannot be received at regular intervals due to delays or fluctuations in the communication network. It is very difficult to perform stable synchronous communication via the Internet. Even if legacy synchronous communication is realized via an IP communication network, a transmission error due to loss of synchronization regularly occurs or clock control occurs frequently frequently, and stable operation is not achieved.

  For this reason, when realizing synchronous communication between legacy devices in the IP communication network, it is assumed that the opposing legacy device is synchronized outside the IP communication network, and only between the IP communication network and the legacy device. It was difficult to realize the synchronous communication.

  In particular, when realizing synchronous communication between legacy multiplex communication devices used for circuit switching for transmitting multi-frame data of a plurality of channels in synchronization with a clock signal in an IP communication network, an IP packet in which multi-frame data is distributed in channels. As the IP packet is sent to the IP communication network, the reception state of the IP packet is random for each channel, and it is difficult to ensure synchronization only by the IP communication network, and synchronization is performed in units of channels by network synchronization outside the IP communication network. Therefore, the change to the IP communication network is made more difficult.

The present invention provides a synchronous asynchronous system that realizes stable synchronous communication between synchronous multiplex communication apparatuses by transmitting multi-frame data of a plurality of channels by a synchronous communication network to an IP communication network by channel distribution without requiring external network synchronization. It is an object of the present invention to provide a communication network conversion device, method, program, recording medium, and communication system.

(apparatus)
The present invention provides a conversion apparatus for synchronous asynchronous communication conversion. The present invention is inserted and connected between a synchronous multiplex communication apparatus that transmits multi-frame data of a plurality of channels in synchronization with a clock signal and an asynchronous communication network composed of devices that asynchronously transfer data, and a plurality of synchronous multiplex In a synchronous / asynchronous communication network converter for transferring data between communication devices,
A clock master is set for a specific conversion device among a plurality of conversion devices, a clock slave is set for the remaining conversion devices, and one specific channel among the assigned channels of the conversion devices set as the clock master is clock-synchronized. A master / slave setting unit that sets the master channel for control,
A variable clock unit capable of variably controlling the frequency of the output clock signal;
A transmission conversion unit that distributes multi-frame data received from the synchronous multiplex communication device and accumulates it in each transmission buffer, generates asynchronous data from the accumulated data in the transmission buffer at regular intervals, and transmits it to the asynchronous communication network;
Asynchronous data distributed from the asynchronous communication network is received and stored in each receive buffer. Multiframe data is generated from the stored data in the receive buffer in synchronization with the clock signal of the variable clock unit, and transmitted to the synchronous multiplex communication device. A receiving conversion unit,
Clock master synchronization control that is enabled in the setting state of the clock master and starts the variable clock unit at a predetermined center frequency when the reception buffer amount stored in the reception buffer of the master channel reaches a predetermined center value. And
It becomes effective in the setting state of the clock slave, and when the reception buffer amount accumulated in the reception buffer of the master channel reaches a predetermined center value, it starts by setting the variable clock unit to the center frequency, and the reception buffer amount after startup is A first clock slave synchronization control unit configured to control the clock frequency of the variable clock unit so as to be stable at the center value, and to synchronize the clock with another conversion device in a setting state of the clock master;
It is provided with.

  Here, the reception conversion unit generates multi-frame data that clears the reception buffer of all channels and sets all channels to no-signal data (for example, mark hold data by the make busy process) at the time of startup upon power-on. Then, synchronous transmission to the synchronous multiplex communication apparatus is started, and after the synchronous transmission is started, switching is performed from the channel in which the reception buffer amount has reached a predetermined center value to the reading and transmission of data accumulated in the reception buffer.

  The reception conversion unit clears the reception buffer of all channels and generates multi-frame data with all channels as no-signal data and synchronizes and transmits to the synchronous multiplex communication device when the master channel abnormality is recovered during operation After the synchronous transmission is started, the channel in which the reception buffer amount has reached a predetermined center value is switched to reading and transmission of buffer accumulated data.

  The reception conversion unit clears the reception buffer of the error recovery channel at the start-up when the error of the channel other than the master channel is recovered during operation, and includes the non-signal data in the multiframe data and synchronously transmits it to the synchronous multiplex communication device. When the reception buffer amount of the error recovery channel reaches the reception buffer amount of the master channel, the buffer storage data is switched to read transmission.

The clock slave synchronization controller
When the reception buffer amount C exceeds the upper limit value Cmax of the buffer fluctuation allowable range after the clock frequency is started from the center frequency fo, it is changed to a predetermined maximum adjustment frequency fmax, and after the change, the reception buffer amount C returns to the center value Co. The process of changing the maximum adjustment frequency fmax to the frequency (fo + α) obtained by adding the predetermined offset frequency α to the center frequency fo is repeated while sequentially increasing the offset frequency as α, 2α, 3α,
When the reception buffer amount C falls below the lower limit value Cmin of the buffer fluctuation allowable range after starting the clock frequency from the center frequency fo, the reception buffer amount C is changed to the predetermined minimum adjustment frequency fmin. The process of changing the minimum adjustment frequency fmin to the frequency (fo-α) obtained by subtracting the predetermined offset frequency α from the center frequency fo when the offset frequency is returned to is repeated while sequentially increasing the offset frequency as α, 2α, 3α,. .

  The synchronous multiplex communication device is a device having a legacy interface, and the device of the synchronous communication network is a device having an Internet protocol interface.

(Method)
The present invention provides a method for converting a synchronous asynchronous network. The present invention
Inserted and connected between a synchronous multiplex communication apparatus that transmits multi-channel data of a plurality of channels in synchronization with a clock signal and an asynchronous communication network composed of devices that transfer data asynchronously. In the conversion method of synchronous asynchronous network that transfers data between
A clock master is set for a specific conversion device among a plurality of conversion devices, a clock slave is set for the remaining conversion devices, and one specific channel among the assigned channels of the conversion devices set as the clock master is clock-synchronized. Master / slave setting step to set to the master channel of control,
A transmission conversion step for distributing multi-frame data received from the synchronous multiplex communication device to each transmission buffer and storing it in each transmission buffer, generating asynchronous data from the stored data in the transmission buffer at regular intervals and transmitting it to the asynchronous communication network;
Asynchronous data distributed from the asynchronous communication network is received and stored in each receive buffer. Multiframe data is generated from the stored data in the receive buffer in synchronization with the clock signal of the variable clock unit, and transmitted to the synchronous multiplex communication device. Receiving conversion step,
Clock master synchronization control that is enabled in the setting state of the clock master and starts the variable clock unit at a predetermined center frequency when the reception buffer amount stored in the reception buffer of the master channel reaches a predetermined center value. Steps,
It becomes valid in the setting state of the clock slave, and when the receive buffer amount stored in the receive buffer of the master channel reaches a predetermined center value, the variable clock unit is set to the center frequency and started. A clock slave synchronization control step of controlling the clock frequency of the variable clock unit so as to be stable to the center value, and synchronizing the clock to another conversion device in the setting state of the clock master;
Is provided.

  The receive conversion step is a start-up process when the power is turned on. When the power is turned on, the receive buffer for all channels is cleared and multi-frame data with all channels as no-signal data is generated to synchronize with the synchronous multiplex communication device. The transmission is started, and after the synchronous transmission is started, the channel is switched from the channel in which the reception buffer amount has reached a predetermined center value to the reading and transmission of the data accumulated in the reception buffer.

(program)
The present invention provides a program for conversion of synchronous asynchronous communication. The program of the present invention is inserted and connected between a synchronous multiplex communication apparatus that transmits multi-frame data of a plurality of channels in synchronization with a clock signal and an asynchronous communication network configured by equipment that transfers data asynchronously. To the computer of the converter of the synchronous asynchronous communication network that transfers data between the synchronous multiplex communication devices,
A clock master is set for a specific conversion device among a plurality of conversion devices, a clock slave is set for the remaining conversion devices, and one specific channel among the assigned channels of the conversion devices set as the clock master is clock-synchronized. Master / slave setting step to set to the master channel of control,
A transmission conversion step for distributing multi-frame data received from the synchronous multiplex communication device to each transmission buffer and storing it in each transmission buffer, generating asynchronous data from the stored data in the transmission buffer at regular intervals and transmitting it to the asynchronous communication network;
Asynchronous data distributed from the asynchronous communication network is received and stored in each receive buffer. Multiframe data is generated from the stored data in the receive buffer in synchronization with the clock signal of the variable clock unit, and transmitted to the synchronous multiplex communication device. Receiving conversion step,
Clock master synchronization control that is enabled in the setting state of the clock master and starts the variable clock unit at a predetermined center frequency when the reception buffer amount stored in the reception buffer of the master channel reaches a predetermined center value. Steps,
It becomes effective in the setting state of the clock slave, and when the reception buffer amount accumulated in the reception buffer of the master channel reaches a predetermined center value, it starts by setting the variable clock unit to the center frequency, and the reception buffer amount after startup is A clock slave synchronization control step of controlling the clock frequency of the variable clock unit so as to be stable to the center value, and synchronizing the clock to another conversion device in the setting state of the clock master;
Is executed.

(recoding media)
The present invention provides a recording medium storing a conversion program for synchronous / asynchronous communication. The recording medium of the present invention is inserted and connected between a synchronous multiplex communication apparatus that transmits multi-channel data of a plurality of channels in synchronization with a clock signal and an asynchronous communication network configured by devices that transfer data asynchronously. A synchronous asynchronous communication network conversion device computer for transferring data between synchronous multiple communication devices of
A clock master is set for a specific conversion device among a plurality of conversion devices, a clock slave is set for the remaining conversion devices, and one specific channel among the assigned channels of the conversion devices set as the clock master is clocked. Master / slave setting step for setting the master channel for synchronous control,
A transmission conversion step for distributing multi-frame data received from the synchronous multiplex communication device to each transmission buffer and storing it in each transmission buffer, generating asynchronous data from the stored data in the transmission buffer at regular intervals and transmitting it to the asynchronous communication network;
Asynchronous data distributed from the asynchronous communication network is received and stored in each receive buffer. Multiframe data is generated from the stored data in the receive buffer in synchronization with the clock signal of the variable clock unit, and transmitted to the synchronous multiplex communication device. Receiving conversion step,
Clock master synchronization control that is enabled in the setting state of the clock master and starts the variable clock unit at a predetermined center frequency when the reception buffer amount stored in the reception buffer of the master channel reaches a predetermined center value. Steps,
It becomes valid in the setting state of the clock slave, and when the receive buffer amount stored in the receive buffer of the master channel reaches a predetermined center value, the variable clock unit is set to the center frequency and started. A clock slave synchronization control step of controlling the clock frequency of the variable clock unit so as to be stable to the center value, and synchronizing the clock to another conversion device in the setting state of the clock master;
A program for executing is stored.

(system)
The present invention provides a communication system having a conversion function of synchronous asynchronous communication. The present invention
A synchronous multiplex communication device that transfers multi-frame data of multiple channels in synchronization with a clock signal is set to a clock master that is connected to an asynchronous communication network composed of devices that transfer data asynchronously. A master conversion device in which one channel is set as a master channel;
A slave conversion device set as a clock slave that connects other synchronous multiplex communication devices to an asynchronous communication network; and
In a communication system for transferring data between a plurality of synchronous multiplex communication devices,
The clock master device
A variable clock unit capable of variably controlling the frequency of the output clock signal;
A transmission conversion unit that distributes multi-frame data received from the synchronous multiplex communication device and accumulates it in each transmission buffer, generates asynchronous data from the accumulated data in the transmission buffer at regular intervals, and transmits it to the asynchronous communication network;
Asynchronous data distributed from the asynchronous communication network is received and stored in each receive buffer. Multiframe data is generated from the stored data in the receive buffer in synchronization with the clock signal of the variable clock unit, and transmitted to the synchronous multiplex communication device. A receiving conversion unit,
Clock master synchronization control that is enabled in the setting state of the clock master and starts the variable clock unit at a predetermined center frequency when the reception buffer amount stored in the reception buffer of the master channel reaches a predetermined center value. And
With
Slave converter is
A variable clock unit capable of variably controlling the frequency of the output clock signal;
A transmission conversion unit that distributes multi-frame data received from the synchronous multiplex communication device and accumulates it in each transmission buffer, generates asynchronous data from the accumulated data in the transmission buffer at regular intervals, and transmits it to the asynchronous communication network;
Asynchronous data distributed from the asynchronous communication network is received and stored in each receive buffer. Multiframe data is generated from the stored data in the receive buffer in synchronization with the clock signal of the variable clock unit, and transmitted to the synchronous multiplex communication device. A receiving conversion unit,
It becomes valid in the setting state of the clock slave, and when the receive buffer amount stored in the receive buffer of the master channel reaches a predetermined center value, the variable clock unit is set to the center frequency and started. A clock slave synchronization control unit that controls the clock frequency of the variable clock unit so as to be stable at the center value, and synchronizes the clock with another conversion device in the setting state of the clock master;
It is provided with.

  According to the present invention, the conversion device of the present invention is inserted and connected between a synchronous multiplex communication device that is a legacy device that transfers multi-frame data of a plurality of channels in synchronization with a clock signal and an IP communication network that is an asynchronous communication network. One of the plurality of converters is set as a clock master and the remaining clock slave, and further, a specific one of the channels allocated to the converter set as the clock master is set as a master channel used for clock synchronization control, Clock conversion is achieved for distributed channel transmission via the IP communication network by increasing or decreasing the clock frequency so that the reception buffer amount of the master channel is stabilized at the specified center value in the conversion device with the clock slave set, and synchronous multiplex communication From the perspective of the equipment, it is possible to achieve high-quality synchronization through channel distribution as if it were connected via a synchronous communication network. Communication can be realized by an IP network.

  For this reason, even if an existing synchronous communication network is changed to an IP communication network that is an asynchronous communication network, by using the conversion device of the present invention, the existing legacy communication network is not required outside the IP communication network. Synchronous multiplex communication devices can be directly connected to the IP communication network for synchronous communication by channel distribution, eliminating the obstacles when changing the existing optical fiber infrastructure from the synchronous communication network to the IP communication network, and the devices that can be connected jump In this way, various merits that the cost of the apparatus is reduced and the cost of the apparatus is reduced can be obtained.

  Also, in multiple converters with clock slaves set, one of the assigned channels from a specific converter with clock master set as the master channel, and the receive buffer amount of this master channel is used for clock control, making it easy Thus, the master-slave relationship of clock synchronization can be set, and the clock synchronization can be reliably maintained for the entire network.

  In the case of distributed channel transmission, the startup processing timing of the conversion device and the reception timing of the IP packet vary at each channel when the system is started up. Although it is necessary to perform synchronous transmission of multi-frame data that sends out all the received channel data in a uniform manner, in the present invention, after clearing the receive buffer for all channels, it is not the stored data in the receive buffer but the make busy. By starting synchronous transmission of multiframe data using no-signal data such as mark hold data generated by processing, it is possible to reliably start synchronous transmission using multiframe data without depending on the state of data stored in the reception buffer. .

  In addition, as a start-up process when an error occurs in the operating channel and recovers, if the error recovery channel is the master channel, clear the reception buffers of all channels and start up, just like when the power is turned on, It is possible to recover clock synchronization that has failed due to an abnormality in the master channel.

In addition, as a startup process when an error occurs in a channel other than the master channel during operation, the receive buffer of the error recovery channel is cleared and synchronous transmission of multiframe data is started from no-signal data. By switching to synchronous data transmission of buffer accumulated data when the amount reaches the reception buffer amount of the master channel, the reception buffer amount of the channel whose error has been recovered is linked to the reception buffer amount of the master channel used for clock synchronization control. Thus, the transition is made at a position almost equal to the reception buffer amount of the master channel, thereby making it difficult for abnormalities such as buffer empty to occur and ensuring higher quality synchronous communication.

  FIG. 1 is an explanatory diagram of a communication system using a synchronous / asynchronous communication network conversion apparatus according to the present invention. In FIG. 1, legacy multiplex transmission apparatuses 10-1 to 10-5 are devices that perform data synchronous communication using a synchronous communication network constructed of, for example, optical fibers. In this embodiment, a legacy interface of 2.048 Mbps is used. Is used as a multiplex transmission apparatus for transferring multi-frame data in which data for 30 channels are time-divisionally arranged using the synthesizer in synchronization with a clock.

  Here, in the legacy multiplex transmission apparatuses 10-1 to 10-6, since the multi-frame data obtained by time-division multiplexing 30-channel data is synchronously transmitted, the bandwidth per channel is 64 Kbps.

  Each of the legacy IP converters 12-1 to 12-6 of the present embodiment is provided between the corresponding legacy multiplex transmission apparatuses 10-1 to 10-6 and an IP network 18 constituted by routers and switches that are asynchronous communication networks. The multi-frame data is mutually communicated between the legacy multiplex transmission apparatuses 10-1 to 10-6 via the IP network 18.

  That is, the legacy IP converters 12-1 to 12-6 of the present embodiment connect the legacy multiple transmission devices 10-1 to 10-6 of the synchronous communication networks 11-1 and 11-2 to the legacy networks 14-1 to 14-6. And an IP network 18 that is an asynchronous communication network 15 via LANs 16-1 to 16-6 such as Ethernet (R). In addition, unique IP addresses are set in the legacy IP converters 12-1 to 12-6.

  The legacy IP converters 12-1 to 12-6 sample the multi-format frame data received from the legacy multiplex transmission apparatuses 10-1 to 10-6 on the basis of the synchronization clock, and then perform channel units by channel dispersion. IP packets are generated and sent to the IP network 18 at regular time intervals.

  Also, after receiving IP packets sent from the IP network 18 in a distributed manner, storing packet data of IP packets corresponding to each reception buffer provided corresponding to 30 channels, and then accumulating reception buffers for 30 channels. Data is collectively read to generate a multi-format frame, and is sent to the legacy multiplex transmission apparatuses 10-1 to 10-6 in synchronization with the clock.

  FIG. 2 is a block diagram showing a functional configuration of the legacy IP converter 12 of the present embodiment. 2, the legacy IP converter 12 includes a legacy interface unit 20, a transmission buffer group 24 including transmission buffers 240-1 to 240-30 for 30 channels, and packet assembly units 260-1 to 260- for 30 channels. A packet assembly group 26 including 30; an IP interface unit 22; a packet disassembly group 28 including packet disassembly units 280-1 to 280-30 for 30 channels; and receive buffers 300-1 to 300-30 for 30 channels. The reception buffer group 30 includes a variable clock unit 32 and a control unit 34.

  The control unit 34 is a function realized by execution of a program by the CPU, and includes a transmission conversion unit 38, a reception conversion unit 40, a clock master synchronization control unit 42, a clock slave synchronization control unit 44, a master slave setting unit 36, and a startup unit 46. And an abnormal startup unit 48.

  A master / slave setting unit 36 provided in the control unit 34 sets a clock master in a specific device among a plurality of legacy IP converters connected to the IP network 18, for example, the legacy IP converter 12-1 in FIG. Clock slaves are set in the remaining legacy IP converters 12-2 to 12-6.

  In addition, the legacy IP converter 12-1 set as the clock master controls the clock synchronization control of a specific channel among the assigned channels of the legacy multiplex transmission apparatus 10-1 connected via the legacy network 14-1. A master channel is set up for use.

  On the other hand, the legacy IP converters 12-2 to 12-6 set as clock slaves use one specific channel among the assigned channels of the legacy IP converter 10-1 set as the clock master for clock synchronization control. The master channel to use is set.

  The transmission conversion unit 38 provided in the control unit 34 samples the synchronous communication of the multi-frame data transmitted from the legacy multiplex transmission apparatus 10 in synchronization with the clock from the variable clock unit 32, and distributes it to the data for 30 channels. Then, after accumulating in each of the transmission buffers 240-1 to 240-30, the transmission buffer 240 at regular time intervals based on the function of the IP interface unit 22, for example, the synchronous clock from the variable clock unit 32 according to the Ethernet (R) standard. Data is read from -1 to 240-30, and an IP packet is generated by the packet assembling units 260-1 to 260-30 and transmitted to the IP network 18.

  The reception conversion unit 40 accumulates the packet data extracted from the IP packet received from the IP network 18 by the packet decomposition units 280-1 to 280-30 in the corresponding reception buffers 300-1 to 300-30. In synchronism with the clock signal from the variable clock unit 32, the legacy interface unit 20 reads data for 30 channels from the reception buffers 300-1 to 300-30 and generates multi-frame data arranged in a time-sharing manner. It transmits to the multiplex transmission apparatus 10.

  The clock master synchronization control unit 42 is enabled in the clock master setting state by the master slave setting unit 36. That is, in FIG. 1, the function as the clock master synchronization control unit 42 is effective only in the legacy IP converter 12-1.

  In this way, the clock master synchronization control unit 42 that has become effective based on the setting of the master clock, for example, the reception buffer amount C stored in the reception buffer 300-1 corresponding to the master channel has reached a predetermined center value Co. At this time, the variable clock unit 32 is fixed and started at a predetermined center frequency fo, so that the IP packet transmission processing by the channel dispersion of the transmission conversion unit 38 and the received IP packet by the channel distribution of the reception conversion unit 40 are performed. Multi-format frame synchronous communication based on the received data is performed based on a clock signal transmitted at a fixed frequency.

  The clock slave synchronization control unit 44 is enabled in the setting state of the clock slave. In other words, the legacy IP converters 12-2 and 12-4 are effective in the case of FIG.

  The valid clock slave synchronization control unit 44 sets the variable clock unit 32 to the center frequency fo when the reception buffer amount C accumulated in the reception buffer 300-1 of the master channel reaches a predetermined center value Co. After starting, control is performed to increase / decrease the clock frequency of the variable clock unit 32 so that the reception buffer amount C of the reception buffer 300-1 of the master channel is stabilized at the center value Co, thereby setting the clock master The legacy IP converters 12-2 to 12-6 in the clock slave setting state are clock-synchronized with the legacy IP converter 12-1 in the state.

  The start-up unit 46 provided in the control unit 34 clears the reception buffers 300-1 to 300-30 of all channels when the legacy IP converter 12 is started up when the power is turned on, and no accumulated data exists at this stage. Therefore, all channels are set as make-busy processing, and multi-format frames are generated from, for example, mark hold data as no-signal data for 30 channels, and synchronous transmission to the legacy multiplex transmission apparatus 10 is started.

  That is, when the legacy IP converter 12 performs distributed channel transmission to the IP network, the packet data accumulation based on the reception of the IP packet to the reception buffers 300-1 to 300-30 at the time of start-up is performed by other legacy IP converters. Therefore, even if the power is turned on, the stored data cannot be stored in the reception buffers 300-1 to 300-30.

  Therefore, in the present embodiment, as a start-up process at the time of start-up, the legacy multiplex transmission apparatus 10 side synchronizes with the clock in the creation of a multi-format frame using mark hold data that does not depend on accumulated data by the make busy process. The transmission of synchronous communication data can be started.

  After startup by such make busy processing, switching is performed from the reception buffer of the channel whose reception buffer amount has reached a predetermined center value Co to reading and transmission of buffer accumulated data.

  Note that the mark hold data generated as no-signal data is all-one data in the case of audio transmission, and this is data indicating a silent state.

  In addition, as a start-up process, at the same time as clearing the reception buffers 300-1 to 300-30, the transmission buffers 240-1 to 240-30 are cleared, and then at a certain time interval according to the timing on the IP interface unit 22 side. Thus, an IP packet for each channel is generated and transmitted to the IP network 18.

  The abnormal time startup unit 48 provided in the control unit 34 stores accumulated data when a reception buffer of any channel that performs channel distributed transmission during the operation of the system has some abnormality, for example, a network abnormality or an individual device abnormality. When a failure occurs when the buffer becomes empty, the startup process is performed when this error is recovered.

There are two types of startup processing at the time of abnormality: startup processing at the time of error recovery of the master channel.

  First, when the master channel error is recovered, the start-up process at the time of abnormality clears the reception buffers 300-1 to 300-30 of all channels and synchronizes multi-format frames with all channels as mark hold data by make busy processing. Communication data is generated and synchronous communication with the legacy multiplex transmission apparatus 10-1 is started. Thereafter, switching is performed from the reception buffer of the channel whose reception buffer amount has reached a predetermined center value Co to reading and transmission of buffer accumulated data.

  This is basically the same as the startup process at the time of startup by turning on the power by the startup unit 46. In other words, when a communication error occurs in the master channel during system operation and recovery, channel distributed transmission with clock synchronization control in the legacy IP converter 12 is broken. Start up startup processing.

  On the other hand, as an abnormal start-up process at the time of error recovery after a communication error has occurred in any of the receive buffers of channels other than the master channel, that is, any of the receive buffers 300-2 to 300-30, the receive buffer of the channel whose error has been recovered For example, the reception buffer 300-2 is cleared, and mark hold data is generated by make busy processing, and a multi-format frame is arranged at a corresponding channel position and is synchronously transmitted to the legacy multiplex transmission apparatus 10.

  Thereafter, the reception buffer amount of the error recovery channel reception buffer 300-2 is not the center value Co as in the case of power-on in this case, but the reception buffer amount of the master channel reception buffer 300-1 at that time. When it reaches, it switches to reading and transmission of buffer accumulated data from the reception buffer 300-2.

  The reason for starting the transmission of stored data to the legacy multiplex transmission apparatus 10 when the reception buffer amount of the reception buffer of the channel thus recovered abnormally reaches the reception buffer amount of the master channel is that of the reception buffer recovered abnormally This is because the reception buffer amount is shifted in conjunction with the reception buffer amount of the master channel so as to be almost the same value.

  If the reception buffer amount of the channel whose error has been recovered reaches the predetermined center value Co as in the case of turning on the power, if the read-out of stored data is started, then the reception buffer amount of the master channel is not necessarily the center value. It shifts according to the communication state of the IP packet at that time, not in Co, and as a result, a difference occurs between the reception buffer amount of the channel that has been recovered abnormally and the reception buffer amount of the master channel.

  When the difference between the two becomes large, the buffer reception amount of the error recovery channel also fluctuates in conjunction with the fluctuation of the buffer reception amount of the master channel according to the clock deviation while keeping the difference, and when the deviation amount is large, When the master channel receive buffer amount decreases, the error recovery channel receive buffer amount may fall below the normal buffer region, causing buffer empty errors.

  On the other hand, in the present embodiment, when the reception buffer amount of the channel that has been recovered abnormally reaches the reception buffer amount of the master channel at that time, reading and transmission of accumulated data is started, so that the reception buffer of the master channel It is possible to match the reception buffer amount of the channel whose error is recovered to almost the same amount, and by changing the variation of the reception buffer amount due to clock synchronization control with the same value for all channels, the buffer empty due to the variation of the reception buffer amount etc. Abnormality can be avoided and stable high-quality synchronous communication can be ensured.

  FIG. 3 is an explanatory diagram of a hardware environment of a computer that realizes the legacy IP converter 12 of FIG. 2 by executing a program. In FIG. 3, the legacy interface unit 20 and the IP interface unit 22 are connected to the bus 56 of the CPU 54 in addition to the RAM 58 and the ROM 60.

  In addition to the BIOS and OS, the ROM 60 stores a conversion program for the legacy IP conversion device of this embodiment. When the computer is started, the OS is read out to the RAM 58 by executing the BIOS of the ROM 60, and then the conversion program is read from the ROM 60 to the RAM 58 and executed by the CPU 54 by the processing of the OS.

  4A to 4F are explanatory diagrams of the channel management tables 50-1 to 50-6 stored in the legacy IP converters 12-1 to 12-6 in FIG.

  Here, the channel assignment of the legacy IP converters 12-1 to 12-6 in the distributed channel transmission using the IP network 18 will be described with reference to FIG.

  In FIG. 5, when six legacy IP converters 12-1 to 12-6 are performing packet transmission by channel distribution of 30-channel multiframe data, the nodes are represented by six nodes N 1 to N 6, respectively. It is necessary to construct N1 to N6 all-point communication (full duplex).

In such distributed channel transmission, if the number of nodes is n, the number m of all-point communication paths is calculated by tournament calculation.
m = n (n-1) / 2
Are in a relationship.

  In the present embodiment, since the number of channels n = 6, the number of paths is m = 15. In FIG. 5, these 15 paths are shown as paths P12 to P16, P23 to P26, P34 to P36, P45 to P46, and P56.

  Further, since nodes N1 to N6 each perform channel distributed transmission of 30 channels, assuming that channels are equally allocated to 5 paths per node, 6 channels are allocated per path. Note that the actually used channel may be a part of the assigned channel.

  The channel management tables 50-1 to 50-6 shown in FIGS. 4A to 4F are set based on the channel distributed transmission paths and channel assignments shown in FIG.

  The channel management tables 50-2 to 50-6 of the legacy IP converters 12-2 to 12-6 in which the clock slave is set include paths P12, P13, and the legacy IP converter 12-1 in which the clock master is set. One of the 6 channels assigned to P14, P15, and P16, for example, channel number = 1, is set as the master channel.

  The legacy IP converters 12-2 to 12-6 to which the clock slave is set have the clock of the variable clock unit 32 so as to keep the reception buffer amount of the reception buffer 300-1 corresponding to the master channel number = 1 at the center value Co. Clock synchronization control for increasing or decreasing the frequency is performed.

  Note that FIG. 5 shows an example of a path configuration based on all-point communication of six legacy IP converters 12-1 to 12-6. However, an arbitrary number is required as long as the bandwidth of the IP network 18 is not exceeded. It can be.

  FIG. 6 is an explanatory diagram showing the functional configuration of the legacy IP converters 12-1 and 12-2 shown in FIG. 1, in which the legacy IP converter 12-1 is set as a clock master, and the legacy IP converter The converter 12-2 is set as a clock slave.

  With the setting of the clock master, the control unit 34-1 of the legacy IP converter 12-1 operates with the function as the clock master synchronization control unit 42 enabled. On the other hand, in the legacy IP converter 12-2 in which the clock slave is set, the function as the clock slave synchronization control unit 44 is activated in the control unit 34-2 and operates.

  On the other hand, for both of the legacy IP converters 12-1 and 12-2, the functions of the startup units 46-1 and 46-2 and the abnormal startup units 48-1 and 48-2 are added to the control units 34-1 and 34-2. Are enabled and operating.

  Although not shown in FIG. 6, each of the control units 34-1 and 34-2 has functions as the transmission conversion unit 38 and the reception conversion unit 40 shown in FIG. Of course to do.

  FIG. 7 is a time chart showing the control of the clock slave synchronization control unit 44 of the legacy IP converter 12-2 in which the clock slave of FIG. 6 is set, and is received at the start-up after the power is turned on or the system abnormality is recovered. The case where the buffer amount increases is taken as an example.

  FIG. 7A shows the reception buffer amount C, and FIG. 7B shows the clock frequency. At the time of start-up, when the reception buffer amount C reaches a predetermined center value Co as shown at time to in FIG. 7A, the clock of the variable clock unit 32-2 as shown in FIG. 7B. The frequency f is set to the center frequency fo, and start-up processing for sending the data stored in the reception buffer 30-2 to the legacy multiplex transmission device 10-2 is started.

  Assuming that the clock frequency on the clock master side is higher than the clock frequency on the clock slave side at this time, in the data transmission to the legacy device 10-2 by the clock having the center frequency fo set at the start-up, the data is sent to the reception buffer 30-2. Since data reading is delayed with respect to accumulation of data received from the IP network 18 side, the reception buffer amount C increases with time.

  When the reception buffer amount C increases and exceeds the upper limit value Cmax at time t1, the clock frequency f is changed from the center frequency fo to the maximum adjustment frequency fmax, whereby the reception multiplex transmission device 10-2 changes from the reception buffer 30-2. Speed up data transmission for. For this reason, the reception buffer amount starts to decrease from time t1, and returns to the center value Co again at time t2.

  At time t2, the clock frequency f is changed from the maximum adjustment frequency fmax so far to a frequency (fo + α) shifted by a predetermined offset frequency α to the plus side with respect to the center frequency fo.

  Thus, by changing to the frequency (fo + α) obtained by adding the offset frequency α to the center frequency fo, the reception buffer amount starts increasing again at a moderate rate compared to the case of the center frequency fo at time to, and at time t3. The upper limit value Cmax is reached. Also in this case, similarly to the time t1, the clock frequency is changed to the maximum adjustment frequency fmax, thereby reducing the reception buffer amount again and returning to the center value Co at the time t4.

  At time t4, the clock frequency fo is changed to a frequency (α + 2α) obtained by adding a frequency n · α obtained by multiplying the center frequency by the offset frequency α and the number of adjustments n. As a result, the increase in the reception buffer amount from time t4 becomes more gradual and reaches the upper limit value Cmax at time t5. At time t5, the clock frequency is changed again to the maximum adjustment frequency fmax, and the reception buffer amount is returned to the center value Co at time t6. In this case, the clock frequency fo is changed to the frequency (fo + 3α).

  When the frequency is changed to frequency (fo + 3α) at time t6, the reception buffer amount C is stabilized at the center value Co in this example. The state in which the reception buffer amount is stable at the center value Co is received based on the amount of data stored in the reception buffer 30-2 upon reception of the IP packet from the IP network 18 and the clock frequency (fo + 3α) of the variable clock unit 32-2. This is a case where the amount of data transmitted from the buffer 30-2 to the legacy device 10-2 matches, and this eventually results in the clock slave side to the clock frequency of the variable clock unit 32-1 on the clock master side via the IP network 18. That is, the state where the clock frequency of the variable clock unit 32-2 is synchronized is established.

  As described above, in the present embodiment, the learning process of adjusting the clock frequency for stabilizing the reception buffer amount at the center value by the clock slave synchronization control unit 44 of the legacy IP converter 12-2 in which the clock slave is set. Through the above, it is possible to realize clock synchronization control for synchronizing the clock frequency on the clock slave side with the clock frequency on the clock master side.

  Here, the frequency change of the maximum adjustment frequency fmax with respect to the center frequency fo of the clock frequency f in FIG. 7B is, for example, +100 ppm, and the change width of the minimum adjustment frequency fmin with respect to the center frequency fo is −100 ppm. The offset frequency α to be adjusted is, for example, a resolution of α = 0.1 ppm.

In addition, ppm is frequency accuracy, and when this is expressed by frequency change width ± Δf, between frequency angle ppm and frequency error, (frequency angle ppm) = Δf / (fo × 10 ⁻⁸ )
For example, when fo = 2 MHz and ppm = 100, Δf = 5 KHz, and the offset frequency α serving as the adjustment resolution is α = 50 Hz.

  In FIG. 7, the clock frequency is stabilized by three adjustment processes. However, since the resolution is actually α = 0.1 ppm, it depends on the clock deviation at the start-up. In order to achieve a synchronized state in which the clock frequency on the clock slave side is stabilized by the clock slave synchronization control of this embodiment, it usually takes a processing time of several hours to several tens of hours.

  However, even if it is such a long time, once it is started and stabilized, the frequency of the + α or −α clock adjustment with respect to the change in the reception buffer amount is about once every several days, for example. Transmission quality comparable to that obtained when clocks are transmitted by an external network to the network to achieve clock synchronization can be ensured.

  FIG. 8 is a time chart showing the clock slave synchronization control of this embodiment when the reception buffer amount decreases at the time of startup.

  In FIG. 8A, when the power supply is turned on or the system is started up upon recovery from the system abnormality, the IP interface unit 22 is transferred from the IP network 18 to the reception buffer 30-2 of the legacy IP converter 12-2 on the clock slave side in FIG. -2 starts accumulating the packet data of the IC packet received at -2, and when the reception buffer amount reaches the center value Co, the clock frequency fo is set to the center value fo as shown in FIG. And the accumulated data in the reception buffer 30-2 is read from the legacy interface unit 20-2 to the legacy multiplex transmission device 10-2 and transmission of synchronous communication data is started.

  In this case, the clock frequency of the variable clock unit 32-2 of the legacy IP converter 12-2 in which the clock slave is set to the clock frequency of the variable clock unit 32-1 in the legacy IP converter 12-1 in which the clock master is set up. Is high, the data transmission from the reception buffer 30-2 to the legacy multiplex transmission device 10-2 is accelerated, so that the reception buffer amount C starts to decrease from time to as shown in FIG. Below Cmin.

  In this case, the clock frequency f is changed from the center frequency fo to the minimum adjustment frequency fmin, and the transmission amount from the reception buffer 30-2 is reduced. For this reason, the reception buffer amount C starts increasing from time t1 and recovers to the center value Co again at time t2.

  When the center value Co is restored, the clock frequency f is changed to the frequency (fo−α) obtained by subtracting the frequency obtained by multiplying the offset frequency α by one adjustment number from the center frequency fo. As a result, the reception buffer amount C from time t2 occurs, and the rate of decrease becomes more gradual than the first time at time to. When the frequency falls below the lower limit Cmin again at time t3, the clock frequency f is changed again to the minimum adjustment frequency fmin. The reception buffer amount C is increased from time t3.

  When the reception buffer amount C recovers to the center value Co at time t4, the clock frequency is changed to (fo-2α), and the decreasing rate of the reception buffer amount C from time t4 is further reduced. Similar processing is repeated at times t5 and t6, and when the clock frequency becomes (fo-3α), the reception buffer amount C is stabilized at the center value Co, and the master slave side clock is synchronized with the master clock side. Stable state can be created.

  Further, in the present embodiment, as shown in FIG. 7 or FIG. 8, if a stable state that is in a clock synchronization state is obtained through learning processing by clock slave synchronization control after startup, the clock frequency in the stable state, For example, in the case of FIG. 7, the stable clock frequency (fo + 3α) is stored, and in the case of FIG. 8, the stable clock frequency (fo-3α) is stored.

  When the power is turned on next time or when the communication buffer is restored, when the reception buffer reaches the center value Co, the clock frequency f is set to the stored stable clock frequency instead of the center frequency fo. Start the clock adjustment process. As a result, the clock adjustment processing time at the second and subsequent startups can be greatly reduced.

  As another embodiment of the clock slave synchronization control, the upper and lower limits of the buffer fluctuation allowable range have two levels of magnitude, and the smaller upper and lower limits are used until the clock frequency is stabilized after being started. After a narrow buffer fluctuation tolerance is set and the clock frequency is stabilized, a wider buffer fluctuation tolerance is set according to the larger upper and lower limit values, thereby shortening the time until the clock frequency stabilizes in a synchronized state. it can.

  According to the clock slave synchronous control in which the buffer upper limit value is set in two stages, it takes a long time of several hours to several tens of hours to reach the stable region of the clock in the case of FIGS. Depending on the degree of the set value when there are two stages, the time can be significantly shortened until the clock is stabilized, such as several minutes to several tens of minutes.

  Then, after adjusting the clock to the stable region in a short time with the narrow buffer fluctuation allowable range, the upper and lower limits of the buffer fluctuation allowable range are increased to widen the range, thereby generating clock adjustment control in the stable region. The frequency can be suppressed and a more stable clock synchronization state can be secured.

FIG. 9 is a flowchart showing an outline of the conversion process according to this embodiment. In FIG. 9, the processing for the legacy IP converter 12 of FIG. 2 will be described as follows. When the legacy IP converter 12 is turned on and started up, initial setting is first performed in step S1. This initial setting includes setting processing by the master / slave setting unit 36, and specifically includes parameter setting for clock master / slave setting master channel setting clock synchronization control.

  Subsequently, in step S2, whether or not the clock master is set is checked. If the clock master is set, the process proceeds to step S3, the function of the clock master synchronization control unit 42 is enabled and the clock master conversion process is executed. The clock master conversion process is repeated until a stop instruction is issued in S4.

  On the other hand, if the setting of the slave master is determined in step S2, the process proceeds to step S5, the clock slave synchronization control unit 44 is enabled and clock slave conversion processing is performed, and this is repeated until a stop instruction is issued in step S6. .

  FIG. 10 is a flowchart showing the clock master transmission conversion process in the present embodiment, which is a process by the transmission conversion unit 38 provided in the control unit 34 in which the clock master of FIG. 2 is set.

  In FIG. 9, in the clock master transmission conversion process, after determining whether or not the IP interface unit 22 has reached a certain transmission timing determined by an IP interface such as Ethernet (R), the transmission buffers 240-1 to 240 in step S2. The packet assembling units 260-1 to 260-30 generate IP packets for all channels, that is, 30 IP packets, from the data stored in −30, and transmit them to the IP network 18.

  The process of generating the IP packet and transmitting it to the IP network is performed by a communication algorithm of the IP network 18 such as Ethernet (R). Such processes of steps S1 to S2 are repeated until a stop instruction is issued in step S3.

  FIG. 11 is a flowchart showing the clock master reception conversion process of this embodiment, which is a process by the reception conversion unit 40 of the legacy IP converter 12 to which the clock master of FIG. 2 is set.

  In FIG. 11, the clock master reception conversion process is started with the clock frequency of the variable clock unit 32 fixed at the center frequency fo in step S1, and then the startup process for all channels is executed in step S2.

  When the start-up process is completed, the data stored in the reception buffers of all channels is read out to create multi-frame data in step S3, and is synchronously transmitted to the legacy multiplex transmission apparatus 10 in synchronization with the clock from the variable clock unit 32.

  Subsequently, in step S4, it is checked whether or not an abnormality has occurred in a specific channel. If an abnormality has occurred, in step S5, the abnormality recovery of the channel is executed after waiting for the recovery of the channel abnormality. . Such processes of steps S1 to S6 are repeated until a stop instruction is issued in step S7.

  FIG. 12 is a flowchart showing details of the startup process shown in step S2 of FIG. In FIG. 11, in the start-up process, the reception buffers 300-1 to 300-30 of all channels are cleared in step S1, and subsequently, in step S2, all channels are set as mark hold data by the make busy process, and the variable clock is generated by the legacy interface unit 20. A multi-format frame is generated in synchronization with the clock of the unit 32 and synchronous communication with the legacy multiplex transmission apparatus is started.

  Subsequently, in step S3, it is checked whether there is a reception buffer that has reached the center value among the reception buffer amounts of the reception buffers 300-1 to 300-30. If there is a reception buffer that has reached the center value, step S4 is performed. Thus, the data stored in the reception buffer is included in the multi-format frame and switched to data read transmission for synchronous communication with the legacy multiplex transmission apparatus.

  In step S5, it is checked whether or not make-busy cancellation has been performed for all channels to determine whether or not make-busy cancellation has been performed. In step S6, a transition is made to a normal processing state in which a multi-format frame is generated from the accumulated data in the reception buffer and transmitted on all channels.

  FIG. 13 is a flowchart showing details of the abnormal startup process shown in step S6 of FIG. In FIG. 13, the startup process at the time of abnormality checks whether or not the master channel has been recovered in step S1. If the master channel has been recovered from the abnormality, the process proceeds to step S2, and after clearing all channel reception buffers, In step S3, start-up processing for all channels is executed. The details of this startup process are the same as the flowchart of the startup process in FIG.

  If it is determined in step S1 that the channel other than the master channel has recovered abnormally, the process proceeds to step S4, the reception buffer of the channel in which the abnormality is recovered is cleared, and then the mark hold data generated by the make busy process in step S5 is abnormal. The communication is started at the position of the multi-format frame corresponding to the recovered channel.

  Subsequently, in step S6, the reception buffer amount of the master channel is read as a reference value, and in step S7, it is checked whether or not the reception buffer amount of the error recovery channel has reached the reference value. When the reception buffer amount of the error recovery channel reaches the reference value in step S7, the process proceeds to step S8, where the transmission of the mark hold data by the make busy processing so far is switched to the transmission of the accumulated data in the reception buffer, and the normal synchronous communication state Migrate to

  FIG. 14 is a flowchart of the clock slave transmission conversion process in the present embodiment. The transmission conversion process when the clock slave is set in the legacy IP converter 12 of FIG. 2 and the function of the clock slave synchronization control unit 44 is enabled. It is.

  In this clock slave conversion process, as in the clock master transmission conversion process of FIG. 10, if it is determined in step S1 that the transmission timing of a certain time interval determined by the standard of the IP interface unit 22 has been reached, in step S2 IP packets are generated from the accumulated data in the transmission buffers 240-1 to 240-30 for all channels and transmitted to the IP network 18.

  FIG. 15 is a flowchart of the clock slave reception conversion process of the present embodiment, in the case where the clock slave is set in the legacy IP converter 12 of FIG. 2 and the function of the clock slave synchronization control unit 44 is enabled. It becomes processing.

  In FIG. 15, in step S1, the clock frequency of the variable clock unit 32 is set to the center frequency fo, and in step S2, all channels are started up. Details of the startup process in step S2 are the same as those in the flowchart of FIG.

  Next, in step S3, the process shifts to multiframe transmission by clock synchronization of all channels. Subsequently, clock synchronization control is executed by the clock slave synchronization control unit 44 in step S4. Subsequently, in step S5, it is checked whether or not an abnormality has occurred in a specific channel. If an abnormality has been determined, abnormality recovery is determined in step S6, and then an abnormal startup process is executed in step S7.

  The details of the abnormal startup process in step S7 are the same as those in the flowchart of FIG. Such processes of steps S3 to S7 are repeated until a stop instruction is issued in step S8.

  FIG. 16 is a flowchart showing details of the clock synchronization control processing in step S4 of FIG. In FIG. 16, the clock synchronization control process reads the reception buffer amount corresponding to the master channel in step S1, for example, the reception buffer amount of the reception buffer 300-1 in FIG. 2, and whether the reception buffer amount is the upper limit value in step S2. To check.

  Here, the processes in steps S2 to S6 are control processes when the reception buffer amount increases as shown in FIG. 7, and steps S7 to S11 are the control processes when the reception buffer amount decreases as shown in FIG.

  Here, as shown in FIG. 7A, if the reception buffer amount C increases from the center value Co at startup and reaches the upper limit Cmax at time t1, this is determined in step S2, and in step S3. The clock frequency f is changed to the maximum adjustment frequency fmax.

Subsequently, in step S4, it is checked whether or not the reception buffer amount has returned to the center value Co. If so, in step S5, the adjustment count n (however, the initial value n = 0) is incremented by one, and in step S6 the clock is increased. The frequency f = fo + n · α obtained by multiplying the center frequency fo by the value obtained by multiplying the frequency by the offset frequency α and the adjustment frequency n
And the process returns to step S1 again.

  The same processing is repeated each time the reception buffer amount reaches the upper limit value, and as shown in FIG. 7, the slave side is controlled in a clock frequency control state that is finally determined when the reception buffer amount C is stable at the center value Co. Can be synchronized with the clock frequency on the master side.

  On the other hand, when the buffer amount decreases from the center value Co as shown in FIG. 8A, the process proceeds to step S7, and when it is determined that the reception buffer amount has reached the lower limit value Cmin, the clock frequency is determined in step S8. Is changed to the minimum adjustment frequency fmin.

Subsequently, in step S9, it is checked whether or not the reception buffer amount has recovered to the center value Co. If it has recovered, the process proceeds to step S10 and the number of adjustments n is increased by 1, and then the clock frequency f is adjusted in step S11. The value obtained by multiplying the frequency n by the offset frequency α is subtracted from the center frequency fo. F = fo−n · α
Adjust to.

  Then, the process returns to step S1 again, and the processes of steps S7 to S11 are repeated via step S2. As shown in FIG. 8, the slave side is mastered by the clock frequency when the reception buffer amount is stabilized at the center value Co. The clock can be synchronized to the side.

  The present invention also provides a synchronous / asynchronous network conversion program executed by the computer of FIG. 3 which functions as the control unit 34 of the legacy IP converter 12 shown in FIG. The contents shown in the flowchart of FIG.

  The present invention also provides a recording medium storing a program executed by the legacy IP converter 12. This recording medium is a portable recording medium such as a CD-ROM, floppy disk (R), DVD disk, magneto-optical disk, IC card, etc., a storage device such as a hard disk drive provided inside or outside the computer system, It includes a database or other computer system that holds a program via a line, the database, and a transmission medium on the line.

  In the above-described embodiment, a 2.048 Mbps 30-channel compatible device is taken as an example of a legacy multiplex transmission device, but other 1.544 Mbps legacy multiplex transmission devices may be used. And legacy equipment that performs synchronous communication of appropriate multi-format frames.

  In the clock slave synchronization control shown in FIGS. 7 and 8, an upper limit value Cmax and a lower limit value Cmin that determine the buffer fluctuation allowable range 62 are set for the reception buffer amount C, and when the upper and lower limit values are reached. Although the clock frequency is increased / decreased, the clock frequency may be increased / decreased according to the rising or falling slope of the reception buffer amount C from the center value Co.

  Further, the clock frequency f can be increased or decreased in accordance with the deviation of the reception buffer amount with respect to the center value Co. That is, with respect to the center value Co, the clock frequency is increased for a positive deviation of the reception buffer amount, and the clock frequency is decreased for a negative deviation, and the decrease amount and the increase amount are controlled according to the deviation amount. So-called feedback control may be performed.

  Further, the present invention includes appropriate modifications that do not impair the object and advantages thereof, and is not limited by the numerical values shown in the above embodiments.

Here, the features of the present invention are enumerated as follows.
(Appendix)

(Appendix 1) (Device)
Inserted and connected between a synchronous multiplex communication apparatus that transmits multi-channel data of a plurality of channels in synchronization with a clock signal and an asynchronous communication network composed of devices that transfer data asynchronously. In a synchronous asynchronous communication network conversion device that transfers data between
A clock master is set for a specific conversion device among a plurality of conversion devices, a clock slave is set for the remaining conversion devices, and one specific channel among the assigned channels of the conversion devices set as the clock master is clocked. A master / slave setting unit for setting the master channel for synchronous control;
A variable clock unit capable of variably controlling the frequency of the output clock signal;
A transmission conversion unit that distributes the multi-frame data received from the synchronous multiplex communication device and accumulates it in each transmission buffer, generates asynchronous data from the accumulated data in the transmission buffer at regular intervals, and transmits the asynchronous data to the asynchronous communication network;
Asynchronous data received from the asynchronous communication network is distributed and stored in each reception buffer, and multiframe data is generated from the data stored in the reception buffer in synchronization with the clock signal of the variable clock unit. A receiving converter for transmitting to the device;
A clock that is valid in the setting state of the clock master and that starts the variable clock unit at a predetermined center frequency when the reception buffer amount stored in the reception buffer of the master channel reaches a predetermined center value. A master synchronization control unit;
It becomes effective in the setting state of the clock slave, and when the reception buffer amount accumulated in the reception buffer of the master channel reaches a predetermined center value, the variable clock unit is set to the center frequency and started. A clock slave synchronization control unit that controls the clock frequency of the variable clock unit so as to stabilize the reception buffer amount at the center value, and synchronizes the clock with another conversion device in the setting state of the clock master;
A conversion device comprising: (1)

(Appendix 2) (Startup process)
In the conversion device according to attachment 1, the reception conversion unit clears the reception buffer of all channels and generates multi-frame data in which all channels are non-signal data at the time of start-up upon power-on to generate the synchronization A conversion apparatus, wherein synchronous transmission is started to a multiplex communication apparatus, and after the synchronous transmission is started, switching is performed from a channel whose reception buffer amount has reached a predetermined center value to reading and transmission of data accumulated in the reception buffer. (2)

(Appendix 3) (Startup process when master channel is abnormal)
The conversion apparatus according to attachment 1, wherein the reception conversion unit clears the reception buffer of all channels and restores all channels to non-signal data when the master channel abnormality is recovered during operation. A conversion apparatus, comprising: generating data, starting synchronous transmission to the synchronous multiplex communication apparatus, and switching to reading and transmission of buffer accumulated data from a channel whose reception buffer amount has reached a predetermined center value after the start of synchronous transmission. (3)

(Appendix 4) (Startup process when a non-master channel error occurs)
The conversion device according to attachment 1, wherein the reception conversion unit clears the reception buffer of the error recovery channel and multi-frames the non-signal data at the time of start-up when an error of a channel other than the master channel is recovered during operation. A conversion device characterized in that the data is synchronously transmitted to the synchronous multiplex communication device and is switched to read transmission of buffer accumulated data when the reception buffer amount of the error recovery channel reaches the reception buffer amount of the master channel. . (4)

(Appendix 5) (Details of clock slave synchronization control)
In the conversion device according to attachment 1, the clock slave synchronization control unit includes:
If the receive buffer amount exceeds the upper limit of the allowable range of buffer fluctuation after starting the clock frequency from the center frequency, it is changed to a predetermined maximum adjustment frequency, and the maximum adjustment is made when the receive buffer amount returns to the center value after the change. The process of changing the frequency to a frequency obtained by adding a predetermined offset frequency to the center frequency is repeated while sequentially increasing the offset frequency,
When the reception buffer amount falls below the lower limit value of the buffer fluctuation allowable range after starting the clock frequency from the center frequency, it is changed to a predetermined minimum adjustment frequency, and when the reception buffer amount returns to the center value after the change, the minimum A conversion device characterized by repeating the process of changing the adjustment frequency to a frequency obtained by subtracting a predetermined offset frequency from the center frequency while increasing the offset frequency sequentially. (5)

(Appendix 6) (Legacy IF and IP communication network)
The conversion apparatus according to claim 1, wherein the synchronous multiplex communication device is a device having a legacy interface, and the device of the asynchronous communication network is a device having an Internet protocol interface.

(Appendix 7) (Method)
Inserted and connected between a synchronous multiplex communication apparatus that transmits multi-channel data of a plurality of channels in synchronization with a clock signal and an asynchronous communication network composed of devices that transfer data asynchronously. In the conversion method of the conversion device for transferring data between,
A clock master is set for a specific conversion device among a plurality of conversion devices, a clock slave is set for the remaining conversion devices, and one specific channel among the assigned channels of the conversion devices set as the clock master is clocked. Master / slave setting step for setting the master channel for synchronous control,
A transmission conversion step of distributing multi-frame data received from the synchronous multiplex communication device to each transmission buffer and storing it in each transmission buffer, generating asynchronous data from the storage data in the transmission buffer at regular intervals, and transmitting it to the asynchronous communication network;
Asynchronous data communication apparatus that receives asynchronous data distributed in channels from the asynchronous communication network and stores the asynchronous data in each reception buffer, and generates multi-frame data from the data stored in the reception buffer in synchronization with the clock signal of the variable clock unit. A receiving conversion step to send to
A clock that is valid in the setting state of the clock master and that starts the variable clock unit at a predetermined center frequency when the reception buffer amount stored in the reception buffer of the master channel reaches a predetermined center value. A master synchronization control step;
It becomes effective in the setting state of the clock slave, and when the reception buffer amount accumulated in the reception buffer of the master channel reaches a predetermined center value, the variable clock unit is set to the center frequency and started. A clock slave synchronization control step of controlling the clock frequency of the variable clock unit to stabilize the reception buffer amount at the center value, and clock-synchronizing with another conversion device in the setting state of the clock master;
A conversion method characterized by comprising: (6)

(Appendix 8) (Startup process)
In the conversion method according to appendix 7, the reception conversion step generates the multi-frame data by clearing the reception buffer of all channels and generating multi-frame data with all the channels as non-signal data at the time of startup upon power-on. A conversion method comprising: starting synchronous transmission to a multiplex communication apparatus, and switching to reading and transmission of data accumulated in a reception buffer from a channel whose reception buffer amount has reached a predetermined center value after the start of synchronous transmission.

(Appendix 9) (Startup process when master channel is abnormal)
In the conversion method according to attachment 7, the reception conversion step includes:
When the master channel abnormality is recovered during operation, the reception buffer of all channels is cleared and multi-frame data with all channels as no-signal data is generated to start synchronous transmission to the synchronous multiplex communication device. , After the start of synchronous transmission, switching from the channel in which the reception buffer amount has reached a predetermined center value to reading transmission of buffer accumulated data,
At the time of start-up when an error of a channel other than the master channel is recovered during operation, the reception buffer of the error recovery channel is cleared and non-signal data is included in multiframe data to be transmitted synchronously to the synchronous multiplex communication device, and the error A conversion method characterized by switching to read transmission of buffer accumulated data when the reception buffer amount of the recovery channel reaches the reception buffer amount of the master channel.

(Appendix 10) (Details of clock slave synchronization control)
In the conversion method according to attachment 7, the clock slave synchronization control step includes:
If the receive buffer amount exceeds the upper limit of the allowable range of buffer fluctuation after starting the clock frequency from the center frequency, it is changed to a predetermined maximum adjustment frequency, and the maximum adjustment is made when the receive buffer amount returns to the center value after the change. The process of changing the frequency to a frequency obtained by adding a predetermined offset frequency to the center frequency is repeated while sequentially increasing the offset frequency,
When the reception buffer amount falls below the lower limit value of the buffer fluctuation allowable range after starting the clock frequency from the center frequency, it is changed to a predetermined minimum adjustment frequency, and when the reception buffer amount returns to the center value after the change, the minimum A conversion method characterized by repeating the process of changing the adjustment frequency to a frequency obtained by subtracting a predetermined offset frequency from the center frequency while increasing the offset frequency sequentially.

(Appendix 11) (Program)
Inserted and connected between a synchronous multiplex communication apparatus that transmits multi-channel data of a plurality of channels in synchronization with a clock signal and an asynchronous communication network composed of devices that transfer data asynchronously. To the computer of the conversion device that transfers data between
A clock master is set for a specific conversion device among a plurality of conversion devices, a clock slave is set for the remaining conversion devices, and one specific channel among the assigned channels of the conversion devices set as the clock master is clocked. Master / slave setting step for setting the master channel for synchronous control,
A transmission conversion step of distributing multi-frame data received from the synchronous multiplex communication device to each transmission buffer and storing it in each transmission buffer, generating asynchronous data from the storage data in the transmission buffer at regular intervals, and transmitting it to the asynchronous communication network;
Asynchronous data communication apparatus that receives asynchronous data distributed in channels from the asynchronous communication network and stores the asynchronous data in each reception buffer, and generates multi-frame data from the data stored in the reception buffer in synchronization with the clock signal of the variable clock unit. A receiving conversion step to send to
A clock that is valid in the setting state of the clock master and that starts the variable clock unit at a predetermined center frequency when the reception buffer amount stored in the reception buffer of the master channel reaches a predetermined center value. A master synchronization control step;
It becomes effective in the setting state of the clock slave, and when the reception buffer amount accumulated in the reception buffer of the master channel reaches a predetermined center value, the variable clock unit is set to the center frequency and started. A first clock slave synchronization control step of controlling the clock frequency of the variable clock unit so as to stabilize the reception buffer amount at the center value and clock-synchronizing with another conversion device in the setting state of the clock master;
A program characterized by having executed.

(Appendix 12) (Startup process)
In the program according to appendix 11, in the reception conversion step, when the power is turned on, the reception buffer of all channels is cleared and multiframe data in which all channels are set to no signal data is generated to generate the synchronous multiplexing. A program characterized by starting synchronous transmission to a communication device and switching to reading and transmission of data accumulated in a reception buffer from a channel whose reception buffer amount has reached a predetermined center value after the start of synchronous transmission.

(Supplementary note 13) (Start-up process when master channel is abnormal)
In the program according to attachment 11, the reception conversion step includes:
When the master channel abnormality is recovered during operation, the reception buffer of all channels is cleared and multi-frame data with all channels as no-signal data is generated to start synchronous transmission to the synchronous multiplex communication device. , After the start of synchronous transmission, switching from the channel in which the reception buffer amount has reached a predetermined center value to reading transmission of buffer accumulated data,
At the time of start-up when an error of a channel other than the master channel is recovered during operation, the reception buffer of the error recovery channel is cleared and non-signal data is included in multiframe data to be transmitted synchronously to the synchronous multiplex communication device, and the error A program for switching to read transmission of buffer accumulated data when the reception buffer amount of the recovery channel reaches the reception buffer amount of the master channel.

(Appendix 14) (Details of clock slave synchronization control)
In the program according to attachment 11, the clock slave synchronization control step includes:
If the receive buffer amount exceeds the upper limit of the allowable range of buffer fluctuation after starting the clock frequency from the center frequency, it is changed to a predetermined maximum adjustment frequency, and the maximum adjustment is made when the receive buffer amount returns to the center value after the change. The process of changing the frequency to a frequency obtained by adding a predetermined offset frequency to the center frequency is repeated while sequentially increasing the offset frequency,
When the reception buffer amount falls below the lower limit value of the buffer fluctuation allowable range after starting the clock frequency from the center frequency, it is changed to a predetermined minimum adjustment frequency, and when the reception buffer amount returns to the center value after the change, the minimum A program characterized by repeating the process of changing the adjustment frequency to a frequency obtained by subtracting a predetermined offset frequency from the center frequency while sequentially increasing the offset frequency.

(Appendix 15) (Recording medium)
Inserted and connected between a synchronous multiplex communication apparatus that transmits multi-channel data of a plurality of channels in synchronization with a clock signal and an asynchronous communication network composed of devices that transfer data asynchronously. To the computer of the conversion device of the synchronous asynchronous communication network that transfers data between
A clock master is set for a specific conversion device among a plurality of conversion devices, a clock slave is set for the remaining conversion devices, and one specific channel among the assigned channels of the conversion devices set as the clock master is clocked. Master / slave setting step for setting the master channel for synchronous control,
A transmission conversion step of distributing multi-frame data received from the synchronous multiplex communication device to each transmission buffer and storing it in each transmission buffer, generating asynchronous data from the storage data in the transmission buffer at regular intervals, and transmitting it to the asynchronous communication network;
Asynchronous data communication apparatus that receives asynchronous data distributed in channels from the asynchronous communication network and stores the asynchronous data in each reception buffer, and generates multi-frame data from the data stored in the reception buffer in synchronization with the clock signal of the variable clock unit. A receiving conversion step to send to
A clock that is valid in the setting state of the clock master and that starts the variable clock unit at a predetermined center frequency when the reception buffer amount stored in the reception buffer of the master channel reaches a predetermined center value. A master synchronization control step;
It becomes effective in the setting state of the clock slave, and when the reception buffer amount accumulated in the reception buffer of the master channel reaches a predetermined center value, the variable clock unit is set to the center frequency and started. A clock slave synchronization control step of controlling the clock frequency of the variable clock unit to stabilize the reception buffer amount at the center value, and clock-synchronizing with another conversion device in the setting state of the clock master;
The computer-readable recording medium characterized by storing the program which performs. (7)

(Appendix 16) (Startup process)
In the recording medium of appendix 15, the reception conversion step generates the multi-frame data by clearing the reception buffers of all channels and generating multi-frame data with all channels as no-signal data at the time of startup upon power-on. A recording medium characterized by starting synchronous transmission to a multiplex communication apparatus, and switching to reading and transmission of data accumulated in a reception buffer from a channel whose reception buffer amount has reached a predetermined center value after the start of synchronous transmission.

(Appendix 17) (Startup process when master channel is abnormal)
In the recording medium according to attachment 15, the reception conversion step includes:
When the master channel abnormality is recovered during operation, the reception buffer of all channels is cleared and multi-frame data with all channels as no-signal data is generated to start synchronous transmission to the synchronous multiplex communication device. , After the start of synchronous transmission, switching from the channel in which the reception buffer amount has reached a predetermined center value to reading transmission of buffer accumulated data,
At the time of start-up when an error of a channel other than the master channel is recovered during operation, the reception buffer of the error recovery channel is cleared and non-signal data is included in multiframe data to be transmitted synchronously to the synchronous multiplex communication device, and the error A recording medium characterized by switching to reading and transmission of buffer accumulated data when the reception buffer amount of the recovery channel reaches the reception buffer amount of the master channel.

(Appendix 18) (System)
A synchronous multiplex communication device that transfers multi-frame data of multiple channels in synchronization with a clock signal is set to a clock master that is connected to an asynchronous communication network composed of devices that transfer data asynchronously. A master conversion device in which one channel is set as a master channel;
A slave conversion device set as a clock slave for connecting another synchronous multiplex communication device to the asynchronous communication network;
In a communication system for transferring data between the plurality of synchronous multiplex communication devices,
The clock master device is
A variable clock unit capable of variably controlling the frequency of the output clock signal;
A transmission conversion unit that distributes the multi-frame data received from the synchronous multiplex communication device and accumulates it in each transmission buffer, generates asynchronous data from the accumulated data in the transmission buffer at regular intervals, and transmits the asynchronous data to the asynchronous communication network;
Asynchronous data received from the asynchronous communication network is distributed and stored in each reception buffer, and multiframe data is generated from the data stored in the reception buffer in synchronization with the clock signal of the variable clock unit. A receiving converter for transmitting to the device;
A clock that is valid in the setting state of the clock master and that starts the variable clock unit at a predetermined center frequency when the reception buffer amount stored in the reception buffer of the master channel reaches a predetermined center value. A master synchronization control unit;
With
The slave converter is
A variable clock unit capable of variably controlling the frequency of the output clock signal;
A transmission conversion unit that distributes the multi-frame data received from the synchronous multiplex communication device and accumulates it in each transmission buffer, generates asynchronous data from the accumulated data in the transmission buffer at regular intervals, and transmits the asynchronous data to the asynchronous communication network;
Asynchronous data received from the asynchronous communication network is distributed and stored in each reception buffer, and multiframe data is generated from the data stored in the reception buffer in synchronization with the clock signal of the variable clock unit. A receiving converter for transmitting to the device;
It becomes effective in the setting state of the clock slave, and when the reception buffer amount accumulated in the reception buffer of the master channel reaches a predetermined center value, the variable clock unit is set to the center frequency and started. A clock slave synchronization control unit that controls the clock frequency of the variable clock unit so as to stabilize the reception buffer amount at the center value, and synchronizes the clock with another conversion device in the setting state of the clock master;
A communication system comprising: (8)

(Appendix 19) (Startup process)
In the communication system according to attachment 18, the reception conversion unit includes:
When the power is turned on, the reception buffer for all channels is cleared and multi-frame data with all channels as no-signal data is generated to start synchronous transmission to the synchronous multiplex communication device. After the synchronous transmission starts, the reception buffer A communication system characterized by switching from a channel whose amount reaches a predetermined center value to reading and transmitting data accumulated in a reception buffer.

(Supplementary note 20) (Start-up process at the time of error recovery)
In the communication system according to attachment 18, the reception conversion unit includes:
When the master channel abnormality is recovered during operation, the reception buffer of all channels is cleared and multi-frame data with all channels as no-signal data is generated to start synchronous transmission to the synchronous multiplex communication device. , After the start of synchronous transmission, switching from the channel in which the reception buffer amount has reached a predetermined center value to reading transmission of buffer accumulated data,
At the time of start-up when an error of a channel other than the master channel is recovered during operation, the reception buffer of the error recovery channel is cleared and non-signal data is included in multiframe data to be transmitted synchronously to the synchronous multiplex communication device, and the error A communication system characterized by switching to reading and transmission of buffer accumulated data when the reception buffer amount of the recovery channel reaches the reception buffer amount of the master channel.

Explanatory drawing of the communication system using the synchronous asynchronous communication conversion apparatus of this invention The block diagram of the functional structure which showed embodiment of the synchronous asynchronous communication converter by this invention Explanatory drawing of the hardware environment of the computer where the conversion program of this embodiment is executed Explanatory drawing of the channel management table stored in six legacy IP converters of FIG. Explanatory diagram of channel distributed transmission in the six legacy IP converters of FIG. The block diagram which showed the functional structure by taking out the legacy IP converter set to the clock master and clock slave of FIG. Time chart showing clock slave synchronization control of this embodiment when the amount of reception buffer increases at startup Time chart showing the clock slave synchronization control of this embodiment when the amount of reception buffer decreases at startup A flowchart showing an outline of conversion processing according to this embodiment. The flowchart which showed the clock master transmission conversion process of this embodiment The flowchart which showed the clock master reception conversion process of this embodiment The flowchart which showed the detail of the startup process in step S2 of FIG. The flowchart which showed the detail of the startup process at the time of abnormality recovery in step S6 of FIG. The flowchart which showed the clock slave transmission conversion process of this embodiment The flowchart which showed the clock slave reception conversion process of this embodiment The flowchart which showed the detail of the clock synchronous control process in FIG.15 S4

Explanation of symbols

10, 10-1 to 10-6: Legacy multiplex transmission apparatus 11-1, 11-2: Synchronous communication network 12, 12-1 to 12-6: Legacy IP converters 14-1 to 14-6: Legacy network 15 : Asynchronous communication networks 16-1 to 16-6: LAN
18: IP network 20, 20-1 to 20-3: legacy interface unit 22, 22-1 to 22-3: IP interface unit 24: transmission buffer group 26: packet assembly group 28: packet decomposition group 30: reception buffer group 32, 32-1, 32-2: Variable clock units 34, 34-1, 34-2: Control units 36, 36-1, 36-2: Master / slave setting unit 38: Transmission conversion unit 40: Reception conversion unit 42 : Clock master synchronization control unit 44: Clock slave synchronization control unit 46, 46-1, 46-2: Startup unit 48, 48-1, 48-2: Abnormal startup unit 50-1 to 50-6: Channel management table 54: CPU
56: Bus 58: RAM
60: ROM
62: Buffer fluctuation tolerance

Claims (8)

Inserted and connected between a synchronous multiplex communication apparatus that transmits multi-channel data of a plurality of channels in synchronization with a clock signal and an asynchronous communication network composed of devices that transfer data asynchronously. In a synchronous asynchronous communication network conversion device that transfers data between
A clock master is set for a specific conversion device among a plurality of conversion devices, a clock slave is set for the remaining conversion devices, and one specific channel among the assigned channels of the conversion devices set as the clock master is clocked. A master / slave setting unit for setting the master channel for synchronous control;
A variable clock unit capable of variably controlling the frequency of the output clock signal;
A transmission conversion unit that distributes the multi-frame data received from the synchronous multiplex communication device and accumulates it in each transmission buffer, generates asynchronous data from the accumulated data in the transmission buffer at regular intervals, and transmits the asynchronous data to the asynchronous communication network;
Asynchronous data received from the asynchronous communication network is distributed and stored in each reception buffer, and multiframe data is generated from the data stored in the reception buffer in synchronization with the clock signal of the variable clock unit. A receiving converter for transmitting to the device;
A clock that is valid in the setting state of the clock master and that starts the variable clock unit at a predetermined center frequency when the reception buffer amount stored in the reception buffer of the master channel reaches a predetermined center value. A master synchronization control unit;
It becomes effective in the setting state of the clock slave, and when the reception buffer amount accumulated in the reception buffer of the master channel reaches a predetermined center value, the variable clock unit is set to the center frequency and started. A clock slave synchronization control unit that controls the clock frequency of the variable clock unit so as to stabilize the reception buffer amount at the center value, and synchronizes the clock with another conversion device in the setting state of the clock master;
A conversion device comprising:
2. The conversion device according to claim 1, wherein the reception conversion unit generates multi-frame data by clearing the reception buffers of all the channels and setting all the channels as no-signal data at the time of start-up upon power-on. A conversion device, wherein synchronous transmission is started to a synchronous multiplex communication device, and after the synchronous transmission is started, switching is performed from a channel whose reception buffer amount has reached a predetermined center value to reading and transmission of data accumulated in the reception buffer.
2. The conversion device according to claim 1, wherein the reception conversion unit is configured to clear a reception buffer of all channels and to set all channels to non-signal data when the master channel abnormality is recovered during operation. A conversion device characterized in that it generates frame data and starts synchronous transmission to the synchronous multiplex communication device, and after the synchronous transmission is started, the channel whose reception buffer amount has reached a predetermined center value is switched to read transmission of buffer accumulated data. .
2. The conversion device according to claim 1, wherein the reception conversion unit clears the reception buffer of the error recovery channel and multi-receives no-signal data at the time of start-up when an error of a channel other than the master channel is recovered during operation. A conversion characterized in that it is included in frame data and synchronously transmitted to the synchronous multiplex communication device, and when the reception buffer amount of the error recovery channel reaches the reception buffer amount of the master channel, switching is performed to read transmission of buffer accumulated data. apparatus.
The conversion device according to claim 1, wherein the clock slave synchronization control unit includes:
If the receive buffer amount exceeds the upper limit of the allowable range of buffer fluctuation after starting the clock frequency from the center frequency, it is changed to a predetermined maximum adjustment frequency, and the maximum adjustment is made when the receive buffer amount returns to the center value after the change. The process of changing the frequency to a frequency obtained by adding a predetermined offset frequency to the center frequency is repeated while sequentially increasing the offset frequency,
When the reception buffer amount falls below the lower limit value of the buffer fluctuation allowable range after starting the clock frequency from the center frequency, it is changed to a predetermined minimum adjustment frequency, and when the reception buffer amount returns to the center value after the change, the minimum A conversion device characterized by repeating the process of changing the adjustment frequency to a frequency obtained by subtracting a predetermined offset frequency from the center frequency while increasing the offset frequency sequentially.
Inserted and connected between a synchronous multiplex communication apparatus that transmits multi-channel data of a plurality of channels in synchronization with a clock signal and an asynchronous communication network composed of devices that transfer data asynchronously. In the conversion method of the conversion device for transferring data between,
A clock master is set for a specific conversion device among a plurality of conversion devices, a clock slave is set for the remaining conversion devices, and one specific channel among the assigned channels of the conversion devices set as the clock master is clocked. Master / slave setting step for setting the master channel for synchronous control,
A transmission conversion step of distributing multi-frame data received from the synchronous multiplex communication device to each transmission buffer and storing it in each transmission buffer, generating asynchronous data from the storage data in the transmission buffer at regular intervals, and transmitting it to the asynchronous communication network;
Asynchronous data communication apparatus that receives asynchronous data distributed in channels from the asynchronous communication network and stores the asynchronous data in each reception buffer, and generates multi-frame data from the data stored in the reception buffer in synchronization with the clock signal of the variable clock unit. A receiving conversion step to send to
A clock that is valid in the setting state of the clock master and that starts the variable clock unit at a predetermined center frequency when the reception buffer amount stored in the reception buffer of the master channel reaches a predetermined center value. A master synchronization control step;
It becomes effective in the setting state of the clock slave, and when the reception buffer amount accumulated in the reception buffer of the master channel reaches a predetermined center value, the variable clock unit is set to the center frequency and started. A clock slave synchronization control step of controlling the clock frequency of the variable clock unit to stabilize the reception buffer amount at the center value, and clock-synchronizing with another conversion device in the setting state of the clock master;
A conversion method characterized by comprising:
Inserted and connected between a synchronous multiplex communication apparatus that transmits multi-channel data of a plurality of channels in synchronization with a clock signal and an asynchronous communication network composed of devices that transfer data asynchronously. To the computer of the conversion device that transfers data between
A clock master is set for a specific conversion device among a plurality of conversion devices, a clock slave is set for the remaining conversion devices, and one specific channel among the assigned channels of the conversion devices set as the clock master is clocked. Master / slave setting step for setting the master channel for synchronous control,
A transmission conversion step of distributing multi-frame data received from the synchronous multiplex communication device to each transmission buffer and storing it in each transmission buffer, generating asynchronous data from the storage data in the transmission buffer at regular intervals, and transmitting it to the asynchronous communication network;
Asynchronous data communication apparatus that receives asynchronous data distributed in channels from the asynchronous communication network and stores the asynchronous data in each reception buffer, and generates multi-frame data from the data stored in the reception buffer in synchronization with the clock signal of the variable clock unit. A receiving conversion step to send to
A clock that is valid in the setting state of the clock master and that starts the variable clock unit at a predetermined center frequency when the reception buffer amount stored in the reception buffer of the master channel reaches a predetermined center value. A master synchronization control step;
It becomes effective in the setting state of the clock slave, and when the reception buffer amount accumulated in the reception buffer of the master channel reaches a predetermined center value, the variable clock unit is set to the center frequency and started. A first clock slave synchronization control step of controlling the clock frequency of the variable clock unit so as to stabilize the reception buffer amount at the center value and clock-synchronizing with another conversion device in the setting state of the clock master;
A program characterized by having executed.
A synchronous multiplex communication device that transfers multi-frame data of multiple channels in synchronization with a clock signal is set to a clock master that is connected to an asynchronous communication network composed of devices that transfer data asynchronously. A master conversion device in which one channel is set as a master channel;
A slave conversion device set as a clock slave for connecting another synchronous multiplex communication device to the asynchronous communication network;
In a communication system for transferring data between the plurality of synchronous multiplex communication devices,
The clock master device is
A variable clock unit capable of variably controlling the frequency of the output clock signal;
A transmission conversion unit that distributes the multi-frame data received from the synchronous multiplex communication device and accumulates it in each transmission buffer, generates asynchronous data from the accumulated data in the transmission buffer at regular intervals, and transmits the asynchronous data to the asynchronous communication network;
Asynchronous data received from the asynchronous communication network is distributed and stored in each reception buffer, and multiframe data is generated from the data stored in the reception buffer in synchronization with the clock signal of the variable clock unit. A receiving converter for transmitting to the device;
A clock that is valid in the setting state of the clock master and that starts the variable clock unit at a predetermined center frequency when the reception buffer amount stored in the reception buffer of the master channel reaches a predetermined center value. A master synchronization control unit;
With
The slave converter is
A variable clock unit capable of variably controlling the frequency of the output clock signal;
A transmission conversion unit that distributes the multi-frame data received from the synchronous multiplex communication device and accumulates it in each transmission buffer, generates asynchronous data from the accumulated data in the transmission buffer at regular intervals, and transmits the asynchronous data to the asynchronous communication network;
Asynchronous data received from the asynchronous communication network is distributed and stored in each reception buffer, and multiframe data is generated from the data stored in the reception buffer in synchronization with the clock signal of the variable clock unit. A receiving converter for transmitting to the device;
It becomes effective in the setting state of the clock slave, and when the reception buffer amount accumulated in the reception buffer of the master channel reaches a predetermined center value, the variable clock unit is set to the center frequency and started. A clock slave synchronization control unit that controls the clock frequency of the variable clock unit so as to stabilize the reception buffer amount at the center value, and synchronizes the clock with another conversion device in the setting state of the clock master;
A communication system comprising:

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