JP2007235217A - Synchronization/asynchronization converter and clock control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a synchronization/asynchronization converter capable of error-freely connecting a synchronous transmitter such as SDH (synchronous digital hierarchy), SONET (synchronous optical network) via an asynchronous transmission network such as a LAN network without providing a dedicated clock line, and to provide a clock control method. <P>SOLUTION: The converter is provided with a transmission processing section for outputting data received from the synchronous transmission network to the asynchronous transmission network; a reception processing section for outputting the data received from the asynchronous transmission network to the synchronous transmission network via a buffer; a buffer monitoring means for monitoring the increase/decrease in the utilization quantity of the buffer; and a clock control means for varying a clock to be read from the buffer depending on an output of the buffer monitoring means. The buffer control means accelerates the clock to be read from the buffer when the buffer utilization quantity increases, and delays the clock to be read from the buffer when the buffer utilization quantity decreases. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a synchronous / asynchronous conversion apparatus and a clock control method for connecting an SDH / SONET apparatus, which is a synchronous transmission apparatus, via a LAN (Local Area Network) network.

In recent years, the Internet has spread rapidly, and it is common to construct a WAN (Wide Area Network) by interconnecting LANs in an office using IP (Internet Protocol) packets. The IP packet used in the LAN is asynchronous communication defined in IEEE 802.3, but is an international standard defined by ITU-T (International Telecommunication Union) for a dedicated line of a communication carrier connecting between LANs. Synchronous transmission systems such as SDH (Synchronous Digital Hierarchy) or the US standard SONET (Synchronous Optical NETwork) are used. (See ITU-T recommendation G series of Non-Patent Document 1)
On the other hand, with the spread of the Internet, an increasing number of telecommunications carriers provide LAN network services that allow WANs to be constructed by connecting LANs as they are with IP packets. In particular, compared to conventional services such as SDH / SONET, where the fee structure varies depending on the distance between the bases, wide-area LAN network services are cheaper, and there is a fixed price regardless of the distance within the service area. The benefits are growing. Furthermore, the equipment investment cost is often cheaper for the LAN-compatible equipment, which is more popular than the equipment for the synchronous network.

As described above, while there are existing dedicated line services such as SDH / SONET, inexpensive LAN network services (such as wide area LAN networks) are rapidly spreading, and asynchronous LAN networks are replacing the existing synchronous communication networks. There is a need for a system that uses the above in a pseudo manner.
FIG. 11A shows a communication system that connects an SDH apparatus 751 and an SDH apparatus 755 via a general SDH / SONET transmission line 901. The SDH device 751 is supplied with a synchronization clock from the master CLK 756, and the synchronization clock is sent to the SDH device 755 via the SDH / SONET transmission line 901 together with the transmission data. The SDH device 755 is a synchronization clock received from the SDH / SONET transmission line 901. Operate and communicate with each other.

However, if an SDH device is to be connected via an inexpensive LAN network 753 without using the SDH / SONET transmission line 901, a synchronous / asynchronous conversion device (SoE device) is obtained as shown in FIG. Necessary. Here, SoE is an abbreviation for SDH / SONET over Ethernet (registered trademark), and is a conversion device that enables an SDH transmission apparatus to communicate via a LAN network 753. In the figure, SDH data input / output by the SDH transmission device 751 is converted into a LAN packet by the SoE device 757 and connected to the communication destination SoE device 758 via the LAN network 753. The SoE device 758 converts a LAN packet to be transmitted / received into SDH data and inputs / outputs it to / from the SDH transmission device 755. However, although the SDH transmission device 751 and the SoE device 757 are supplied with a master clock serving as a reference from the master CLK 756, since the LAN network 753 is an asynchronous communication network and clock transmission is not performed, a separate dedicated clock line is prepared. Thus, a synchronous clock is supplied to the communication destination SoE device 758 and the SDH transmission device 755.
ITU-T recommendation G series standard (G.774 series)

  However, ITU-T Recommendation G. As described in the 774 series, a transmission apparatus connected to SDH / SONET or the like needs to receive a synchronous clock from the network side and transmit / receive data in synchronization therewith. On the other hand, in the LAN network, burst communication or the like for placing data on the physical layer is performed only when information is sent, and it is not necessary to always transmit a synchronous clock. For this reason, in order to connect an existing SDH / SONET device to the LAN network, a separate transmission path for transmitting a clock for operating the SDH / SONET device is required. In order to use the LAN network, a dedicated clock line is used. However, there is a problem that the cost becomes high.

In addition, when data is transmitted through the LAN network, the arrival time of the packet differs depending on the packet transmission path and the like, so that there is a difference between the data interval on the transmission side and the data interval on the reception side. When such fluctuations become large, it becomes impossible to cope with them and a data error occurs.
In view of the above, an object of the present invention is to provide a synchronous / asynchronous connection that can connect a synchronous transmission device such as an SDH / SONET device without error via an asynchronous transmission network such as a LAN network without providing a dedicated clock line. A conversion device and a clock control method are provided.

  The invention according to claim 1 is a synchronous / asynchronous conversion apparatus for connecting a synchronous transmission network not having a master clock and an asynchronous transmission network, and transmitting the data received from the synchronous transmission network to the asynchronous transmission network A reception processing unit that outputs data received from the asynchronous transmission network to the synchronous transmission network via a buffer, a buffer monitoring unit that monitors increase / decrease in the buffer usage, and an output of the buffer monitoring unit Clock control means for varying the clock read from the buffer, the clock control means speeds up the clock read from the buffer when the buffer usage increases, and the clock usage when the buffer usage decreases. The clock read from the buffer is delayed.

  According to a second aspect of the present invention, in a synchronous / asynchronous conversion apparatus for connecting a synchronous transmission network not having a master clock and an asynchronous transmission network, a transmission process for outputting data received from the synchronous transmission network to the asynchronous transmission network A reception processing unit that outputs data received from the asynchronous transmission network to the synchronous transmission network via a buffer, and a buffer monitoring unit that monitors increase and decrease of the buffer usage. Furthermore, an apparatus clock control unit for supplying a clock read from the buffer according to the output of the buffer monitoring means is provided.

According to a third aspect of the present invention, in the synchronous / asynchronous conversion device according to the first or second aspect, the buffer monitoring unit causes the device clock control unit to quickly increase the clock when the buffer usage increases. When the buffer usage decreases, the output is output to the device clock control unit so as to delay the clock immediately.
According to a fourth aspect of the present invention, in the synchronous / asynchronous conversion device according to the first or second aspect, a statistical processing unit is provided in the device clock control unit, and the statistical processing unit receives information output from the buffer monitoring unit. Statistical processing is performed during a predetermined period, and the speed of the clock output from the device clock control unit is increased or decreased according to the result of the statistical processing.

  According to a fifth aspect of the present invention, in the synchronous / asynchronous conversion device according to the first or second aspect, when the buffer usage amount approaches the full capacity of the buffer capacity, the buffer monitoring unit is configured to control the apparatus clock control unit. The clock is output so as to increase the speed, and when the buffer usage approaches zero, the clock is output to the apparatus clock control section so as to delay the clock.

According to a sixth aspect of the present invention, in the synchronous / asynchronous conversion device according to the first or second aspect, when the buffer usage amount overflows, the buffer monitoring means outputs to the device clock control unit to speed up the clock. When the buffer usage amount underflows, the device clock control unit outputs the clock so as to be delayed.
The invention according to claim 7 is a first synchronous / asynchronous converter connected to a synchronous transmission network having a master clock, and a second synchronous / asynchronous converter connected to a synchronous transmission network not having a master clock, In the synchronous / asynchronous conversion apparatus for connecting the first synchronous / asynchronous conversion apparatus via the asynchronous transmission network, the first synchronous / asynchronous conversion apparatus receives the received frame from the second synchronous / asynchronous conversion apparatus, and the timing packet generation / transmission means The second synchronous / asynchronous conversion device is provided with timing packet receiving means and clock control means for controlling a clock for outputting data to the synchronous transmission network not having the master clock. The received frame monitoring means transmits the number of frames transmitted in a unit time periodically transmitted to the second synchronous / asynchronous conversion device by the timing packet generating and transmitting means, and the timing packet receiving means comprises: The received timing packet information is output to the clock control means, and the clock control means slows the clock when the number of frames in a unit time is large, and speeds up the clock when the number of frames in a unit time is small. It is characterized by that.

  The invention according to claim 8 is the clock control method of the synchronous / asynchronous conversion apparatus for connecting the synchronous transmission network not having the master clock and the asynchronous transmission network, and the data received from the synchronous transmission network is transferred to the asynchronous transmission network. A transmission processing unit for outputting, a reception processing unit for outputting data received from the asynchronous transmission network to the synchronous transmission network via a buffer, a buffer monitoring unit for monitoring an increase or decrease in the buffer usage, and the buffer monitoring unit The apparatus clock control unit that supplies a clock to be read from the buffer according to the output of the buffer and the statistical processing unit are provided in the apparatus clock control unit. Here, the statistical processing unit performs statistical processing on information output from the buffer monitoring unit in a predetermined period, and according to a result of the statistical processing, a speed of a clock output from the device clock control unit. It controls to increase / decrease.

  The invention according to claim 9 is the clock control method of the synchronous / asynchronous conversion device according to claim 8, wherein the buffer monitoring means speeds up the clock to the device clock control unit when the buffer usage amount overflows. When the buffer usage amount underflows, the device clock control unit outputs the clock so as to delay the clock.

  The synchronous / asynchronous conversion apparatus and the clock control method according to the present invention include a synchronous / asynchronous conversion without a master clock connected via an asynchronous transmission network from a synchronous / asynchronous conversion apparatus connected to a synchronous transmission network having a master clock. The apparatus can always follow the clock of the synchronous transmission network having the master clock, and transmission errors due to buffer overflow and underflow can be prevented. In addition, the influence of fluctuations generated in the asynchronous transmission network can be reduced by controlling the buffer.

  As a result, the existing SDH / SONET apparatus can be used as it is in a wide-area LAN network, and the equipment cost and communication cost can be reduced.

  An embodiment of the synchronous / asynchronous conversion apparatus and clock control method according to the present invention will be described. First, the configuration of the entire communication system using the synchronous / asynchronous conversion apparatus will be described with reference to FIG. Note that the configuration shown in the figure is common to all the embodiments. In the figure, reference numeral 751 denotes an SDH transmission apparatus or SDH / SONET network, 752 a synchronous / asynchronous conversion apparatus (SoE apparatus) having a master clock, 753 a LAN network which is an asynchronous communication network, and 754 an SoE apparatus having no master clock. , 755 denotes an SDH transmission apparatus or SDH / SONET network, and 756 denotes a master CLK.

  The SDH transmission device 751 and the SoE device 752 on the side having the master CLK 756 are supplied with the master clock from the master CLK 756 and operate in accordance with this synchronization timing. However, since the master clock is not supplied to the SDH transmission device 755 and the SoE device 754 on the side that does not have the master clock, the SoE device 754 must supply a synchronization clock to the SDH transmission device 755. The first to sixth embodiments described below relate to an SoE device 754 that does not have a master clock.

(First embodiment)
FIG. 1 is a block diagram showing the configuration of the SoE device 101 according to the first embodiment of the present invention. The SoE device 101 monitors a clock processing system that extracts a clock from a received LAN frame and controls the device, and a buffer that accumulates SDH data decomposed from the received LAN frame independently of the clock processing system. A dedicated PLL for controlling the reading speed is provided, and the main signal processing system feeds back to the PLL so that the read amount of the buffer becomes constant.

In the figure, reference numeral 102 denotes a main signal processing unit constituting the SoE apparatus 101, and 103 denotes information for controlling the clock speed from either received packet information or buffer information output from the main signal processing unit 102. A CLK extraction unit 104 is a CLK unit that supplies a clock to each unit in the SoE device 101.
In the CLK unit 104, 121 indicates a REF generation unit, 122 indicates a PLL, and 123 indicates a CLK distribution unit that distributes and supplies a clock in the apparatus. The REF generation unit 121 generates a reference clock according to information that controls the speed of the clock output from the CLK extraction unit 103. The PLL 122 performs a PLL operation with the reference clock output from the REF generation unit 121 and generates a clock with a VCO (not shown). The clock generated by the PLL 122 is supplied to a necessary place in the apparatus by the CLK distribution unit 123.

  In the main signal processing unit 102, reference numeral 106 denotes a LAN terminator for receiving received packet data 105 from the LAN network, 107 denotes a received packet processor for processing the LAN packet received by the LAN terminator 106 in accordance with IEEE 802.3, and 108 Capsule separation / SDH sending unit 109 disassembles the LAN packet and extracts and transmits the encapsulated SDH data, and 109 temporarily holds the SDH data separated from the capsule so that the capsule separation / SDH sending unit 108 matches the sending timing. A buffer 110 is an SDH / TDM termination unit that outputs time-division multiplexed (TDM) SDH data to an externally connected SDH / SONET transmission apparatus or SDH / SONET network. Received packet data 105 received from the LAN network is processed in the order of LAN termination unit 106, received packet processing unit 107, capsule separation / SDH transmission unit 108, and SDH / TDM termination unit 110, and converted into SDH data.

  Reference numeral 111 denotes an SDH / SODM transmission unit or an SDH / SODM network (not shown) connected to an SDH / SODM network (not shown), and an SDH / TDM terminal unit 112 inputs the input SDH data according to the IEEE 802.3 standard. An SDH reception / encapsulation unit that encapsulates packets, a transmission packet processing unit 113 that transmits encapsulated LAN packets, and a LAN termination unit that transmits transmission packet data 115 to the LAN network. The SDH / TDM terminators 110 and 111 are portions for interfacing with the SDH physical layer, and the LAN terminators 106 and 114 are portions for interfacing with the LAN physical layer. The SDH data input from the SDH / SONET apparatus is processed in the order of the SDH / TDM termination unit 110, the SDH reception / encapsulation unit 112, the transmission packet processing unit 113, and the LAN termination unit 114, and converted into LAN packet data. In this manner, SDH data transmitted / received to / from the SDH / SONET transmission apparatus or the SDH / SONET network can be converted into LAN packet data and transmitted / received via the LAN network.

  Next, a clock processing method will be described. In the main signal processing unit 102, 116 is a buffer monitoring unit, 117 is a CLK fluctuation extraction unit, 118 is a frequency correction unit, 119 is a REF generation unit, and 120 is a PLL. When reading the SDH data stored in the buffer 109, the capsule separation / SDH sending unit 108 reads the SDH data in synchronization with the clock output from the PLL 120, and outputs it to the SDH / SONET network via the SDH / TDM termination unit 110. .

  Here, generation of a reference clock used by the PLL 120 will be described. The buffer monitoring unit 116 constantly monitors the buffer usage of the buffer 109 and outputs the buffer usage to the CLK fluctuation extraction unit 117. The CLK fluctuation extraction unit 117 instructs the frequency correction unit 118 to increase the clock frequency when the buffer usage exceeds a predetermined value, and conversely, the buffer usage is predetermined. When the value is smaller than the value, the frequency correction unit 118 is instructed to delay the clock frequency. The frequency correction unit 118 adjusts the in-device clock output from the CLK unit 104 by increasing or decreasing the frequency according to the instruction from the CLK fluctuation extraction unit 117, and outputs the adjusted clock to the REF generation unit 119. The REF generation unit 119 generates a reference clock for the PLL 120 by, for example, dividing the clock input from the frequency correction unit 118. In this way, the main signal processing unit 102 can control so that the amount of use of the buffer 109 does not increase or decrease too much.

  As described above, in the first embodiment, the SoE device 101 performs the buffer monitoring by the main signal processing unit 102 independently of the clock system that extracts the CLK and supplies the clock to the device, and only reads the buffer. The PLL 120 is provided to control the reading speed of the buffer 109. Therefore, fine control independent of the clock system can be performed by feeding back to the PLL 120 so that the amount of use of the buffer 109 becomes constant. As a result, even when connected to a synchronous SONET / SDH transmission network having a master clock via a LAN that is an asynchronous network, it is possible to perform error-free communication without being affected by a clock shift or LAN network fluctuation. be able to.

(Second Embodiment)
Next, a second embodiment of the synchronous / asynchronous conversion apparatus according to the present invention will be described with reference to FIG. The difference from the first embodiment is that the main signal processing unit 102 of the SoE device 200 does not have the frequency correction unit 118, the REF generation unit 119, and the PLL 120 of FIG. 1, and the output of the CLK fluctuation extraction unit 117 is CLK. It is in the part 104. In addition, a frequency correction unit 201 is newly provided in the CLK unit 104, and an output of the CLK fluctuation extraction unit 117 of the main signal processing unit 102 is input to the frequency correction unit 201. That is, in the first embodiment, the control of the read clock of the buffer 109 that is independently performed by the main signal processing unit 102 is also used by the CLK unit 104. Since other parts are the same as those in the first embodiment, description thereof is omitted here.

  In FIG. 2, the CLK fluctuation extraction unit 117 that has received the usage status of the buffer 109 from the buffer monitoring unit 116 has a buffer usage amount higher than a predetermined value as in the case of the first embodiment. When the number is increased, the frequency correction unit 201 is instructed to increase the clock frequency, and conversely, when the buffer usage amount is smaller than a predetermined value, the frequency correction unit 201 is delayed so as to delay the clock frequency. Instruct. The frequency correction unit 201 of the CLK unit 104 increases or decreases the frequency output from the clock generator (not shown) in the apparatus according to the instructions of both the CLK fluctuation extraction unit 117 and the CLK extraction unit 103. And adjust the result to output to the REF generation unit 121. The REF generation unit 121 generates a reference clock for the PLL 122 by, for example, dividing the clock input from the frequency correction unit 201. The PLL 122 outputs a clock having a frequency locked to the reference clock to the CLK distribution unit 123, and the clock is supplied from the CLK distribution unit 123 to each unit in the SoE device 200.

  As described above, in the second embodiment, the SoE device 200 can monitor the buffer by the main signal processing unit 102 and can control the read clock of the buffer 109 using the clock system of the CLK unit 104. Therefore, even when connected to a synchronous SONET / SDH transmission network having a master clock through a LAN network which is an asynchronous network, it can be fed back to the PLL 122 so that the amount of use of the buffer 109 becomes constant. It is possible to perform error-free communication without being affected by fluctuations in the LAN network.

(Third embodiment)
Next, a third embodiment of the synchronous / asynchronous conversion apparatus according to the present invention will be described with reference to FIG. This figure mainly depicts the configuration of the CLK extraction unit 103, where 301 indicates a frame count parameter table, 302 indicates a reception frame rate statistical processing unit, and 303 indicates a frame count unit. Note that the SoE device of this embodiment may have any of the configurations shown in FIGS. 1 and 2 described in the first and second embodiments.

  In FIG. 3, information regarding the reception packet interval (the number of received frames per unit time) output from the reception packet processing unit 107 of the main signal processing unit 102 is input to the reception frame rate statistical processing unit 302 and the frame count unit 303. . The reception frame rate statistical processing unit 302 selects a time for counting the number of received frames from the frame count parameter table 301 according to the reception packet interval input from the reception packet processing unit 107. For example, when the number of received frames per unit time is larger or smaller than a predetermined value, the time for counting received frames is shortened. Conversely, when the number of received frames per unit time is close to a predetermined value, Is selected and the frame count unit 303 is instructed. Receiving this, the frame count unit 303 outputs the counted value to the CLK unit 104, and the CLK unit 104 controls the clock to be faster or slower according to this count value, and sends the clock to each unit in the apparatus. Supply.

  Next, the flow of the clock control process will be described using a flowchart. The flowchart of FIG. 4 shows the processing of the reception frame rate statistical processing unit 302 and the frame count unit 303 in the CLK extraction unit 103 of FIG. 3 and the processing of the CLK unit 104.

  4, S101 is a process start, S102 is a received frame information input process, S103 is a received frame information storage process, S104 is a parameter selection process, S105 is a frame count process, S106 is a count value output process, and S107 is a count comparison process. , S108 indicates a process for increasing the clock frequency, S109 indicates a process for decreasing the clock frequency, and S110 indicates the end of the process. Note that steps S102 to S104 show processing of the reception frame rate statistical processing unit 302, steps S105 and S106 show processing of the frame count unit 303, and steps S107 to S109 show processing of the CLK unit 104, respectively.

  When processing is started in step S101, the number of received frames per unit time is input from the received packet processing unit 107 of the main signal processing unit 102 in step S102. In step S103, the number of received frames per unit time input in step S102 is stored in the past frame rate data storage unit 401. In step S104, a rate change rate is calculated from the current number of received frames per unit time output in step S103 and the past number of received frames per unit time stored in the past frame rate data storage unit 401. A count parameter corresponding to the rate change rate calculated from the frame count parameter table 301 is extracted. Here, the frame count parameter table 301 stores a table as indicated by reference numeral 305.

  For example, the table 305 shows that the count parameter is 1 hour when the rate change rate is less than 3%, the count parameter is 30 minutes when the rate change rate is 3% or more and less than 10%, and the rate change rate is 10% or more and 30%. If it is less than 10 minutes, the count parameter is 10 minutes, if the rate change rate is 30% or more and less than 50%, the count parameter is 1 minute, if the rate change rate is 50% or more, the count parameter is 1 second, etc. The rate is associated with the count parameter. In step S104, when referring to past frame rate data stored in the past frame rate data storage unit 401, an average value for a predetermined period in the past, for example, several days or months is referred to. You may be made to refer to it by dividing into daytime and nighttime. It is characterized by statistically processing past frame rate data.

  Next, the processing proceeds to the frame count unit 303. In step S105, the number of received frames is counted based on the count parameter selected in step S104. For example, if the frame count parameter is 1 minute, the number of received frames per minute is counted. In step S106, the number of received frames (count value) counted in the predetermined time in step S105 is output to the CLK unit 104.

  Next, the process proceeds to the processing of the CLK unit 104. In step S107, the count value output in step S106 is compared with the preset reference value. When it is larger than the reference value, that is, when the number of received frames within a predetermined time is large, the process proceeds to step S108. If it is smaller than the reference value, that is, if the number of received frames in the predetermined time is small, the process proceeds to step S109. In step S108, processing is performed to increase the clock frequency. In step S109, processing is performed to lower the clock frequency. In step S110, a series of clock frequency control ends.

  As described above, when the number of received frames within a predetermined time is large, the clock frequency is increased so that the received frames are not accumulated in the buffer 109. When the number of received frames within the predetermined time is small, the clock frequency is increased. Since the received frame of the buffer 109 is processed so as not to be insufficient, overflow and underflow of the buffer 109 can be prevented, and data can be always stably converted from the LAN network to the SDH / SONET network. it can. In particular, in step S105, since the time for counting received frames is changed according to the rate change rate, when the number of received frames per unit time changes suddenly, the count parameter becomes small, and tracking in a short time is possible. It becomes possible. Conversely, when the number of received frames per unit time hardly changes, the count parameter is increased and counting is performed for a long time, so that it is possible to cope with a subtle change over a long time such as wander.

(Fourth embodiment)
Next, a fourth embodiment of the synchronous / asynchronous conversion apparatus according to the present invention will be described. The block diagram of the fourth embodiment is the same as that of FIG. 3 of the third embodiment, and a description thereof will be omitted. The third embodiment is different from the third embodiment in the part relating to the flow of the clock control process, which will be described with reference to a flowchart. The flowchart of FIG. 5 shows the processing of the reception frame rate statistical processing unit 302 and the frame count unit 303 in the CLK extraction unit 103 of FIG. 3 and the processing of the CLK unit 104. Moreover, the part shown with the same code | symbol as 3rd Embodiment shows the same process.

  In FIG. 5, step S603 indicates a process for calculating a frame rate per unit time, and S604 indicates a process for selecting a frame count parameter based on a rate change rate. Instead of statistically processing past frame rate data as in the third embodiment, the rate change rate is calculated by simply comparing the received frame rate calculated in step S603 with a preset reference value. . A count parameter corresponding to the calculated rate change rate is selected from the table 305 of the frame count parameter table 301. The parts processed by the frame count unit 303 and the CLK unit 104 are the same as those in the third embodiment.

  As described above, when the rate of change of the reception frame rate is large, the clock frequency is increased so that the received frames are not accumulated in the buffer 109. When the rate of change of the reception frame rate is small, the clock frequency is decreased. Thus, processing is performed so that the data in the buffer 109 is not insufficient. In this way, overflow and underflow of the buffer 109 are prevented, and data can be converted from the LAN network to the SDH / SONET network constantly and stably.

In the block diagram of FIG. 3, the clock control process of FIG. 4 of the third embodiment and the clock control process of FIG. 5 of the fourth embodiment can be selected, and the operation according to the use situation is performed. It is also possible to make it.
(Fifth embodiment)
Next, a fifth embodiment of the synchronous / asynchronous conversion apparatus according to the present invention will be described. FIG. 6 is basically the same as FIG. 3 of the third embodiment, and is a diagram mainly illustrating the configuration of the CLK extraction unit 103. In addition, the SoE device of this embodiment may have any of the configurations shown in FIGS. 1 and 2 described in the first and second embodiments. The difference from the third embodiment is that a CLK extraction parameter processing unit 702 is arranged instead of the reception frame rate statistical processing unit 302 in the CLK extraction unit 103 in FIG. 3 and a buffer of the main signal processing unit 102. The output of the monitoring unit 116 is input to the CLK extraction parameter processing unit 702.

  In FIG. 6, the CLK extraction parameter processing unit 702 receives the usage amount (or remaining amount) of the buffer 109 from the buffer monitoring unit 116 of the main signal processing unit 102, and receives the number of received frames from the frame count parameter table 301 according to the usage amount. Select the time to count. For example, the CLK extraction parameter processing unit 702 selects a frame count parameter that shortens the time for counting received frames when the usage amount of the buffer 109 is larger or smaller than a preset range. Is within the preset range, a frame count parameter for increasing the time for counting the received frames is selected and the frame count unit 303 is instructed. Receiving this, the frame counting unit 303 outputs the value obtained by counting the received frames of the received packet processing unit 107 to the CLK unit 104, and the CLK unit 104 controls the speed of the clock according to this count value, and the SoE. A clock is supplied to each part in the apparatus.

Next, the flow of the clock control process will be described using a flowchart. The flowchart of FIG. 7 shows the processing of the CLK extraction parameter processing unit 702 and the frame count unit 303 in the CLK extraction unit 103 of FIG. 6 and the processing of the CLK unit 104.
In FIG. 7, S802 is a process for inputting the usage amount of the buffer 109, S803 is a process for storing the buffer usage, and S804 is a parameter selection process. Steps S802 to S804 show the processing of the CLK extraction parameter processing unit 702. Note that the same reference numerals as those in the third embodiment indicate the same processing.

  When processing is started in step S101, the usage amount of the buffer 109 is received from the buffer monitoring unit 116 of the main signal processing unit 102 in step S802. In step S803, the buffer usage amount input in step S802 is stored in the past buffer usage data storage unit 801. In step S804, a change rate of the buffer usage is calculated from the current buffer usage output in step S803 and the past buffer usage stored in the past buffer usage data storage unit 801. Further, a count parameter corresponding to the buffer usage rate change rate calculated from the frame count parameter table 301 is extracted. Here, the frame count parameter table 301 stores a table as indicated by reference numeral 805.

  The table 805 shows, for example, that the count parameter is 1 hour when the buffer usage rate is less than 3%, the count parameter is 30 minutes when the usage rate change rate is 3% or more and less than 10%, and the usage rate change rate is The count parameter is 10 minutes if it is 10% or more and less than 30%, the count parameter is 1 minute if the usage rate change rate is 30% or more and less than 50%, and the count parameter is 1 if the usage rate change rate is 50% or more. The usage rate change rate and the count parameter are associated with each other such as seconds. In step S804, when referring to past buffer usage data stored in the past buffer usage data storage unit 801, reference is made to an average value in a past predetermined period, for example, several days or months. You may make it process so that it may carry out, and you may make it refer to divided into daytime and nighttime. It is characterized by statistically processing past buffer usage data.

  Next, the processing proceeds to the frame count unit 303. In step S105, the number of received frames is counted based on the count parameter selected in step S804. The processing after step S106 is performed in the same manner as in the third embodiment, and the number of received frames is counted at a time corresponding to the frame count parameter, and the clock frequency is controlled by the count value. In other words, if the buffer usage is large, processing is performed to increase the clock frequency in step S108, and if the buffer usage is small, processing is performed to decrease the clock frequency in step S109.

  As described above, when the amount of use of the buffer 109 output from the buffer monitoring unit 116 of the main signal processing unit 102 is large, the clock frequency is increased and processing is performed so that received frames do not accumulate in the buffer 109. When the usage amount is small, the clock frequency is lowered and processing is performed so that the received frame of the buffer 109 does not become insufficient. Therefore, overflow and underflow of the buffer 109 are prevented, and the SDH / SD is always stably transmitted from the LAN network. Data can be converted to a SONET network. In particular, in step S804, since the time for counting received frames is changed depending on the rate of change of the usage amount of the buffer 109, the count parameter becomes smaller and shorter when the number of received frames per unit time changes abruptly. It is possible to follow in time. Conversely, when the number of received frames per unit time hardly changes, the count parameter is increased and counting is performed for a long time, so that it is possible to cope with a subtle change over a long time such as wander.

(Sixth embodiment)
Next, a sixth embodiment of the synchronous / asynchronous conversion apparatus according to the present invention will be described. The block diagram of the sixth embodiment is the same as FIG. 7 of the fifth embodiment, and the processing of the CLK extraction parameter processing unit 702 is different. FIG. 8 is a flowchart showing the flow of the clock control processing, and shows the processing of the CLK extraction parameter processing unit 702 and the frame count unit 303 in the CLK extraction unit 103 of FIG. Moreover, the part shown with the same code | symbol as 5th Embodiment shows the same process. Hereinafter, a different part from 5th Embodiment is demonstrated.

  In step S152 of FIG. 8, the flow information (information indicating whether overflow or underflow) of the buffer 109 is received from the buffer monitoring unit 116 of the main signal processing unit 102. In step S154, a count parameter is selected from the frame count parameter table 301 based on the flow information input in step S152. Here, the frame count parameter table 301 stores a table as indicated by reference numeral 806.

  In the table 806, for example, when the buffer flow state is overflow or underflow, the count parameter is 1 second, and when the buffer flow state is not overflow or underflow, the count parameter is 10 minutes. Then, the selected frame count parameter is delivered to step S105. The subsequent processing in the frame count unit 303 and the CLK unit 104 is performed in the same manner as in the third embodiment, and the number of received frames is counted in a time corresponding to the frame count parameter, and the clock frequency is controlled by the count value. To do. That is, when the number of received frames in the time corresponding to the frame count parameter is large, processing is performed to increase the clock frequency in step S108, and when the number of received frames is small, processing is performed to decrease the clock frequency in step S109. .

  In this way, when overflow or underflow occurs in the buffer 109, processing is performed with the count parameter shortened, so that overflow or underflow of the buffer 109 can be quickly avoided. Further, when overflow or underflow does not occur in the buffer 109, the count parameter is increased and counted for a long time, so that it is possible to cope with a subtle change over a long time such as wander.

In the sixth embodiment, processing is performed after an overflow or underflow has occurred. However, when overflow or underflow is likely to occur in the buffer monitoring unit 116, flow information is sent to the CLK extraction parameter processing unit 702. In this case, overflow and underflow of the buffer 109 can be prevented beforehand.
Further, in the block diagram of FIG. 6, the clock control process of FIG. 7 of the fifth embodiment and the clock control process of FIG. 8 of the sixth embodiment may be selected. Alternatively, by combining the fifth embodiment and the sixth embodiment, it is possible to perform an operation in accordance with the use situation.

  As described above, from the first embodiment to the sixth embodiment, according to the synchronous / asynchronous conversion device and the clock control method according to the present invention, the synchronous / asynchronous network connected to the synchronous transmission network having the master clock. The received data sent from the asynchronous converter via the asynchronous transmission network is stored in the buffer of the synchronous / asynchronous converter connected to the synchronous transmission network that does not have a master clock, and the buffer usage and the reception frame rate are stored. Since the clock read from the buffer is made variable according to the rate of change, it can always follow the clock of the synchronous transmission network having the master clock, and transmission errors due to buffer overflow and underflow can be prevented. . Further, the influence of fluctuations generated in the wander or the asynchronous transmission network can be reduced by controlling the clock read from the buffer.

  As described above, the first to sixth embodiments relate to the SoE device 754 shown in FIG. 9, and reproduce the SDH data based on the received frame rate received from the LAN network 753, the buffer usage, and the like. The data can be output to the transmission device 755 and the SDH / SONET network. As a result, an existing SDH / SONET device can be used as it is in a wide-area LAN network without providing a dedicated clock line, and facility costs and communication costs can be reduced. The SoE device 752 on the side having the master clock does not perform clock control in the SoE device 754 on the side not having the master clock described in the first to sixth embodiments, and is all supplied from the master CLK 756. 2 can be realized with the same configuration as in FIG. 1 or FIG.

(Seventh embodiment)
Next, a seventh embodiment of the synchronous / asynchronous conversion apparatus according to the present invention will be described. Although the first to sixth embodiments relate to the SoE device 754 of FIG. 9 that does not have a master clock, this embodiment is configured to operate the SoE device 752 and the SoE device 754 in cooperation with each other. Yes. In FIG. 10, the SoE device 752 and the SoE device 754 are shown only for the part related to clock control, and the other parts are the same as those in FIG. 1 or FIG.

  In the SoE device 752 having the master CLK 756, the frame count unit 703 counts the number of received frames received by the received packet processing unit 107 with a clock of the master CLK 756 every predetermined time. The counter device frequency control unit 851 instructs frequency control information to instruct to lower the frequency when the count value of the frame count unit 703 is larger than the reference value determined in advance, and to increase the frequency when it is smaller. Frequency control information to be output to the LAN frame generation unit 852. The LAN frame generation unit 852 is a part that performs processing that combines the SDH reception / encapsulation unit 112 and the transmission packet processing unit 113 of the first embodiment of FIG. 1, and the frequency control output by the counter device frequency control unit 851. The information is encapsulated and transmitted as a LAN packet to the SoE device 754 via the LAN network 753.

  In the SoE device 754 that does not have a master clock, the LAN packet including the frequency control information transmitted via the LAN network 753 is decapsulated by the frequency control information separation unit 854, and the frequency control information is extracted. The CLK generation unit 855 that has received the frequency control information increases the clock frequency when the frequency control information instructs to increase the frequency, and decreases the clock frequency when the frequency control information instructs to decrease the frequency. A clock is supplied into the 754 device. Note that the CLK generation unit 855 is a part that performs processing that combines the CLK extraction unit 103 and the CLK unit 104 in FIG. 1, and controls the clock frequency supplied into the apparatus based on the frequency control information. The LAN frame generation unit 853 operates in the same manner as the LAN frame generation unit 852 of the SoE device 752, and encapsulates transmission data and transmits it as a LAN packet to the SoE device 752 via the LAN network 753.

  Thus, by counting the received frame of the LAN packet sent by the SoE device 754 with the master CLK 756 of the SoE device 752, the deviation from the master CLK 756 can always be accurately measured. In order to control the clock of the SoE device 754 in a direction to eliminate this deviation, the SoE device 752 sends the frequency control information indicating the control direction of the clock to the SoE device 754, so that the SoE device 754 is synchronized with the master CLK 756. be able to.

It is a block diagram of the SoE apparatus which concerns on the 1st Embodiment of this invention. It is a block diagram of the SoE apparatus which concerns on the 2nd Embodiment of this invention. It is a block diagram of the clock control part of 3rd and 4th embodiment. It is a flowchart of the clock processing of 3rd Embodiment. It is a flowchart of the clock processing of 4th Embodiment. It is a block diagram of the clock control part of 5th and 6th embodiment. It is a flowchart of the clock process of 5th Embodiment. It is a flowchart of the clock processing of 6th Embodiment. It is a block diagram of the whole communication system of 1st thru | or 6th Embodiment. It is a block diagram of the clock control part of 7th Embodiment. It is a block diagram of the whole conventional communication system.

Explanation of symbols

101, 200, 752, 754 ... SoE device 102 ... main signal processing unit 103 ... CLK extraction unit 104 ... CLK unit 107 ... received packet processing unit 109 ... buffer 116 ... Buffer monitoring unit 117 ... CLK fluctuation extraction unit 118, 201 ... frequency correction unit 119,121 ... REF generation unit 120,122 ... PLL
301 ... Frame count parameter table 302 ... Received frame rate statistical processing unit 303, 703 ... Frame count unit 401 ... Past frame rate data storage unit 702 ... CLK extraction parameter processing unit 756 ...・ Master CLK
801... Past buffer usage data storage unit 851 .. Counter device frequency control unit 852, 853... LAN frame generation unit 854.

Claims (9)

In a synchronous / asynchronous conversion device that connects a synchronous transmission network not having a master clock and an asynchronous transmission network,
A transmission processing unit that outputs data received from the synchronous transmission network to the asynchronous transmission network;
A reception processing unit that outputs data received from the asynchronous transmission network to the synchronous transmission network via a buffer;
Buffer monitoring means for monitoring an increase or decrease in the buffer usage;
Clock control means for varying the clock read from the buffer according to the output of the buffer monitoring means, and
The synchronous / asynchronous conversion characterized in that the clock control means speeds up a clock read from the buffer when the buffer usage increases, and slows down a clock read from the buffer when the buffer usage decreases. apparatus. In a synchronous / asynchronous conversion device that connects a synchronous transmission network not having a master clock and an asynchronous transmission network,
A transmission processing unit that outputs data received from the synchronous transmission network to the asynchronous transmission network;
A reception processing unit that outputs data received from the asynchronous transmission network to the synchronous transmission network via a buffer;
Buffer monitoring means for monitoring an increase or decrease in the buffer usage;
A synchronous / asynchronous conversion device, comprising: a device clock control unit that supplies a clock read from the buffer in accordance with an output of the buffer monitoring means. The synchronous / asynchronous conversion device according to claim 1 or 2,
The buffer monitoring means outputs the clock immediately to the device clock controller when the buffer usage increases, and immediately delays the clock to the device clock controller when the buffer usage decreases. A synchronous / asynchronous conversion device characterized in that the output is as follows. The synchronous / asynchronous conversion device according to claim 1 or 2,
A statistical processing unit is provided in the device clock control unit,
The statistical processing unit performs statistical processing on information output from the buffer monitoring unit in a predetermined period, and increases or decreases a clock speed output from the device clock control unit according to a result of the statistical processing. A synchronous / asynchronous conversion device characterized by the above. The synchronous / asynchronous conversion device according to claim 1 or 2,
The buffer monitoring means outputs the clock to the device clock controller when the buffer usage approaches the full capacity of the buffer so as to make the clock faster, and the buffer clock when the buffer usage approaches zero. A synchronous / asynchronous conversion device, characterized in that a clock is output to a control unit so as to be delayed. The synchronous / asynchronous conversion device according to claim 1 or 2,
The buffer monitoring means outputs the clock to the device clock control unit when the buffer usage amount overflows, and delays the clock to the device clock control unit when the buffer usage amount underflows. A synchronous / asynchronous conversion device characterized by outputting. A first synchronous / asynchronous conversion device connected to a synchronous transmission network having a master clock and a second synchronous / asynchronous conversion device connected to a synchronous transmission network not having a master clock are connected via an asynchronous transmission network. In the synchronous / asynchronous conversion device,
The first synchronous / asynchronous conversion device is provided with a received frame monitoring means for receiving from the second synchronous / asynchronous conversion device, and a timing packet generation / transmission means,
The second synchronous / asynchronous conversion device is provided with timing packet receiving means and clock control means for controlling a clock for outputting data to the synchronous transmission network not having the master clock,
The received frame monitoring means transmits the number of frames in a unit time that are periodically transmitted to the second synchronous / asynchronous conversion device by the timing packet generation and transmission means,
The timing packet receiving means outputs information of the received timing packet to the clock control means,
The synchronous / asynchronous conversion apparatus characterized in that the clock control means slows the clock when the number of frames in a unit time is large, and speeds up the clock when the number of frames in a unit time is small. In a clock control method of a synchronous / asynchronous conversion apparatus for connecting a synchronous transmission network not having a master clock and an asynchronous transmission network,
A transmission processing unit that outputs data received from the synchronous transmission network to the asynchronous transmission network;
A reception processing unit that outputs data received from the asynchronous transmission network to the synchronous transmission network via a buffer;
Buffer monitoring means for monitoring an increase or decrease in the buffer usage;
A device clock controller for supplying a clock to be read from the buffer according to the output of the buffer monitoring means;
A statistical processing unit is provided in the device clock control unit,
The statistical processing unit performs statistical processing on information output from the buffer monitoring unit in a predetermined period, and increases or decreases a clock speed output from the device clock control unit according to a result of the statistical processing. A clock control method for a synchronous / asynchronous conversion apparatus, characterized in that The clock control method for a synchronous / asynchronous conversion device according to claim 8,
The buffer monitoring means outputs the clock to the device clock control unit when the buffer usage amount overflows, and delays the clock to the device clock control unit when the buffer usage amount underflows. A clock control method for a synchronous / asynchronous conversion device, characterized in that:

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