JP4877873B2 - Display device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a display device, a manufacturing method thereof, and a television device using the display device.

  In recent years, flat panel displays (FPDs) have attracted attention as display devices that replace conventional CRTs. In particular, the development of a large-screen television apparatus equipped with a large display panel driven by an active matrix is an important issue for panel manufacturers to focus on.

    In a conventional display device, as a semiconductor element for driving each pixel, a thin film transistor (hereinafter also referred to as a TFT (Thin Film Transistor)) using amorphous silicon as a semiconductor active layer is used (see Patent Document 1). ).

On the other hand, in conventional liquid crystal televisions, image blurring due to the limitation of viewing angle characteristics and the limitation of high-speed operation due to liquid crystal materials and the like has been a drawback. In recent years, OCB (optically compensated bend) mode has been proposed (Non-Patent Document 1).
JP-A-5-35207 Nagahiro Yasuaki et al., “Nikkei Microdevices separate volume flat panel display 2002”, Nikkei BP, October 2001, P102-109

  However, when a TFT using an amorphous silicon (amorphous semiconductor) film is DC-driven, the threshold value tends to shift and TFT characteristic variation tends to occur accordingly. For this reason, luminance unevenness occurs in a display device in which a TFT using an amorphous semiconductor film is used for pixel switching. Such a phenomenon becomes more conspicuous as a large-screen television apparatus having a diagonal of 30 inches or more (typically 40 inches or more), and deterioration in image quality is a serious problem.

  On the other hand, there is a need for a switching element that can operate at high speed in order to improve image quality. However, a TFT using an amorphous semiconductor film has a limit in operation speed. For example, it is difficult to realize an OCB mode liquid crystal display device.

  The present invention has been made in view of such a situation, and an object of the present invention is to provide a method for manufacturing a display device having a TFT that can operate at high speed without causing a threshold shift with a small number of photomasks. And It is another object of the present invention to provide a method for manufacturing a display device which can display with high switching characteristics and excellent contrast.

  In order to solve the above-described problems of the prior art, the following measures are taken in the present invention.

  In the present invention, a catalytic element is added to an amorphous semiconductor film and heated to form a crystalline semiconductor film. After removing the catalytic element from the crystalline semiconductor film, an inverted staggered thin film transistor is manufactured. Further, according to the present invention, the gate electrode layer and the pixel electrode layer of the thin film transistor are formed using the same material in the same process, thereby achieving simplification of the process and reduction of material loss. In the present invention, a display device includes a liquid crystal display element using a liquid crystal material or a light emitting element (EL element) as a display element, and can also be referred to as a liquid crystal display device, a light emitting display device, or an EL display device.

  An element that promotes or promotes crystallization (hereinafter mainly referred to as a metal element or a catalyst element) is added to an amorphous semiconductor film and heated to form a crystalline semiconductor film. Forming a semiconductor film having a periodic group 15 element or a semiconductor film having a rare gas element in contact with the crystalline semiconductor film and heating to remove the metal element from the crystalline semiconductor film, and then forming an inverted staggered thin film transistor Is the gist. Note that in the case where a semiconductor film having a periodic group 15 element is formed in contact with the crystalline semiconductor film, an n-channel thin film transistor is formed using the semiconductor film having a periodic group 15 element as a source region and a drain region. . Further, a p-channel thin film transistor is formed by adding a periodic group 13 element as an impurity element imparting p-type to a semiconductor film having a periodic group 15 element as an impurity element imparting n-type. Further, when a semiconductor film containing a rare gas element is formed, the semiconductor film containing the rare gas element is removed after heating, and a source region and a drain region are formed, so that an n-channel thin film transistor or a p-channel thin film transistor is formed. To do.

    One display device of the present invention includes a gate electrode layer and a first electrode layer provided over an insulating surface, a gate insulating layer over the gate electrode layer, and a crystalline semiconductor layer over the gate insulating layer A semiconductor layer having one conductivity type in contact with the crystalline semiconductor layer, a source electrode layer and a drain electrode layer in contact with the semiconductor layer having one conductivity type, and a source electrode layer and a drain electrode layer And a first insulating layer on the first electrode layer, the first insulating layer has a first opening reaching the source electrode layer or the drain electrode layer, and the gate insulating layer and the first insulating layer Has a second opening reaching the first electrode layer, and the source or drain electrode layer and the first electrode layer are electrically connected to the first opening and the second opening. A wiring layer; a part of the first electrode layer; a second insulating layer covering the wiring layer; It has an electroluminescent layer on electrode layer, a second electrode layer over the electroluminescent layer.

    One display device of the present invention includes a gate electrode layer and a first electrode layer provided over an insulating surface, a gate insulating layer over the gate electrode layer, and a source region and a drain over the gate insulating layer. A crystalline semiconductor layer provided with a region; a source electrode layer; a drain electrode layer in contact with the source region and the drain region; a first electrode layer over the source electrode layer, the drain electrode layer, and the first electrode layer; An insulating layer, the first insulating layer has a first opening reaching the source or drain electrode layer, and the gate insulating layer and the first insulating layer reach the first electrode layer; A first electrode layer having a wiring layer electrically connected to the source or drain electrode layer and the first electrode layer in the first opening and the second opening; And a second insulating layer covering the wiring layer, and an electric field on the first electrode layer It has a light layer, having a second electrode layer over the electroluminescent layer.

    One display device of the present invention includes a pixel region and a driver circuit region over the same substrate, the driver circuit region includes a first gate electrode layer and a second gate electrode layer over the substrate, A gate insulating layer is provided on the gate electrode layer and the second gate electrode layer, and a first crystalline semiconductor layer and a second crystalline semiconductor layer are provided on the gate insulating layer, and the first crystalline semiconductor layer is provided. A first source electrode layer having a n-type semiconductor layer in contact with the first crystalline semiconductor layer, a p-type semiconductor layer in contact with the first crystalline semiconductor layer, and a first source electrode layer in contact with the n-type semiconductor layer; The second source electrode layer and the second drain electrode layer in contact with the p-type semiconductor layer, the first electrode layer on the substrate in the pixel region, A first electrode having an electroluminescent layer on the electrode layer and a second electrode layer on the electroluminescent layer Some of is covered with the gate insulating layer.

    According to one method for manufacturing a display device of the present invention, a conductive layer is formed over an insulating surface, a resist is formed over the conductive layer, the resist is exposed and patterned with laser light, a mask is formed, and the mask is used. The conductive layer is patterned to form a gate electrode layer and a first electrode layer, a gate insulating layer is formed on the gate electrode layer and the first electrode layer, and an amorphous semiconductor layer is formed on the gate insulating layer Then, a metal element is added to the amorphous semiconductor layer and heated, the amorphous semiconductor layer is crystallized, a crystalline semiconductor layer is formed, and a semiconductor layer having one conductivity type is formed in contact with the crystalline semiconductor layer And heating the crystalline semiconductor layer and the semiconductor layer having one conductivity type, patterning the semiconductor layer having one conductivity type, forming a source region and a drain region, and in contact with the source region and the drain region, Drain electrode layer shaped Then, a first insulating layer is formed over the source electrode layer, the drain electrode layer, and the gate insulating layer, a first opening reaching the source electrode layer or the drain electrode layer, and a first insulating layer are formed in the first insulating layer. A second opening reaching the first electrode layer is formed in the layer and the gate insulating layer, and the source electrode layer, the drain electrode layer, and the first electrode layer are electrically connected to the first opening and the second opening. A wiring layer to be connected electrically, a part of the first electrode layer and a second insulating layer covering the wiring layer are formed, an electroluminescent layer is formed on the first electrode layer, and the electroluminescent layer is formed. A second electrode layer is formed thereon.

    According to one method for manufacturing a display device of the present invention, a conductive layer is formed over an insulating surface, a resist is formed over the conductive layer, the resist is exposed and patterned with laser light, a mask is formed, and the mask is used. The conductive layer is patterned to form a gate electrode layer and a first electrode layer, a gate insulating layer is formed on the gate electrode layer and the first electrode layer, and a first semiconductor layer is formed on the gate insulating layer Then, a metal element is added to the first semiconductor layer and heated to form a second semiconductor layer having the first impurity element in contact with the first semiconductor layer, and the first semiconductor layer and the first semiconductor layer The second semiconductor layer including the impurity element is heated, the second semiconductor layer including the first impurity element is removed, the second impurity element is added to the first semiconductor layer, and the source region and the drain region are formed. A source electrode in contact with the source region and the drain region. Forming a layer and a drain electrode layer; forming a first insulating layer on the source electrode layer, the drain electrode layer, and the gate insulating layer; and a first opening reaching the source electrode layer or the drain electrode layer in the first insulating layer A second opening reaching the first electrode layer is formed in the first insulating layer and the gate insulating layer, and a source electrode layer or a drain electrode layer is formed in the first opening and the second opening. And a wiring layer electrically connecting the first electrode layer, a second insulating layer covering a part of the first electrode layer and the wiring layer is formed, and electroluminescence is formed on the first electrode layer. Forming a layer and forming a second electrode layer on the electroluminescent layer.

    According to one method for manufacturing a display device of the present invention, a conductive layer is formed over a substrate in a pixel region and a driver circuit region, the conductive layer is exposed and patterned using a laser beam, and a first layer is formed in the driver circuit region. Forming a first gate electrode layer, a second gate electrode layer, a third gate electrode layer, a third gate electrode layer, and a third gate electrode. A gate insulating layer is formed over the layer and the first electrode layer, a semiconductor film is formed over the gate insulating layer, a metal element is added to the semiconductor film, and the semiconductor film is heated to form an n-type semiconductor over the semiconductor film Forming a film, heating the semiconductor film and the n-type semiconductor film, patterning the semiconductor film and the n-type semiconductor film, and forming a first semiconductor layer, a second semiconductor layer, and a first semiconductor layer in the driver circuit region Semiconductor layer having n-type and semiconductor having second n-type Forming a layer, forming a third semiconductor layer and a third n-type semiconductor layer in the pixel region, and covering the first n-type semiconductor layer and the third n-type semiconductor layer A first mask is formed, an impurity element imparting p-type conductivity is added to the second n-type semiconductor layer, the second n-type semiconductor layer is inverted to a p-type semiconductor layer, and the second n-type semiconductor layer is inverted. A first source electrode layer and a first drain electrode layer in contact with a first n-type semiconductor layer; a second source electrode layer and a second drain electrode layer in contact with a p-type semiconductor layer; A third source electrode layer and a third drain electrode layer are formed in contact with the third n-type semiconductor layer, and the first source electrode layer, the first drain electrode layer, the second source electrode layer, Second drain electrode layer, third source electrode layer, third drain electrode layer, and gate A first insulating layer is formed on the edge layer, a first opening reaching the third source electrode layer or the third drain electrode layer in the first insulating layer, and the first insulating layer and the gate insulating layer A second opening reaching the first electrode layer is formed, and a third source electrode layer or a third drain electrode layer and a first electrode layer are formed in the first opening and the second opening. A wiring layer that electrically connects the electrodes, a part of the first electrode layer and a second insulating layer that covers the wiring layer are formed, and an electroluminescent layer is formed on the first electrode layer. A second electrode layer is formed on the light emitting layer.

    One embodiment of the display device of the present invention includes a gate electrode layer and a pixel electrode layer provided over an insulating surface, a gate insulating layer over the gate electrode layer, and a crystalline semiconductor layer over the gate insulating layer. A semiconductor layer having one conductivity type in contact with the crystalline semiconductor layer, a source electrode layer and a drain electrode layer in contact with the semiconductor layer having one conductivity, and a source electrode layer, a drain electrode layer, and a pixel. An insulating layer is provided over the electrode layer, the insulating layer has a first opening reaching the source electrode layer or the drain electrode layer, and the gate insulating layer and the insulating layer have a second opening reaching the pixel electrode layer. In addition, the first opening and the second opening each include a wiring layer in which the source or drain electrode layer and the pixel electrode layer are electrically connected.

    One embodiment of the display device of the present invention includes a gate electrode layer and a pixel electrode layer provided over an insulating surface, a gate insulating layer over the gate electrode layer, and a source region and a drain region over the gate insulating layer. A crystalline semiconductor layer provided; a source electrode layer and a drain electrode layer in contact with the source region and the drain region; an insulating layer over the source electrode layer, the drain electrode layer, and the pixel electrode layer; The layer has a first opening reaching the source or drain electrode layer, and the gate insulating layer and the insulating layer have a second opening reaching the pixel electrode layer, and the first opening and the second opening A wiring layer in which the source or drain electrode layer and the pixel electrode layer are electrically connected is provided in the opening.

    One display device of the present invention includes a pixel region and a driver circuit region over the same substrate, the driver circuit region includes a first gate electrode layer and a second gate electrode layer over the substrate, A gate insulating layer is provided on the gate electrode layer and the second gate electrode layer, and a first crystalline semiconductor layer and a second crystalline semiconductor layer are provided on the gate insulating layer, and the first crystalline semiconductor layer is provided. A first source electrode layer having a n-type semiconductor layer in contact with the first crystalline semiconductor layer, a p-type semiconductor layer in contact with the first crystalline semiconductor layer, and a first source electrode layer in contact with the n-type semiconductor layer; A drain electrode layer, a second source electrode layer and a second drain electrode layer in contact with a p-type semiconductor layer, a pixel electrode layer on a substrate in a pixel region, Part of it is covered with a gate insulating layer.

    According to one method for manufacturing a display device of the present invention, a conductive layer is formed over an insulating surface, a resist is formed over the conductive layer, the resist is exposed and patterned with laser light, a mask is formed, and the mask is used. The conductive layer is patterned to form a gate electrode layer and a pixel electrode layer, a gate insulating layer is formed over the gate electrode layer and the pixel electrode layer, an amorphous semiconductor layer is formed over the gate insulating layer, and an amorphous layer is formed. A crystalline semiconductor layer is heated by adding a metal element to the crystalline semiconductor layer, crystallizing the amorphous semiconductor layer, forming a crystalline semiconductor layer, and forming a semiconductor layer having one conductivity type in contact with the crystalline semiconductor layer. The semiconductor layer and the semiconductor layer having one conductivity type are heated, the semiconductor layer having one conductivity type is patterned, a source region and a drain region are formed, and the source electrode layer and the drain electrode layer are in contact with the source region and the drain region. Forming An insulating layer is formed over the source electrode layer, the drain electrode layer, and the gate insulating layer, a first opening reaching the source electrode layer or the drain electrode layer in the insulating layer, and a pixel electrode layer reaching the insulating layer and the gate insulating layer A second opening is formed, and a wiring layer that electrically connects the source or drain electrode layer and the pixel electrode layer is formed in the first opening and the second opening.

    According to one method for manufacturing a display device of the present invention, a conductive layer is formed over an insulating surface, a resist is formed over the conductive layer, the resist is exposed and patterned with laser light, a mask is formed, and the mask is used. The conductive layer is patterned to form a gate electrode layer and a pixel electrode layer, a gate insulating layer is formed over the gate electrode layer and the pixel electrode layer, a first semiconductor layer is formed over the gate insulating layer, A metal element is added to the semiconductor layer and heated to form a second semiconductor layer having the first impurity element in contact with the first semiconductor layer, and having the first semiconductor layer and the first impurity element The second semiconductor layer is heated, the second semiconductor layer having the first impurity element is removed, the second impurity element is added to the first semiconductor layer to form a source region and a drain region, and the source Source electrode layer in contact with region and drain region And a drain electrode layer, an insulating layer is formed on the source electrode layer, the drain electrode layer, and the gate insulating layer, a first opening reaching the source electrode layer or the drain electrode layer, and the insulating layer and the gate A wiring layer that forms a second opening reaching the pixel electrode layer in the insulating layer and electrically connects the source or drain electrode layer and the pixel electrode layer to the first opening and the second opening. Form.

According to one method for manufacturing a display device of the present invention, a conductive layer is formed over a substrate in a pixel region and a driver circuit region, the conductive layer is exposed and patterned using laser light, and a first layer is formed in the driver circuit region. Forming a gate electrode layer, a second gate electrode layer, a third gate electrode layer and a pixel electrode layer in the pixel region, a first gate electrode layer, a second gate electrode layer, a third gate electrode layer, And a gate insulating layer is formed over the pixel electrode layer, a first semiconductor film is formed over the gate insulating layer, a metal element is added to the semiconductor film and heated, and a semiconductor film having an n-type over the semiconductor film The semiconductor film and the n-type semiconductor film are heated, the semiconductor film and the n-type semiconductor film are patterned, and the first semiconductor layer, the second semiconductor layer, and the first n are formed in the driver circuit region. A semiconducting layer having a mold and a second n-type semiconductor layer A body layer is formed, a third semiconductor layer and a third n-type semiconductor layer are formed in the pixel region, and the first n-type semiconductor layer and the third n-type semiconductor layer are formed A first mask is formed, an impurity element imparting p-type conductivity is added to the second n-type semiconductor layer, the second n-type semiconductor layer is inverted to a p-type semiconductor layer, and The first source electrode layer and the first drain electrode layer are in contact with the first n-type semiconductor layer, and the second source electrode layer and the second drain electrode layer are in contact with the p-type semiconductor layer. The third source electrode layer and the third drain electrode layer are formed in contact with the third n-type semiconductor layer, and the first source electrode layer, the first drain electrode layer, and the second source electrode layer are formed. , Second drain electrode layer, third source electrode layer, third drain electrode layer, and gate An insulating layer is formed over the insulating layer, a first opening reaching the third source electrode layer or the third drain electrode layer in the insulating layer, and a second reaching the pixel electrode layer in the insulating layer and the gate insulating layer And a wiring layer for electrically connecting the third source electrode layer or the third drain electrode layer and the pixel electrode layer is formed in the first opening and the second opening.

    According to the present invention, an inverted staggered thin film transistor having a crystalline semiconductor film can be formed. Therefore, a TFT can be formed with a small number of masks. In addition, since the TFT formed according to the present invention is formed using a crystalline semiconductor film, it has higher mobility than an inverted staggered TFT formed using an amorphous semiconductor film. In addition to the impurity element imparting p-type (acceptor-type element) or the impurity element imparting n-type (donor-type element), the source region and the drain region also include a metal element that is an element that promotes crystallization. Including. For this reason, a source region and a drain region with low resistivity can be formed. As a result, a display device capable of high speed operation can be manufactured. Typically, it is possible to manufacture a display device that can display with a high response speed and a high viewing angle like the OCB mode.

    Further, as compared with a thin film transistor formed using an amorphous semiconductor film, threshold shift is less likely to occur, and variation in TFT characteristics can be reduced. Therefore, display unevenness can be reduced and a highly reliable display device can be manufactured.

    Further, since the metal element mixed in the semiconductor film in the film formation step is gettered by the gettering step, off current can be reduced. For this reason, it is possible to improve contrast by providing such a TFT in a switching element of a display device.

  Further, according to the present invention, material loss is small, and cost reduction can be achieved. Therefore, a high-performance and highly reliable display device can be manufactured with high yield.

(Embodiment 1)
Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in structures of the present invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated.

  FIG. 29A is a top view illustrating a structure of a display panel according to the present invention. A pixel portion 2701 in which pixels 2702 are arranged in a matrix over a substrate 2700 having an insulating surface, a scan line side input terminal 2703, a signal A line side input terminal 2704 is formed. The number of pixels may be provided in accordance with various standards. For XGA, 1024 × 768 × 3 (RGB), for UXGA, 1600 × 1200 × 3 (RGB), and for full specification high vision, 1920 × 1080. X3 (RGB) may be used.

  The pixels 2702 are arranged in a matrix by a scan line extending from the scan line side input terminal 2703 and a signal line extending from the signal line side input terminal 2704 intersecting. Each of the pixels 2702 includes a switching element and a pixel electrode connected to the switching element. A typical example of the switching element is a TFT. By connecting the gate electrode side of the TFT to a scanning line and the source or drain side to a signal line, each pixel can be controlled independently by a signal input from the outside. Yes.

    FIG. 29A shows a structure of a display panel in which signals input to the scanning lines and the signal lines are controlled by an external driving circuit. As shown in FIG. The driver IC 2751 may be mounted on the substrate 2700 by the Glass method. As another mounting mode, a TAB (Tape Automated Bonding) method as shown in FIG. 30B may be used. The driver IC may be formed on a single crystal semiconductor substrate or may be a circuit in which a TFT is formed on a glass substrate. In FIG. 30, the driver IC 2751 is connected to the FPC 2750.

    In the case where a TFT provided for a pixel is formed using SAS, a scan line driver circuit 3702 can be formed over the substrate 3700 and integrated as shown in FIG. In FIG. 29B, reference numeral 3701 denotes a pixel portion, and the signal line side driver circuit is controlled by an external driver circuit as in FIG. In the case where a TFT provided for a pixel is formed using a polycrystalline (microcrystalline) semiconductor, a single crystal semiconductor, or the like with high mobility, in FIG. It can also be integrally formed on 4700.

    The present invention relates to an object necessary for manufacturing a display panel such as a conductive layer for forming a wiring layer or an electrode or a mask layer for forming a predetermined pattern (all forms such as a film and a layer depending on its purpose and function). The display device is manufactured by forming at least one or more of them in a method that can be selectively formed into a desired shape. The present invention includes all conductive layers such as a gate electrode layer, a source electrode layer, and a drain electrode layer, a semiconductor layer, a mask layer, an insulating layer, and the like that constitute a thin film transistor and a display device. Applicable to components. As a method that can be selectively formed into a desired shape, a conductive layer, an insulating layer, or the like is formed, and droplets of a composition prepared for a specific purpose are selectively ejected (ejected) to form a predetermined pattern. It is possible to use a droplet discharge (ejection) method (also called an ink jet method depending on the method). In addition, a method in which an object can be transferred or drawn in a desired pattern, for example, various printing methods (a method in which a desired pattern such as screen (stencil) printing, offset (lithographic) printing, letterpress printing or gravure (intaglio printing) is formed) Etc. can also be used.

    This embodiment mode uses a method in which a composition containing a material having fluidity is ejected (ejected) as droplets to form a desired pattern. A droplet containing a material to be formed is ejected onto a formation region of the formed product, and fixed by firing, drying, or the like to form an object with a desired pattern.

    One mode of a droplet discharge apparatus used for the droplet discharge method is shown in FIG. The individual heads 1405 and 1412 of the droplet discharge means 1403 are connected to the control means 1407, which can be drawn in a pre-programmed pattern under the control of the computer 1410. The drawing timing may be performed with reference to a marker 1411 formed on the substrate 1400, for example. Alternatively, the reference point may be determined based on the edge of the substrate 1400. This is detected by the imaging means 1404, converted into a digital signal by the image processing means 1409, is recognized by the computer 1410, a control signal is generated, and sent to the control means 1407. As the imaging unit 1404, an image sensor using a charge coupled device (CCD) or a complementary metal oxide semiconductor (CMOS) can be used. Of course, the information on the pattern to be formed on the substrate 1400 is stored in the storage medium 1408. Based on this information, a control signal is sent to the control means 1407, and each head 1405 of the droplet discharge means 1403 is sent. The heads 1412 can be individually controlled. The material to be discharged is supplied from the material supply source 1413 and the material supply source 1414 to the head 1405 and the head 1412 through piping.

    The inside of the head 1405 has a structure having a space filled with a liquid material as indicated by a dotted line 1406 and a nozzle that is a discharge port. Although not shown, the head 1412 has the same internal structure as the head 1405. The nozzle sizes of the head 1405 and the head 1412 are different, and different materials can be drawn simultaneously with different widths. With one head, conductive material, organic material, inorganic material, etc. can be discharged and drawn respectively. When drawing in a wide area like an interlayer film, the same material is used from multiple nozzles to improve throughput. It is possible to discharge and draw at the same time. In the case of using a large substrate, the head 1405 and the head 1412 can freely scan on the substrate in the direction of the arrow to freely set a drawing area, and a plurality of the same pattern can be drawn on a single substrate. it can.

    In the present invention, in the patterning process of the formed product, a light exposure is performed by irradiating light to a photosensitive resist or a material containing a photosensitive substance. The light used for exposure is not particularly limited, and any one of infrared light, visible light, ultraviolet light, or a combination thereof can be used. For example, light emitted from an ultraviolet lamp, black light, halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, or high pressure mercury lamp may be used. In that case, the lamp light source may be lit and irradiated for a necessary time, or may be irradiated multiple times.

    Laser light (also referred to as a laser beam) may be used. When the laser light is used, the formation region can be exposed with a more precise pattern, so that an object formed there can be highly fine. A laser light direct drawing apparatus that draws a pattern by irradiating a processing region with laser light that can be used in the present invention will be described with reference to FIG. In this embodiment mode, a laser beam direct drawing apparatus is used in order to select a processing region and directly irradiate and process it instead of selecting a region to be irradiated with laser light through a mask or the like. As shown in FIG. 26, a laser beam direct drawing apparatus 1001 includes a personal computer (hereinafter referred to as a PC) 1002 that executes various controls when irradiating a laser beam, a laser oscillator 1003 that outputs a laser beam, and a laser. A power source 1004 of the oscillator 1003, an optical system (ND filter) 1005 for attenuating the laser light, an acousto-optic modulator (AOM) 1006 for modulating the intensity of the laser light, and an enlargement or reduction of the cross section of the laser light An optical system 1007 composed of a lens for carrying out an optical path, a mirror for changing an optical path, etc., a substrate moving mechanism 1009 having an X stage and a Y stage, and D / D for digital-analog conversion of control data output from the PC 1002 Acousto-optic modulator 100 according to analog voltage output from A converter 1010 and D / A converter A driver 1011 for controlling, and a driver 1012 for outputting a driving signal for driving the substrate moving mechanism 1009.

As the laser oscillator 1003, a laser oscillator that can oscillate ultraviolet light, visible light, or infrared light can be used. As the laser oscillator, excimer laser oscillators such as KrF, ArF, KrF, XeCl, and Xe, gas laser oscillators such as He, He-Cd, Ar, He-Ne, and HF, YAG, GdVO ₄ , YVO ₄ , YLF, and YAlO Cr crystal such as _{3, Nd, Er, Ho,} Ce, Co, solid-state laser oscillator using a crystal doped with Ti or Tm, can be used GaN, GaAs, GaAlAs, a semiconductor laser oscillator of InGaAsP or the like. In the solid-state laser oscillator, it is preferable to apply the second to fifth harmonics of the fundamental wave.

    Next, a substance (surface) exposure process using a laser beam direct drawing apparatus will be described. When the substrate 1008 is mounted on the substrate moving mechanism 1009, the PC 1002 detects the position of the marker attached to the substrate 1008 by a camera (not shown). Next, the PC 1002 generates movement data for moving the substrate movement mechanism 1009 based on the detected marker position data and drawing pattern data input in advance. Thereafter, the PC 1002 controls the output light amount of the acousto-optic modulator 1006 via the driver 1011, so that the laser light output from the laser oscillator 1003 is attenuated by the optical system 1005 and then the acousto-optic modulator 1006. The light amount is controlled so as to be a predetermined light amount. On the other hand, the laser light output from the acousto-optic modulator 1006 is changed in the optical path and the shape of the laser light (beam spot) by the optical system 1007, condensed by the lens, and then applied to the object formed on the substrate. Irradiation with the laser beam modifies the object to be processed. At this time, according to the movement data generated by the PC 1002, the movement of the substrate moving mechanism 1009 is controlled in the X direction and the Y direction. As a result, the predetermined place is irradiated with laser light, and the exposure processing of the workpiece is performed.

    As a result, the workpiece is exposed and exposed in the region irradiated with the laser beam. Photosensitive materials are roughly divided into negative types and positive types. In the case of the negative type, a chemical reaction occurs in the exposed part, and only the part in which the chemical reaction is caused by the developer is left to form a pattern. In the case of the positive type, a chemical reaction occurs in the exposed portion, the portion in which the chemical reaction has occurred is dissolved by the developing solution, and only the unexposed portion is left to form a pattern. A part of the energy of the laser beam is converted into heat by the material to be processed, and a part of the object to be processed reacts. Therefore, the width of the processed object region is slightly larger than the width of the laser beam to be processed. Sometimes. Further, the shorter the wavelength of the laser light, the shorter the diameter of the laser light can be condensed. Therefore, it is preferable to irradiate the laser light with a short wavelength in order to form a processing region with a fine width.

  The spot shape on the film surface of the laser beam is processed by an optical system so as to be a dot, circle, ellipse, rectangle, or line (strictly, a long and narrow rectangle).

  The apparatus shown in FIG. 26 shows an example in which exposure is performed by irradiating a laser beam from the front surface side of the substrate. However, the optical system and the substrate moving mechanism are appropriately changed to irradiate the laser beam from the back surface side of the substrate. Alternatively, a laser beam drawing apparatus that performs exposure may be used.

    Note that here, the laser beam is selectively irradiated by moving the substrate, but the present invention is not limited to this, and the laser beam can be irradiated by scanning the laser beam in the X-Y axis direction. In this case, it is preferable to use a polygon mirror or a galvanometer mirror for the optical system 1007.

    In addition, light can also be used in combination with light from a lamp light source and laser light, and the only area where patterning is relatively wide is to perform irradiation with a lamp using a mask to perform high-definition patterning. Irradiation treatment can also be performed with laser light. By performing the light irradiation treatment in this way, it is possible to improve the throughput and obtain a highly finely patterned wiring board or the like.

    Embodiment Modes of the present invention will be described with reference to FIGS. More specifically, a method for manufacturing a display device to which the present invention is applied will be described. First, a method for manufacturing a display device having a channel-etched thin film transistor to which the present invention is applied will be described. 2 to 6A are top views of the pixel portion of the display device, and FIG. 2B to FIG. 6B are cross-sectional views taken along line A—C in FIG. 2 to FIG. FIG. 6C is a cross-sectional view taken along line B-D in FIGS.

    As the substrate 100, a glass substrate made of barium borosilicate glass, alumino borosilicate glass, or the like, a quartz substrate, a silicon substrate, a metal substrate, a stainless steel substrate, or a plastic substrate having heat resistance that can withstand the processing temperature in this manufacturing process is used. Further, polishing may be performed by a CMP method or the like so that the surface of the substrate 100 is planarized. Note that an insulating layer may be formed over the substrate 100. The insulating layer is formed as a single layer or a stacked layer using an oxide material or a nitride material containing silicon by a known method such as a CVD method, a plasma CVD method, a sputtering method, or a spin coating method. This insulating layer may not be formed, but has an effect of blocking contaminants from the substrate 100. As the substrate 100, a large area substrate such as 320 mm × 400 mm, 370 mm × 470 mm, 550 mm × 650 mm, 600 mm × 720 mm, 680 mm × 880 mm, 1000 mm × 1200 mm, 1100 mm × 1250 mm, 1150 mm × 1300 mm can be used.

    A conductive film 101 is formed over the substrate 100. The conductive film 101 is patterned into a gate electrode layer and a pixel electrode layer. The conductive film 101 is preferably formed using a high melting point material by a known method such as a printing method, an electroplating method, a PVD method (Physical Vapor Deposition), a CVD method (Chemical Vapor Deposition), or an evaporation method. As a forming method, a desired pattern can be formed by a droplet discharge method. By using a high melting point material, a later heating step is possible. High melting point materials include tungsten (W), molybdenum (Mo), zirconia (Zr), hafnium (Hf), bismuth (Bi), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co) A metal such as nickel (Ni) or platinum (Pt), an alloy thereof, or a metal nitride thereof can be used as appropriate. Further, a plurality of these layers may be stacked. Typically, a tantalum nitride film may be stacked on the substrate surface, and a tungsten film may be stacked thereon. LRTA (Lamp Rapid Thermal Anneal) method in which the subsequent heating process is performed by radiation from one or more kinds selected from halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high pressure sodium lamps, and high pressure mercury lamps. When using a GRTA (Gas Rapid Thermal Anneal) method using an inert gas such as nitrogen or argon as a heating medium, aluminum (Al), silver (Ag), and gold (Cu ) May be used to form a conductive film. Such a metal having reflectivity is preferable when a top emission display panel is manufactured. Alternatively, a material in which an impurity element imparting one conductivity type is added to silicon may be used. For example, an n-type silicon film in which an amorphous silicon film contains an impurity element imparting n-type such as phosphorus (P) can be used.

Since the conductive film 101 also functions as a pixel electrode layer, the conductive film 101 can be formed using a transparent conductive material. Therefore, the conductive film 101 may be formed using indium tin oxide (ITO), indium tin oxide containing silicon oxide (ITSO), zinc oxide (ZnO), tin oxide (SnO ₂ ), or the like. Preferably, it is formed of indium tin oxide (ITO), indium tin oxide containing silicon oxide (ITSO), zinc oxide (ZnO), or the like by a sputtering method. More preferably, an indium tin oxide film containing silicon oxide formed by a sputtering method using a target in which 2 to 10% by weight of silicon oxide is contained in ITO is used. In addition, a conductive material such as an indium zinc oxide alloy in which silicon oxide is included and indium oxide is mixed with 2 to 20% zinc oxide (ZnO) may be used.

    In this embodiment, the conductive film 101 is formed by discharging a composition containing indium tin oxide as a conductive material and baking at 550 ° C. The droplet discharge means is a general term for a device having means for discharging droplets such as a nozzle having a composition discharge port and a head having one or a plurality of nozzles. The diameter of the nozzle provided in the droplet discharge means is set to 0.02 to 100 μm (preferably 30 μm or less), and the discharge amount of the composition discharged from the nozzle is 0.001 pl to 100 pl (preferably 0). .1pl or more and 40pl or less, more preferably 10pl or less). The discharge amount increases in proportion to the size of the nozzle diameter. In addition, the distance between the object to be processed and the nozzle outlet is preferably as close as possible in order to drop it at a desired location, preferably about 0.1 to 3 mm (preferably about 1 mm or less). Set.

  A composition in which a conductive material is dissolved or dispersed in a solvent is used as the composition discharged from the discharge port. Conductive materials include metals such as Ag, Au, Cu, Ni, Pt, Pd, Ir, Rh, W, and Al, metal sulfides of Cd, Zn, Fe, Ti, Si, Ge, Si, Zr, Ba It corresponds to oxides such as silver halide fine particles or dispersible nanoparticles. Further, it corresponds to indium tin oxide (ITO) used as a transparent conductive film, ITSO composed of indium tin oxide and silicon oxide, organic indium, organic tin, zinc oxide, titanium nitride, and the like. A plurality of the aforementioned metal materials and the like may be mixed as the conductive layer material. However, it is preferable to use a composition in which any of gold, silver and copper is dissolved or dispersed in a solvent in consideration of the specific resistance value, more preferably the composition discharged from the discharge port. It is preferable to use low resistance silver or copper. However, when silver or copper is used, a barrier film may be provided as a countermeasure against impurities. As the barrier film, a silicon nitride film or nickel boron (NiB) can be used.

  Alternatively, particles in which a conductive material is coated with another conductive material to form a plurality of layers may be used. For example, particles having a three-layer structure in which nickel boron (NiB) is coated around copper and silver is coated around it may be used. As the solvent, esters such as butyl acetate and ethyl acetate, alcohols such as isopropyl alcohol and ethyl alcohol, organic solvents such as methyl ethyl ketone and acetone are used. The viscosity of the composition is preferably 20 mPa · s (cp) or less, in order to prevent the drying from occurring or to smoothly discharge the composition from the discharge port. The surface tension of the composition is preferably 40 mN / m or less. However, the viscosity and the like of the composition may be appropriately adjusted according to the solvent to be used and the application. As an example, the viscosity of a composition in which ITO, organic indium, or organic tin is dissolved or dispersed in a solvent is 5 to 20 mPa · s, the viscosity of a composition in which silver is dissolved or dispersed in a solvent is 5 to 20 mPa · s, The viscosity of the composition in which gold is dissolved or dispersed in a solvent is preferably set to 5 to 20 mPa · s.

  Further, the conductive film 101 to be the electrode layer may be formed by stacking a plurality of conductive materials. Alternatively, first, silver may be used as a conductive material, and a conductive layer may be formed by a droplet discharge method, followed by plating with copper or the like. The plating may be performed by electroplating or chemical (electroless) plating. For plating, the substrate surface may be immersed in a container filled with a solution having a plating material, but the substrate is placed at an angle (or vertically) so that the solution having the material to be plated flows on the substrate surface. It may be applied. When plating is performed so that the solution is applied while standing the substrate, there is an advantage that the process apparatus is reduced in size.

  Although depending on the diameter of each nozzle and the desired pattern shape, the diameter of the conductor particles is preferably as small as possible for preventing nozzle clogging and producing a high-definition pattern. 1 μm or less is preferable. The composition is formed by a known method such as an electrolytic method, an atomizing method, or a wet reduction method, and its particle size is generally about 0.01 to 10 μm. However, when formed in a gas evaporation method, the nanomolecules protected with the dispersant are as fine as about 7 nm. When the surface of each particle is covered with a coating agent, the nanoparticles are aggregated in the solvent. And stably disperse at room temperature and shows almost the same behavior as liquid. Therefore, it is preferable to use a coating agent.

  When the step of discharging the composition is performed under reduced pressure, the solvent of the composition is volatilized between the time of discharging the composition and landing on the object to be processed, and the subsequent drying and baking steps are omitted. be able to. Further, it is preferable to perform under reduced pressure because an oxide film or the like is not formed on the surface of the conductor. In addition, after discharging the composition, one or both steps of drying and baking are performed. The drying and firing steps are both heat treatment steps. For example, drying is performed at 100 degrees for 3 minutes, and firing is performed at 200 to 350 degrees for 15 minutes to 60 minutes. Time is different. The drying process and the firing process are performed under normal pressure or reduced pressure by laser light irradiation, rapid thermal annealing, a heating furnace, or the like. In addition, the timing which performs this heat processing is not specifically limited. In order to satisfactorily perform the drying and firing steps, the substrate may be heated, and the temperature at that time depends on the material of the substrate or the like, but is generally 100 to 800 degrees (preferably 200). ~ 350 degrees). By this step, the solvent in the composition is volatilized or the dispersant is chemically removed, and the surrounding resin is cured and contracted to bring the nanoparticles into contact with each other, thereby accelerating fusion and fusion.

For the laser light irradiation, a continuous-wave (CW: continuous-wave) or pulsed gas laser or solid-state laser may be used. Examples of the former gas laser include an excimer laser and a YAG laser, and examples of the latter solid-state laser include a laser using a crystal such as YAG, YVO ₄ or GdVO ₄ doped with Cr, Nd, or the like. . Note that it is preferable to use a continuous wave laser because of the absorption rate of the laser light. Further, a laser irradiation method combining pulse oscillation and continuous oscillation may be used. However, depending on the heat resistance of the substrate 100, the heat treatment by laser light irradiation may be performed instantaneously within a few microseconds to several tens of seconds so that the substrate 100 is not destroyed. Instantaneous thermal annealing (RTA) uses an infrared lamp or a halogen lamp that irradiates ultraviolet light or infrared light in an inert gas atmosphere, and rapidly raises the temperature for several minutes to several microseconds. This is done by applying heat instantaneously. Since this treatment is performed instantaneously, only the outermost thin film can be heated substantially without affecting the lower layer film. That is, it does not affect a substrate having low heat resistance such as a plastic substrate.

  Alternatively, after the conductive film 101 is formed by discharging a composition by a droplet discharge method, the surface may be pressed and flattened by pressure in order to improve the flatness. As a pressing method, unevenness may be reduced by scanning a roller-like object on the surface, or the surface may be pressed vertically with a flat plate-like object. A heating step may be performed when pressing. Alternatively, the surface may be softened or melted with a solvent or the like, and the surface irregularities may be removed with an air knife. Further, polishing may be performed using a CMP method. This step can be applied when the surface is flattened when unevenness is generated by the droplet discharge method. Further, the planarization step may be performed after the conductive film 101 is patterned by the mask 102a, the mask 102b, and the mask 102c and the gate electrode layer 103 and the first electrode layer 120 are formed.

    A resist mask is formed over the conductive film 101. The mask made of resist is finely processed by being exposed to laser light 170a, laser light 170b, and laser light 170c to form a mask 102a, a mask 102b, and a mask 102c (see FIG. 2). The resist for forming the mask in this embodiment is a negative resist that makes the exposed region insoluble in the etchant. Therefore, the region remaining as a mask is irradiated with laser light. A resist mask before processing by laser light can also be formed by a droplet discharge method. By combining the droplet discharge method, material loss can be prevented and costs can be reduced as compared to the entire surface coating formation by spin coating or the like.

  For the mask, a commercially available resist material containing a photosensitizer may be used. For example, a novolak resin that is a typical positive resist and a naphthoquinonediazide compound that is a photosensitizer, a base resin that is a negative resist, diphenylsilanediol In addition, an acid generator or the like may be used. Whichever material is used, the surface tension and viscosity are appropriately adjusted by adjusting the concentration of the solvent or adding a surfactant or the like. Further, when a conductive material containing a photosensitive material having photosensitivity is used for the conductive film 101, the conductive film 101 is directly irradiated with laser light without being formed with a resist mask, and is removed by exposure and etchant. Thus, it can be patterned into a desired pattern. In this case, there is an advantage that the process is simplified because it is not necessary to form a mask. The conductive material containing a photosensitive substance is a photosensitive material composed of a metal or alloy such as Ag, Au, Cu, Ni, Al, Pt, and an organic polymer resin, a photopolymerization initiator, a photopolymerization monomer, or a solvent. What contains a functional resin may be used. As the organic polymer resin, a novolak resin, an acrylic copolymer, a methacrylic copolymer, a cellulose derivative, a cyclized rubber resin, or the like is used.

    The conductive film 101 is patterned using the finely processed mask 102a, mask 102b, and mask 102c in this manner, so that the gate electrode layer 103, the gate electrode layer 104, and the first electrode layer 120 that becomes the pixel electrode layer are formed. (See FIG. 3).

Next, the gate insulating layer 105a and the gate insulating layer 105b are formed over the gate electrode layer 103, the gate electrode layer 104, and the first electrode layer 120 which serves as a pixel electrode layer. As the gate insulating layer 105a and the gate insulating layer 105b, silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), silicon nitride oxide (SiNxOy) (x> y), or the like is used as appropriate. be able to. Further, the gate electrode layer 103 and the gate electrode layer 104 may be anodized to form an anodized film instead of the gate insulating layer 105a. Note that in order to prevent diffusion of impurities and the like from the substrate side, the gate insulating layer 105a is preferably formed using silicon nitride (SiNx), silicon nitride oxide (SiNxOy) (x> y), or the like. The gate insulating layer 105b is preferably formed using silicon oxide (SiOx) or silicon oxynitride (SiOxNy) (x> y) because of interface characteristics with a semiconductor layer to be formed later. However, the present invention is not limited to this step, and it is formed of any one of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), silicon nitride oxide (SiNxOy) (x> y), and the like. It may be formed of a single layer. Note that the gate insulating layer 105b contains hydrogen. In addition, when silver or copper is used for a conductive layer formed by a droplet discharge method, if a silicon nitride film or a NiB film is formed thereon as a barrier film, diffusion of impurities can be prevented and the surface can be planarized. is there. Note that in order to form a dense insulating film with low gate leakage current at a low deposition temperature, a rare gas element such as argon is preferably contained in a reaction gas and mixed into the formed insulating film. In this embodiment, a gate insulating layer 105a is formed with a silicon nitride film having a thickness of 50 nm using SiH ₄ and NH ₃ as a reaction gas, and a silicon oxide film is formed with a film thickness of 100 nm using SiH ₄ and N ₂ O as a reaction gas. The insulating layer 105b is formed. The thickness of the silicon nitride oxide film may be 140 nm, the thickness of the stacked silicon oxynitride film may be 100 nm, and the thickness of the gate insulating layer 105a and the gate insulating layer 105b is preferably 50 nm to 100 nm, respectively.

    Next, a semiconductor film is formed. A detailed method for manufacturing the semiconductor layer will be described with reference to FIGS. Although FIG. 9 illustrates a method for manufacturing a thin film transistor formed over the gate electrode layer 103, a thin film transistor formed over the gate electrode layer 104 can be manufactured in a similar manner. The semiconductor film may be formed by a known means (a sputtering method, an LPCVD method, a plasma CVD method, or the like) with a thickness of 25 to 200 nm (preferably 30 to 150 nm). In this embodiment mode, it is preferable to use a crystallized semiconductor film obtained by crystallizing an amorphous semiconductor film.

    As a material for forming the semiconductor film, an amorphous semiconductor (hereinafter also referred to as “amorphous semiconductor: AS”) manufactured by a vapor deposition method or a sputtering method using a semiconductor material gas typified by silane or germane is used. A polycrystalline semiconductor obtained by crystallizing a crystalline semiconductor using thermal energy, a semi-amorphous (also referred to as microcrystal or microcrystal, hereinafter, also referred to as “SAS”) semiconductor, or the like can be used.

SAS is a semiconductor having an intermediate structure between amorphous and crystalline structures (including single crystal and polycrystal) and having a third state that is stable in terms of free energy and has a short-range order and a lattice. It includes a crystalline region with strain. A crystal region of 0.5 to 20 nm can be observed in at least a part of the film, and when silicon is the main component, the Raman spectrum shifts to a lower wave number side than 520 cm ^−1. Yes. In X-ray diffraction, diffraction peaks of (111) and (220) that are derived from the silicon crystal lattice are observed. In order to terminate dangling bonds (dangling bonds), hydrogen or halogen is contained at least 1 atomic% or more. The SAS is formed by glow discharge decomposition (plasma CVD) of a silicide gas. As the silicide gas, SiH ₄ , Si ₂ H ₆ , SiH ₂ Cl ₂ , SiHCl ₃ , SiCl ₄ , SiF _{4, and the} like can be used. Further, F ₂ and GeF ₄ may be mixed. This silicide gas may be diluted with H ₂ , or H ₂ and one or more kinds of rare gas elements selected from He, Ar, Kr, and Ne. The dilution rate is in the range of 2 to 1000 times, the pressure is in the range of approximately 0.1 Pa to 133 Pa, and the power supply frequency is 1 MHz to 120 MHz, preferably 13 MHz to 60 MHz. The substrate heating temperature is preferably 300 ° C. or lower, and can be formed even at a substrate heating temperature of 100 to 200 ° C. Here, as an impurity element mainly taken in at the time of film formation, it is desirable that impurities derived from atmospheric components such as oxygen, nitrogen, and carbon be 1 × 10 ²⁰ cm ⁻³ or less, and in particular, the oxygen concentration is 5 × 10 5. It is preferable to be ¹⁹ cm ⁻³ or less, preferably 1 × 10 ¹⁹ cm ⁻³ or less. Further, by adding a rare gas element such as helium, argon, krypton, or neon to further promote lattice distortion, stability is improved and a favorable SAS can be obtained. Further, a SAS layer formed of a gas containing hydrogen may be stacked on a SAS layer formed of a gas containing fluorine as the semiconductor film.

Note that in order to obtain a semiconductor film having a good crystal structure by subsequent crystallization, the concentration of impurities such as oxygen and nitrogen contained in the amorphous semiconductor film 403 shown in FIG. 9 is set to 5 × 10 ¹⁸ / cm 3. ³ (Hereinafter, all concentrations are shown as atomic concentrations measured by secondary ion mass spectrometry (SIMS)). These impurities are likely to react with the catalytic element, hinder subsequent crystallization, and increase the density of capture centers and recombination centers even after crystallization.

    In this embodiment mode, a thermal crystallization method using an element that promotes crystallization is used for an amorphous semiconductor film or a SAS film. As a heating method, there are RTA methods such as a GRTA (Gas Rapid Thermal Anneal) method using heated gas and an LRTA (Lamp Rapid Thermal Anneal) method using lamp light.

    The method of introducing the metal element into the amorphous semiconductor film is not particularly limited as long as the metal element can be present on the surface of the amorphous semiconductor film or inside the amorphous semiconductor film. For example, sputtering, CVD, Plasma treatment methods (including plasma CVD methods), adsorption methods, metal salt solution coating methods, ion implantation methods, and ion doping methods can be used. Among these, the method using a solution is simple and useful in that the concentration of the metal element can be easily adjusted. At this time, in order to improve the wettability of the surface of the amorphous semiconductor film and to spread the aqueous solution over the entire surface of the amorphous semiconductor film, irradiation with UV light in an oxygen atmosphere, thermal oxidation method, hydroxy radical It is desirable to form an oxide film by treatment with ozone water or hydrogen peroxide.

In this embodiment, an amorphous semiconductor film 403 is formed over the gate insulating layer 105b, and the amorphous semiconductor film 403 is crystallized, whereby the crystalline semiconductor film 405 is formed. As the amorphous semiconductor film 403, amorphous silicon formed using a reaction gas of SiH ₄ and H ₂ is used. In this embodiment mode, the gate insulating layer 105a, the gate insulating layer 105b, and the amorphous semiconductor film 403 are formed using the reactive gas at the same temperature (330 ° C. in this embodiment) without breaking the vacuum in the same chamber. Form continuously while cutting. Further, in this embodiment, after forming the gate insulating layer 105a and the gate insulating layer 105b, SiH ₄ reactive gas is allowed to flow without generating plasma in the chamber to remove oxygen in the chamber. Thereafter, an amorphous semiconductor film 403 is continuously formed. By removing oxygen in the chamber, the oxygen concentration in the amorphous semiconductor film 403 can be reduced to 5 × 10 ¹⁹ atom / cm ³ or lower, preferably 2 × 10 ¹⁹ atom / cm ³ or lower. Nickel added as an element is easily gettered. The thickness of the amorphous semiconductor film 403 is preferably 100 nm to 300 nm. In this embodiment mode, the amorphous semiconductor film 403 is formed with a thickness of 150 nm.

    After removing the oxide film formed on the amorphous semiconductor film, the oxide film is made 1 by irradiation with UV light in an oxygen atmosphere, a thermal oxidation method, treatment with ozone water containing hydrogen radicals or hydrogen peroxide, and the like. Form ~ 5 nm. In this embodiment mode, Ni is used as an element for promoting crystallization. An aqueous solution containing 10 ppm to 100 ppm (preferably 10 ppm to 50 ppm) of Ni element in terms of weight is applied by a spin coating method to form a metal film 404 (see FIG. 9A). As elements for promoting crystallization, metal elements for promoting crystallization of silicon include iron (Fe), nickel (Ni), cobalt (Co), ruthenium (Ru), rhodium (Rh), palladium (Pd). The metal film 404 can be formed using one kind or plural kinds selected from osmium (Os), iridium (Ir), platinum (Pt), copper (Cu), and gold (Au). The metal film 404 has an extremely thin film thickness depending on the formation conditions, and may not be kept in the form of a film. It may be formed in contact with the amorphous semiconductor film 403 so as to obtain an effect of promoting crystallization.

  Next, the amorphous semiconductor film is heated to form a crystalline semiconductor film 405. In this case, in crystallization, silicide is formed in the portion of the semiconductor film in contact with the metal element that promotes crystallization of the semiconductor, and crystallization proceeds using the silicide as a nucleus. Here, after the heat treatment for dehydrogenation, heat treatment for crystallization (550 ° C. to 650 ° C. for 5 minutes to 24 hours) is performed. Further, crystallization may be performed by RTA or GRTA. Here, by performing crystallization without laser light irradiation for heating, variation in crystallinity can be reduced, and variation in TFTs to be formed later can be suppressed.

    In this embodiment mode, the heat treatment is performed at 550 ° C. for 4 hours, but the heat treatment may be performed at 650 ° C. for 6 minutes by the RTA method.

The crystalline semiconductor film 405 thus obtained may be doped with a trace amount of an impurity element (boron or phosphorus) in order to control the threshold voltage of the thin film transistor. This doping of the impurity element may be performed on the amorphous semiconductor film before the crystallization process, or may be performed after the metal element in the crystalline semiconductor film 405 is reduced and removed by the gettering process. In this embodiment mode, boron is added by an ion doping method in which diborane (B ₂ H ₆ ) is plasma-excited without mass separation. Note that an ion implantation method in which mass separation is performed may be used. When the impurity element is doped in the state of the amorphous semiconductor film, the impurity can be activated by heat treatment for subsequent crystallization. In addition, defects and the like generated during doping can be improved.

    When crystallization using a metal element is performed, a gettering step is performed in order to reduce or remove the metal element. A semiconductor film is formed in contact with the crystalline semiconductor film 405 as a layer which sucks and takes in the metal element in the crystalline semiconductor film 405. In this embodiment, an amorphous semiconductor film containing an impurity element is formed as a gettering sink that captures a metal element. First, the oxide film formed over the crystalline semiconductor film 405 is removed by a cleaning process. Next, a semiconductor film 406a and a semiconductor film 406b are formed by a plasma CVD method. The thickness of the semiconductor film 406a is 30 to 100 nm (typically 40 to 60 nm), and the thickness of the semiconductor film 406b is 20 to 200 nm (typically 50 to 150 nm). The semiconductor film 406a and the semiconductor film 406b include an impurity element. As the impurity element, an impurity element imparting n-type conductivity, an impurity element imparting p-type conductivity, a rare gas element, or the like can be used, for example, phosphorus (P ), Nitrogen (N), arsenic (As), antimony (Sb), bismuth (Bi), boron (B), helium (He), neon (Ne), argon (Ar), Kr (krypton), Xe (xenon) 1 type or a plurality of types selected from. The n-type semiconductor layer containing the impurity element imparting n-type conductivity can be formed so as to contain a rare gas element such as argon. In this embodiment, the semiconductor film 406a and the semiconductor film 406b include an impurity element imparting n-type conductivity (in this embodiment, phosphorus is used). It is formed so as to be lower than the film 406b. The impurity element may be formed by a CVD method or the like so as to include the impurity element, or may be added by an ion doping method or the like after the semiconductor film is formed.

    The impurity profile of the semiconductor film containing the impurity element imparting n-type at this time is shown in FIG. FIG. 38A shows a profile 900a of an impurity element imparting n-type when the semiconductor films 901a and 901b containing an impurity element imparting n-type are formed over the crystalline semiconductor film 903 by a plasma CVD method. Show. The semiconductor film 901a and the semiconductor film 901b correspond to the semiconductor film 406a and the semiconductor film 406b, the semiconductor film 901a is formed as an n-type low-concentration impurity region (also referred to as an n− region), and the semiconductor film 901b is an n-type. Is formed as a high concentration impurity region (also referred to as an n + region). Therefore, an impurity element imparting a constant concentration of n-type in the depth direction is distributed in each of the semiconductor film 901a and the semiconductor film 901b, and the semiconductor film 901a has a lower concentration than the semiconductor film 901b. An impurity element imparting n-type is distributed. The semiconductor film 901b which is an n + region later functions as a source region and a drain region, and the semiconductor film 901a which is an n− region functions as an LDD (Lightly Doped Drain) region. Note that an interface exists because the n + region and the n− region are separately formed. The film thickness control of the n + region and the n− region can be achieved by controlling the film thickness of each concentration of semiconductor film.

    As the impurity element imparting p-type conductivity, boron is added to the semiconductor film 901a and the semiconductor film 901b formed in FIG. 38A by an ion doping method or an ion implantation method, so that the p-type when the semiconductor film 911 is formed is imparted. An impurity element profile 913 is shown in FIG. It can be seen that the concentration of the impurity element imparting p-type is higher than the concentration of the impurity element imparting n-type, and the semiconductor film 911 is a p-type semiconductor film. The impurity element imparting p-type conductivity is also added to the crystalline semiconductor film 903 because it is channel-doped. As shown in FIG. 39A, the vicinity of the surface of the semiconductor film 911 is a p-type impurity region (also referred to as a p + region) 912b having a relatively high concentration of an impurity element imparting p-type, As the crystalline semiconductor film 903 is approached, the concentration of the impurity element imparting p-type is relatively reduced, and a p-type low-concentration impurity region (also referred to as p-region) 912a is formed.

On the other hand, in FIG. 38B, a semiconductor film having a state selected from an amorphous semiconductor, a SAS, a microcrystalline semiconductor, and a crystalline semiconductor is formed over the crystalline semiconductor film 903, A profile 900b of an impurity element imparting n-type when the semiconductor film 902 is formed by adding an impurity element imparting n-type to the semiconductor film by an ion doping method or an ion implantation method is shown. As shown in FIG. 38B, the concentration of an impurity element imparting n-type conductivity is relatively high in the vicinity of the surface of the semiconductor film 902. A region where the concentration of an impurity element imparting n-type conductivity is 1 × 10 ¹⁹ / cm ³ or more is referred to as an n-type high-concentration impurity region (also referred to as an n + region) 904b. On the other hand, as the crystalline semiconductor film 903 is approached, the concentration of the impurity element imparting n-type decreases relatively. A region in which the concentration of an impurity element imparting n-type conductivity is 5 × 10 ¹⁷ to 1 × 10 ¹⁹ / cm ³ is referred to as an n-type low-concentration impurity region (also referred to as an n− region) 904a. The n + region 904b functions as a source region and a drain region later, and the n− region 904a functions as an LDD region. Note that there is no interface between the n + region and the n− region, and the occupied regions in the semiconductor film of the n + region and the n− region vary depending on the concentration of the impurity element imparting relative n-type. In this manner, the semiconductor film 902 including the impurity element imparting n-type formed by the ion doping method or the ion implantation method can control the concentration profile depending on the addition conditions, and the n + region and the n− region can be controlled. The film thickness can be appropriately controlled. By having the n + region and the n− region, the effect of relaxing the electric field is increased, and a thin film transistor with improved hot carrier resistance can be formed.

    Profile of the impurity element imparting p-type when boron is added as an impurity element imparting p-type to the semiconductor film 902 formed in FIG. 38B by an ion doping method or an ion implantation method. 923 is shown in FIG. The concentration of the impurity element imparting p-type is higher than the concentration of the impurity element imparting n-type, and the semiconductor film 921 is a p-type semiconductor film (also referred to as a semiconductor film having a p-type impurity region). I can see that The impurity element imparting p-type conductivity is also added to the crystalline semiconductor film 903 because it is channel-doped. As shown in FIG. 39B, the vicinity of the surface of the semiconductor film 921 is a p-type impurity region (also referred to as a p + region) 922b having a relatively high concentration of an impurity element imparting p-type conductivity, As the crystalline semiconductor film 903 is approached, the concentration of the impurity element imparting p-type is relatively reduced, and a p-type low-concentration impurity region (also referred to as p-region) 922a is formed. Further, in the step of adding an impurity element imparting n-type, the impurity element concentration on the film surface may be high depending on the addition conditions. In such a case, a process of adding an impurity element imparting p-type may be performed after the film surface is thinly etched and the film in the high impurity element concentration region is removed.

In this embodiment, as the semiconductor film 406a and the semiconductor film 406b, an n-type semiconductor film containing phosphorus which is an impurity element imparting n-type (donor type element) is formed by a plasma CVD method. Further, since the concentration of the impurity element imparting n-type contained in the semiconductor film 406a and the semiconductor film 406b is different, the semiconductor film 406a becomes an n-type low-concentration impurity region, and the semiconductor film 406b has an n-type high concentration. It is an impurity region. The impurity concentration of the n-type low-concentration impurity region is 1 × 10 ^{17 to} 3 × 10 ¹⁹ / cm ³ , preferably 1 × 10 ¹⁸ to 1 × 10 ¹⁹ / cm ³ , and the impurity concentration of the n-type high-concentration impurity region Is preferably 10 to 100 times, and can be 1 × 10 ^{19 to} 3 × 10 ²¹ / cm ³ . The thickness of the semiconductor film 406a which is an n-type low concentration impurity region is 20 to 200 nm, typically 50 to 150 nm. In this embodiment, the semiconductor film 406a is formed with a thickness of 50 nm. The thickness of the semiconductor film 406b which is an n-type high concentration impurity region is 30 to 100 nm, typically 40 to 60 nm. In this embodiment, the semiconductor film 406b is formed with a thickness of 50 nm.

Thereafter, heat treatment is performed to reduce or remove the metal element. As shown in FIG. 9C, the metal element in the crystalline semiconductor film 405 moves in the arrow direction by heat treatment, and is captured in the semiconductor film 406a and the semiconductor film 406b. The crystalline semiconductor film 405 is formed by removing a metal element in the film to be a crystalline semiconductor film 407, and the semiconductor film 406a and the semiconductor film 406b are a semiconductor film 408a and a semiconductor film 408b containing a metal element that promotes crystallization. In this embodiment, the semiconductor film 408a and the semiconductor film 408b include an impurity element imparting n-type conductivity and a metal element that promotes crystallization. By this step, the concentration at which an element that promotes crystallization in the crystalline semiconductor film (in this embodiment, nickel element) does not affect the device characteristics, that is, the nickel concentration in the film is 1 × 10 ¹⁸ / cm ³ or less. Desirably, it can be set to 1 × 10 ¹⁷ / cm ³ or less. In addition, the semiconductor film 408a and the semiconductor film 408b to which the metal element after gettering has moved may be crystallized by heat treatment. Note that in this embodiment, an impurity element imparting n-type conductivity (a donor element) in the semiconductor films 408a and 408b is activated along with the gettering step. The heat treatment may be performed in a nitrogen atmosphere. In this embodiment mode, the heat treatment is performed at 550 ° C. for 4 hours, but the heat treatment may be performed at 650 ° C. for 6 minutes by the RTA method.

    Next, the crystalline semiconductor film 407, the semiconductor film 408a, and the semiconductor film 408b are patterned using a mask. In this embodiment, a photomask is manufactured, and a semiconductor layer 107, an n-type semiconductor layer 109, and an n-type semiconductor layer 111 are formed by patterning treatment using a photolithography method (see FIG. 4). . Similarly, the semiconductor layer 106, the n-type semiconductor layer 108, and the n-type semiconductor layer 110 are also formed. As in the case of forming the mask 102a, a photomask may be formed by selectively forming a resist on the entire surface by spin coating or by a droplet discharge method, and forming a fine pattern mask by exposure by laser light irradiation. . The semiconductor film can be finely and finely patterned into a desired shape with a fine pattern mask.

    When the mask is formed by selectively discharging the composition without performing exposure processing, a resin material such as an epoxy resin, an acrylic resin, a phenol resin, a novolac resin, an acrylic resin, a melamine resin, or a urethane resin can be used. Also, using organic materials such as benzocyclobutene, parylene, flare, permeable polyimide, compound materials made by polymerization of siloxane polymers, composition materials containing water-soluble homopolymers and water-soluble copolymers, etc. It is formed by a droplet discharge method. Whichever material is used, the surface tension and viscosity are appropriately adjusted by adjusting the concentration of the solvent or adding a surfactant or the like.

As the etching process at the time of patterning, either plasma etching (dry etching) or wet etching may be employed, but plasma etching is suitable for processing a large area substrate. As an etching gas, a fluorine-based gas such as CF ₄ , NF ₃ , SF ₆ , or CHF ₃ , a chlorine-based gas typified by Cl ₂ , BCl ₃ , SiCl _4, or CCl ₄ , or an O ₂ gas is used. An inert gas such as He or Ar may be added as appropriate. Further, if an atmospheric pressure discharge etching process is applied, a local electric discharge process is also possible, and it is not necessary to form a mask layer on the entire surface of the substrate.

    A composition containing a conductive material is discharged to form a source or drain electrode layer 112, a source or drain electrode layer 113, a source or drain electrode layer 114, and a source or drain electrode layer 115. The semiconductor layer 106, a semiconductor having n-type conductivity, using the source or drain electrode layer 112, the source or drain electrode layer 113, the source or drain electrode layer 114, and the source or drain electrode layer 115 as a mask The layer 108, the n-type semiconductor layer 110, the semiconductor layer 107, the n-type semiconductor layer 109, and the n-type semiconductor layer 111 are patterned to form a semiconductor layer 146, an n-type semiconductor layer 148 a, and an n-type Semiconductor layer 148b having n-type, semiconductor layer 150a having n-type, semiconductor layer 150b having n-type, half Body layer 147, a semiconductor layer 149a having a n-type semiconductor layer 149b having a n-type semiconductor layer 151a having a n-type, a semiconductor layer 151b having a n-type (refer to FIG. 5.). The steps of forming the source or drain electrode layer 112, the source or drain electrode layer 113, the source or drain electrode layer 114, and the source or drain electrode layer 115 also include the gate electrode layer 103 and the gate electrode described above. It can be formed in the same manner as when the layer 104 is formed. The source or drain electrode layer 112 and the source or drain electrode layer 114 also function as a wiring layer.

  The conductive material for forming the source electrode layer or the drain electrode layer is mainly composed of metal particles such as Ag (silver), Au (gold), Cu (copper), W (tungsten), Al (aluminum). Compositions can be used. Further, light-transmitting indium tin oxide (ITO), ITSO made of indium tin oxide and silicon oxide, organic indium, organic tin, zinc oxide, titanium nitride, or the like may be combined.

  A method for forming the source electrode layer or the drain electrode layer will be described with reference to FIGS. The source or drain electrode layer 112, the source or drain electrode layer 113, the source or drain electrode layer 114, and the source or drain electrode layer 115 are formed in a fine pattern and formed with high controllability. Failure to do so will cause defects such as short circuits due to formation defects. Therefore, fine patterning on the semiconductor layer is performed by fine processing with a laser beam. As shown in FIG. 7A, a gate electrode layer 201a, a gate electrode layer 201b, a gate insulating layer 202a, a gate insulating layer 202b, a semiconductor layer 203a, a semiconductor layer 203b, an n-type semiconductor layer 204a, An n-type semiconductor layer 204b is formed, and a conductive film 205 is formed over the entire surface so as to cover them. The conductive film 205 can be formed by an evaporation method, a CVD method, a sputtering method, or the like. Thereafter, a mask 230 made of resist is formed.

  The resist mask 230 is irradiated with laser light 240a, laser light 240b, and laser light 240c and exposed to expose the regions 231a, 231b, and 231c (see FIG. 7B). Since a positive photosensitive resist is used in this embodiment mode, the exposed region 231a, region 231b, and region 231c are removed by an etchant, so that an opening 232a, an opening 232b, and an opening 232c are formed (FIG. 7 (C).) By patterning the conductive film 205 by etching using a mask having the openings 232a, 232b, and 232c, the source or drain electrode layer 208a, the source or drain electrode layer 208b, the source electrode layer or A drain electrode layer 208c and a source or drain electrode layer 208d are formed. With this source or drain electrode layer 208a, source or drain electrode layer 208b, source or drain electrode layer 208c, source or drain electrode layer 208d as a mask, the semiconductor layer 203a, the semiconductor layer 203b, and the n-type are formed. The semiconductor layer 204a, the n-type semiconductor layer 204b, and the semiconductor layer 206a, the semiconductor layer 206b, the n-type semiconductor layer 207a, the n-type semiconductor layer 207b, the n-type semiconductor layer 207c, and the n-type are etched. A semiconductor layer 207d including can be formed (see FIG. 7D). By forming a mask by fine processing with laser light and patterning the conductive film in this way, the conductive film can be patterned with high controllability and a desired shape of the source electrode layer and the drain electrode layer can be formed. Can do. Therefore, since the formation failure does not occur, the reliability of the thin film transistor is also improved.

    FIG. 8 is also a conductive film patterning method using an exposure process using laser light as in FIG. 7, but the conductive film 205 is not formed on the entire surface as in FIG. 7, but is selectively formed by a droplet discharge method. Indicates. After the semiconductor layer is formed as shown in FIG. 7A, the conductive film 215a and the conductive film 215b are selectively formed by the droplet discharge device 280a and the droplet discharge device 280b (see FIG. 8A). . Thereafter, the resist is similarly exposed by laser light to form a fine mask. Using the mask, the conductive film 215a and the conductive film 215b are finely patterned on the semiconductor channel formation region. In FIG. 8, the conductive film 215a and the conductive film 215b are selectively formed by the droplet discharge method without being in contact with each other, so that it is not necessary to form the opening 232b as shown in FIG. In addition, end portions of the source or drain electrode layer 218a, the source or drain electrode layer 218b, the source or drain electrode layer 218c, and the source or drain electrode layer 218d that are obtained because patterning by etching is not performed. Can have a rounded shape with a radius of curvature. Therefore, when the droplet discharge method is used, material loss is reduced and the process is simplified, so that there is an advantage in that cost is low and productivity is increased.

    After forming the source or drain electrode layer 112, the source or drain electrode layer 113, the source or drain electrode layer 114, and the source or drain electrode layer 115, as in the case of the gate electrode layer 103, press or the like You may perform the planarization process by. In addition to flattening the electrode layer, the source electrode layer or the drain electrode layer is included in the electrode layer by ejecting the source electrode layer or the drain electrode layer by a droplet discharge method and performing preliminary firing, and then sandwiching a pressing step during the main firing. The released oxygen is released and the oxygen concentration is lowered, so that the electrical resistance is also reduced.

    An insulating film 140 serving as a passivation film is preferably formed so as to cover the source or drain electrode layer, the semiconductor layer, the gate electrode layer, and the gate insulating layer. The insulating film 140 is formed using a thin film formation method such as a plasma CVD method or a sputtering method, and contains silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, aluminum oxynitride, or aluminum oxide, diamond-like carbon (DLC), and nitrogen. It can be formed using carbon (CN) or other insulating materials. Note that the passivation film may be a single layer or a laminated structure. Here, silicon oxide or silicon oxynitride is formed from the interface characteristics of the semiconductor layer 146 and the semiconductor layer 147, and then silicon nitride or silicon nitride oxide is formed to prevent external impurities from entering the semiconductor element. A laminated structure is preferable. In this embodiment mode, a silicon oxide film having a thickness of 150 nm is formed in contact with the semiconductor layer 146 and the semiconductor layer 147, and then gas switching is performed in the same chamber to continuously form a silicon nitride film having a thickness of 200 nm. Then, the insulating film 140 is formed.

    Thereafter, the semiconductor layer 146 and the semiconductor layer 147 are preferably hydrogenated by heating in a hydrogen atmosphere or a nitrogen atmosphere. Note that an insulating film containing hydrogen is preferably formed as the insulating film 140 in the case of heating in a nitrogen atmosphere.

    Next, the insulating layer 116 is formed. In this embodiment mode, the insulating layer 116 is formed over the entire surface, and is etched and patterned with a mask such as a resist. When the insulating layer 116 is formed using a droplet discharge method, a printing method, or the like that can be directly and selectively formed, patterning by etching is not necessarily required. In this embodiment mode, an insulating layer 116 is provided as an interlayer insulating layer, and a second sensitizing layer functioning as a partition is provided. In this case, the insulating layer 116 can also be said to be a first insulating layer.

    The insulating layer 116 includes silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, diamond-like carbon (DLC), nitrogen-containing carbon film (CN), other inorganic insulating materials, or acrylic acid, Methacrylic acid and derivatives thereof, or polyimide, aromatic polyamide, polybenzimidazole, polybenzoimidazole, benzocyclobutene, polysilazane, or other organic insulating materials, or silicon formed using a siloxane material as a starting material, oxygen, Among compounds composed of hydrogen, an inorganic siloxane containing a Si—O—Si bond, or an organic siloxane insulating material in which hydrogen on silicon is substituted with an organic group such as methyl or phenyl can be used. You may form using photosensitive and non-photosensitive materials, such as an acryl and a polyimide.

    In this embodiment mode, a siloxane resin may be used as the material of the insulating layer 116. Note that a siloxane resin corresponds to a resin including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent.

    An opening 136 reaching the source or drain electrode layer 113 and an opening 138 reaching the source or drain electrode layer 115 are formed in the insulating film 140 and the insulating layer 116 with a gate insulating layer 105a, a gate insulating layer 105b, An opening 139 reaching the first electrode layer 120, an opening 135 reaching the gate electrode layer 103, and an opening 137 reaching the gate electrode layer 104 are formed in the film 140 and the insulating layer 116. This opening is also formed by etching using a resist mask. The mask used for patterning can be a mask having a fine shape by performing exposure by laser light irradiation. A wiring layer 119 is formed in the opening 138 and the opening 139 thus formed, and the source or drain electrode layer 115 and the first electrode layer 120 are electrically connected. A wiring layer 118 is formed in the opening 136 and the opening 137, and the source or drain electrode layer 113 and the gate electrode layer 104 are electrically connected. A gate wiring layer 117 is also formed in the opening 135 so as to be electrically connected to the gate electrode layer 103. By forming the gate wiring layer 117 with a low-resistance material, high-speed operation is possible even when the gate electrode layer 103 is a slightly high-resistance material, and a large current can flow.

    Through the above steps, a TFT substrate for a display panel in which a bottom gate type (also referred to as an inverted staggered type) thin film transistor and a pixel electrode are connected to the substrate 100 is completed. The thin film transistor of this embodiment mode is a channel etch type.

    Next, an insulating layer 121 (also referred to as a partition wall or a bank) is selectively formed. The insulating layer 121 is formed over the first electrode layer 120 so as to have an opening and covers the wiring layer 119. In this embodiment mode, the insulating layer 121 is formed over the entire surface, and is etched and patterned with a mask such as a resist. When the insulating layer 121 is formed using a droplet discharge method, a printing method, or the like that can be directly and selectively formed, patterning by etching is not necessarily required. The insulating layer 121 can also be formed in a desired shape by the pretreatment of the present invention.

    The insulating layer 121 is formed using silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, or other inorganic insulating materials, or acrylic acid, methacrylic acid, and derivatives thereof, polyimide, aromatic Heat-resistant polymers such as polyamide, polybenzimidazole, or inorganic siloxanes containing Si-O-Si bonds among silicon, oxygen, and hydrogen compounds formed from siloxane materials, hydrogen on silicon Can be formed of an organic siloxane insulating material substituted with an organic group such as methyl or phenyl. You may form using photosensitive and non-photosensitive materials, such as an acryl and a polyimide. The insulating layer 121 preferably has a shape in which the radius of curvature continuously changes, and the coverage of the electroluminescent layer 122 and the second electrode layer 123 formed thereon is improved.

    Alternatively, after the insulating layer 121 is formed by discharging a composition by a droplet discharge method, the surface may be pressed and flattened by pressure in order to improve the flatness. As a pressing method, unevenness may be reduced by scanning a roller-like object on the surface, or the surface may be pressed vertically with a flat plate-like object. Alternatively, the surface may be softened or melted with a solvent or the like, and the surface irregularities may be removed with an air knife. Further, polishing may be performed using a CMP method. This step can be applied when the surface is flattened when unevenness is generated by the droplet discharge method. When flatness is improved by this step, display unevenness of the display panel can be prevented and a high-definition image can be displayed.

    A light-emitting element is formed so as to be electrically connected to the thin film transistor (see FIG. 1).

    Before forming the electroluminescent layer 122, heat treatment is performed at 200 ° C. under atmospheric pressure to remove moisture adsorbed in the first electrode layer 120 and the insulating layer 121 or on the surface thereof. In addition, it is preferable to perform heat treatment at 200 to 400 ° C., preferably 250 to 350 ° C. under reduced pressure, and to form the electroluminescent layer 122 by vacuum deposition or droplet discharge under reduced pressure without being exposed to the air as it is. .

    As the electroluminescent layer 122, materials that emit red (R), green (G), and blue (B) light are selectively formed by an evaporation method using an evaporation mask or the like. A material that emits red (R), green (G), and blue (B) light can be formed by a droplet discharge method (such as a low-molecular or high-molecular material) in the same manner as a color filter. In this case, a mask is not used. Both are preferable because RGB can be separately applied. A second electrode layer 123 is stacked over the electroluminescent layer 122 to complete a display device having a display function using a light emitting element.

Although not shown, it is effective to provide a passivation film so as to cover the second electrode layer 123. The protective film provided when forming the display device may have a single layer structure or a multilayer structure. As the passivation film, silicon nitride (SiN), silicon oxide (SiO ₂ ), silicon oxynitride (SiON), silicon nitride oxide (SiNO), aluminum nitride (AlN), aluminum oxynitride (AlON), nitrogen content is oxygen It is composed of an insulating film containing aluminum nitride oxide (AlNO) or aluminum oxide, diamond-like carbon (DLC), or nitrogen-containing carbon film (CN _x ) that is higher than the content, and a single layer or a combination of insulating films is used. it can. For example, a laminate such as a nitrogen-containing carbon film (CN _x ) and silicon nitride (SiN), an organic material can be used, and a polymer laminate such as a styrene polymer may be used. A siloxane resin may also be used.

At this time, it is preferable to use a film with good coverage as the passivation film, and it is effective to use a carbon film, particularly a DLC film. Since the DLC film can be formed in a temperature range from room temperature to 100 ° C., it can be easily formed over the electroluminescent layer having low heat resistance. The DLC film is formed by a plasma CVD method (typically, an RF plasma CVD method, a microwave CVD method, an electron cyclotron resonance (ECR) CVD method, a hot filament CVD method, etc.), a combustion flame method, a sputtering method, or an ion beam evaporation method. It can be formed by laser vapor deposition. A reactive gas used for film formation is hydrogen gas and a hydrocarbon gas (for example, CH ₄ , C ₂ H ₂ , C ₆ H _6, etc.), ionized by glow discharge, and a negative self-biased cathode. The film is formed by accelerating and colliding ions. The CN film may be formed using C ₂ H ₄ gas and N ₂ gas as the reaction gas. The DLC film has a high blocking effect against oxygen and can suppress oxidation of the electroluminescent layer. Therefore, the problem that the electroluminescent layer is oxidized during the subsequent sealing process can be prevented.

  Subsequently, a sealing material is formed and sealed using a sealing substrate. After that, a flexible wiring board may be connected to a gate wiring layer formed by being electrically connected to the gate electrode layer 103 to be electrically connected to the outside. The same applies to the source wiring layer formed by being electrically connected to the source or drain electrode layer 112 and the source or drain electrode layer 114 which are also the source wiring layers.

  Subsequently, a wiring board for connection is provided so that the wiring layer in the display device is electrically connected via the anisotropic conductor layer. The wiring board plays a role of transmitting signals and potentials from the outside, and FPC (Flexible printed circuit) or the like can be used. Through the above process, a display panel including a channel etch type switching TFT, a driving TFT, and a capacitor is completed. The capacitor is formed of the source or drain electrode layer 114 and the gate insulating layer 105a, and the gate insulating layer 105b and the gate electrode layer 104.

    The wiring layer in the display device and the FPC are connected using a terminal electrode layer. The terminal electrode layer is the same material and process as the gate electrode layer, and the same material and process as the source wiring layer that also serves as the source electrode layer and the drain electrode layer. The gate wiring layer and the same material can be manufactured in the same process. A connection example between the FPC and a wiring layer in the display device will be described with reference to FIG.

    In FIG. 43, a first electrode layer 6 provided with a thin film transistor 9 and a light emitting element is formed on a substrate 1, and is bonded to a counter substrate 8 with a sealant 3. A wiring layer extending from the inside of the display device and formed outside the sealant is bonded to the FPC 2b and FPC 2a by an anisotropic conductive film 7a and an anisotropic conductive film 7b.

    43 (A1), (B1), and (C1) are top views of the display device, and FIGS. 43 (A2), (B2), and (C2) are in FIGS. 43 (A1), (B1), and (C1). It is sectional drawing of line OP and line RQ. 43A1 and 43A2, the terminal electrode layer 5a and the terminal electrode layer 5b are formed of the same material and the same process as the gate electrode layer. A source wiring layer 4a formed to extend to the outside of the sealing material is connected to the terminal electrode layer 5a, and the terminal electrode layer 5a and the FPC 2a are connected via an anisotropic conductive film 7a. On the other hand, a gate wiring layer 4b formed to extend to the outside of the sealing material is connected to the terminal electrode layer 5b, and the terminal electrode layer 5b and the FPC 2b are connected via an anisotropic conductive film 7b.

    43B1 and 43B2, the terminal electrode layer 55a and the terminal electrode layer 55b are formed of the same material and step as the source wiring layer. The terminal electrode layer 55a is formed of a source wiring layer formed to extend to the outside of the sealing material, and the terminal electrode layer 55a and the FPC 2a are connected via an anisotropic conductive film 7a. On the other hand, a gate wiring layer 54b formed to extend to the outside of the sealing material is connected to the terminal electrode layer 55b, and the terminal electrode layer 55b and the FPC 2b are connected via an anisotropic conductive film 7b.

    43 (C1) and 43 (C2), the terminal electrode layer 64a and the terminal electrode layer 64b are formed of the same material and process as the gate wiring layer. A terminal electrode layer 64a is connected to a source wiring layer 65a formed to extend outside the sealing material, and the terminal electrode layer 64a and the FPC 2a are connected via an anisotropic conductive film 7a. On the other hand, the terminal electrode layer 64b is formed of a gate wiring layer formed to extend to the outside of the sealing material, and the terminal electrode layer 64b and the FPC 2b are connected via the anisotropic conductive film 7b.

  In this embodiment mode, the switching TFT has a single gate structure, but a multi-gate structure such as a double gate structure may be used.

Through the above steps, an inverted staggered thin film transistor having a crystalline semiconductor film can be formed. Since the thin film transistor formed in this embodiment is formed using a crystalline semiconductor film, it has higher mobility (about ^{2 to} 50 cm ² / Vsec) than a thin film transistor formed using an amorphous semiconductor film. In addition to the impurity element imparting one conductivity type, the source region and the drain region also include a metal element having a function of promoting crystallization. For this reason, a source region and a drain region with low resistivity can be formed. As a result, a display device capable of high speed operation can be manufactured.

  Further, compared with a thin film transistor formed using an amorphous semiconductor film, a threshold shift is less likely to occur, and variations in thin film transistor characteristics can be reduced.

  Further, since the metal element mixed in the semiconductor film in the film formation stage is also gettered by the gettering step, off current can be reduced. For this reason, it is possible to improve contrast by providing such a TFT in a switching element of a display device.

    In addition, it is possible to freely design thinning of wirings and the like by fine processing of laser light irradiation. According to the present invention, a desired pattern can be formed with good controllability, material loss is small, and cost reduction can be achieved. Therefore, a high-performance and highly reliable display device can be manufactured with high yield.

(Embodiment 2)
An embodiment of the present invention will be described with reference to FIG. This embodiment is an example in which the gettering process of the crystalline semiconductor film is different from that in Embodiment 1. Therefore, repetitive description of the same portion or a portion having a similar function is omitted.

    A gate electrode layer 401 is formed over the substrate 400, and a gate insulating layer 402a and a gate insulating layer 402b are formed so as to cover the gate electrode layer 401. An amorphous semiconductor film 403 is formed over the gate insulating layer 402b, and a metal film 404 is formed (see FIG. 10A). After that, the amorphous semiconductor film 403 is crystallized by heat treatment, so that a crystalline semiconductor film 405 is formed (see FIG. 10B).

    In this embodiment, the semiconductor layer 421 including a rare gas element as an impurity element is formed as a gettering layer for gettering a metal element included in the crystalline semiconductor film 405 for promoting crystallization. As the rare gas element, helium, argon, xenon, krypton, or the like can be used. In this embodiment, a semiconductor film containing argon as an impurity element is formed. After that, the metal element contained in the crystalline semiconductor film 405 is moved in the direction of the arrow in FIG. Accordingly, a crystalline semiconductor film 423 in which metal elements contained in the film are reduced is formed. Then, the semiconductor film 422 serving as a gettering sink and the oxide film formed over the semiconductor film 422 are removed with hydrofluoric acid or the like, so that the crystalline semiconductor film 423 from which the metal element is reduced or removed can be obtained. it can. In this embodiment mode, the semiconductor film 422 serving as a gettering sink is removed using TMAH (Tetramethyl ammonium hydroxide). A semiconductor film 424 having one conductivity type is formed over the crystalline semiconductor film 423 as illustrated in FIG. 10D and patterned, and then a source or drain electrode layer 425a, a source or drain electrode layer 425b is formed. (See FIG. 10E). In this embodiment, an n-type semiconductor film containing P which is an impurity element imparting n-type conductivity is formed as the semiconductor film 424 having one conductivity type.

    The n-type semiconductor film and the crystalline semiconductor film are etched using the source or drain electrode layer 425a and the source or drain electrode layer 425b as a mask, and the n-type functioning as the semiconductor layer 426 and the source or drain region is formed. A semiconductor layer 427a and an n-type semiconductor layer 427b are formed (see FIG. 10F).

    Through the above steps, a crystalline semiconductor film crystallized with a metal element is gettered, the semiconductor layer has a semiconductor layer with reduced metal element, and the semiconductor layer has one conductivity type that functions as a source region or a drain region. A thin film transistor containing no metal element can be formed.

    The thin film transistor illustrated in FIG. 9 in Embodiment Mode 1 and FIG. 10 in this embodiment mode is a thin film transistor having one conductivity type, but two or more thin film transistors may be manufactured in the same step. it can. For example, a circuit can be configured with NMOS by forming a plurality of n-channel thin film transistors and electrically connecting them, and a PMOS can be formed by forming a plurality of p-channel thin film transistors and electrically connecting them similarly. A circuit can be constructed. In addition, a CMOS structure in which an n-channel thin film transistor and a p-channel thin film transistor are electrically connected can be formed, and a display device is manufactured by incorporating such NMOS, PMOS, or CMOS in a pixel region or a drive region. Can do.

    This embodiment can be used in combination with Embodiment 1.

(Embodiment 3)
An embodiment of the present invention will be described with reference to FIG. This embodiment is an example of manufacturing two types of thin film transistors: an n-channel thin film transistor and a p-channel thin film transistor. Therefore, repetitive description of the same portion or a portion having a similar function is omitted.

  A gate electrode layer 431a and a gate electrode layer 431b are formed over the substrate 430, and a gate insulating layer 433a and a gate insulating layer 433b are formed. An amorphous semiconductor film is formed over the gate insulating layer 433b, a metal element is added, and heat crystallization is performed to form a crystalline semiconductor film. An n-type semiconductor film 435 is formed over the crystalline semiconductor film and heated (see FIG. 11A).

  By the heat treatment, the metal element contained in the crystalline semiconductor film is gettered, moved to and trapped in the n-type semiconductor film 435 in the direction of the arrow, and the crystalline semiconductor film 434 is formed. The crystalline semiconductor film 434 and the n-type semiconductor film 435 are patterned to form a semiconductor layer 436a, a semiconductor layer 436b, and an n-type semiconductor layer 437. After that, a mask 438a covering the semiconductor layer 436a and the n-type semiconductor layer 437 and a mask 438b covering the n-type semiconductor layer 444 over the channel formation region in the semiconductor layer 436b are formed, and an impurity element imparting p-type conductivity 439 is added to the n-type semiconductor layer. The semiconductor layer having n-type conductivity is added to the p-type semiconductor layer by adding the impurity element imparting p-type so that the concentration is 2 to 10 times the concentration of the impurity element imparting n-type. The type is inverted, so that a p-type impurity region 445a and a p-type impurity region 445b can be formed (see FIG. 11B).

  The source or drain electrode layer 440a, the source or drain electrode layer 440b, the source or drain electrode layer 440c, and the source or drain electrode layer 440d are formed by a droplet discharge method and fine exposure with laser light. (See FIG. 11C.) Using the source or drain electrode layer 440a, the source or drain electrode layer 440b, the source or drain electrode layer 440c, and the source or drain electrode layer 440d as a mask, the semiconductor layer 436a, the semiconductor layer 436b, and the n-type The semiconductor layer 437 having n type and the semiconductor layer 444 having n type are etched, and the semiconductor layer 442a, the semiconductor layer 442b, the semiconductor layer 443a having n type, the semiconductor layer 443b having n type, the semiconductor layer 443c having p type, and the p type A semiconductor layer 443d including can be formed (see FIG. 11D). Etching of the semiconductor layer and the n-type semiconductor layer may be performed in a state where a resist mask formed at the time of patterning the source electrode layer or the drain electrode layer is provided. Etching may be performed by dry etching or wet etching, the source electrode layer or the drain electrode layer may be etched by wet etching using an etchant, and the semiconductor layer may be etched by dry etching.

    Through the above steps, an n-channel thin film transistor and a p-channel thin film transistor can be formed over the same substrate. In addition, a CMOS structure can be obtained by electrically connecting an n-channel thin film transistor and a p-channel thin film transistor, and a display device can be manufactured by incorporating this CMOS structure in a pixel region and a driver circuit region.

    This embodiment can be used in combination with each of Embodiment 1 and Embodiment 2.

(Embodiment 4)
An embodiment of the present invention will be described with reference to FIG. This embodiment is an example of manufacturing two types of thin film transistors: an n-channel thin film transistor and a p-channel thin film transistor. Therefore, repetitive description of the same portion or a portion having a similar function is omitted.

  A gate electrode layer 451a and a gate electrode layer 451b are formed over the substrate 450, and a gate insulating layer 452a and a gate insulating layer 452b are formed. An amorphous semiconductor film is formed over the gate insulating layer 452b, and a metal element is added to be crystallized by heating to form a crystalline semiconductor film. A semiconductor film 454 containing a rare gas element as an impurity element is formed over the crystalline semiconductor film and heated (see FIG. 12A).

  By the heat treatment, the metal element contained in the crystalline semiconductor film is gettered, moved and captured in the semiconductor film 454 having a rare gas element in the direction of the arrow, and the crystalline semiconductor film 453 is formed. The semiconductor film 454 used as the gettering sink is removed by etching. The crystalline semiconductor film 453 is patterned, a mask 456a covering the channel formation region 455a and a mask 456b covering the semiconductor layer 455b are formed, an impurity element 458 imparting n-type conductivity is added, and n-type impurity regions 457a and n-type are added. The impurity region 457b is formed (see FIG. 12B).

  The mask 456a and the mask 456b are removed, and a mask 459a covering the n-type impurity region 457a, the channel formation region 455a, the n-type impurity region 457b, and a mask 459b covering the channel formation region 463 are newly formed. An impurity element 461 to be added is added. A p-type impurity region 460a and a p-type impurity region 460b are formed using an impurity element imparting p-type (see FIG. 12C). The n-type impurity region 457a, the n-type impurity region 457b, the p-type impurity region 460a, and the p-type impurity region 460b function as a source region or a drain region. A source or drain electrode layer 462a, a source or drain electrode layer 462b, a source or drain electrode layer 462c, and a source or drain electrode layer 462d are formed in contact with the source or drain region (FIG. 12). (See (D).)

    Through the above steps, an n-channel thin film transistor and a p-channel thin film transistor can be formed over the same substrate. In addition, a CMOS structure can be obtained by electrically connecting an n-channel thin film transistor and a p-channel thin film transistor, and a display device can be manufactured by incorporating this CMOS structure in a pixel region and a driver circuit region. According to this embodiment mode, the number of film formation steps can be reduced as compared with Embodiment Mode 3, and thus throughput can be improved.

(Embodiment 5)
An embodiment of the present invention will be described with reference to FIG. This embodiment is an example in which two types of thin film transistors, an n-channel thin film transistor and a p-channel thin film transistor, are manufactured, and the gettering process is different. Therefore, repetitive description of the same portion or a portion having a similar function is omitted.

  A gate electrode layer 471a and a gate electrode layer 471b are formed over the substrate 470, and a gate insulating layer 472a and a gate insulating layer 472b are formed. An amorphous semiconductor film is formed over the gate insulating layer 472b, and a metal element is added to be crystallized by heating to form a crystalline semiconductor film. The crystalline semiconductor film is patterned to form a semiconductor layer 473a and a semiconductor layer 473b (see FIG. 13A).

  A mask 474a covering the channel formation region 483a and a mask 474b covering the channel formation region 483b are formed, an n-type impurity element 476 is added, and an n-type impurity region 475a, an n-type impurity region 475b, and an n-type impurity region 475b are added. An impurity region 475c and an n-type impurity region 475d are formed (see FIG. 13B). Thereafter, heat treatment is performed.

    By the heat treatment, the metal elements contained in the channel formation region 483a and the channel formation region 483b in the semiconductor layer are gettered, and the n-type impurity region 477a, the n-type impurity region 477b, and the n-type impurity are respectively illustrated in the directions of the arrows. The channel formation region 478a and the channel formation region 478b from which the metal element is removed and reduced are formed by moving to and capture the region 477c and the n-type impurity region 477d (see FIG. 13C). In addition, the added impurity element imparting n-type can be activated by this heat treatment.

  A mask 479a covering the n-type impurity region 477a, the channel formation region 478a, and the n-type impurity region 477b and a mask 479b covering the channel formation region 478b are formed, and an impurity element 481 imparting p-type conductivity is added. A p-type impurity region 480a and a p-type impurity region 480b are formed using an impurity element imparting p-type (see FIG. 13D). The n-type impurity region 477a, the n-type impurity region 477b, the p-type impurity region 480a, and the p-type impurity region 480b function as a source region or a drain region. A source or drain electrode layer 482a, a source or drain electrode layer 482b, a source or drain electrode layer 482c, and a source or drain electrode layer 482d are formed in contact with the source or drain region (FIG. 13). (See (D).)

    Through the above steps, an n-channel thin film transistor and a p-channel thin film transistor can be formed over the same substrate. In addition, a CMOS structure can be obtained by electrically connecting an n-channel thin film transistor and a p-channel thin film transistor, and a display device can be manufactured by incorporating this CMOS structure in a pixel region and a driver circuit region. According to this embodiment mode, the number of film forming steps can be reduced as compared with Embodiment Mode 3, and thus throughput can be improved.

(Embodiment 6)
This embodiment will be described with reference to FIGS. In this embodiment mode, the pixel region is the pixel region manufactured in Embodiment Mode 1, the peripheral driver circuit region is also manufactured using the thin film transistor using the present invention, and the n-channel thin film transistor and p-channel device manufactured in Embodiment Mode 2 are used. A CMOS comprising a thin film transistor is applied. Therefore, repetitive description of the same portion or a portion having a similar function is omitted.

    FIG. 19 is a top view of a pixel region of a display device manufactured in this embodiment mode. FIGS. 14 to 17 and FIG. 18B are cross-sectional views taken along lines AC and BD in FIG. Corresponds to the figure. 14 to 17 are cross-sectional views corresponding to a line IJ which is a peripheral driver circuit region of the display device in FIG. 18A.

  A conductive film is formed over the substrate 300 and patterned using a resist mask, and the gate electrode layer 301, the gate electrode layer 302, the gate electrode layer 303, the gate electrode layer 360a, the gate electrode layer 360b, and the first electrode layer 304 are formed. (Also referred to as a pixel electrode layer) is formed. In this embodiment mode, the gate electrode layer is formed using a single layer of a transparent conductive film, but may have a stacked structure. As the laminated structure, it is possible to use a laminated film of Ta, Ti, W, Mo, Cr, nitride films of the above elements, specifically, a laminated film of TaN and W, a laminated film of TaN and Mo, or a TaN and Cr film. , TiN and W, TiN and Mo, TiN and Cr, and the like can be used. In this embodiment, a composition containing indium tin oxide containing silicon oxide (ITSO) is discharged by a droplet discharge method, and baked to form a conductive film in the vicinity including the gate electrode layer formation region. This conductive film is precisely patterned using a mask finely processed by exposure with laser light, and the gate electrode layer 301, the gate electrode layer 302, the gate electrode layer 303, the gate electrode layer 360a, the gate electrode layer 360b, One electrode layer 304 is formed.

    A gate insulating layer is formed over the gate electrode layer 301, the gate electrode layer 302, the gate electrode layer 303, the gate electrode layer 360a, the gate electrode layer 360b, and the first electrode layer 304, and an amorphous semiconductor film is formed over the gate insulating layer 306 is formed. In this embodiment, a gate insulating layer 305a made of silicon nitride and a gate insulating layer 305b made of silicon oxide are stacked as the gate insulating layer. As the amorphous semiconductor film 306, an amorphous silicon film is used. The gate insulating layer 305a, the gate insulating layer 305b, and the amorphous semiconductor film 306 are continuously formed by only plasma gas switching by a plasma CVD method. By forming continuously, a process is simplified and it can prevent that the pollutant in air | atmosphere adheres to the film | membrane surface and an interface.

    As a method for introducing an element which promotes and promotes crystallization, a metal film 307 is formed over the amorphous semiconductor film 306 (see FIG. 14A). Since the metal film 307 is very thin, the shape as a film may not be maintained. In this embodiment, an aqueous solution containing 30 ppm of Ni is applied by a spin coating method to form the metal film 307. The amorphous semiconductor film 306 coated with the metal film 307 is heated and crystallized. In this embodiment, heat treatment is performed at 550 ° C. for 8 hours, so that the crystalline semiconductor film 309 is formed.

    An n-type semiconductor film 308 is formed over the crystalline semiconductor film 309 (see FIG. 14B). In this embodiment, as the semiconductor film 308 having n-type, an amorphous silicon film containing phosphorus (P) as an impurity element imparting n-type is formed to a thickness of 100 nm by a plasma CVD method. Heat treatment is performed using the n-type semiconductor film 308 as a gettering sink, so that the metal element in the crystalline semiconductor film 309 is gettered (see FIG. 14C). In this embodiment, heat treatment is performed at 550 ° C. for 4 hours. The metal element in the crystalline semiconductor film 309 moves in the direction of the arrow by heat treatment, and is captured in the n-type semiconductor film 308. Therefore, the crystalline semiconductor film 309 becomes the crystalline semiconductor film 310 in which the metal element in the film is reduced, and the n-type semiconductor film 308 includes an impurity element imparting n-type (P in this embodiment). An n-type semiconductor film 311 containing a metal element (Ni in this embodiment) is formed.

    The crystalline semiconductor film 310 and the n-type semiconductor film 311 are patterned to form a semiconductor layer 312, a semiconductor layer 313, a semiconductor layer 314, a semiconductor layer 361, an n-type semiconductor layer 315, an n-type semiconductor layer 316, n A semiconductor layer 317 having a type and a semiconductor layer 362 having an n-type can be formed (see FIG. 15A). The patterning of these semiconductor layers can also be performed precisely using a mask finely processed by exposure with the laser beam of the present invention.

    Next, the mask 318a covering the semiconductor layer 312, the n-type semiconductor layer 315, the channel formation region of the semiconductor layer 313 and the mask 318b covering the channel formation region of the n-type semiconductor layer 316, the semiconductor layer 314, and the n-type are formed. A mask 318c covering the semiconductor layer 317, a semiconductor layer 361, and a mask 318d covering the n-type semiconductor layer 362 are formed. An impurity element 319 imparting p-type conductivity is added to form a p-type impurity region 320a and a p-type impurity region 320b in the n-type semiconductor layer 316 (see FIG. 15B). In this embodiment, an impurity element imparting p-type conductivity (boron (B) in this embodiment) is added by an ion doping method. After that, heat treatment is performed at 550 ° C. for 4 hours to activate the impurity element addition region.

    In this embodiment mode, a CMOS structure is used in the drive circuit area to function as an inverter. In the case of only PMOS and NMOS only, the gate electrode layer of some TFTs and the source electrode layer or drain electrode layer are connected. Such an example is shown in FIG. A part of the gate insulating layer 305a and the gate insulating layer 305b is etched using a photomask to form a contact hole 890 as shown in FIG. In this embodiment mode, the first electrode layer to be the pixel electrode layer is connected to the source electrode layer or the drain electrode layer through a contact hole formed in the insulating layer. The first electrode layer may be connected without an insulating layer. In this case, an opening reaching the first electrode layer can be formed at the same time as the contact hole 890. After that, a source electrode layer or a drain electrode layer is formed in these contact holes and electrically connected to the gate electrode layer or the first electrode layer, respectively. By connecting the source or drain electrode layer 327b and the gate electrode layer 302, a thin film transistor 335 and a thin film transistor 336 to be formed later can function as an inverter even if they are NMOS transistors and PMOS transistors. As described above, in this embodiment mode, the thin film transistor 335 and the thin film transistor 336 have a CMOS structure, and thus can function as an inverter without using the structure shown in FIG.

    After the mask 318a, the mask 318b, and the mask 318c are removed, the conductive layer 321, the conductive layer 322, and the conductive layer 363 are formed over the semiconductor layer 312, the semiconductor layer 313, the semiconductor layer 314, and the semiconductor layer 362. In this embodiment, the conductive layer 321, the conductive layer 322, and the conductive layer 363 are selectively formed by a droplet discharge method, so that material loss is reduced. Silver (Ag) is used as the conductive material, and a composition containing Ag is discharged from the droplet discharge device 380a, the droplet discharge device 380b, and the droplet discharge device 380c, and is baked at 300 ° C. A layer 322 and a conductive layer 363 are formed (see FIG. 15C). In the same step, a conductive layer 370 which serves as a source electrode layer or a drain electrode layer which also forms a capacitor is formed over the gate insulating layer 305b over the gate electrode layer 360a.

    As described with reference to FIG. 8 in Embodiment 1, the conductive layer 321, the conductive layer 322, the conductive layer 363, and the conductive layer 370 are precisely patterned, and the source or drain electrode layer 327a, the source electrode layer, A drain electrode layer 327b, a source or drain electrode layer 327c, a source or drain electrode layer 328, a source or drain electrode layer 366a, a source or drain electrode layer 366b, a source or drain electrode layer 366c; Form. Source or drain electrode layer 327a, Source or drain electrode layer 327b, Source or drain electrode layer 327c, Source or drain electrode layer 328, Source or drain electrode layer 366a, Source or drain electrode layer 366a Using the electrode layer 366b as a mask, the semiconductor layer 312, the semiconductor layer 313, the semiconductor layer 314, the semiconductor layer 361, the n-type semiconductor layer 315, the n-type semiconductor layer 316, the n-type semiconductor layer 317, and the n-type The semiconductor layer 362 including the semiconductor layer 372 is etched, and the semiconductor layer 371, the semiconductor layer 372, the semiconductor layer 373, the semiconductor layer 375, the n-type semiconductor layer 324a, the n-type semiconductor layer 324b, the p-type semiconductor layer 325a, and the p-type Semiconductor layer 325b having n-type, semiconductor layer 326a having n-type, n-type Semiconductor layer 326b, a semiconductor layer 365a having a n-type, a semiconductor layer 365b having a n-type. Etching can be dry etching or wet etching. In this embodiment mode, a dry etching method is used.

    Through the above steps, an n-channel thin film transistor 335, a p-channel thin film transistor 336, an n-channel thin film transistor 337, an n-channel thin film transistor 364, and a capacitor 338 which form a CMOS can be formed (see FIG. 16A). ). In this embodiment mode, a CMOS configuration is used. However, the present invention is not limited to this, and a PMOS configuration or an NMOS configuration may be used.

    An insulating film 330 to be a passivation film is formed. In this embodiment, the insulating film 330 is formed using a stacked film of a silicon oxide film with a thickness of 150 nm and a silicon nitride film with a thickness of 200 nm from the side in contact with the semiconductor layer. The insulating film 330 may be formed using another silicon-containing film, or a silicon oxynitride film may be used instead of the silicon oxide film, and a silicon oxynitride film and a silicon nitride film may be stacked.

    The insulating film 330 is formed so as to contain hydrogen, and heat treatment is performed in a nitrogen atmosphere at a temperature of 300 to 500 ° C. to hydrogenate the semiconductor layer.

    An insulating layer 339 is formed over the insulating film 330. In this embodiment, a silicon oxide film including an alkyl group is formed using a slit coater. The insulating layer 339, the opening 340b reaching the source or drain electrode layer 328, and the opening 340d reaching the source or drain electrode layer 366b are formed in the insulating layer 339, the insulating film 330, and the gate insulating layer 305a. In the gate insulating layer 305b, an opening 340a reaching the gate electrode layer 303, an opening 340c reaching the gate electrode layer 360a, and an opening 340e reaching the first electrode layer 304 are formed (see FIG. 16B). ). For the patterning for forming the opening, the fine processing by the laser beam of the present invention can be used. In this embodiment mode, the opening is formed by dry etching.

    Next, a wiring layer 341, a gate wiring layer 342, and a gate wiring layer 367 are formed. In this embodiment mode, a gate wiring layer or a wiring layer is formed using Ag and a droplet discharge method. A composition containing Ag as a conductive material is discharged into the opening 340a, the opening 340b, the opening 340c, the opening 340d, and the opening 340e and is baked at 300 ° C. Through the above steps, the gate wiring layer 367 that electrically connects the source or drain electrode layer 328 and the gate electrode layer 360a, the source or drain electrode layer 366b, and the first electrode layer 304 are electrically connected. A wiring layer 341 connected to each other and a gate wiring layer 342 electrically connected to the gate electrode layer 303 are formed (see FIG. 16C).

  Subsequently, an insulating layer 343 serving as a bank (also referred to as a partition wall) is formed. As for the insulating layer 343, an insulating layer is formed on the entire surface by a spin coating method or a dip method, and then an opening is formed as shown in FIG. 17 by etching. Further, if the insulating layer 343 is formed by a droplet discharge method, etching is not necessarily required.

  The insulating layer 343 is formed to include openings of through holes in accordance with positions where pixels are formed corresponding to the first electrode layer 304.

    An electroluminescent layer 344 and a second electrode layer 345 are stacked over the first electrode layer 304. After that, the filler 346 is sealed with a sealing substrate 347 and sealed. Instead of the filler 346, an inert gas such as nitrogen may be filled. Further, by installing the desiccant in the display device, the light emitting element can be prevented from being deteriorated by moisture. The installation place of the desiccant may be on the sealing substrate 347 side or on the substrate 300 side where elements are formed, or may be installed in a region where the sealing material 348 is formed with a recess formed in the substrate. Further, when the sealing substrate 347 is installed at a location corresponding to a region that does not contribute to display, such as a drive circuit region or a wiring region, the aperture ratio is not lowered even if the desiccant is an opaque substance. The filler 346 may be formed so as to include a hygroscopic material, and may have a function of a desiccant. Thus, a display device having a display function using a light-emitting element is completed (see FIG. 17).

  In addition, an FPC 354 is bonded to a terminal electrode layer 352 for electrically connecting the inside and the outside of the display device with an anisotropic conductive film 353 to be electrically connected to the terminal electrode layer 352.

    FIG. 18A shows a top view of a display device. As shown in FIG. 18A, the pixel region 390, the scanning line driving region 391a, the scanning line driving region 391b, and the connection region 393 are sealed between the substrate 300 and the sealing substrate 347 with a sealant 348. A signal line driver circuit 392 formed by a driver IC is provided on the substrate 300.

    In the display device in FIG. 18 described in this embodiment, the gate electrode layer 301, the gate electrode layer 302, the gate electrode layer 303, the gate electrode layer 360a, the gate electrode layer 360b, and the first electrode layer 304 are illustrated in a single layer structure. However, as described above, two or more gate electrode layers may be stacked. FIG. 44 shows an example in which the gate electrode layer and the first electrode layer are stacked.

  As the laminated structure, it is possible to use a laminated film of Ta, Ti, W, Mo, Cr, nitride films of the above elements, specifically, a laminated film of TaN and W, a laminated film of TaN and Mo, or a TaN and Cr film. , TiN and W, TiN and Mo, TiN and Cr, and the like can be used. In this embodiment, TaN is used as the first gate electrode layer 301a, the first gate electrode layer 302a, the first gate electrode layer 303a, the first gate electrode layer 360a1, and the first gate electrode layer 360b1, W is used for the second gate electrode layer 301b, the second gate electrode layer 302b, the second gate electrode layer 303b, the second gate electrode layer 360a2, and the second gate electrode layer 360b2. Also in the pixel electrode layer formed in the same step, a TaN film is formed as the first electrode layer 304a and a W film is formed as the first electrode layer 304b. Thus, the gate electrode layer and the pixel electrode layer can have a stacked structure. In addition, the pixel electrode layer may be formed in a single layer structure, and the gate electrode layer may be formed in a laminated structure. Conversely, the pixel electrode layer may be formed in a laminated structure and the gate electrode layer may be formed in a single layer structure. What is necessary is just to set suitably according to the function requested | required of a display apparatus.

    Through the above steps, an inverted staggered thin film transistor having a crystalline semiconductor film can be formed. Since the thin film transistor formed in this embodiment is formed using a crystalline semiconductor film, it has higher mobility than a thin film transistor formed using an amorphous semiconductor film. In addition, the source region and the drain region include a metal element in addition to the impurity element imparting one conductivity type. For this reason, a source region and a drain region with low resistivity can be formed. As a result, a display device capable of high speed operation can be manufactured.

    Further, compared with a thin film transistor formed using an amorphous semiconductor film, a threshold shift is less likely to occur, and variations in thin film transistor characteristics can be reduced.

    Further, since the metal element mixed in the semiconductor film in the film formation stage is also gettered by the gettering step, off current can be reduced. Therefore, the contrast can be improved by providing such a thin film transistor in the switching element of the display device.

(Embodiment 7)
In this embodiment, an example in which a connection structure between wirings is different in the display device in Embodiment 6 will be described with reference to FIGS. Therefore, repetitive description of the same portion or a portion having a similar function is omitted.

    In Embodiment 6, when the source electrode layer or the drain electrode layer and the gate electrode layer or the first electrode layer are electrically connected to each other, the insulating film 140 and the insulating layer 116 which are the gate electrode layer and the interlayer insulating layer are formed. Patterned openings are formed. This method has an advantage of simplifying the process because all the openings can be formed in a single process. An example in which the connection structure between the opening to be formed and the wiring is different is shown in FIG.

    FIG. 19 shows a pixel region of a display device manufactured in this embodiment mode. 19A is a top view of the display device in this embodiment mode, FIG. 19B is a cross-sectional view taken along line A-C in FIG. 19A, and FIG. 19C is FIG. It is sectional drawing of line BD in A).

    The source electrode layer 193 and the gate electrode layer 104 are directly connected to each other through an opening 197 formed in the gate insulating layer without passing through a wiring layer. In addition, the source or drain electrode layer 195 and the first electrode layer 120 are also directly connected to each other without a wiring layer. In this manner, after forming the gate insulating layer and before forming the source electrode layer or the drain electrode layer, if the gate electrode layer or the opening reaching the first electrode layer is formed in the gate insulating layer, By forming a source electrode layer or a drain electrode layer in the opening, it is not necessary to provide a wiring layer therebetween. After that, the insulating film 140 and the insulating layer 116 are formed, and the opening 135 and the opening 139 are formed. A gate wiring layer 117 is formed in the opening 135 and is electrically connected to the gate electrode layer 103. When the step of forming the opening is divided as described above, a structure in which a wiring layer for connecting wirings does not need to be formed can be obtained. In the case of a top emission display device, a structure in which a reflective material is used for the source or drain electrode layer 195 and the first electrode layer 120 may be stacked may be employed.

    This embodiment mode can be used in combination with each of Embodiment Modes 1 to 6.

(Embodiment 8)
In Embodiment 1, a gate electrode layer, a source electrode layer or a drain electrode layer (including a source wiring layer) and a capacitor wiring layer are stacked with a gate insulating layer interposed therebetween, and a source electrode layer or a drain electrode layer (source wiring) A multilayer structure in which a gate wiring layer and a gate wiring layer are stacked with an interlayer insulating layer interposed therebetween. In this embodiment, an example in which these stacked structures are different will be described with reference to FIGS. 31 to 36 and FIG. FIGS. 31A to 33A are top views of the display device, and FIGS. 31B to 33B are lines X1-V1 in FIGS. 31A to 33A. , Line X2-V2, line X3-V3. 34A to 36A are top views of the display device, and FIGS. 34B to 36B are lines Y1-Z1 in FIGS. 34A to 36A. , Line Y2-Z2, line Y3-Z3.

    FIG. 31A is a top view of the display device, and FIG. 31B is a cross-sectional view taken along line X1-V1 in FIG.

    In FIG. 31, in the pixel region of the display device, a gate electrode layer 601a, a gate electrode layer 601b, a pixel electrode layer 611, a gate insulating layer 602a, a gate insulating layer 602b, a capacitor wiring layer 604, and a source electrode layer are formed over a substrate 600. Or a drain electrode layer 603a, a source or drain electrode layer 603b, a gate wiring layer 607, a semiconductor layer 608, an n-type semiconductor layer 609a, an n-type semiconductor layer 609b, an insulating film 605 which is a passivation film, an insulating layer 606 is formed.

    Although the insulating film 605 is not necessarily required, when the insulating film 605 is formed, the insulating film 605 functions as a passivation film, and thus the reliability of the display device is further improved. In addition, when the insulating film 605 is formed and heat treatment is performed, the semiconductor layer can be hydrogenated with hydrogen contained in the insulating film 605.

    As shown in FIG. 31B, the source or drain electrode layer 603b is stacked with the gate wiring layer 607 with the insulating layer 606 which is an interlayer insulating layer interposed therebetween. The gate electrode layer 601b is connected to the insulating layer 606, the insulating film 605, the gate insulating layer 602a, and the contact hole formed in the gate insulating layer 602b. Thus, the gate wiring layer 607 is not short-circuited with the source or drain electrode layer 603b and the capacitor wiring layer 604.

    FIG. 32A is a top view of the display device, and FIG. 32B is a cross-sectional view taken along line X2-V2 in FIG. 32, in the pixel region of the display device, a gate electrode layer 621a, a gate electrode layer 621b, a gate insulating layer 622a, a gate insulating layer 622b, a capacitor wiring layer 624, a source electrode layer or a drain electrode layer 623a are formed over a substrate 620. A source or drain electrode layer 623b, a gate wiring layer 627a, a gate wiring layer 627b, an insulating film 625 which is a passivation film, and an insulating layer 626 are formed.

    As shown in FIG. 32B, the source or drain electrode layer 623b is stacked with the gate wiring layer 627b with an insulating layer 626 that is an interlayer insulating layer interposed therebetween. The gate wiring layer 627b includes a gate electrode layer The gate electrode layer 621b is connected to the insulating layer 626, the insulating film 625, the gate insulating layer 622a, and the contact hole formed in the gate insulating layer 622b. Therefore, the gate wiring layer 627b is not short-circuited with the source or drain electrode layer 623b and the capacitor wiring layer 624. Further, the display device shown in FIG. 32 has a structure in which the gate wiring layer and the gate electrode layer are formed intermittently, not continuously, and are electrically connected to each other through a contact hole. Yes. Therefore, in the region where the source or drain electrode layer 623b and the capacitor wiring layer 624 are formed, the gate electrode layer 621a and the gate electrode layer 621b are formed in contact with the gate wiring layer 627b formed over the insulating layer 626. It is electrically connected by connecting.

    FIG. 33A is a top view of the display device, and FIG. 33B is a cross-sectional view taken along line X3-V3 in FIG. 33, in the pixel region of the display device, a gate electrode layer 631a, a gate electrode layer 631b, a gate insulating layer 632a, a gate insulating layer 632b, a capacitor wiring layer 634, a source electrode layer or a drain electrode layer 633a are formed over a substrate 630. A source or drain electrode layer 633b, a gate wiring layer 637a, a gate wiring layer 637b, a wiring layer 638a, a wiring layer 638b, an insulating film 635 which is a passivation film, and an insulating layer 636 are formed.

    As shown in FIG. 33B, the source or drain electrode layer 633b is stacked over the gate wiring layer 637b with an insulating layer 636 that is an interlayer insulating layer interposed therebetween. In the display device illustrated in FIG. 32, the gate electrode layer 621a is directly connected to the gate wiring layer 627a and the gate wiring layer 627b. However, in the display device shown in FIG. 33, the gate electrode layer 631a is electrically connected to the gate wiring layer 637a and the gate wiring layer 637b through the wiring layer 638a formed by the same material and in the same process as the source electrode layer. Is done. Therefore, the gate electrode layer 631a is connected to the wiring layer 638a formed over the gate insulating layer 632a and the gate insulating layer 632b through a contact hole, and the wiring layer 638a is connected to the gate wiring layer 637a and the gate wiring layer 637b through the contact hole. Connect. Therefore, the gate electrode layer 631a, the gate wiring layer 637a, and the gate wiring layer 637b are electrically connected. Since the source or drain electrode layer 633b and the capacitor wiring layer 634 are stacked with the gate wiring layer 637b through the insulating layer 636 which is an interlayer insulating layer, the source or drain electrode layer 633b and the capacitor wiring layer 634 and the gate are stacked. The wiring layer 637b is not short-circuited.

    31, 32 and 33 show the case where an insulating layer is formed as an interlayer insulating layer so as to cover a wide range. FIG. 34, FIG. 35 and FIG. 36 show an example in which an interlayer insulating layer separating wiring layers is selectively formed only at a necessary portion using a droplet discharge method.

    34 corresponds to the display device of FIG. 31, FIG. 35 corresponds to the display device of FIG. 32, and FIG. 36 corresponds to the display device of FIG. FIG. 34A is a top view of the display device, and FIG. 34B is a cross-sectional view taken along line Y1-Z1 in FIG. In FIG. 34, an insulating layer 650 is formed by a droplet discharge method so as to cover the source or drain electrode layer 603b and the capacitor wiring layer 604. A gate wiring layer 607 is formed so as to straddle over the insulating layer 650. An insulating film 660 is formed on the gate wiring layer 607 as a passivation film. Although the insulating film 660 is not necessarily required, formation of the insulating film 660 can improve reliability. In this embodiment mode, the insulating layer 650 is a single layer; however, an insulating film may be formed on or below the insulating layer 650 to have a stacked structure.

    FIG. 35A is a top view of the display device, and FIG. 35B is a cross-sectional view taken along line Y2-Z2 in FIG. 35, as in FIG. 34, an insulating layer 651 is selectively formed by a droplet discharge method so as to cover the source or drain electrode layer 623b and the capacitor wiring layer 624. A gate wiring layer 627b is formed so as to straddle over the insulating layer 651, and is connected to the gate electrode layer 621a through a contact hole. An insulating film 661 is formed as a passivation film over the gate wiring layer 627a.

    36A is a top view of the display device, and FIG. 36B is a cross-sectional view taken along line Y3-Z3 in FIG. 36, as in FIG. 34, an insulating layer 652 is selectively formed by a droplet discharge method so as to cover the source or drain electrode layer 633b and the capacitor wiring layer 634. A gate wiring layer 637b is formed so as to straddle over the insulating layer 652, and is electrically connected to the gate wiring layer 637a and the gate electrode layer 631a through the wiring layer 638a.

    When an insulating layer for preventing a short circuit between wiring layers such as the insulating layer 650, the insulating layer 651, and the insulating layer 652 is selectively formed by a droplet discharge method, material loss is reduced. Further, since the wirings can be formed so as to be in direct contact with each other, the number of steps for forming a contact hole in the insulating layer is reduced. Therefore, the process can be simplified and low cost and high productivity can be obtained.

    The display device in FIG. 41 is also an example in which an insulating layer 653 provided to physically separate the source or drain electrode layer 643b and the capacitor wiring layer 644 from the wiring layer 647b is selectively formed by a droplet discharge method. . In the display device in FIGS. 34 to 36, the source wiring layer or the drain electrode layer and the gate wiring layer are prevented from being short-circuited by being formed on the insulating layer so as to straddle the gate wiring layer. In the display device in FIG. 41, the wiring layer 647a and the wiring layer 647b are formed in the step of forming the gate electrode layer 641a and the gate electrode layer 641b. After that, before forming the source or drain electrode layer 643a and the capacitor wiring layer 644, part of the gate insulating layer 642 covering the wiring layer 647a and the wiring layer 647b is removed by etching. As shown in the top view of the display device in FIG. 41A, the gate insulating layer 642 exists over the semiconductor layer, the region where the gate electrode layer and the source or drain electrode layer are stacked, and the region where the capacitor is formed. However, regions where the wiring layer 647a, the wiring layer 647b, the wiring layer 648a, and the wiring layer 648b are formed are removed. Therefore, the wiring layers can be directly connected without forming a contact hole. An insulating layer 653 is selectively formed over part of the wiring layer 647b by a droplet discharge method, and a source or drain electrode layer 643a and a capacitor wiring layer 644 are formed over the insulating layer 653. In the same process as the formation of the source or drain electrode layer 643b and the capacitor wiring layer 644, the wiring layer 648a and the wiring layer 648b are formed in contact with the gate electrode layer 641a and the gate electrode layer 641b, respectively. The wiring layer 648a and the wiring layer 648b are electrically connected by the wiring layer 647b under the insulating layer 653. In this manner, the gate wiring layer and the gate electrode layer can be electrically connected under the insulating layer 653.

    As shown in the above steps, a highly reliable display device can be manufactured with low cost and high productivity.

    This embodiment mode can be used in combination with each of Embodiment Modes 1 to 7.

(Embodiment 9)
Next, a mode in which a driver circuit for driving is mounted on the display panel manufactured according to Embodiment Modes 1 to 7 will be described.

  First, a display device employing a COG method is described with reference to FIG. A pixel portion 2701 for displaying information such as characters and images is provided over the substrate 2700. A substrate provided with a plurality of drive circuits is divided into rectangular shapes, and a divided drive circuit (hereinafter referred to as a driver IC) 2751 is mounted on the substrate 2700. FIG. 30A illustrates a mode in which an FPC 2750 is mounted on the top of a plurality of driver ICs 2751 and driver ICs 2751. Further, the size to be divided may be substantially the same as the length of the side of the pixel portion on the signal line side, and a tape may be mounted on the tip of the driver IC on a single driver IC.

  Alternatively, a TAB method may be employed. In that case, a plurality of tapes may be attached and driver ICs may be mounted on the tapes as shown in FIG. As in the case of the COG method, a single driver IC may be mounted on a single tape. In this case, a metal piece or the like for fixing the driver IC may be attached together due to strength problems.

  A plurality of driver ICs mounted on these display panels may be formed on a rectangular substrate having a side of 300 mm to 1000 mm or more from the viewpoint of improving productivity.

  That is, a plurality of circuit patterns having a drive circuit portion and an input / output terminal as one unit may be formed on the substrate, and finally divided and taken out. The long side of the driver IC may be formed in a rectangular shape having a long side of 15 to 80 mm and a short side of 1 to 6 mm in consideration of the length of one side of the pixel portion and the pixel pitch. Or a length obtained by adding one side of the pixel portion and one side of each driver circuit.

  The advantage of the external dimensions of the driver IC over the IC chip lies in the length of the long side. When a driver IC formed with a long side of 15 to 80 mm is used, the number required for mounting corresponding to the pixel portion is as follows. This is less than when an IC chip is used, and the manufacturing yield can be improved. Further, when a driver IC is formed over a glass substrate, the shape of the substrate used as a base is not limited, and thus productivity is not impaired. This is a great advantage compared with the case where the IC chip is taken out from the circular silicon wafer.

  In the case where the driver circuit 3704 on the scanning line side is formed over the substrate as shown in FIG. 29B, the driver in which the driver circuit driver circuit on the signal line side is formed in the region outside the pixel region 3701. IC is mounted. These driver ICs are drive circuits on the signal line side. In order to form a pixel region corresponding to RGB full color, the number of signal lines in the XGA class is 3072 and the number in the UXGA class is 4800. The signal lines formed in such a number are divided into several blocks at the end of the pixel region 3701 to form lead lines, and are collected according to the pitch of the output terminals of the driver IC.

  The driver IC is preferably formed of a crystalline semiconductor formed over a substrate, and a thin film transistor using the present invention can be used. In addition, since the mobility and response speed are good, high-speed driving is possible, the operating frequency of the element can be improved as compared with the prior art, and there is less variation in characteristics, so that high reliability can be obtained.

  In the pixel region, signal lines and scanning lines intersect to form a matrix, and transistors are arranged corresponding to the respective intersections. A thin film transistor using the present invention can also be applied to a transistor arranged in a pixel region. A thin film transistor manufactured by applying the present invention is effective in manufacturing a large-screen display device because relatively high mobility can be obtained by a simplified process. Therefore, this thin film transistor can be used as a switching element of a pixel or an element constituting a driving circuit on the scanning line side. Therefore, a display panel that realizes system-on-panel can be manufactured.

  As shown in FIGS. 30A and 30B, driver ICs may be mounted as both the scanning line driver circuit and the signal line driver circuit. In that case, the specifications of the driver ICs used on the scanning line side and the signal line side may be different.

  In that case, it is preferable that the specifications of the driver ICs used on the scanning line side and the signal line side are different. For example, although a transistor constituting the driver IC on the scanning line side is required to have a withstand voltage of about 30 V, the driving frequency is 100 kHz or less, and a relatively high speed operation is not required. Therefore, it is preferable to set the channel length (L) of the transistors forming the driver on the scanning line side to be sufficiently large. On the other hand, it is sufficient for the transistor of the driver IC on the signal line side to have a withstand voltage of about 12V, but the drive frequency is about 65 MHz at 3V, and high speed operation is required. Therefore, it is preferable to set the channel length and the like of the transistors constituting the driver on the micron rule. Note that the channel length direction corresponds to the direction in which current flows in the channel formation region.

  The method for mounting the driver IC is not particularly limited, and a known COG method, wire bonding method, or TAB method can be used.

  By setting the thickness of the driver IC to be the same as that of the counter substrate, the height between the two becomes substantially the same, which contributes to the reduction in thickness of the entire display device. In addition, since each substrate is made of the same material, thermal stress is not generated even when a temperature change occurs in the display device, and the characteristics of a circuit made of TFTs are not impaired. In addition, the number of driver ICs to be mounted in one pixel region can be reduced by mounting the driver circuit with a driver IC longer than the IC chip as shown in this embodiment mode. .

  As described above, a driver circuit can be incorporated in the display panel.

    This embodiment mode can be used in combination with each of Embodiment Modes 1 to 7.

(Embodiment 10)
In this embodiment mode, FIG. 25 shows the positional relationship between the end portions of the gate electrode layer, the source electrode layer, and the drain electrode layer, that is, the relationship between the width of the gate electrode layer and the channel length in the above embodiment mode. It explains using.

  FIG. 25A illustrates a gate electrode layer 541, a gate insulating layer 542a, a gate insulating layer 542b, a semiconductor layer 543, a semiconductor layer 544a having one conductivity type, and a semiconductor layer 544b having one conductivity type formed over a substrate 540. , A thin film transistor including a source or drain electrode layer 545a and a source or drain electrode layer 545b.

    In FIG. 25A, the end portion of the source or drain electrode layer 545a and the source or drain electrode layer 545b overlaps with the gate electrode layer 541 by c1. Here, a region where the source or drain electrode layer 545a and the source or drain electrode layer 545b overlap with the gate electrode layer 541 is referred to as an overlap region. That is, the width b1 of the gate electrode layer is larger than the channel length a1. The width c1 of the overlap region is represented by (b1-a1) / 2. An n-channel TFT having such an overlap region preferably has an n + region and an n − region between the source and drain electrode layers and the semiconductor region. With this structure, the effect of relaxing the electric field is increased, and hot carrier resistance can be increased.

  FIG. 25B illustrates a gate electrode layer 551, a gate insulating layer 552a, a gate insulating layer 552b, a semiconductor layer 553, a semiconductor layer 554a having one conductivity type, and a semiconductor layer 554b having one conductivity type, which are formed over a substrate 550. , A thin film transistor including a source or drain electrode layer 555a and a source or drain electrode layer 555b.

    In FIG. 25B, the end portion of the gate electrode layer 551 is aligned with the end portions of the source or drain electrode layer 555a and the source or drain electrode layer 555b. That is, the width b2 of the gate electrode layer is equal to the channel length a2.

  FIG. 25C illustrates a gate electrode layer 561, a gate insulating layer 562a, a gate insulating layer 562b, a semiconductor layer 563, a semiconductor layer 564a having one conductivity type, and a semiconductor layer 564b having one conductivity type, which are formed over a substrate 560. , A thin film transistor including a source or drain electrode layer 565a and a source or drain electrode layer 565b.

  In FIG. 25C, the gate electrode layer 561 is separated from the end portions of the source or drain electrode layer 565a and the source or drain electrode layer 565b by c3. Here, a region where the gate electrode layer 561 is separated from the source or drain electrode layer 565a and the source or drain electrode layer 565b is referred to as an offset region. That is, the width b3 of the gate electrode layer is smaller than the channel length a3. The width c3 of the offset region is represented by (a3−b3) / 2. Since the TFT having such a structure can reduce off-state current, contrast can be improved when the TFT is used as a switching element of a display device.

  Further, a TFT having a so-called multi-gate structure in which the semiconductor region covers a plurality of gate electrodes may be used. A TFT having such a structure can also reduce off-state current.

    This embodiment mode can be used in combination with each of Embodiment Modes 1 to 9.

(Embodiment 11)
In the above embodiment mode, the source electrode layer and the drain electrode layer having end portions perpendicular to the surface of the channel formation region are shown; however, the present invention is not limited to this structure. In this embodiment, an example in which the shape of a semiconductor layer having one conductivity type is different will be described with reference to FIGS.

    24 shows a gate electrode layer 521, a gate insulating layer 522a, a gate insulating layer 522b, a semiconductor layer 523, a semiconductor layer 524a having one conductivity type, a semiconductor layer 524b having one conductivity type, and a source electrode formed over the substrate 520. A thin film transistor including a layer or drain electrode layer 525a and a source or drain electrode layer 525b.

    As shown in FIG. 24, the semiconductor layer 524a having one conductivity type and the semiconductor layer 524b having one conductivity type are larger than 90 degrees and smaller than 180 degrees, preferably 95 to 140 degrees with respect to the surface of the channel formation region. More preferably, it may be an end portion having 135 to 140 degrees. Further, if the angle between the source electrode layer and the channel formation region surface is θ1, and the angle between the drain electrode layer and the channel formation region surface is θ2, θ1 and θ2 may be equal. It may be different. The source electrode and the drain electrode having such a shape can be formed by a dry etching method.

    This embodiment mode can be used in combination with each of Embodiment Modes 1 to 10.

(Embodiment 12)
In this embodiment mode, a crystallization process of a semiconductor film which can be applied to the above embodiment mode will be described with reference to FIGS.

    In FIG. 22, a gate electrode layer 491, a gate insulating layer 492a, and a gate insulating layer 492b are formed over a substrate 490, and a semiconductor film 493 is formed. A mask 494a and a mask 494b formed using an insulating film are formed over the semiconductor film 493, and a metal layer 495 is selectively formed, so that the semiconductor film can be crystallized. When the semiconductor film is heated, crystal growth occurs in a direction parallel to the surface of the substrate from a contact portion between the metal layer 495 and the semiconductor film, as indicated by an arrow in FIG. Form. Note that crystallization is not performed in a portion far from the metal layer 495, and an amorphous portion remains.

    Alternatively, as shown in FIG. 23A, the crystallization may be performed by selectively forming a metal layer 504 by a droplet discharge method without using a mask. FIG. 23B is a top view of FIG. FIG. 23D is a top view of FIG.

    23, a gate electrode layer 501, a gate insulating layer 502a, and a gate insulating layer 502b are formed over a substrate 500, and a semiconductor film 503 is formed. A metal layer 504 is selectively formed over the semiconductor film 503 by a droplet discharge method. When the semiconductor film is crystallized by heat treatment, crystal growth occurs in the direction parallel to the surface of the substrate from the contact portion between the metal layer and the semiconductor film, as shown in FIGS. 23C and 23D. To do. Again, crystallization is not performed at a portion far away from the metal layer 504, and an amorphous portion remains.

    Thus, crystal growth in a direction parallel to the substrate is referred to as lateral growth or lateral growth. Since crystal grains having a large grain size can be formed by lateral growth, a thin film transistor having higher mobility can be formed.

    This embodiment mode can be used in combination with each of Embodiment Modes 1 to 11.

(Embodiment 13)
An example of a protection circuit included in the semiconductor device of the present invention will be described.

  As shown in FIG. 30, a protection circuit 2703 and a protection circuit 2713 can be formed between the external circuit and the internal circuit. The protection circuit is composed of one or a plurality of elements selected from a TFT, a diode, a resistance element, a capacitance element, and the like, and the configurations and operations of some protection circuits will be described below. First, a configuration of an equivalent circuit diagram of a protection circuit arranged between an external circuit and an internal circuit and corresponding to one input terminal will be described with reference to FIG. The protection circuit illustrated in FIG. 42A includes p-channel thin film transistors 7220 and 7230, capacitor elements 7210 and 7240, and a resistance element 7250. The resistance element 7250 is a two-terminal resistor, and an input voltage Vin (hereinafter referred to as Vin) is applied to one end, and a low potential voltage VSS (hereinafter referred to as VSS) is applied to the other end.

  The protection circuit illustrated in FIG. 42B is an equivalent circuit diagram in which the p-channel thin film transistors 7220 and 7230 are substituted with rectifying diodes 7260 and 7270. The protection circuit illustrated in FIG. 42C is an equivalent circuit diagram in which the p-channel thin film transistors 7220 and 7230 are substituted with TFTs 7350, 7360, 7370, and 7380. As a protection circuit having a structure different from the above, the protection circuit illustrated in FIG. 42D includes resistors 7280 and 7290 and an n-channel thin film transistor 7300. The protection circuit illustrated in FIG. 42E includes resistors 7280 and 7290, a p-channel thin film transistor 7310, and an n-channel thin film transistor 7320. Providing the protective circuit prevents abrupt fluctuations in potential and can prevent element destruction or damage, improving reliability. Note that the element forming the protection circuit is preferably formed using an amorphous semiconductor with excellent withstand voltage.

    This embodiment mode can be used in combination with each of Embodiment Modes 1 to 12.

(Embodiment 14)
A thin film transistor is formed by applying the present invention, and a display device can be formed using the thin film transistor. When a light emitting element is used and an N-type transistor is used as a transistor for driving the light emitting element, The light emitted from the light emitting element performs any one of bottom emission, top emission, and dual emission. Here, a stacked structure of light-emitting elements corresponding to each case will be described with reference to FIGS.

In this embodiment mode, channel-etched thin film transistors 671, 681, and 691 to which the present invention is applied are used. In this embodiment mode, a silicon film having a crystalline structure is used as the semiconductor layer, and an N-type semiconductor layer is used as the one-conductivity-type semiconductor layer. Instead of forming the N-type semiconductor layer, the semiconductor layer may be given a conductivity type by performing plasma treatment with a PH ₃ gas. The semiconductor layer is not limited to this embodiment mode, and an impurity region having one conductivity type may be formed by introducing (adding) an impurity into the crystalline semiconductor layer without forming the one conductivity type semiconductor layer.

  The thin film transistor may be a channel protective thin film transistor having a channel protective layer, and the channel protective layer may be formed by dropping polyimide or polyvinyl alcohol by a droplet discharge method. As a result, the exposure process can be omitted. Channel protective layers include inorganic materials (silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, etc.), photosensitive or non-photosensitive organic materials (organic resin materials) (polyimide, acrylic, polyamide, polyimide amide, benzo Cyclobutene, etc.), a resist, a low-k material having a low dielectric constant, or a film made of a plurality of types, or a stack of these films can be used. A siloxane resin may also be used. As a manufacturing method, a vapor deposition method such as a plasma CVD method or a thermal CVD method, or a sputtering method can be used. Alternatively, a droplet discharge method or a printing method (a method for forming a pattern such as screen printing or offset printing) can be used. A TOF film or an SOG film obtained by a coating method can also be used.

  First, the case where radiation is emitted to the substrate 680 side, that is, the case where bottom emission is performed will be described with reference to FIG. In this case, the first electrode layer 684, the electroluminescent layer 685, and the second electrode layer 686 are in contact with the wiring layer 682 connected to the source electrode layer or the drain electrode layer so as to be electrically connected to the thin film transistor 681. Laminated sequentially. The substrate 680 through which light is transmitted needs to have a light-transmitting property. Next, the case where radiation is performed on the side opposite to the substrate 690, that is, the case where top surface radiation is performed will be described with reference to FIG. The thin film transistor 691 can be formed in a manner similar to that of the thin film transistor described above.

  A wiring layer 692 connected to the source electrode layer or the drain electrode layer electrically connected to the thin film transistor 691 is in contact with and electrically connected to the first electrode layer 684. The gate electrode layer of the thin film transistor 691 has a stacked structure, and the first electrode layer formed using the same material in the same process also has a stacked structure of a first electrode layer 693a and a first electrode layer 693b. The first electrode layer 693a is a reflective metal layer and reflects light emitted from the light-emitting element to the upper surface of the arrow. Therefore, even when light is transmitted through the first electrode layer 693b, the light is reflected by the first electrode layer 693a and emitted to the side opposite to the substrate 690. Of course, the first electrode layer may have a single-layer structure of a reflective metal layer. A first electrode layer 693a, a first electrode layer 693b, an electroluminescent layer 694, and a second electrode layer 695 are sequentially stacked. Finally, a case where light is emitted to the substrate 670 side and the opposite side, that is, a case where dual emission is performed will be described with reference to FIG. The thin film transistor 671 is a channel-etch thin film transistor similar to the thin film transistor 681. It can be formed in a manner similar to that of the thin film transistor 681. A first electrode layer 672 is electrically connected to a wiring layer 675 connected to a source electrode layer or a drain electrode layer electrically connected to the thin film transistor 671. A first electrode layer 672, an electroluminescent layer 673, and a second electrode layer 674 are sequentially stacked. At this time, when both the first electrode layer 672 and the second electrode layer 674 are formed using a light-transmitting material or a thickness capable of transmitting light, dual emission is realized. In this case, the insulating layer through which light is transmitted and the substrate 670 also need to have a light-transmitting property.

  A mode of a light-emitting element which can be applied to this embodiment mode is shown in FIG. The light-emitting element has a structure in which an electroluminescent layer 860 is sandwiched between a first electrode layer 870 and a second electrode layer 850. It is necessary to select materials for the first electrode layer and the second electrode layer in consideration of the work function, and the first electrode layer and the second electrode layer are both anodes or cathodes depending on the pixel configuration. sell. In this embodiment mode, since the polarity of the driving TFT is an N-channel type, it is preferable that the first electrode layer be a cathode and the second electrode layer be an anode. In the case where the polarity of the driving TFT is a p-channel type, the first electrode layer may be an anode and the second electrode layer may be a cathode.

  45A and 45B show the case where the first electrode layer 870 is an anode and the second electrode layer 850 is a cathode, and the electroluminescent layer 860 is formed from the first electrode layer 870 side. , HIL (hole injection layer) / HTL (hole transport layer) 804, EML (light emitting layer) 803, ETL (electron transport layer) / EIL (electron injection layer) 802, and second electrode layer 850 are stacked in this order. preferable. FIG. 45A illustrates a structure in which light is emitted from the first electrode layer 870. The first electrode layer 870 includes an electrode layer 805 made of a light-transmitting oxide conductive material, The electrode layer includes an electrode layer 801 containing an alkali metal or alkaline earth metal such as LiF or MgAg and an electrode layer 800 formed of a metal material such as aluminum from the electroluminescent layer 860 side. FIG. 45B illustrates a structure in which light is emitted from the second electrode layer 850. The first electrode layer is formed using a metal such as aluminum or titanium or nitrogen at a concentration equal to or lower than the stoichiometric composition ratio with the metal. An electrode layer 807 formed of a metal material containing silicon, and a second electrode layer 806 formed of an oxide conductive material containing silicon oxide at a concentration of 1 to 15 atomic%. The second electrode layer is composed of an electrode layer 801 containing an alkali metal or alkaline earth metal such as LiF or MgAg and an electrode layer 800 formed of a metal material such as aluminum from the electroluminescent layer 860 side. However, it is possible to emit light from the second electrode layer 850 by setting each layer to a thickness of 100 nm or less so that light can be transmitted.

  45C and 45D show the case where the first electrode layer 870 is a cathode and the second electrode layer 850 is an anode, and the electroluminescent layer 860 is formed from an EIL (electron injection layer) from the cathode side. ) / ETL (electron transport layer) 802, EML (light emitting layer) 803, HTL (hole transport layer) / HIL (hole injection layer) 804, and the second electrode layer 850 which is an anode are preferably stacked in this order. FIG. 45C illustrates a structure in which light is emitted from the first electrode layer 870. The first electrode layer 870 includes an electrode layer containing an alkali metal or an alkaline earth metal such as LiF or MgAg from the electroluminescent layer 860 side. 801 and an electrode layer 800 formed of a metal material such as aluminum, but each layer emits light from the first electrode layer 870 by setting the thickness to 100 nm or less so that light can be transmitted. It becomes possible to do. The second electrode layer includes, from the electroluminescent layer 860 side, a second electrode layer 806 formed of an oxide conductive material containing silicon oxide at a concentration of 1 to 15 atomic%, a metal such as aluminum or titanium, or the The electrode layer 807 is formed of a metal material containing nitrogen at a concentration equal to or lower than the stoichiometric composition ratio of metal. FIG. 45D illustrates a structure in which light is emitted from the second electrode layer 850, and the first electrode layer 870 includes an electrode layer containing an alkali metal or an alkaline earth metal such as LiF or MgAg from the electroluminescent layer 860 side. 801 and an electrode layer 800 formed of a metal material such as aluminum. The film thickness is large enough to reflect light emitted from the electroluminescent layer 860. The second electrode layer 850 includes an electrode layer 805 made of a light-transmitting oxide conductive material. The electroluminescent layer can have a single layer structure or a mixed structure in addition to the laminated structure.

  In addition, as the electroluminescent layer, materials that emit red (R), green (G), and blue (B) light are selectively formed by an evaporation method using an evaporation mask, respectively. A material that emits red (R), green (G), and blue (B) light can be formed by a droplet discharge method (such as a low-molecular or high-molecular material) in the same manner as a color filter. In this case, a mask is not used. Both are preferable because RGB can be separately applied.

In the case of a top emission type, when light-transmitting ITO or ITSO is used for the second electrode layer, BzOS-Li in which Li is added to a benzoxazole derivative (BzOS) or the like can be used. Further, for example, EML may be Alq ₃ doped with a dopant corresponding to each emission color of R, G, and B (DCM in the case of R, DMQD in the case of G).

  Note that the electroluminescent layer is not limited to the above materials. For example, instead of CuPc or PEDOT, an oxide such as molybdenum oxide (MoOx: x = 2 to 3) and α-NPD or rubrene can be co-evaporated to improve the hole injection property. The material of the electroluminescent layer can be used as an organic material (including a low molecule or a polymer), or a composite material of an organic material and an inorganic material. Hereinafter, materials for forming the light emitting element will be described in detail.

Among the charge injecting and transporting materials, materials having a particularly high electron transporting property include, for example, tris (8-quinolinolato) aluminum (abbreviation: Alq ₃ ), tris (5-methyl-8-quinolinolato) aluminum (abbreviation: Almq ₃ ), Bis (10-hydroxybenzo [h] -quinolinato) beryllium (abbreviation: BeBq ₂ ), bis (2-methyl-8-quinolinolato) -4-phenylphenolato-aluminum (abbreviation: BAlq), quinoline skeleton or benzoquinoline Examples thereof include metal complexes having a skeleton. As a substance having a high hole-transport property, for example, 4,4′-bis [N- (1-naphthyl) -N-phenyl-amino] -biphenyl (abbreviation: α-NPD), N, N′-bis ( 3-methylphenyl) -N, N′-diphenyl- [1,1′-biphenyl] -4,4′-diamine (abbreviation: TPD) and 4,4 ′, 4 ″ -tris (N, N-diphenyl) -Amino) -triphenylamine (abbreviation: TDATA), 4,4 ′, 4 ″ -tris [N- (3-methylphenyl) -N-phenyl-amino] -triphenylamine (abbreviation: MTDATA), etc. Aromatic amine-based compounds (that is, having a benzene ring-nitrogen bond) can be mentioned.

Among the charge injecting and transporting materials, materials having particularly high electron injecting properties include alkali metals or alkaline earths such as lithium fluoride (LiF), cesium fluoride (CsF), calcium fluoride (CaF ₂ ) and the like. Metal compounds can be mentioned. In addition, a mixture of a substance having a high electron transport property such as Alq ₃ and an alkaline earth metal such as magnesium (Mg) may be used.

Among the charge injecting and transporting materials, examples of the material having a high hole injecting property include molybdenum oxide (MoOx), vanadium oxide (VOx), ruthenium oxide (RuOx), tungsten oxide (WOx), and manganese oxide. Examples thereof include metal oxides such as (MnOx). In addition, phthalocyanine compounds such as phthalocyanine (abbreviation: H ₂ Pc) and copper phthalocyanine (CuPC) can be given.

  The light emitting layer may be configured to perform color display by forming light emitting layers having different emission wavelength bands for each pixel. Typically, a light emitting layer corresponding to each color of R (red), G (green), and B (blue) is formed. In this case as well, it is possible to improve color purity and prevent mirror reflection (reflection) of the pixel portion by providing a filter that transmits light in the emission wavelength band on the light emission side of the pixel. Can do. By providing the filter, it is possible to omit a circularly polarized plate that has been conventionally required, and it is possible to eliminate the loss of light emitted from the light emitting layer. Furthermore, a change in color tone that occurs when the pixel portion (display screen) is viewed obliquely can be reduced.

There are various kinds of light emitting materials. As the low-molecular organic light-emitting material, 4-dicyanomethylene-2-methyl-6- [2- (1,1,7,7-tetramethyl-9-julolidin-9-yl) -ethenyl] -4H-pyran (abbreviation) : DCJT), 4-dicyanomethylene-2-t-butyl-6- [2- (1,1,7,7-tetramethyljulolidin-9-yl) ethenyl] -4H-pyran (abbreviation: DCJTB), Periflanthene, 2,5-dicyano-1,4-bis [2- (10-methoxy-1,1,7,7-tetramethyljulolidin-9-yl) ethenyl] benzene, N, N′-dimethylquinacridone ( Abbreviations: DMQd), coumarin 6, coumarin 545T, tris (8-quinolinolato) aluminum (abbreviation: Alq ₃ ), 9,9′-bianthryl, 9,10-diphenylanthracene (abbreviation: DPA) and 9,10-bis ( 2-naphthyl ) Anthracene (abbreviation: DNA) or the like can be used. Other substances may also be used.

  On the other hand, the high molecular organic light emitting material has higher physical strength than the low molecular weight, and the durability of the device is high. In addition, since the film can be formed by coating, the device can be manufactured relatively easily. The structure of a light-emitting element using a high-molecular organic light-emitting material is basically the same as that when a low-molecular organic light-emitting material is used, and sequentially becomes a cathode, an organic light-emitting layer, and an anode. However, when forming a light emitting layer using a polymer organic light emitting material, it is difficult to form a laminated structure as in the case of using a low molecular weight organic light emitting material, and in many cases, a two layer structure is formed. Specifically, the structure is a cathode, a light emitting layer, a hole transport layer, and an anode in this order.

  Since the light emission color is determined by the material for forming the light emitting layer, a light emitting element exhibiting desired light emission can be formed by selecting these materials. Examples of the polymer organic light emitting material that can be used for forming the light emitting layer include polyparaphenylene vinylene, polyparaphenylene, polythiophene, and polyfluorene.

  The polyparaphenylene vinylene system includes derivatives of poly (paraphenylene vinylene) [PPV], poly (2,5-dialkoxy-1,4-phenylene vinylene) [RO-PPV], poly (2- (2′- Ethyl-hexoxy) -5-methoxy-1,4-phenylenevinylene) [MEH-PPV], poly (2- (dialkoxyphenyl) -1,4-phenylenevinylene) [ROPh-PPV] and the like. The polyparaphenylene series includes derivatives of polyparaphenylene [PPP], poly (2,5-dialkoxy-1,4-phenylene) [RO-PPP], poly (2,5-dihexoxy-1,4-phenylene). ) And the like. The polythiophene series includes polythiophene [PT] derivatives, poly (3-alkylthiophene) [PAT], poly (3-hexylthiophene) [PHT], poly (3-cyclohexylthiophene) [PCHT], poly (3-cyclohexyl). -4-methylthiophene) [PCHMT], poly (3,4-dicyclohexylthiophene) [PDCHT], poly [3- (4-octylphenyl) -thiophene] [POPT], poly [3- (4-octylphenyl) -2,2 bithiophene] [PTOPT] and the like. Examples of the polyfluorene series include polyfluorene [PF] derivatives, poly (9,9-dialkylfluorene) [PDAF], poly (9,9-dioctylfluorene) [PDOF], and the like.

  Note that when a hole-transporting polymer organic light-emitting material is sandwiched and formed between the anode and the light-emitting polymer organic light-emitting material, the hole injection property from the anode can be improved. In general, an acceptor material dissolved in water is applied by spin coating or the like. In addition, since it is insoluble in an organic solvent, it can be stacked with the above-described light-emitting organic light-emitting material. Examples of the hole-transporting polymer organic light-emitting material include a mixture of PEDOT and camphor sulfonic acid (CSA) as an acceptor material, a mixture of polyaniline [PANI] and polystyrene sulfonic acid [PSS] as an acceptor material, and the like.

  The light emitting layer can be configured to emit monochromatic or white light. In the case of using a white light emitting material, color display can be made possible by providing a filter (colored layer) that transmits light of a specific wavelength on the light emission side of the pixel.

To form a light emitting layer that emits white light, for _{example, Alq 3, Alq 3, Alq} 3 doped with Nile Red which is partly red light emitting pigment, p-EtTAZ, by TPD (aromatic diamine) evaporation A white color can be obtained by sequentially laminating. In the case where the EL is formed by a coating method using spin coating, it is preferable that baking is performed by vacuum heating after coating. For example, a poly (ethylenedioxythiophene) / poly (styrenesulfonic acid) aqueous solution (PEDOT / PSS) that acts as a hole injection layer is applied and baked on the entire surface, and then a luminescent center dye (1, 1,4,4-tetraphenyl-1,3-butadiene (TPB), 4-dicyanomethylene-2-methyl-6- (p-dimethylamino-styryl) -4H-pyran (DCM1), Nile Red, Coumarin 6 Etc.) A doped polyvinyl carbazole (PVK) solution may be applied to the entire surface and fired.

  The light emitting layer can also be formed as a single layer, and an electron transporting 1,3,4-oxadiazole derivative (PBD) may be dispersed in hole transporting polyvinyl carbazole (PVK). Further, white light emission can be obtained by dispersing 30 wt% PBD as an electron transporting agent and dispersing an appropriate amount of four kinds of dyes (TPB, coumarin 6, DCM1, Nile red). In addition to the light-emitting element that can emit white light as shown here, a light-emitting element that can obtain red light emission, green light emission, or blue light emission can be manufactured by appropriately selecting the material of the light-emitting layer.

  Furthermore, a triplet excitation material containing a metal complex or the like may be used for the light emitting layer in addition to a singlet excitation light emitting material. For example, among red light emitting pixels, green light emitting pixels, and blue light emitting pixels, a red light emitting pixel having a relatively short luminance half time is formed of a triplet excitation light emitting material, and the other A singlet excited luminescent material is used. The triplet excited luminescent material has a feature that the light emission efficiency is good, so that less power is required to obtain the same luminance. That is, when applied to a red pixel, the amount of current flowing through the light emitting element can be reduced, so that reliability can be improved. As a reduction in power consumption, a red light-emitting pixel and a green light-emitting pixel may be formed using a triplet excitation light-emitting material, and a blue light-emitting pixel may be formed using a singlet excitation light-emitting material. By forming a green light-emitting element having high human visibility with a triplet excited light-emitting material, power consumption can be further reduced.

  Examples of triplet excited luminescent materials include those using a metal complex as a dopant, and metal complexes having a third transition series element platinum as the central metal and metal complexes having iridium as the central metal are known. Yes. The triplet excited light-emitting material is not limited to these compounds, and a compound having the above structure and having an element belonging to group 8 to 10 in the periodic table as a central metal can also be used.

  The substances forming the light-emitting layer listed above are examples, and functional layers such as a hole injection layer, a hole transport layer, an electron injection layer, an electron transport layer, a light-emitting layer, an electron block layer, and a hole block layer are included. A light-emitting element can be formed by stacking as appropriate. Moreover, you may form the mixed layer or mixed junction which combined these each layer. The layer structure of the light-emitting layer can be changed, and instead of having a specific electron injection region or light-emitting region, an electrode layer for this purpose is provided, or a light-emitting material is dispersed. Modifications can be made without departing from the spirit of the present invention.

  A light-emitting element formed using the above materials emits light by being forward-biased. A pixel of a display device formed using a light-emitting element can be driven by a simple matrix method or an active matrix method as described in Embodiment 2. In any case, each pixel emits light by applying a forward bias at a specific timing, but is in a non-light emitting state for a certain period. By applying a reverse bias during this non-light emitting time, the reliability of the light emitting element can be improved. The light emitting element has a degradation mode in which the light emission intensity decreases under a constant driving condition and a degradation mode in which the non-light emitting area is enlarged in the pixel and the luminance is apparently decreased. However, alternating current that applies a bias in the forward and reverse directions. By performing a typical drive, the progress of deterioration can be slowed and the reliability of the light emitting device can be improved. Further, either digital driving or analog driving can be applied.

  Therefore, although not shown in FIG. 46, a color filter (colored layer) may be formed over the sealing substrate of the substrate 680. The color filter (colored layer) can be formed by a droplet discharge method. In that case, light irradiation treatment or the like can be applied as the above-described base pretreatment. By using the present invention, a color filter (colored layer) can be formed in a desired pattern with good controllability. When a color filter (colored layer) is used, high-definition display can be performed. This is because the color filter (colored layer) can correct a broad peak to be sharp in the emission spectrum of each RGB.

  As described above, the case where a material that emits light of each RGB is formed has been described. However, full color display can be performed by forming a material that emits light of a single color and combining a color filter and a color conversion layer. The color filter (colored layer) and the color conversion layer may be formed, for example, on the second substrate (sealing substrate) and attached to the substrate. In addition, as described above, any of the material that emits monochromatic light, the color filter (colored layer), and the color conversion layer can be formed by a droplet discharge method.

  Of course, monochromatic light emission may be displayed. For example, an area color type display device may be formed using monochromatic light emission. As the area color type, a passive matrix type display unit is suitable, and characters and symbols can be mainly displayed.

In the above configuration, a material having a low work function can be used as the cathode, and for example, Ca, Al, CaF ₂ , MgAg, AlLi, or the like is desirable. The electroluminescent layer may be any of a single layer type, a laminated type, and a mixed type having no layer interface. It is also formed from singlet materials, triplet materials, or a combination of these materials, charge injection transport materials including organic compounds or inorganic compounds, and light-emitting materials. An organic compound having a molecule number of 20 or less, or a chained molecule length of 10 μm or less), including one or more layers selected from macromolecular organic compounds, and having an electron injecting and transporting property Alternatively, it may be combined with a hole injection / transport inorganic compound. The first electrode layer 684, the first electrode layer 693a, and the first electrode layer 672 are formed using a transparent conductive film that transmits light. For example, in addition to ITO and ITSO, indium oxide is oxidized at 2 to 20%. A transparent conductive film mixed with zinc (ZnO) is used. Note that plasma treatment in an oxygen atmosphere or heat treatment in a vacuum atmosphere is performed before the first electrode layer 684, the first electrode layer 693a, the first electrode layer 693b, and the first electrode layer 672 are formed. Good. A partition wall (also referred to as a bank) is formed using a material containing silicon, an organic material, and a compound material. A porous film may be used. However, it is preferable to use a photosensitive or non-photosensitive material such as acrylic or polyimide because the side surface has a shape in which the radius of curvature continuously changes and the upper thin film is formed without being cut off. This embodiment mode can be used in combination with each of Embodiment Modes 1 to 13.

(Embodiment 15)
A structure of a pixel of the display panel described in this embodiment will be described with reference to an equivalent circuit diagram shown in FIG.

  In the pixel shown in FIG. 47A, a signal line 710, a power supply line 711, a power supply line 712, a power supply line 713 are arranged in the column direction, and a scanning line 714 is arranged in the row direction. The TFT 701 is a switching TFT, the TFT 703 is a driving TFT, the TFT 704 is a current control TFT, and further includes a capacitor 702 and a light emitting element 705.

  The pixel shown in FIG. 47C is different from the pixel shown in FIG. 47A except that the gate electrode of the TFT 703 is connected to the power supply line 715 arranged in the row direction. is there. That is, both pixels shown in FIGS. 47A and 47C show the same equivalent circuit diagram. However, when the power supply line 712 is arranged in the row direction (FIG. 47A) and in the case where the power supply line 715 is arranged in the column direction (FIG. 47C), each power supply line is conductive on a different layer. Formed with body layers. Here, attention is paid to the wiring to which the gate electrode of the TFT 703 is connected, and FIGS. 47A and 47C are shown separately to show that the layers for producing these are different.

47A and 47C, the TFT 703 and the TFT 704 are connected in series in the pixel, and the channel length L ₃ and channel width W _{3 of} the TFT 703 and the channel length L ₄ and channel width of the TFT 704 are obtained. W ₄ may be set to satisfy L ₃ / W ₃ : L ₄ / W ₄ = 5 to 6000: 1. As an example when 6000: 1 is satisfied, there is a case where L ₃ is 500 μm, W ₃ is 3 μm, L ₄ is 3 μm, and W ₄ is 100 μm. In addition, since fine patterning can be performed by using the present invention, such a fine wiring having a short channel width can be stably formed without causing a defect such as a short circuit. Therefore, a TFT having electrical characteristics necessary for sufficiently functioning a pixel as shown in FIGS. 47A and 47C can be formed, and a highly reliable display panel with excellent display capability can be manufactured. .

Note that the TFT 703 operates in a saturation region and has a role of controlling a current value flowing through the light emitting element 705, and the TFT 704 has a role of operating in a linear region and controls supply of current to the light emitting element 705. Both TFTs preferably have the same conductivity type in terms of manufacturing process. The TFT 703 may be a depletion type TFT as well as an enhancement type. In the present invention having the above structure, since the TFT 704 operates in a linear region, a slight change in V _GS of the TFT 704 does not affect the current value of the light emitting element 705. That is, the current value of the light emitting element 705 is determined by the TFT 703 operating in the saturation region. The present invention having the above structure can provide a display device in which luminance unevenness of a light emitting element due to variation in TFT characteristics is improved and image quality is improved.

  In the pixel shown in FIGS. 47A to 47D, a TFT 701 controls input of a video signal to the pixel. When the TFT 701 is turned on and a video signal is input into the pixel, the capacitor 702 The video signal is held in Note that FIGS. 47A and 47C illustrate a structure in which the capacitor 702 is provided; however, the present invention is not limited to this, and the capacity for holding a video signal can be covered by a gate capacity or the like. The capacitor 702 is not necessarily provided explicitly.

  The light-emitting element 705 has a structure in which an electroluminescent layer is sandwiched between two electrodes, and a potential difference is generated between the pixel electrode and the counter electrode (between the anode and the cathode) so that a forward bias voltage is applied. Is provided. The electroluminescent layer is composed of a wide variety of materials such as organic materials and inorganic materials. The luminescence in the electroluminescent layer includes light emission (fluorescence) when returning from a singlet excited state to a ground state, and a triplet excited state. And light emission (phosphorescence) when returning to the ground state.

  The pixel shown in FIG. 47B has the same pixel structure as that shown in FIG. 47A except that a TFT 706 and a scanning line 716 are added. Similarly, the pixel illustrated in FIG. 47D has the same pixel structure as that illustrated in FIG. 47C except that a TFT 706 and a scanning line 716 are added.

  The TFT 706 is controlled to be turned on or off by a newly arranged scanning line 716. When the TFT 706 is turned on, the charge held in the capacitor 702 is discharged, and the TFT 706 is turned off. That is, the arrangement of the TFT 706 can forcibly create a state in which no current flows through the light emitting element 705. Therefore, the configurations in FIGS. 47B and 47D can improve the duty ratio because the lighting period can be started simultaneously with or immediately after the start of the writing period without waiting for signal writing to all the pixels. It becomes possible.

  In the pixel shown in FIG. 47E, a signal line 750, a power supply line 751, a power supply line 752, and a scanning line 753 are arranged in the column direction. Further, the TFT 741 is a switching TFT, the TFT 743 is a driving TFT, and further includes a capacitor element 742 and a light emitting element 744. The pixel shown in FIG. 47F has the same pixel structure as that shown in FIG. 47E except that a TFT 745 and a scanning line 754 are added. Note that the duty ratio of the structure in FIG. 47F can also be improved by the arrangement of the TFTs 745.

    As described above, when the present invention is used, a pattern such as a wiring can be accurately and stably formed without causing defective formation, so that high electrical characteristics and reliability can be imparted to the TFT. Therefore, it can sufficiently cope with applied technology for improving the display capability of the pixel in accordance with the purpose of use.

    This embodiment mode can be used in combination with each of Embodiment Modes 1 to 14.

(Embodiment 16)
FIG. 20 shows an example in which an EL display module is formed using a TFT substrate 2800 manufactured by applying the present invention. In FIG. 20, a pixel portion including pixels is formed over the TFT substrate 2800.

  In FIG. 20, the same TFT as that formed in the pixel or the gate of the TFT and one of the source and the drain is connected between the driving circuit and the pixel, outside the pixel portion. The protection circuit portion 2801 operated in the above is provided. As the driver circuit 2809, a driver IC formed of a single crystal semiconductor, a stick driver IC formed of a polycrystalline semiconductor film over a glass substrate, a driver circuit formed of SAS, or the like is applied.

  The TFT substrate 2800 is fixed to the sealing substrate 2820 through spacers 2806a and 2806b formed by a droplet discharge method. The spacer is preferably provided to keep the distance between the two substrates constant even when the substrate is thin and the area of the pixel portion is increased. A space between the TFT substrate 2800 and the sealing substrate 2820 on the light-emitting element 2804 and the light-emitting element 2805 connected to the TFT 2802 and the TFT 2803, respectively, may be solidified by filling a light-transmitting resin material. Then, it may be filled with dehydrated nitrogen or inert gas.

  FIG. 20 shows a case where the light-emitting element 2804, the light-emitting element 2805, and the light-emitting element 2815 have a top emission type (top emission type) structure, in which light is emitted in the direction of the arrow shown in the drawing. Each pixel can perform multicolor display by changing the emission color of the pixels to red, green, and blue. At this time, by forming the colored layer 2807a, the colored layer 2807b, and the colored layer 2807c corresponding to each color on the sealing substrate 2820 side, the color purity of the emitted light can be increased. Alternatively, the pixel may be combined with a colored layer 2807a, a colored layer 2807b, or a colored layer 2807c as a white light emitting element.

  A driver circuit 2809 which is an external circuit is connected to a scanning line or a signal line connection terminal provided at one end of the external circuit board 2811 through a wiring board 2810. Further, a heat pipe 2813 and a heat radiating plate 2812 may be provided in contact with or in proximity to the TFT substrate 2800 to enhance the heat radiation effect.

  In FIG. 20, the top emission EL module is used. However, the configuration of the light emitting element and the arrangement of the external circuit board may be changed to have a bottom emission structure, of course, a dual emission structure in which light is emitted from both the upper and lower surfaces. In the case of a top emission type structure, an insulating layer serving as a partition wall may be colored and used as a black matrix. The partition walls can be formed by a droplet discharge method, and may be formed by mixing a resin material such as polyimide with a pigment-based black resin, carbon black, or the like, or may be a laminate thereof.

  Further, in the TFT substrate 2800, a sealing structure may be formed by attaching a resin film to the side where the pixel portion is formed using a sealing material or an adhesive resin. Although glass sealing using a glass substrate is described in this embodiment mode, various sealing methods such as resin sealing using a resin, plastic sealing using a plastic, and film sealing using a film can be used. A gas barrier film for preventing the permeation of water vapor may be provided on the surface of the resin film. By adopting a film sealing structure, further reduction in thickness and weight can be achieved.

    This embodiment mode can be used in combination with each of Embodiment Modes 1 to 15.

(Embodiment 17)
A television device (a liquid crystal television device or an EL television device) can be completed by using the display panel (a liquid crystal display panel or an EL display panel) manufactured according to the above embodiment mode. In the display panel, only the pixel portion is formed as shown in FIG. 29A, and the scanning line side driver circuit and the signal line side driver circuit are mounted by the TAB method as shown in FIG. And a case where the TFT is formed by SAS as shown in FIG. 29B, and the pixel portion and the scanning line side driver circuit are integrated on the substrate. In some cases, the signal line side driver circuit is separately mounted as a driver IC, and the pixel portion, the signal line side driver circuit, and the scanning line side driver circuit are integrally formed over the substrate as shown in FIG. However, any form is acceptable.

  As other external circuit configurations, on the video signal input side, among the signals received by the tuner, the video signal amplification circuit that amplifies the video signal, and the signal output from it corresponds to each color of red, green, and blue And a control circuit for converting the video signal into the input specification of the driver IC. The control circuit outputs signals to the scanning line side and the signal line side, respectively. In the case of digital driving, a signal dividing circuit may be provided on the signal line side and an input digital signal may be divided into m pieces and supplied.

  Of the signals received by the tuner, the audio signal is sent to the audio signal amplifier circuit, and the output is supplied to the speaker via the audio signal processing circuit. The control circuit receives control information of the receiving station (reception frequency) and volume from the input unit, and sends a signal to the tuner and the audio signal processing circuit.

  As shown in FIGS. 37A and 37B, the display module can be incorporated into a housing to complete the television device. When an EL display module as shown in FIG. 20 is used, an EL television device can be completed. A main screen 2003 is formed by the display module, and a speaker portion 2009, operation switches, and the like are provided as other accessory equipment. Thus, a television device can be completed according to the present invention.

  Further, as shown in FIG. 21, the EL display module may be configured to block reflected light of light incident from the outside using a phase difference plate or a polarizing plate. FIG. 21 shows a top emission type structure in which an insulating layer 3605 serving as a partition is colored and used as a black matrix. This partition wall can be formed by a droplet discharge method, and carbon black or the like may be mixed with a resin material such as polyimide, or may be a laminate thereof. A different material may be discharged to the same region a plurality of times by a droplet discharge method to form a partition wall. In the present embodiment, a pigment-based black resin is used. A λ / 4 plate or a λ / 2 plate may be used as the phase difference plate 3603 and the phase difference plate 3604 so that light can be controlled. As a structure, it becomes the structure of the TFT substrate 2800, the light emitting element 2804, the sealing substrate (sealing material) 2820, the phase difference plate 3603, the phase difference 3604 (λ / 4 plate, λ / 2 plate), and the polarizing plate 3602. The light emitted from the light emitting element passes through these and is emitted to the outside from the polarizing plate side. The retardation plate and the polarizing plate may be installed on the side from which light is emitted, and may be installed on both sides as long as the display is a double-sided emission type that emits light on both sides. Further, an antireflection film 3601 may be provided outside the polarizing plate. Thereby, it is possible to display a higher-definition and precise image.

  FIG. 61 illustrates an example of a liquid crystal display module. A TFT substrate 6600 and a counter substrate 6601 are fixed to each other with a sealant 6602, and a pixel portion 6603 and a liquid crystal layer 6604 are provided therebetween to form a display region. The colored layer 6605 is necessary for color display. In the case of the RGB method, a colored layer corresponding to each color of red, green, and blue is provided corresponding to each pixel. Polarizing plates 6606 and 6607 and a lens film 6613 are disposed outside the TFT substrate 6600 and the counter substrate 6601. The light source is composed of a cold cathode tube 6610 and a reflection plate 6611. The circuit board 6612 is connected to the TFT substrate 6600 by a flexible wiring board 6609, and external circuits such as a control circuit and a power supply circuit are incorporated.

  Further, the liquid crystal display device manufactured according to the present invention can have higher performance by using an OCB mode capable of high-speed response. FIG. 71 shows an example in which the OCB mode is applied to the liquid crystal display module of FIG. 61, which is an FS-LCD (Field sequential-LCD). The FS-LCD emits red light, green light, and blue light in one frame period, and each light emission is performed by a light emitting diode or the like, so that a color filter is unnecessary. Therefore, since it is not necessary to arrange the color filters of the three primary colors, 9 times as many pixels can be displayed with the same area. On the other hand, since three colors of light are emitted in one frame period, a high-speed response of the liquid crystal is required. Since the thin film transistor included in the liquid crystal display device of the present invention can operate at high speed, an OCB mode can be used. Therefore, the FS mode and the OCB mode can be applied to the liquid crystal display device of the present invention, and a liquid crystal display device and a liquid crystal television with higher performance and higher image quality can be completed. Further, as a mode corresponding to the FS mode, HV-FLC, SS-FLC using a ferroelectric liquid crystal (FLC: Ferroelectric Liquid Crystal), or the like can be used. In the OCB mode, nematic liquid crystal having a relatively low viscosity is used, and smectic liquid crystal is used in HV-FLC and SS-FLC. The liquid crystal display module in FIG. 71 is a transmissive liquid crystal display module, and a red light source 6910a, a green light source 6910b, and a blue light source 6910c are provided as light sources. A control unit 6912 is provided to control on / off of the red light source 6910a, the green light source 6910b, and the blue light source 6910c. Light emission of each color is controlled by the control unit 6912, and light enters the liquid crystal and is displayed as an image.

  A display panel 2002 using a display element such as a liquid crystal element or a light-emitting element (EL element) is incorporated in the housing 2001, and a general television broadcast is received by a receiver 2005, and is wired or wirelessly via a modem 2004. It is also possible to perform information communication in one direction (from the sender to the receiver) or two-way (between the sender and the receiver or between the receivers) by connecting to the communication network. The television device can be operated by a switch incorporated in the housing or a separate remote control device 2006, and the remote control device 2006 also includes a display unit 2007 for displaying information to be output. good.

  In addition, the television device may have a configuration in which a sub screen 2008 is formed using the second display panel in addition to the main screen 2003 to display channels, volume, and the like. In this configuration, the main screen 2003 may be formed using an EL display panel with an excellent viewing angle, and the sub screen may be formed using a liquid crystal display panel that can display with low power consumption. In order to prioritize the reduction in power consumption, the main screen 2003 may be formed using a liquid crystal display panel, the sub screen may be formed using an EL display panel, and the sub screen may blink. By using the present invention, a highly reliable EL display device can be obtained even when such a large substrate is used and a large number of TFTs and electronic components are used.

  FIG. 37B illustrates a television device having a large display portion of 20 to 80 inches, for example, which includes a housing 2010, a display portion 2011, a remote control device 2012 as an operation portion, a speaker portion 2013, and the like. The present invention is applied to manufacture of the display portion 2011. The television set in FIG. 37B is a wall-hanging type and does not require a large installation space.

  Of course, the present invention is not limited to a television device, but can be applied to various uses such as a monitor for a personal computer, an information display board in a railway station or airport, an advertisement display board in a street, etc. can do.

(Embodiment 18)
Various display devices can be manufactured by applying the present invention. That is, the present invention can be applied to various electronic devices in which these display devices are incorporated in a display portion.

  Such electronic devices include cameras such as video cameras and digital cameras, projectors, head mounted displays (goggles type displays), car navigation systems, car stereos, personal computers, game machines, personal digital assistants (mobile computers, mobile phones or An electronic book), and an image reproducing apparatus (specifically, an apparatus having a display capable of reproducing a recording medium such as a digital versatile disc (DVD) and displaying the image). Examples thereof are shown in FIG.

  FIG. 28A illustrates a personal computer, which includes a main body 2101, a housing 2102, a display portion 2103, a keyboard 2104, an external connection port 2105, a pointing mouse 2106, and the like. The present invention is applied to manufacturing the display portion 2103. When the present invention is used, a highly reliable high-quality image can be displayed even if the size is reduced and wiring and the like are refined.

  FIG. 28B shows an image reproducing device (specifically, a DVD reproducing device) provided with a recording medium, which includes a main body 2201, a housing 2202, a display portion A 2203, a display portion B 2204, and a recording medium (DVD etc.) reading portion 2205. , An operation key 2206, a speaker portion 2207, and the like. The display portion A 2203 mainly displays image information, and the display portion B 2204 mainly displays character information. The present invention is applied to the production of the display portions A, B 2203, and 2204. When the present invention is used, a highly reliable high-quality image can be displayed even if the size is reduced and wiring and the like are refined.

  FIG. 28C illustrates a mobile phone, which includes a main body 2301, an audio output portion 2302, an audio input portion 2303, a display portion 2304, operation switches 2305, an antenna 2306, and the like. By applying the display device manufactured according to the present invention to the display portion 2304, a highly reliable and high-quality image can be displayed even in a mobile phone that is downsized and wiring and the like are precise.

  FIG. 28D shows a video camera, which includes a main body 2401, a display portion 2402, a housing 2403, an external connection port 2404, a remote control receiving portion 2405, an image receiving portion 2406, a battery 2407, an audio input portion 2408, operation keys 2409, and the like. . The present invention can be applied to the display portion 2402. By applying the display device manufactured according to the present invention to the display portion 2402, a highly reliable and high-quality image can be displayed even with a video camera that is downsized and wiring and the like are precise. This embodiment mode can be freely combined with the above embodiment modes.

(Embodiment 19)
Embodiments of the present invention will be described with reference to FIGS. 48 to 53, FIG. 7, FIG. 8, and FIG. More specifically, a method for manufacturing a liquid crystal display device to which the present invention is applied will be described. First, a method for manufacturing a liquid crystal display device having a channel-etched thin film transistor to which the present invention is applied is described. 49 to 53A are top views of the pixel portion of the liquid crystal display device, and FIG. 49B to FIG. 53B are cross-sectional views taken along line ab in FIG. 49 to FIG. FIG. 53C is a cross-sectional view taken along line cd in FIGS. 49 to 53A.

    As the substrate 5100, a glass substrate made of barium borosilicate glass, alumino borosilicate glass, or the like, a quartz substrate, a silicon substrate, a metal substrate, a stainless steel substrate, or a plastic substrate having heat resistance that can withstand the processing temperature in this manufacturing process is used. Further, polishing may be performed by a CMP method or the like so that the surface of the substrate 5100 is planarized. Note that an insulating layer may be formed over the substrate 5100. The insulating layer is formed as a single layer or a stacked layer using an oxide material or a nitride material containing silicon by a known method such as a CVD method, a plasma CVD method, a sputtering method, or a spin coating method. This insulating layer is not necessarily formed, but has an effect of blocking contaminants from the substrate 5100. As the substrate 5100, a large-area substrate can be used.

    A conductive film 5101 is formed over the substrate 5100. The conductive film 5101 is patterned into a gate electrode layer and a pixel electrode layer. The conductive film 5101 is preferably formed using a high melting point material by a known method such as a printing method, an electrolytic plating method, a PVD method, a CVD method, or an evaporation method. As a forming method, a desired pattern can be formed by a droplet discharge method. By using a high melting point material, a later heating step is possible. High melting point materials include tungsten (W), molybdenum (Mo), zirconia (Zr), hafnium (Hf), bismuth (Bi), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co) A metal such as nickel (Ni) or platinum (Pt), an alloy thereof, or a metal nitride thereof can be used as appropriate. Further, a plurality of these layers may be stacked. Typically, a tantalum nitride film may be stacked on the substrate surface, and a tungsten film may be stacked thereon. In addition, the subsequent heating process is performed using radiation from one or more kinds selected from halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high pressure sodium lamps, high pressure mercury lamps, LRTA methods, nitrogen and argon, etc. When the GRTA method using an inert gas as a heating medium is used, the conductive film may be formed using aluminum (Al), silver (Ag), or gold (Cu) having a relatively low melting point for heat treatment in a short time. . Such a reflective metal is preferable when a reflective liquid crystal display panel is manufactured. Alternatively, a material in which an impurity element imparting one conductivity type is added to silicon may be used. For example, an n-type silicon film in which an amorphous silicon film contains an impurity element imparting n-type such as phosphorus (P) can be used.

Since the conductive film 5101 also functions as a pixel electrode layer, the conductive film 5101 can also be formed using a transparent conductive material. When a transmissive liquid crystal display panel is manufactured, the pixel electrode layer is made of indium tin oxide (ITO), indium tin oxide containing silicon oxide (ITSO), zinc oxide (ZnO), tin oxide (SnO ₂ ). You may form by. Preferably, it is formed of indium tin oxide (ITO), indium tin oxide containing silicon oxide (ITSO), zinc oxide (ZnO), or the like by a sputtering method. More preferably, an indium tin oxide film containing silicon oxide formed by a sputtering method using a target in which 2 to 10% by weight of silicon oxide is contained in ITO is used. In addition, a conductive material such as an indium zinc oxide alloy in which silicon oxide is included and indium oxide is mixed with 2 to 20% zinc oxide (ZnO) may be used.

    In this embodiment, the conductive film 5101 is formed by discharging a composition containing indium tin oxide as a conductive material and baking at 550 ° C.

  Alternatively, after the conductive film 5101 is formed by discharging a composition by a droplet discharge method, the surface may be pressed and flattened by pressure in order to improve the flatness. As a pressing method, unevenness may be reduced by scanning a roller-like object on the surface, or the surface may be pressed vertically with a flat plate-like object. A heating step may be performed when pressing. Alternatively, the surface may be softened or melted with a solvent or the like, and the surface irregularities may be removed with an air knife. Further, polishing may be performed using a CMP method. This step can be applied when the surface is flattened when unevenness is generated by the droplet discharge method. The planarization step may be performed after the conductive film 5101 is patterned by the masks 5102a and 5102b and the gate electrode layer 5103 and the pixel electrode layer 5111 are formed.

    A resist mask is formed over the conductive film 5101. The mask made of resist is finely processed by being exposed to laser light 5170 to form a mask 5102a and a mask 5102b (see FIG. 49). A resist mask before processing by laser light can also be formed by a droplet discharge method. By combining the droplet discharge method, material loss can be prevented and costs can be reduced as compared to the entire surface coating formation by spin coating or the like.

  For the mask, a commercially available resist material containing a photosensitizer may be used. For example, a novolak resin that is a typical positive resist and a naphthoquinonediazide compound that is a photosensitizer, a base resin that is a negative resist, diphenylsilanediol In addition, an acid generator or the like may be used. Whichever material is used, the surface tension and viscosity are appropriately adjusted by adjusting the concentration of the solvent or adding a surfactant or the like. When a conductive material containing a photosensitive photosensitive material is used for the conductive film 5101, the conductive film 5101 is directly irradiated with laser light without being formed with a resist mask, and is removed by exposure and an etchant. Thus, it can be patterned into a desired pattern. In this case, there is an advantage that the process is simplified because it is not necessary to form a mask. The conductive material containing a photosensitive substance is a photosensitive material composed of a metal or alloy such as Ag, Au, Cu, Ni, Al, Pt, and an organic polymer resin, a photopolymerization initiator, a photopolymerization monomer, or a solvent. What contains a functional resin may be used. As the organic polymer resin, a novolak resin, an acrylic copolymer, a methacrylic copolymer, a cellulose derivative, a cyclized rubber resin, or the like is used.

    The conductive film 5101 is patterned using the mask 5102a and the mask 5102b which are finely processed in this manner, so that the gate electrode layer 5103 and the pixel electrode layer 5111 are formed (see FIG. 50).

Next, a gate insulating layer 5105 a and a gate insulating layer 5105 b are formed over the gate electrode layer 5103 and the pixel electrode layer 5111. As the gate insulating layer 5105a and the gate insulating layer 5105b, silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), silicon nitride oxide (SiNxOy) (x> y), or the like is used as appropriate. be able to. Further, the gate electrode layer 5103 may be anodized to form an anodized film instead of the gate insulating layer 5105a. Note that in order to prevent diffusion of impurities and the like from the substrate side, the gate insulating layer 5105a is preferably formed using silicon nitride (SiNx), silicon nitride oxide (SiNxOy) (x> y), or the like. The gate insulating layer 5105b is preferably formed using silicon oxide (SiOx) or silicon oxynitride (SiOxNy) (x> y) because of interface characteristics with a semiconductor layer to be formed later. However, the present invention is not limited to this step, and it is formed of any one of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), silicon nitride oxide (SiNxOy) (x> y), and the like. It may be formed of a single layer. Note that the gate insulating layer 5105b contains hydrogen. In addition, when silver or copper is used for a conductive layer formed by a droplet discharge method, if a silicon nitride film or a NiB film is formed thereon as a barrier film, diffusion of impurities can be prevented and the surface can be planarized. is there. Note that in order to form a dense insulating film with low gate leakage current at a low deposition temperature, a rare gas element such as argon is preferably contained in a reaction gas and mixed into the formed insulating film. In this embodiment, a gate insulating layer 5105a is formed with a silicon nitride film having a thickness of 50 nm using SiH ₄ and NH ₃ as a reaction gas, and a silicon oxide film is formed with a film thickness of 100 nm using SiH ₄ and N ₂ O as a reaction gas. An insulating layer 5105b is formed. The thickness of the silicon nitride oxide film may be 140 nm, the thickness of the stacked silicon oxynitride film may be 100 nm, and the thickness of the gate insulating layer 5105a and the gate insulating layer 5105b is preferably 50 nm to 100 nm, respectively.

    Next, a semiconductor film is formed. The detailed manufacturing method of the semiconductor layer may be manufactured as shown in FIGS. 9A and 9B using the same materials and steps as those in Embodiment Mode 1. Therefore, detailed description is omitted here. 9D, in the thin film transistor manufactured in this embodiment, the semiconductor layer 107 is included in the semiconductor layer 5106, the n-type semiconductor layer 109 is included in the n-type semiconductor layer 5107a, and the n-type semiconductor layer 111 is included. Corresponds to the n-type semiconductor layer 5107b, the source or drain electrode layer 114 corresponds to the source or drain electrode layer 5108, and the source or drain electrode layer 115 corresponds to the source or drain electrode layer 5130, respectively. . 9D and 9E, in the thin film transistor manufactured in this embodiment, the semiconductor layer 147 is the semiconductor layer 5115, the n-type semiconductor layer 149a is the n-type semiconductor layer 5116a, and the n-type The n-type semiconductor layer 151a corresponds to the n-type semiconductor layer 5116b, the n-type semiconductor layer 151a corresponds to the n-type semiconductor layer 5117a, and the n-type semiconductor layer 151b corresponds to the n-type semiconductor layer 5117b. To do.

    In this embodiment, a photomask is manufactured and a semiconductor layer 5106, an n-type semiconductor layer 5107a, and an n-type semiconductor layer 5107b are formed by a patterning process using a photolithography method (see FIG. 51). . As in the case of forming the mask 5102a, a photomask may be formed by selectively forming a resist on the entire surface by a spin coat method or the like, or a droplet discharge method, and forming a fine pattern mask by exposure by laser light irradiation. . The semiconductor film can be finely and finely patterned into a desired shape with a fine pattern mask.

    When the mask is formed by selectively discharging the composition without performing exposure processing, a resin material such as an epoxy resin, an acrylic resin, a phenol resin, a novolac resin, an acrylic resin, a melamine resin, or a urethane resin can be used. Also, using organic materials such as benzocyclobutene, parylene, flare, permeable polyimide, compound materials made by polymerization of siloxane polymers, composition materials containing water-soluble homopolymers and water-soluble copolymers, etc. It is formed by a droplet discharge method. Whichever material is used, the surface tension and viscosity are appropriately adjusted by adjusting the concentration of the solvent or adding a surfactant or the like.

As the etching process at the time of patterning, either plasma etching (dry etching) or wet etching may be employed, but plasma etching is suitable for processing a large area substrate. As an etching gas, a fluorine-based gas such as CF ₄ , NF ₃ , SF ₆ , or CHF ₃ , a chlorine-based gas typified by Cl ₂ , BCl ₃ , SiCl _4, or CCl ₄ , or an O ₂ gas is used. An inert gas such as He or Ar may be added as appropriate. Further, if an atmospheric pressure discharge etching process is applied, a local electric discharge process is also possible, and it is not necessary to form a mask layer on the entire surface of the substrate.

    A composition containing a conductive material is discharged to form a source or drain electrode layer 5130, a source or drain electrode layer 5108, and a capacitor wiring layer 5104. The source or drain electrode layer 5130 and the source electrode The semiconductor layer 5106, the n-type semiconductor layer 5107a, and the n-type semiconductor layer 5107b are patterned using the layer or drain electrode layer 5108 as a mask, so that the semiconductor layer 5115, the n-type semiconductor layer 5116a, and the n-type semiconductor layer 5107b The semiconductor layer 5116b including the n-type, the semiconductor layer 5117a including the n-type, and the semiconductor layer 5117b including the n-type are formed (see FIG. 52). The step of forming the source or drain electrode layer 5130 and the source or drain electrode layer 5108 can be performed in a manner similar to that of forming the gate electrode layer 5103 described above. The source or drain electrode layer 5130 also functions as a wiring layer.

  As a conductive material for forming the source or drain electrode layer 5130 and the source or drain electrode layer 5108, Ag (silver), Au (gold), Cu (copper), W (tungsten), Al (aluminum) A composition mainly composed of metal particles such as the above can be used. Further, light-transmitting indium tin oxide (ITO), ITSO made of indium tin oxide and silicon oxide, organic indium, organic tin, zinc oxide, titanium nitride, or the like may be combined.

  The source electrode layer or the drain electrode layer may be formed as described in Embodiment Mode 1 with reference to FIGS. Therefore, detailed description here is saved. The source or drain electrode layer 5130 and the source or drain electrode layer 5108 are formed in a fine pattern. If the source or drain electrode layer 5108 is not formed with good controllability, a defect such as a short circuit due to formation failure is caused. Therefore, fine patterning on the semiconductor layer is performed by fine processing with a laser beam. By forming a mask by fine processing using laser light and patterning the conductive film, the conductive film can be patterned with high controllability and a source electrode layer and a drain electrode layer having desired shapes can be formed. Therefore, since the formation failure does not occur, the reliability of the thin film transistor is also improved.

    FIG. 8 is also a conductive film patterning method using an exposure process using laser light as in FIG. 7, but the conductive film 205 is not formed on the entire surface as in FIG. 7, but is selectively formed by a droplet discharge method. It is. In FIG. 8, the conductive film 215a and the conductive film 215b are selectively formed by the droplet discharge method without being in contact with each other, so that it is not necessary to form the opening 232b as shown in FIG. In addition, end portions of the source or drain electrode layer 218a, the source or drain electrode layer 218b, the source or drain electrode layer 218c, and the source or drain electrode layer 218d that are obtained because patterning by etching is not performed. Can have a rounded shape with a radius of curvature. Therefore, when the droplet discharge method is used, material loss is reduced and the process is simplified, so that there is an advantage in that cost is low and productivity is increased.

    After the source or drain electrode layer 5130 and the source or drain electrode layer 5108 are formed, a planarization step by pressing or the like may be performed as in the case of the gate electrode layer 5103. In addition to flattening the electrode layer, the source electrode layer or the drain electrode layer is included in the electrode layer by ejecting the source electrode layer or the drain electrode layer by a droplet discharge method and performing preliminary firing, and then sandwiching a pressing step during the main firing. The released oxygen is released and the oxygen concentration is lowered, so that the electrical resistance is also reduced.

    An insulating film 5109 serving as a passivation film is preferably formed so as to cover the source or drain electrode layer, the semiconductor layer, the gate electrode layer, and the gate insulating layer. The insulating film 5109 is formed using a thin film formation method such as a plasma CVD method or a sputtering method, and contains silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, aluminum oxynitride, or aluminum oxide, diamond-like carbon (DLC), and nitrogen. It can be formed using carbon (CN) or other insulating materials. Note that the passivation film may be a single layer or a laminated structure. Here, a stacked structure in which silicon oxide or silicon oxynitride is formed from the interface characteristics of the semiconductor layer 5115 and then silicon nitride or silicon nitride oxide is formed to prevent external impurities from entering the semiconductor element. preferable. In this embodiment mode, the silicon oxide film is formed to a thickness of 150 nm in contact with the semiconductor layer 5115, and then the gas is switched in the same chamber so that the silicon nitride film is continuously formed to a thickness of 200 nm. Form.

    After that, the semiconductor layer 5115 is preferably hydrogenated by heating in a hydrogen atmosphere or a nitrogen atmosphere. Note that in the case of heating in a nitrogen atmosphere, an insulating film containing hydrogen is preferably formed as the insulating film 5109.

    Next, the insulating layer 5110 is formed. In this embodiment, the insulating layer 5110 is formed over the entire surface, and is etched and patterned with a mask such as a resist. In the case where the insulating layer 5110 is formed using a droplet discharge method, a printing method, or the like that can be directly and selectively formed, patterning by etching is not necessarily required.

    The insulating layer 5110 includes silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, diamond-like carbon (DLC), nitrogen-containing carbon film (CN), other inorganic insulating materials, or acrylic acid, Methacrylic acid and derivatives thereof, or polyimide, aromatic polyamide, polybenzimidazole, polybenzoimidazole, benzocyclobutene, polysilazane, or other organic insulating materials, or silicon formed using a siloxane material as a starting material, oxygen, Among compounds composed of hydrogen, an inorganic siloxane containing a Si—O—Si bond, or an organic siloxane insulating material in which hydrogen on silicon is substituted with an organic group such as methyl or phenyl can be used. You may form using photosensitive and non-photosensitive materials, such as an acryl and a polyimide.

    In this embodiment mode, a siloxane resin may be used as the material for the insulating layer 5110.

    An opening 5135 reaching the source or drain electrode layer 5108 in the insulating film 5109 and the insulating layer 5110, and an opening reaching the pixel electrode layer 5111 in the gate insulating layer 5105a, the gate insulating layer 5105b, the insulating film 5109, and the insulating layer 5110 An opening 5137 that reaches 5136 and the gate electrode layer 5103 is formed. This opening is also formed by etching using a resist mask. The mask used for patterning can be a mask having a fine shape by performing exposure by laser light irradiation. A wiring layer 5113 is formed in the opening 5135 and the opening 5137 thus formed, and the source or drain electrode layer 5108 and the pixel electrode layer 5111 are electrically connected. A gate wiring layer 5112 is also formed in the opening 5137 so as to be electrically connected to the gate electrode layer 5103. When the gate wiring layer 5112 is formed using a low-resistance material, high-speed operation is possible even when the gate electrode layer 5103 is made of a slightly high-resistance material, and a large current can flow.

    Through the above steps, a TFT substrate for a liquid crystal display panel in which a bottom gate type (also referred to as an inverted stagger type) thin film transistor and a pixel electrode are connected to the substrate 5100 is completed. The thin film transistor of this embodiment mode is a channel etch type.

    Next, as illustrated in FIG. 48, an insulating layer 5114 called an alignment film is formed by a printing method or a spin coating method so as to cover the pixel electrode layer 5111. 48 is a cross-sectional view taken along line AB of the top view shown in FIGS. 49 to 53, and is a completed view of the liquid crystal display panel. Note that the insulating layer 5114 can be selectively formed by a screen printing method or an offset printing method. Then, rubbing is performed. Subsequently, a sealing material is formed in a peripheral region where pixels are formed by a droplet discharge method (not shown).

  After that, an insulating substrate 5121 functioning as an alignment film, a colored layer 5122 functioning as a color filter, a conductor layer 5123 functioning as a counter electrode, a counter substrate 5124 provided with a polarizing plate 5125, and a substrate 5100 having TFTs are provided with spacers. And a liquid crystal display panel can be manufactured by providing a liquid crystal layer 5120 in the gap (see FIG. 48). A filler may be mixed in the sealing material, and a shielding film (black matrix) or the like may be formed on the counter substrate 5124. Note that as a method for forming the liquid crystal layer, a dispenser type (dropping type) or a dip type (pumping type) in which liquid crystal is injected using a capillary phenomenon after the counter substrate 5124 is bonded can be used.

  A liquid crystal dropping injection method employing a dispenser method will be described with reference to FIG. In FIG. 60, 40 is a control device, 42 is an imaging means, 43 is a head, 33 is a liquid crystal, 35 and 41 are markers, 34 is a barrier layer, 32 is a sealing material, 30 is a TFT substrate, and 20 is a counter substrate. A closed loop is formed by the sealing material 32, and the liquid crystal 33 is dropped from the head 43 once or plural times therein. The head 43 includes a plurality of nozzles, and a large amount of liquid crystal material can be dropped at a time, thereby improving the throughput. At that time, a barrier layer 34 is provided to prevent the sealing material 32 and the liquid crystal 33 from reacting. Subsequently, the substrates are bonded together in a vacuum, and thereafter UV curing is performed to fill the liquid crystal.

A connection portion is formed in order to connect the pixel portion formed in the above steps and an external wiring substrate. The insulator layer in the connection portion is removed by ashing using oxygen gas at or near atmospheric pressure. This treatment is performed using oxygen gas and one or more selected from hydrogen, CF ₄ , NF ₃ , H ₂ O, and CHF ₃ . In this step, in order to prevent damage and destruction due to static electricity, ashing is performed after sealing using the counter substrate. However, if there is little influence from static electricity, it may be performed at any timing. .

  Subsequently, a wiring board for connection is provided so that the wiring layer in the liquid crystal display device is electrically connected via the anisotropic conductor layer. The wiring board plays a role of transmitting signals and potentials from the outside, and FPC (Flexible printed circuit) or the like can be used. Through the above steps, a liquid crystal display panel including a channel etch type switching TFT and a capacitor is completed. The capacitor is formed of a capacitor wiring layer 5104, a gate insulating layer 5105a, a gate insulating layer 5105b, and a pixel electrode layer 5111.

    The wiring layer in the liquid crystal display device and the FPC are connected using a terminal electrode layer. The terminal electrode layer is made of the same material and process as the gate electrode layer, and the same material and the same material as the source wiring layer that also serves as the source and drain electrode layers. It can be fabricated in the same process and the same material as the gate wiring layer. A connection example between the FPC and a wiring layer in the liquid crystal display device will be described with reference to FIG.

    In FIG. 69, a thin film transistor 709 and a pixel electrode layer 706 are formed over a substrate 701 and bonded to a counter substrate 708 with a sealant 703. A wiring layer extending from the inside of the liquid crystal display device and formed outside the sealant is bonded to the FPC 702b and the FPC 702a by an anisotropic conductive film 707a and an anisotropic conductive film 707b.

    69 (A1), (B1), and (C1) are top views of the liquid crystal display device, and FIGS. 69 (A2), (B2), and (C2) are FIGS. 69 (A1), (B1), and (C1). It is sectional drawing of line OP and line RQ in FIG. 69A1 and 69A2, the terminal electrode layer 705a and the terminal electrode layer 705b are formed of the same material and in the same step as the gate electrode layer. A source wiring layer 704a formed to extend to the outside of the sealant is connected to the terminal electrode layer 705a, and the terminal electrode layer 705a and the FPC 702a are connected to each other through an anisotropic conductive film 707a. On the other hand, a gate wiring layer 704b formed to extend outside the sealant is connected to the terminal electrode layer 705b, and the terminal electrode layer 705b and the FPC 702b are connected to each other through an anisotropic conductive film 707b.

    69B and 69B, the terminal electrode layer 755a and the terminal electrode layer 755b are formed of the same material and step as the source wiring layer. The terminal electrode layer 755a is formed of a source wiring layer formed to extend to the outside of the sealing material, and the terminal electrode layer 755a and the FPC 702a are connected to each other through an anisotropic conductive film 707a. On the other hand, a gate wiring layer 754b formed to extend to the outside of the sealant is connected to the terminal electrode layer 755b, and the terminal electrode layer 755b and the FPC 702b are connected through an anisotropic conductive film 707b.

    69C1 and 69C2, the terminal electrode layer 764a and the terminal electrode layer 764b are formed using the same material and step as the gate wiring layer. A terminal electrode layer 764a is connected to a source wiring layer 765a formed outside the sealing material, and the terminal electrode layer 764a and the FPC 702a are connected through an anisotropic conductive film 707a. On the other hand, the terminal electrode layer 764b is formed of a gate wiring layer formed to extend outside the sealant, and the terminal electrode layer 764b and the FPC 702b are connected to each other through an anisotropic conductive film 707b.

  In this embodiment mode, the switching TFT has a single gate structure, but a multi-gate structure such as a double gate structure may be used.

Through the above steps, an inverted staggered thin film transistor having a crystalline semiconductor film can be formed. Since the thin film transistor formed in this embodiment is formed using a crystalline semiconductor film, it has higher mobility (about ^{2 to} 50 cm ² / Vsec) than a thin film transistor formed using an amorphous semiconductor film. In addition, the source region and the drain region include a metal element in addition to the impurity element imparting one conductivity type. For this reason, a source region and a drain region with low resistivity can be formed. As a result, a liquid crystal display device capable of high-speed operation can be manufactured. Therefore, it is possible to manufacture a liquid crystal display device that can display with a high response speed and a high viewing angle as in the OCB mode.

  Further, compared with a thin film transistor formed using an amorphous semiconductor film, a threshold shift is less likely to occur, and variations in thin film transistor characteristics can be reduced.

  Further, since the metal element mixed in the semiconductor film in the film formation stage is also gettered by the gettering step, off current can be reduced. For this reason, it is possible to improve contrast by providing such a TFT in a switching element of a liquid crystal display device.

    In addition, it is possible to freely design thinning of wirings and the like by fine processing of laser light irradiation. According to the present invention, a desired pattern can be formed with good controllability, material loss is small, and cost reduction can be achieved. Accordingly, a high-performance and highly reliable liquid crystal display device can be manufactured with high yield.

(Embodiment 20)
This embodiment will be described with reference to FIGS. In this embodiment, the pixel region is a pixel region manufactured in Embodiment Mode 1 and the thin film transistor included in the pixel is a multi-gate type. In addition, the peripheral driver circuit region is also formed using a thin film transistor using the present invention, and a CMOS including an n-channel thin film transistor and a p-channel thin film transistor manufactured in Embodiment Mode 2 is applied. Therefore, repetitive description of the same portion or a portion having a similar function is omitted.

    59 is a top view of a pixel region of the liquid crystal display device manufactured in this embodiment mode, and FIGS. 54 to 57 and FIG. 58B show lines ef and gh in FIG. 59 in each step. It is sectional drawing. 54 to 57 are cross-sectional views corresponding to lines ls, tk, and ij, which are peripheral driver circuit regions of the liquid crystal display device of FIG. .

  A conductive film is formed over the substrate 5300 and patterned with a resist mask to form a gate electrode layer 5301, a gate electrode layer 5302, a gate electrode layer 5303a, a gate electrode layer 5303b, a gate electrode layer 5303c, and a pixel electrode layer 5304. To do. In this embodiment mode, the gate electrode layer is formed using a single layer of a transparent conductive film, but may have a stacked structure. As the laminated structure, it is possible to use a laminated film of Ta, Ti, W, Mo, Cr, nitride films of the above elements, specifically, a laminated film of TaN and W, a laminated film of TaN and Mo, or a TaN and Cr film. , TiN and W, TiN and Mo, TiN and Cr, and the like can be used. In this embodiment, a composition containing indium tin oxide containing silicon oxide (ITSO) is discharged by a droplet discharge method, and baked to form a conductive film in the vicinity including the gate electrode layer formation region. This conductive film is precisely patterned using a mask finely processed by exposure with laser light, and a gate electrode layer 5301, a gate electrode layer 5302, a gate electrode layer 5303a, a gate electrode layer 5303b, a gate electrode layer 5303c, and a pixel An electrode layer 5304 is formed.

    A gate insulating layer is formed over the gate electrode layer 5301, the gate electrode layer 5302, the gate electrode layer 5303a, the gate electrode layer 5303b, the gate electrode layer 5303c, and the pixel electrode layer 5304, and an amorphous semiconductor film 5306 is formed over the gate insulating layer. It is formed (see FIG. 54A). In this embodiment, a gate insulating layer 5305a made of silicon nitride and a gate insulating layer 5305b made of silicon oxide are stacked as the gate insulating layer. As the amorphous semiconductor film 5306, an amorphous silicon film is used. The gate insulating layer 5305a, the gate insulating layer 5305b, and the amorphous semiconductor film 5306 are continuously formed by a plasma CVD method only by switching the gas type. By forming continuously, a process is simplified and it can prevent that the pollutant in air | atmosphere adheres to the film | membrane surface and an interface.

    A metal film 5307 is formed over the amorphous semiconductor film 5306 as a method for introducing an element that promotes or promotes crystallization. Since the metal film 5307 is very thin, the shape as a film may not be maintained. In this embodiment mode, a metal film 5307 is formed by applying an aqueous solution containing Ni of 100 ppm by a spin coating method. The amorphous semiconductor film 5306 coated with the metal film 5307 is heated and crystallized. In this embodiment, heat treatment is performed at 550 ° C. for 4 hours, so that a crystalline semiconductor film 5309 is formed (see FIG. 54B).

    An n-type semiconductor film 5308 is formed over the crystalline semiconductor film 5309. In this embodiment, as the semiconductor film 5308 having n-type, an amorphous silicon film containing phosphorus (P) as an impurity element imparting n-type is formed to a thickness of 100 nm by a plasma CVD method. Heat treatment is performed using the n-type semiconductor film 5308 as a gettering sink, so that the metal element in the crystalline semiconductor film 5309 is gettered (see FIG. 54C). The metal element in the crystalline semiconductor film moves in the direction of the arrow by heat treatment, and is captured in the semiconductor film 5308 having n-type conductivity. Therefore, the crystalline semiconductor film 5309 becomes a crystalline semiconductor film 5310 in which the metal element in the film is reduced, and the n-type semiconductor film 5308 includes an impurity element imparting n-type (P in this embodiment). An n-type semiconductor film 5311 containing a metal element (Ni in this embodiment) is formed.

    The crystalline semiconductor film 5310 and the n-type semiconductor film 5311 are patterned to have a semiconductor layer 5312, a semiconductor layer 5313, a semiconductor layer 5314, an n-type semiconductor layer 5315, an n-type semiconductor layer 5316, and an n-type. A semiconductor layer 5317 can be formed (see FIG. 55A). The patterning of these semiconductor layers can also be performed precisely using a mask finely processed by exposure with the laser beam of the present invention.

    Next, the mask 5318a covering the semiconductor layer 5312, the n-type semiconductor layer 5315, the channel formation region of the semiconductor layer 5316, and the mask 5318b covering the channel formation region of the n-type semiconductor layer 5316, the semiconductor layer 5314, and the n-type are formed. A mask 5318c which covers the semiconductor layer 5317 is formed. An impurity element 5319 imparting p-type conductivity is added to form a p-type impurity region 5320a and a p-type impurity region 5320b in the p-type semiconductor layer 5316 (see FIG. 55B). In this embodiment mode, an impurity element imparting p-type conductivity is added using an ion doping method. After that, heat treatment is performed at 550 ° C. for 4 hours to activate the impurity element addition region.

    Next, in the driver circuit region, part of the gate insulating layer 5305a and the gate insulating layer 5305b is etched using a photomask in order to connect the gate electrode and the source or drain electrode of some TFTs. A contact hole 890 as shown in FIG. 40 is formed. 40, in this embodiment, the gate electrode layer 301 is the gate electrode layer 5301, the gate electrode layer 302 is the gate electrode layer 5302, the semiconductor layer 371 is the semiconductor layer 5371, the semiconductor layer 372 is the semiconductor layer 5372, The source or drain electrode layer 327a is the source or drain electrode layer 5327a, the source or drain electrode layer 327b is the source or drain electrode layer 5327b, and the source or drain electrode layer 327c is the source electrode layer. Alternatively, it corresponds to the drain electrode layer 5327c. In this embodiment mode, the pixel electrode layer and the source or drain electrode layer are connected to each other through a contact hole formed in the interlayer insulating layer. However, the source or drain electrode layer and the pixel electrode layer are interlayer-insulated. You may connect without passing through a layer. In this case, an opening reaching the pixel electrode layer can be formed at the same time as the contact hole 890. After that, a source electrode layer or a drain electrode layer is formed in these contact holes, and electrically connected to the gate electrode layer or the pixel electrode layer, respectively.

    After the mask 5318a, the mask 5318b, and the mask 5318c are removed, a conductive layer 5321 and a conductive layer 5322 are formed over the semiconductor layer 5312, the semiconductor layer 5313, and the semiconductor layer 5314. In this embodiment, the conductive layer 5321 and the conductive layer 5322 are selectively formed by a droplet discharge method, so that material loss is reduced. Silver (Ag) is used as the conductive material, and a composition containing Ag is discharged from the droplet discharge device 5380a and the droplet discharge device 5380b and is baked at 300 ° C., so that the conductive layer 5321 and the conductive layer 5322 are formed ( (See FIG. 55C). In the same step, a conductive layer 370 serving as a capacitor wiring layer is also formed over the gate insulating layer 5305b over the pixel electrode layer 5304.

    As described in Embodiment Mode 1 with reference to FIGS. 8A and 8B, the conductive layer 5321 and the conductive layer 5322 are precisely patterned to form a source or drain electrode layer 5327a, a source or drain electrode layer 5327b, and a source electrode layer. Alternatively, the drain electrode layer 5327c, the source or drain electrode layer 5328a, the source or drain electrode layer 5328b, the source or drain electrode layer 5328c, and the capacitor wiring layer 5332 are formed. Source or drain electrode layer 5327a, Source or drain electrode layer 5327b, Source or drain electrode layer 5327c, Source or drain electrode layer 5328a, Source or drain electrode layer 5328b, Source or drain electrode layer 5328b The semiconductor layer 5312, the semiconductor layer 5313, the semiconductor layer 5314, the n-type semiconductor layer 5315, the n-type semiconductor layer 5316, and the n-type semiconductor layer 5317 are etched using the electrode layer 5328c as a mask, and the semiconductor layer 371, a semiconductor layer 372, a semiconductor layer 373, an n-type semiconductor layer 5324a, an n-type semiconductor layer 5324b, a p-type semiconductor layer 5325a, a p-type semiconductor layer 5325b, an n-type semiconductor layer 5326a, Semiconductor layer 5326 having n-type To form a semiconductor layer 5326c having n-type. Etching can be dry etching or wet etching. In this embodiment mode, a dry etching method is used.

    Through the above steps, an n-channel thin film transistor 5335, a p-channel thin film transistor 5336, an n-channel thin film transistor 5337, and a capacitor 5338 which form a CMOS can be formed (see FIG. 56A). Although a CMOS structure is used in this embodiment mode, the present invention is not limited to this, and a PMOS structure or an NMOS structure may be used.

    An insulating film 5330 to be a passivation film is formed. In this embodiment, the insulating film 5330 is formed using a stacked film of a silicon oxide film with a thickness of 150 nm and a silicon nitride film with a thickness of 200 nm from the side in contact with the semiconductor layer. The insulating film 5330 may be formed using another silicon-containing film, or a silicon oxynitride film may be used instead of the silicon oxide film, and a silicon oxynitride film and a silicon nitride film may be stacked.

    The insulating film 5330 is formed so as to contain oxygen, and heat treatment is performed in a nitrogen atmosphere at a temperature of 300 to 500 ° C. to hydrogenate the semiconductor layer.

    An insulating layer 5339 is formed over the insulating film 5330. In this embodiment, a silicon oxide film including an alkyl group is formed using a slit coater. An opening 5340a reaching the source or drain electrode layer 5328b is formed in the insulating layer 5339 and the insulating film 5330, and an opening reaching the pixel electrode layer 5304 is formed in the insulating layer 5339, the insulating film 5330, the gate insulating layer 5305a, and the gate insulating layer 5305b. An opening 5340c reaching 5340b and the gate electrode layer 5303c is formed (see FIG. 56B). For the patterning for forming the opening, the fine processing by the laser beam of the present invention can be used. In this embodiment mode, the opening is formed by dry etching.

    Next, a gate wiring layer 5341 and a gate wiring layer 5342 are formed. In this embodiment mode, the gate wiring layer is formed using Ag and a droplet discharge method. A composition containing Ag as a conductive material is discharged into the opening 5340a, the opening 5340b, and the opening 5340c and is baked at 300 ° C. Through the above steps, a gate wiring layer 5341 that electrically connects the source or drain electrode layer 5328b and the pixel electrode layer 5304 and a gate wiring layer 5342 that is electrically connected to the gate electrode layer 5303c are formed (FIG. 56). (See (C).)

    FIG. 59 shows a top view of a pixel region of a liquid crystal display device manufactured in this embodiment mode. The thin film transistor provided in the pixel region is a multi-gate type. In the pixel region, a gate electrode layer 5303a, a gate electrode layer 5303b, a pixel electrode layer 5304, a semiconductor layer 373, a source or drain electrode layer 5328a, a source or drain electrode layer 5328b, a source or drain electrode layer 5328c , Capacitor wiring layer 5332, gate wiring layer 5342, and gate wiring layer 5341.

  Next, as illustrated in FIG. 57, an insulating layer 5343 called an alignment film is formed by a printing method or a spin coating method so as to cover the pixel electrode layer 5304. Note that the insulating layer 5343 can be selectively formed by a screen printing method or an offset printing method. Thereafter, a rubbing process is performed. Subsequently, a sealant 5351 is formed in a peripheral region where the pixels are formed.

  After that, an insulating substrate 5345 functioning as an alignment film, a colored layer 5346 functioning as a color filter, a conductor layer 5347 functioning as a counter electrode, a counter substrate 5348 provided with a polarizing plate 5350 and a substrate 5300 are interposed through a spacer 5375. A liquid crystal display panel can be manufactured by bonding and providing a liquid crystal layer 5344 in the gap (see FIG. 58). The spacer may be provided by dispersing particles having a size of several μm, but in this embodiment, a method of forming a resin film on the entire surface of the substrate and then patterning it is employed. After applying such a spacer material with a spinner, it is formed into a predetermined pattern by exposure and development processing. Further, it is cured by heating at 150 to 200 ° C. in a clean oven or the like. The spacers produced in this way can have different shapes depending on the conditions of exposure and development processing, but preferably, the spacers are columnar and the top is flat, so that the opposite substrate is When combined, the mechanical strength of the liquid crystal display panel can be ensured. The shape can be a conical shape, a pyramid shape or the like, and there is no particular limitation. A filler may be mixed in the sealing material, and a shielding film (black matrix) or the like may be formed on the counter substrate 5348. In addition, an FPC 5354 is bonded to a terminal electrode layer 5352 for electrically connecting the inside and the outside of the liquid crystal display device with an anisotropic conductive film 5353 so as to be electrically connected to the terminal electrode layer 5352.

    FIG. 58A is a top view of the display device. As shown in FIG. 58A, the pixel region 5360, the scan line drive region 5361a, and the scan line drive region 5361b are sealed between the substrate 5300 and the sealing substrate 5348 with a sealant 5351, and are formed on the substrate 5300. A signal line driver circuit 5362 formed by an IC driver is provided. In this embodiment mode, the polarizing plate is provided only on the counter substrate 3548 side; however, the polarizing plate may also be provided on the substrate 5300 side including a TFT.

    In the liquid crystal display device in FIGS. 58A and 58B described in this embodiment, the gate electrode layer 5301, the gate electrode layer 5302, the gate electrode layer 5303a, the gate electrode layer 5303b, and the pixel electrode layer 5304 have a single-layer structure. As described above, two or more gate electrode layers may be stacked. An example in which the gate electrode layer and the pixel electrode layer are stacked is shown in FIG.

  As the stacked structure, Ta, Ti, W, Mo, Cr, and a nitride film of the above elements can be used. Specifically, TaN \ W, TaN \ Mo, TaN \ Cr, TiN \ W, TiN \ Mo, TiN \ Cr, etc. can be used. In this embodiment, TaN is used as the first gate electrode layer 5301a, the first gate electrode layer 5302a, the first gate electrode layer 5303a1, the first gate electrode layer 5303b1, and the first gate electrode layer 5303c1, W is used as the second gate electrode layer 5301b, the second gate electrode layer 5302b, the second gate electrode layer 5303a2, the second gate electrode layer 5303b2, and the second gate electrode layer 5303c2. Also in the pixel electrode layer formed in the same step, a TaN film is formed as the first pixel electrode layer 5304a, and a W film is formed as the second pixel electrode layer 5304b. Thus, the gate electrode layer and the pixel electrode layer can have a stacked structure. In addition, the pixel electrode layer may be formed in a single layer structure, and the gate electrode layer may be formed in a laminated structure. Conversely, the pixel electrode layer may be formed in a laminated structure and the gate electrode layer may be formed in a single layer structure. What is necessary is just to set suitably according to the function requested | required of a liquid crystal display device.

    Through the above steps, an inverted staggered thin film transistor having a crystalline semiconductor film can be formed. Since the thin film transistor formed in this embodiment is formed using a crystalline semiconductor film, it has higher mobility than a thin film transistor formed using an amorphous semiconductor film. In addition, the source region and the drain region include a metal element in addition to the impurity element imparting one conductivity type. For this reason, a source region and a drain region with low resistivity can be formed. As a result, a liquid crystal display device capable of high-speed operation can be manufactured. Therefore, it is possible to manufacture a liquid crystal display device that can display with a high response speed and a high viewing angle as in the OCB mode.

    Further, compared with a thin film transistor formed using an amorphous semiconductor film, a threshold shift is less likely to occur, and variations in thin film transistor characteristics can be reduced.

    Further, since the metal element mixed in the semiconductor film in the film formation stage is also gettered by the gettering step, off current can be reduced. Therefore, the contrast can be improved by providing such a thin film transistor in the switching element of the liquid crystal display device.

(Embodiment 21)
In Embodiment 1, a gate electrode layer, a source electrode layer or a drain electrode layer (including a source wiring layer) and a capacitor wiring layer are stacked with a gate insulating layer interposed therebetween, and a source electrode layer or a drain electrode layer (source wiring) A multilayer structure in which a gate wiring layer and a gate wiring layer are stacked with an interlayer insulating layer interposed therebetween. In this embodiment, an example in which these stacked structures are different will be described with reference to FIGS. 62 to 67 and FIG. 62A to 67A are top views of the liquid crystal display device, and FIGS. 62B to 64B are lines x1− in FIGS. 62A to 64A. It is sectional drawing by v1, line x2-v2, and line x3-v3. 65A to 68A are top views of the liquid crystal display device, and FIGS. 65B to 68B are illustrated in FIG. 65A to FIG. It is sectional drawing by z1, line y2-z2, and line y3-z3.

    62A is a top view of the liquid crystal display device, FIG. 62B is a cross-sectional view taken along line x1-v1 in FIG. 62A, and FIG. 62C is in FIG. It is sectional drawing by line MN. The liquid crystal display device illustrated in FIG. 62 does not have a structure in which the source electrode layer or the drain electrode layer and the pixel electrode layer are electrically connected to each other through the gate wiring layer as described in Embodiment Mode 1. The electrode layer 5600 is formed to be in direct contact with the pixel electrode layer 5611 and is electrically connected. In this manner, the source or drain electrode layer 5610 may be directly connected to the pixel electrode layer 5611. In the case of a reflective liquid crystal display device, a reflective material is used for the source or drain electrode layer 5610, and the pixel A structure in which the electrode layer 5611 is stacked may be employed.

    62, in a pixel region of the liquid crystal display device, a gate electrode layer 5601a, a gate electrode layer 5601b, a pixel electrode layer 5601, a gate insulating layer 5602a, a gate insulating layer 5602b, a capacitor wiring layer 5604, and a source electrode are formed over a substrate 5600. Layer or drain electrode layer 5603a, source or drain electrode layer 5603b, gate wiring layer 5607, semiconductor layer 5608, n-type semiconductor layer 5609a, n-type semiconductor layer 5609b, insulating film 5605 which is a passivation film, insulating Layer 5606 is formed.

    Although the insulating film 5605 is not necessarily required, when the insulating film 5605 is formed, the insulating film 5605 functions as a passivation film, and thus the reliability of the liquid crystal display device is further improved. In addition, when the insulating film 5605 is formed and heat treatment is performed, the semiconductor layer can be hydrogenated with hydrogen contained in the insulating film 5605.

    As shown in FIG. 62B, the source or drain electrode layer 5603b is stacked with the gate wiring layer 5607 with the insulating layer 5606 which is an interlayer insulating layer interposed therebetween. 5601a and the gate electrode layer 5601b are connected to the insulating layer 5606, the insulating film 5605, the gate insulating layer 5602a, and the contact hole formed in the gate insulating layer 5602b. Therefore, the gate wiring layer 5607 is not short-circuited with the source or drain electrode layer 5603b and the capacitor wiring layer 5604.

    63A is a top view of the liquid crystal display device, and FIG. 63B is a cross-sectional view taken along line x2-v2 in FIG. 63A. 63, a gate electrode layer 5621a, a gate electrode layer 5621b, a gate insulating layer 5622a, a gate insulating layer 5622b, a capacitor wiring layer 5624, a source electrode layer or a drain electrode layer are formed over a substrate 5620 in a pixel region of the liquid crystal display device. 5623a, a source or drain electrode layer 5623b, a gate wiring layer 5627a, a gate wiring layer 5627b, an insulating film 5625 which is a passivation film, and an insulating layer 5626 are formed.

    As shown in FIG. 63B, the source or drain electrode layer 5623b is stacked over the gate wiring layer 5627b with the insulating layer 5626 which is an interlayer insulating layer interposed therebetween. 5621a, the gate electrode layer 5621b, the insulating layer 5626, the insulating film 5625, the gate insulating layer 5622a, and the contact hole formed in the gate insulating layer 5622b. Therefore, the gate wiring layer 5627b, the source or drain electrode layer 5623b, and the capacitor wiring layer 5624 are not short-circuited. The liquid crystal display device shown in FIG. 63 has a structure in which the gate wiring layer and the gate electrode layer are formed intermittently rather than continuously, and are electrically connected to each other through contact holes. ing. Therefore, in the region where the source or drain electrode layer 5623b and the capacitor wiring layer 5624 are formed, the gate electrode layer 5621a and the gate electrode layer 5621b are formed in contact with the gate wiring layer 5627b and the contact hole formed over the insulating film 5626. It is electrically connected by connecting.

    64A is a top view of the liquid crystal display device, and FIG. 64B is a cross-sectional view taken along line x3-v3 in FIG. 64A. In FIG. 64, in a pixel region of the liquid crystal display device, a gate electrode layer 5631a, a gate electrode layer 5632b, a gate insulating layer 5632a, a gate insulating layer 5632b, a capacitor wiring layer 5634, a source electrode layer or a drain electrode layer are formed over a substrate 5630. 5633a, a source or drain electrode layer 5633b, a gate wiring layer 5537a, a gate wiring layer 5537b, a wiring layer 5638a, a wiring layer 5638b, an insulating film 5635 which is a passivation film, and an insulating layer 5636 are formed.

    As shown in FIG. 64B, the source or drain electrode layer 5633b is stacked with the gate wiring layer 5537b with the insulating layer 5636 which is an interlayer insulating layer interposed therebetween. In the liquid crystal display device illustrated in FIG. 63, the gate electrode layer 5621a is directly connected to the gate wiring layer 5627a and the gate wiring layer 5627b. However, in the liquid crystal display device illustrated in FIG. 64, the gate electrode layer 5631a, the gate wiring layer 5537a, and the gate wiring layer 5537b are electrically connected to each other through the wiring layer 5638a formed in the same process and using the same material as the source electrode layer. Connected. Accordingly, the gate electrode layer 5632a is connected to the wiring layer 5638a formed over the gate insulating layer 5632a and the gate insulating layer 5632b through a contact hole, and the wiring layer 5638a is connected to the gate wiring layer 5537a and the gate wiring layer 5637b through the contact hole. Connect. Therefore, the gate electrode layer 5631a, the gate wiring layer 5637a, and the gate wiring layer 5637b are electrically connected. Since the source or drain electrode layer 5633b and the capacitor wiring layer 5634 are stacked with the gate wiring layer 5537b through the insulating layer 5636 which is an interlayer insulating layer, the source or drain electrode layer 5633b and the capacitor wiring layer 5634 and the gate are stacked. The wiring layer 5637b is not short-circuited.

    62, 63 and 64 show the case where an insulating layer is formed as an interlayer insulating layer so as to cover a wide range. FIG. 65, FIG. 66 and FIG. 67 show an example in which an interlayer insulating layer separating wiring layers is selectively formed only at a necessary portion using a droplet discharge method.

    FIG. 65 corresponds to FIG. 62, FIG. 66 corresponds to FIG. 63, and FIG. 67 corresponds to the liquid crystal display device of FIG. 64. The structure of the interlayer insulating layer is different. FIG. 65A is a top view of the liquid crystal display device, and FIG. 65B is a cross-sectional view taken along line Y1-Z1 in FIG. In FIG. 65, an insulating layer 5650 is formed by a droplet discharge method so as to cover the source or drain electrode layer 5603b and the capacitor wiring layer 5604. A gate wiring layer 5607 is formed so as to straddle over the insulating layer 5650. Over the gate wiring layer 5607, an insulating film 5660 is formed as a passivation film. Although the insulating film 5660 is not necessarily required, formation of the insulating film 5660 can improve reliability. In this embodiment mode, the insulating layer 5650 is a single layer; however, an insulating film may be formed over or below the insulating layer 5650 to have a stacked structure.

    66A is a top view of the liquid crystal display device, and FIG. 66B is a cross-sectional view taken along line Y2-Z2 in FIG. 66A. 66, as in FIG. 65, an insulating layer 5651 is selectively formed by a droplet discharge method so as to cover the source or drain electrode layer 5623b and the capacitor wiring layer 5624. A gate wiring layer 5627b is formed so as to straddle over the insulating layer 5651, and is connected to the gate electrode layer 5621a through a contact hole. An insulating film 5661 is formed as a passivation film over the gate wiring layer 5627a.

    67A is a top view of the liquid crystal display device, and FIG. 67B is a cross-sectional view taken along line Y3-Z3 in FIG. 67A. In FIG. 67, as in FIG. 65, an insulating layer 5562 is selectively formed by a droplet discharge method so as to cover the source or drain electrode layer 5633b and the capacitor wiring layer 5634. A gate wiring layer 5637b is formed so as to straddle over the insulating layer 5562, and is electrically connected to the gate wiring layer 5637a and the gate electrode layer 5631a through the wiring layer 5638a.

    When an insulating layer for preventing a short circuit between wiring layers such as the insulating layer 5650, the insulating layer 5651, and the insulating layer 5562 is selectively formed by a droplet discharge method, material loss is reduced. Further, since the wirings can be formed so as to be in direct contact with each other, the number of steps for forming a contact hole in the insulating layer is reduced. Therefore, the process can be simplified and low cost and high productivity can be obtained.

    The liquid crystal display device in FIG. 68 is also an example in which an insulating layer 5653 provided to physically separate the source or drain electrode layer 5634b and the capacitor wiring layer 5644 from the wiring layer 5647b is selectively formed by a droplet discharge method. is there. In the liquid crystal display device in FIGS. 65 to 67, the source electrode layer or the drain electrode layer and the gate wiring layer are prevented from being short-circuited by being formed on the insulating layer so as to straddle the gate wiring layer. In the liquid crystal display device in FIG. 68, the wiring layer 5647a and the wiring layer 5647b are formed in the step of forming the gate electrode layer 5541a and the gate electrode layer 5541b. After that, part of the gate insulating layer covering the wiring layers 5647a and 5647b is removed by etching before forming the source or drain electrode layer 5634a and the capacitor wiring layer 5644. An insulating layer 5653 is selectively formed over part of the wiring layer 5647b by a droplet discharge method, and a source or drain electrode layer 5634a and a capacitor wiring layer 5644 are formed over the insulating layer 5653. In the same process as the formation of the source or drain electrode layer 5634b and the capacitor wiring layer 5644, the wiring layer 5648a and the wiring layer 5648b are formed in contact with the gate electrode layer 5541a and the gate electrode layer 5541b, respectively. The wiring layer 5648a and the wiring layer 5648b are electrically connected to each other by the wiring layer 5647b under the insulating layer 5653. In this manner, the gate wiring layer and the gate electrode layer can be electrically connected under the insulating layer 5653.

    As shown in the above steps, a highly reliable liquid crystal display device can be manufactured with low cost and high productivity.

6A and 6B illustrate a display device of the present invention. 4A to 4D illustrate a method for manufacturing a display device of the present invention. 4A to 4D illustrate a method for manufacturing a display device of the present invention. 4A to 4D illustrate a method for manufacturing a display device of the present invention. 4A to 4D illustrate a method for manufacturing a display device of the present invention. 4A to 4D illustrate a method for manufacturing a display device of the present invention. 4A to 4D illustrate a method for manufacturing a display device of the present invention. 4A to 4D illustrate a method for manufacturing a display device of the present invention. 4A to 4D illustrate a method for manufacturing a display device of the present invention. 4A to 4D illustrate a method for manufacturing a display device of the present invention. 4A to 4D illustrate a method for manufacturing a display device of the present invention. 4A to 4D illustrate a method for manufacturing a display device of the present invention. 4A to 4D illustrate a method for manufacturing a display device of the present invention. 4A to 4D illustrate a method for manufacturing a display device of the present invention. 4A to 4D illustrate a method for manufacturing a display device of the present invention. 4A to 4D illustrate a method for manufacturing a display device of the present invention. 4A to 4D illustrate a method for manufacturing a display device of the present invention. 4A to 4D illustrate a method for manufacturing a display device of the present invention. 4A to 4D illustrate a method for manufacturing a display device of the present invention. FIG. 6 illustrates a structure of an EL display module of the present invention. FIG. 6 illustrates a structure of an EL display module of the present invention. 3A and 3B illustrate a display device of the present invention. 3A and 3B illustrate a display device of the present invention. 3A and 3B illustrate a display device of the present invention. 3A and 3B illustrate a display device of the present invention. 1A and 1B illustrate a structure of a laser beam direct drawing apparatus that can be applied to the present invention. 2A and 2B illustrate a structure of a droplet discharge device that can be applied to the present invention. FIG. 11 illustrates an electronic device to which the present invention is applied. FIG. 14 is a top view illustrating an EL display panel of the present invention. FIG. 14 is a top view illustrating an EL display panel of the present invention. 3A and 3B illustrate a display device of the present invention. 3A and 3B illustrate a display device of the present invention. 3A and 3B illustrate a display device of the present invention. 3A and 3B illustrate a display device of the present invention. 3A and 3B illustrate a display device of the present invention. 3A and 3B illustrate a display device of the present invention. FIG. 11 illustrates an electronic device to which the present invention is applied. 3A and 3B illustrate a display device of the present invention. 3A and 3B illustrate a display device of the present invention. 3A and 3B illustrate a display device of the present invention. 3A and 3B illustrate a display device of the present invention. The figure which shows the protection circuit to which this invention is applied. 4A and 4B illustrate an EL display panel of the present invention. 3A and 3B illustrate a display device of the present invention. 3A and 3B each illustrate a structure of a light-emitting element that can be applied to the present invention. 3A and 3B illustrate a display device of the present invention. FIG. 10 is a circuit diagram illustrating a structure of a pixel that can be applied to an EL display panel of the present invention. 6A and 6B illustrate a display device of the present invention. 4A to 4D illustrate a method for manufacturing a display device of the present invention. 4A to 4D illustrate a method for manufacturing a display device of the present invention. 4A to 4D illustrate a method for manufacturing a display device of the present invention. 4A to 4D illustrate a method for manufacturing a display device of the present invention. 4A to 4D illustrate a method for manufacturing a display device of the present invention. 4A to 4D illustrate a method for manufacturing a display device of the present invention. 4A to 4D illustrate a method for manufacturing a display device of the present invention. 4A to 4D illustrate a method for manufacturing a display device of the present invention. 4A to 4D illustrate a method for manufacturing a display device of the present invention. 4A to 4D illustrate a method for manufacturing a display device of the present invention. 4A to 4D illustrate a method for manufacturing a display device of the present invention. 4A and 4B illustrate a liquid crystal dropping method that can be applied to the present invention. FIG. 6 illustrates a structure of a display module of the present invention. 3A and 3B illustrate a display device of the present invention. 3A and 3B illustrate a display device of the present invention. 3A and 3B illustrate a display device of the present invention. 3A and 3B illustrate a display device of the present invention. 3A and 3B illustrate a display device of the present invention. 3A and 3B illustrate a display device of the present invention. 3A and 3B illustrate a display device of the present invention. 4A and 4B illustrate a display panel of the present invention. 3A and 3B illustrate a display device of the present invention. FIG. 6 illustrates a structure of a display module of the present invention.

Claims (10)

A gate electrode layer and a pixel electrode layer provided on the insulating surface;
A gate insulating layer provided on the gate electrode layer;
A crystalline semiconductor layer provided on the gate insulating layer;
A semiconductor layer having one conductivity type provided in contact with the crystalline semiconductor layer;
A source electrode layer and a drain electrode layer provided in contact with the semiconductor layer having the one conductivity type ;
An insulating layer provided on the source electrode layer, the drain electrode layer, and the pixel electrode layer;
The insulating layer has a first opening reaching the source electrode layer or the drain electrode layer;
The gate insulating layer and the insulating layer has a second opening reaching the pixel electrode layer,
A display device comprising: a wiring layer that is provided in the first opening and the second opening and electrically connects the source or drain electrode layer and the pixel electrode layer. . Oite to claim 1,
The display device, wherein the semiconductor layer having one conductivity type includes a metal element that promotes or promotes crystallization of the semiconductor layer. A gate electrode layer and a pixel electrode layer provided on the insulating surface;
A gate insulating layer provided on the gate electrode layer;
A crystalline semiconductor layer having a source region and a drain region provided on the gate insulating layer;
A source electrode layer and a drain electrode layer provided in contact with the source region and the drain region;
An insulating layer provided on the source electrode layer, the drain electrode layer, and the pixel electrode layer;
The insulating layer has a first opening reaching the source electrode layer or the drain electrode layer;
The gate insulating layer and the insulating layer has a second opening reaching the pixel electrode layer,
A display device comprising: a wiring layer that is provided in the first opening and the second opening and electrically connects the source or drain electrode layer and the pixel electrode layer. . In claim 3 ,
The display device, wherein the source region and the drain region contain a metal element that promotes or promotes crystallization of the semiconductor layer. In any one of claims 1 to 4,
The gate electrode layer and the pixel electrode layer are formed on the same surface and are made of one or more selected from tungsten, molybdenum, zirconia, hafnium, bismuth, niobium, tantalum, chromium, cobalt, nickel, and platinum. Characteristic display device. In any one of claims 1 to 4,
The gate electrode layer and the pixel electrode layer are formed on the same surface and are made of indium tin oxide, indium tin oxide containing silicon oxide, zinc oxide, tin oxide, or an indium zinc oxide alloy. apparatus. In any one of Claims 1 thru | or 6 ,
The gate insulating layer and before Kize' Enso has a third opening reaching the gate electrode layer,
A display device comprising a gate wiring layer in contact with the gate electrode layer provided in the third opening. Forming a conductive layer on the insulating surface;
Forming a resist on the conductive layer;
The resist is exposed to a laser beam and patterned to form a mask,
Patterning the conductive layer using the mask to form a gate electrode layer and a pixel electrode layer;
Forming a gate insulating layer on the gate electrode layer and the pixel electrode layer;
Forming an amorphous semiconductor layer on the gate insulating layer;
A metal element that promotes or promotes crystallization of the amorphous semiconductor layer is added to the amorphous semiconductor layer and heated to crystallize the amorphous semiconductor layer to form a crystalline semiconductor layer. ,
Forming a semiconductor layer having one conductivity type in contact with the crystalline semiconductor layer;
Heating the crystalline semiconductor layer and the semiconductor layer having one conductivity type;
Patterning the semiconductor layer having one conductivity type to form a source region and a drain region;
Forming a source electrode layer and a drain electrode layer in contact with the source region and the drain region;
Forming an insulating layer on the source electrode layer, the drain electrode layer, and the gate insulating layer;
Forming a first opening reaching the source electrode layer or the drain electrode layer with respect to the insulating layer, and a second opening reaching the pixel electrode layer with respect to the insulating layer and the gate insulating layer;
In the display device, a wiring layer that electrically connects the source electrode layer or the drain electrode layer and the pixel electrode layer is formed in the first opening and the second opening. Manufacturing method. Forming a conductive layer on the insulating surface;
Forming a resist on the conductive layer;
The resist is exposed to a laser beam and patterned to form a mask,
Patterning the conductive layer using the mask to form a gate electrode layer and a pixel electrode layer;
Forming a gate insulating layer on the gate electrode layer and the pixel electrode layer;
Forming a first semiconductor layer on the gate insulating layer;
Adding and heating a metal element that promotes or promotes crystallization of the first semiconductor layer to the first semiconductor layer;
Forming a second semiconductor layer having a first impurity element in contact with the first semiconductor layer;
By heating the first semiconductor layer and the second semiconductor layer having the first impurity element, the metal element is moved to the second semiconductor layer,
Removing the second semiconductor layer having the first impurity element;
Adding a second impurity element to the first semiconductor layer to form a source region and a drain region;
Forming a source electrode layer or a drain electrode layer in contact with the source region and the drain region;
Forming an insulating layer on the source electrode layer, the drain electrode layer, and the gate insulating layer;
A first opening reaching the source electrode layer or the drain electrode layer is formed with respect to the insulating layer, and a second opening reaching the pixel electrode layer is formed with respect to the insulating layer and the gate insulating layer. ,
In the display device, a wiring layer that electrically connects the source electrode layer or the drain electrode layer and the pixel electrode layer is formed in the first opening and the second opening. Manufacturing method. Oite to claim 8 or 9,
The conductive layer, the source electrode layer and the drain electrode layer, a method for manufacturing a display device characterized by selectively forming by discharging a composition comprising an electrically conductive material.

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