JP4858367B2 - Manufacturing method of solid-state imaging device - Google Patents

Description

  The present invention relates to a method for manufacturing a solid-state image sensor, and more particularly to a method for manufacturing a so-called back-illuminated solid-state image sensor.

As semiconductor devices become highly integrated, transistors and other semiconductor elements tend to be further reduced to further increase the packaging density.
For this reason, even in a CMOS sensor (CMOS type solid-state imaging device), it is required to miniaturize a pixel and highly integrate the device.

  However, in the conventional CMOS sensor, the light receiving sensor unit is irradiated with light from the lens formed on the wiring unit and detected through the wiring layer. As the device becomes finer, vignetting of incident light occurs due to obstacles such as a wiring layer, so the aperture ratio of the light receiving sensor portion is reduced, and sufficient light cannot be irradiated to the light receiving sensor portion. . For this reason, the problem that a sensitivity falls or a shading becomes large also arises.

Therefore, by irradiating the light receiving sensor part with light from the back side (the side opposite to the wiring part), it becomes possible to achieve an effective aperture ratio of 100% without being affected by obstacles such as a wiring layer, The sensitivity can be greatly increased.
For this reason, development of a so-called back-illuminated CMOS sensor, which is configured to irradiate light to the light-receiving sensor unit from the back side (the side opposite to the wiring unit), has been performed.

  In a back-illuminated image sensor, it is considered to obtain a high sensitivity by thinning the silicon layer of the light receiving sensor portion (for example, see Patent Document 1 or Patent Document 2).

A schematic cross-sectional view of a back-illuminated CMOS sensor to which this configuration is applied is shown in FIG.
In the CMOS sensor 100, since the silicon substrate 101 of the light receiving sensor unit 102 is formed thin, the sensitivity of the incident light L can be increased.
Further, even if the wiring layer 104 is formed on the light receiving sensor portion 102, the incident light L is not blocked, so that the degree of freedom in the layout of the wiring layer 104 is increased. Thus, the wiring layer 104 is formed in multiple layers and the area of the pixel is reduced, so that high integration of elements can be achieved.

  As a method for manufacturing such a back-illuminated image sensor with a thin silicon layer, for example, a method of forming a photodiode of a light receiving sensor portion on a silicon substrate and then polishing and thinning the silicon substrate from the back surface can be considered. ing.

JP-A-6-77461 (FIG. 3) JP-A-6-283702 (FIG. 2)

However, in the above manufacturing method, the interface of the silicon substrate after the back surface is polished becomes electrically unstable. In addition, mechanical damage enters the silicon substrate.
For these reasons, dark current is caused.

For this reason, the application of the image sensor having the above-described configuration of the back-illuminated structure has been limited, for example, by cooling.
Furthermore, the light absorption depends on the thickness of the silicon layer, but since it is thinned by polishing, the controllability of the thickness of the silicon layer (silicon substrate) of the light-receiving sensor part is poor, and therefore the spectral characteristics as a sensor are poor. It will vary.
Due to such a problem, the production yield deteriorates and the cost increases.

  Therefore, the back-illuminated structure is used only for very limited applications, although the sensitivity of the light receiving sensor portion can be increased.

In addition, in the conventional back-illuminated structure image sensor, the thickness of the silicon layer on which the light receiving sensor portion for photoelectric conversion is formed is several tens of μm. As a result, the signal charge diffuses and color mixing occurs.
For this reason, it is difficult to realize a fine pixel.

  In order to solve the above-described problems, in the present invention, a solid-state imaging device having a configuration that has high sensitivity and hardly generates shading and that can achieve pixel miniaturization is manufactured with a good yield. The present invention provides a method for manufacturing a solid-state imaging device.

  The method for manufacturing a solid-state imaging device of the present invention uses a laminated substrate in which a silicon substrate, an intermediate layer, and a silicon layer are laminated, and a step of forming a semiconductor region of the light receiving sensor portion on the silicon layer of the laminated substrate; A step of forming a wiring portion having a wiring layer in an insulating layer above the silicon layer, a step of pasting a supporting substrate on the wiring portion, and a step of removing the silicon substrate and the intermediate layer to expose the silicon layer And at least.

According to the method for manufacturing a solid-state imaging device of the present invention described above, the wiring portion is formed above the silicon layer, the silicon substrate (of the laminated substrate) and the intermediate layer are removed, and the silicon layer is exposed. A back-side illuminated structure in which the silicon layer on the back surface opposite to the formed front surface side is exposed and light is irradiated from the back surface side can be obtained.
In addition, in order to form the semiconductor region of the light receiving sensor unit in the silicon layer of the laminated substrate using the laminated substrate in which the silicon substrate, the intermediate layer, and the silicon layer are stacked, silicon forming the semiconductor region of the light receiving sensor unit The interface of the layers is relatively stable, and it becomes easy to control the thickness of the silicon layer and stabilize the spectral characteristics of the solid-state imaging device.
Moreover, for the silicon layer forming the semiconductor region, the wiring portion is formed on the front surface side, and the silicon substrate and the intermediate layer on the back surface side are removed. It is possible to prevent damage from entering.
If a laminated substrate having a thin silicon layer is used, the solid-state imaging device of the present invention described above, that is, the silicon layer in which the semiconductor region of the light receiving sensor portion is formed is 10 μm or less (or 5 μm or less) and the solid structure is thin. An image sensor can be manufactured.

According to the method for manufacturing a solid-state imaging device of the present invention, the wiring portion is formed above the silicon layer, and then the support substrate is bonded to the wiring portion, and the silicon substrate and the intermediate layer are removed to expose the silicon layer. Therefore, the interface of the silicon layer is stable, and the thickness of the silicon layer can be controlled to stabilize the spectral characteristics of the solid-state imaging device, so that a solid-state imaging device with good spectral characteristics is manufactured with high yield. be able to.
If a laminated substrate having a thin silicon layer is used, a solid-state imaging device having a thin silicon layer in which the semiconductor region of the light receiving sensor portion is formed can be easily manufactured.
In particular, since it can be manufactured by heat treatment at a relatively low temperature, it is possible to reduce the influence of heat treatment on the transistor and the like, thereby forming a transistor with a narrow pitch and reducing the pixel size. It becomes easy to plan. In addition, there is little increase in the number of processes.

FIG. 1 shows a schematic configuration diagram (cross-sectional view) of a solid-state imaging device as an embodiment of the present invention.
In this embodiment, the present invention is applied to a CMOS sensor (CMOS type solid-state imaging device).
The solid-state imaging device 1 is configured by forming a support substrate 2, a wiring portion 3, a silicon substrate 4, a color filter 5, and an on-chip lens 6 from the front side.
The wiring part 3 is formed by forming a plurality of wiring layers 12 via an interlayer insulating layer 11. A thin insulating film 13 serving as a gate insulating film is formed between the wiring portion 3 and the silicon substrate 4, and a gate electrode 14 for reading out charges is formed on the surface side of the insulating film 13.
In the silicon substrate 4, an N-type region 17 constituting a photodiode of the light-receiving sensor portion is formed thick in the thickness direction, and a positive charge accumulation region (P ⁺ region) 16 is formed on the surface side of the N-type region 17. Is formed. In addition, an N-type floating diffusion (FD) 15 is formed through a readout region under the gate electrode 14.
Although not shown, the support substrate 2 and the wiring part 3 are bonded by an adhesive layer or the like. As the support substrate 2, for example, a silicon substrate can be used. A substrate made of another material may be used as long as the material has good flatness and a small difference in thermal expansion coefficient from silicon.
The light L is incident from the lens 6 side, that is, the back surface side opposite to the wiring portion 3, so that a so-called back-illuminated CMOS sensor is configured.

A read transistor is configured by the gate electrode 14, the tip of the N-type region 17, and the floating diffusion 15.
In the cross section (not shown), other transistors in the pixel and circuit elements in the peripheral portion are formed on the surface side of the silicon substrate 4.

In particular, in the present embodiment, the thickness D of the silicon layer (silicon substrate) 4 on which the light receiving sensor part is formed is 10 μm or less. More preferably, the thickness D of the silicon layer 4 is 5 μm or less.
Thereby, since the thickness D of the silicon layer 4 is formed thin, it is possible to suppress the occurrence of color mixing due to the incidence of light on adjacent pixels, and to realize high sensitivity.
Furthermore, a drift electric field of about 200 mV / μm or more can be formed by designing in a driving voltage range (2.5 V to 3.3 V) normally used in a CMOS sensor. It is possible to reliably read out the charges.
Further, noise due to light irradiation is equal to or less than that of the CMOS type solid-state imaging device having the surface irradiation type structure.

  When the thickness D of the silicon layer 4 is 10 μm or less, high sensitivity can be obtained in a wide wavelength range including the infrared region.

When the thickness D of the silicon layer 4 is 5 μm or less, high sensitivity can be obtained in the visible light region.
In addition, since a drift electric field of about 400 mV / μm or more can be formed when designed in the above-described driving voltage range, it is possible to easily read out charges to the surface side.

As described above, when the thickness D of the silicon layer 4 is set to 5 μm or less, there is an advantage that the manufacturing is facilitated.
When the thickness D of the silicon layer 4 exceeds 5 μm, in order to form the N-type region 17 having the configuration shown in FIG. 1, ultrahigh energy ion implantation or a hard film such as an oxide film before ion implantation is performed. It is necessary to form a mask.
On the other hand, when the thickness D of the silicon layer 4 is set to 5 μm or less, ion implantation for forming the N-type region 17 using a resist mask can be performed, so that the manufacturing can be easily performed.

Further, in the solid-state imaging device 1 of the present embodiment, a P ⁺ region (high-concentration P-type region) 18 is deep as a pixel separation region between the N-type regions 17 of the light receiving sensor portions of adjacent pixels. It is formed over the entire direction.
Thereby, the N-type region 17 of each pixel can be electrically separated, and electrical color mixing between adjacent pixels can be prevented.

Further, in the solid-state imaging device 1 of the present embodiment, the P ⁺ region 19 is also formed on the back surface side of the N-type region 17, that is, on the color filter 5 side.
Thereby, the dark current resulting from the interface state on the back surface side of the silicon layer 4 can also be reduced.

In the solid-state imaging device 1, as shown in a cross-sectional view in the vicinity of the light receiving sensor portion in FIG. 2, incident light is photoelectrically converted at a relatively deep position (back side portion) of the N type region of the light receiving sensor portion. As indicated by an arrow in FIG. 2, the electric charge e ⁻ moves to the surface side. This movement is performed more smoothly as the drift electric field is larger.
Then, the charge e ⁻ is read out to the floating diffusion 15 by turning on the gate electrode 14.

Here, in the solid-state imaging device 1 having the configuration shown in FIG. 1, the relationship between the thickness D of the silicon layer and the wavelength dependency of the incident light L of the quantum efficiency in the light receiving sensor unit was examined.
FIG. 3 and FIG. 4 show the relationship between the thickness D (μm) of the silicon layer and the dependency of the quantum efficiency on the wavelength (nm) of the incident light L in the light receiving sensor unit. FIG. 3 shows the thickness D of the silicon layer and the quantum efficiency of the entire silicon layer of that thickness. FIG. 4 shows the quantum efficiency (absorption ratio in each part) in the thickness section every 1 μm from the incident side of the light L. For example, the section of thickness 2 μm to 3 μm is plotted at 2.5 μm. ing.

From FIG. 3, blue (wavelength near 400 nm) is 2 μm or less, and green (wavelength near 550 nm) is about 5 μm, and each is 100% absorbed. Red (wavelength around 750 nm) does not absorb 100% even at 10 μm.
From FIG. 4, when the thickness of the silicon layer is 5 μm, the ratio of red (750 nm) absorbed at a depth of 4.75 to 5.25 μm (assuming the diffusion layer of the transistor) is 2% at the maximum. Green and blue are negligibly small.

In addition, in a solid-state imaging device for image application viewed with the human eye, an infrared cut filter is provided so that infrared rays do not enter.
The spectral characteristics of this infrared cut filter are shown in FIG. FIG. 5 shows both an evaporation type infrared cut filter and an absorption type infrared cut filter. Normally, a vapor deposition type is used, and as shown in FIG. 5, light having a wavelength of 650 nm or less is almost transmitted, but light having a wavelength longer than 650 nm is cut off.
Therefore, a solid-state imaging device for image application viewed by the human eye does not need to have sensitivity on the longer wavelength side than 650 nm. In the case of monitoring, it is better to have sensitivity to infrared rays.
Even when the thickness D of the silicon layer 4 is 5 μm or less, sufficient sensitivity to light having a wavelength of 650 nm or less can be obtained. Therefore, in the solid-state imaging device for image application viewed with the human eye, By adopting the configuration, sufficiently high sensitivity can be obtained.

Further, the occurrence of color mixing due to diffracted light in a surface-illuminated structure CMOS sensor was examined by two-dimensional wave analysis.
On the other hand, in a CMOS sensor having a backside illumination structure, color mixing due to diffracted light hardly occurs, and is below the detection limit of wave analysis (0.1% or less).
However, in a CMOS sensor having a backside illumination structure, light incident from the backside may affect a device (for example, a transistor) on the front side and become a noise source.
Therefore, by setting the thickness of the silicon layer to, for example, 5 μm, it is possible to suppress the influence of light incident from the back surface on the surface side element (for example, transistor), and to reduce the total noise amount of the surface irradiation type structure. This can be reduced as compared with a CMOS sensor.

  According to the configuration of the solid-state imaging device 1 of the present embodiment described above, the on-chip lens 6 is provided on the opposite side (rear surface side) to the wiring portion 3 side (front surface side) of the silicon layer 4 on which the light receiving sensor portion is formed. Etc., and has a back-illuminated structure in which the light L is incident from the back side, and there is no wiring layer 12 between the on-chip lens 6 and the light receiving sensor unit, and the vignetting of incident light by the wiring layer 12 Does not occur. As a result, the amount of incident light can be increased even if the area of the light receiving sensor portion is the same, and the area of the light receiving sensor portion can be increased or the pattern shape of the N-type region 17 can be set so that light can easily enter. Thus, the sensitivity can be improved. In addition, the occurrence of shading in peripheral pixels can be suppressed.

Since the solid-state imaging device 1 shown in FIG. 1 does not require light to pass through the back-illuminated structure, the layout and layout of the wiring layer 12 and the degree of design freedom increase. For example, the film thickness and resistance of the wiring layer 13 can be optimized.
Thereby, the solid-state imaging device 1 of each pixel can be further miniaturized to achieve high integration and miniaturization. Although it is difficult to configure a CMOS sensor having one million pixels or more with the front-illuminated structure, it is easy to realize one million pixels or more with the configuration of this embodiment.

  Further, according to the configuration of the solid-state imaging device 1 of the present embodiment, since the thickness D of the silicon layer 4 is 10 μm or less, more preferably 5 μm or less, the silicon layer has a thickness of about several tens of μm. Compared with the configuration of the conventional back-illuminated structure, the thickness D of the silicon layer 4 is reduced, and the distance between the lens 6 and the N-type region 17 of the light receiving sensor portion can be further shortened. In this respect as well, the sensitivity can be improved and the occurrence of color mixing due to incidence on adjacent pixels can be suppressed. Thereby, even when the pixels are miniaturized, the occurrence of color mixing can be suppressed.

And, when the thickness D of the silicon layer 4 is reduced, a drift electric field can be strongly formed when designed in a range of normal voltage (2.5 V to 3.3 V), and photoelectric conversion is performed on the back side. The charged charges can be easily read out to the surface side.
Thereby, even if the amount of charge accumulated in the light receiving sensor unit is increased, the charge can be sufficiently read out, and thus the dynamic range can be improved by increasing the amount of accumulated charge.

Furthermore, according to the configuration of the solid-state imaging device 1 of the present embodiment, the pixel separation region is formed over the entire thickness of the silicon layer 4 between the N-type regions 17 constituting the photodiode of the light receiving sensor portion of each pixel. Since the P ⁺ region 18 is formed, the pixels can be electrically separated, and electrical color mixing with adjacent pixels can be prevented.

Furthermore, according to the configuration of the solid-state imaging device 1 of the present embodiment, the P ⁺ region 19 is also provided on the back surface side of the N-type region 17 of the silicon layer 4, so that the surface side (positive charge accumulation region) Similar to 16), a so-called HAD (Hole Accumulated Diode) structure is also formed on the back side. Thereby, generation | occurrence | production of the dark current in the interface vicinity of the silicon layer 4 on the back side can be suppressed.

  And since the solid-state image sensor 1 of this Embodiment is a CMOS sensor (CMOS type solid-state image sensor), generation | occurrence | production of the smear which becomes a problem with a CCD solid-state image sensor does not arise.

Next, a method for manufacturing a solid-state imaging device having a back-illuminated structure having the same configuration as that of the solid-state imaging device 1 of FIG. 1 will be described as an embodiment of the manufacturing method of the solid-state imaging device of the present invention.
In the present embodiment, as shown in a cross-sectional view in FIG. 6, an SOI substrate 24 in which a silicon layer 21 is formed on a silicon substrate 23 via a silicon oxide film (SiO ₂ film) as an intermediate layer 22 is used. .
The total thickness of the SOI substrate 24 is, for example, 725 μm or less, and the thickness of the silicon layer 21 is 10 μm or less (more preferably, 5 μm or less).

First, as shown in FIG. 7A, in the silicon layer 21 of the SOI substrate 24, an N-type region 25, which is a main part (a part on the back side) of the N-type region 17 constituting the photodiode, and a P ⁺ region on the back side. 19 are formed by ion implantation. In addition, an alignment mark 26 for positioning the color filter and the on-chip lens is also formed.

Next, as illustrated in FIG. 7B, an adhesive layer 32 is formed on one surface of the first support substrate 31, and the first support substrate 31 is bonded to the silicon layer 21 of the SOI substrate 24 through the adhesive layer 32. To do. Then, adhesion is performed by performing a heat treatment at 1100 ° C., for example. At this time, impurities in the N-type region 25 and the P ⁺ region 19 of the silicon layer 21 are activated.

Next, as shown in FIG. 7C, the wafer is turned upside down.
Subsequently, the silicon substrate 23 and the intermediate layer 22 on the silicon layer 21 are sequentially removed by, for example, a back grinding method, a CMP (chemical mechanical polishing) method, wet etching, or the like. As a result, as shown in FIG. 8D, the silicon layer 21 is exposed.

Next, the gate electrode 14 of the read transistor is formed on the silicon layer 21 through a thin insulating film. Further, N-type impurities are ion-implanted into the silicon layer 21 from the surface side, and an N-type region 27 that becomes a remaining surface-side portion of the N-type region 17 constituting the photodiode and an N-type region are included. A floating diffusion 15 is formed. Further, P-type impurity ions are implanted into the silicon layer 21 from the surface side to form the P-type (P ⁺ ) positive charge accumulation region 16 on the surface of the N-type region 27 (see FIG. 8E above).
Thereby, the N-type region 17 of the light receiving sensor part is formed by the N-type region 25 formed from the back surface side and the N-type region 27 formed from the front surface side.

Subsequently, as illustrated in FIG. 8F, the wiring portion 3 is formed on the silicon layer 21 by forming the multilayer wiring layer 12 via the interlayer insulating layer 11.
Further, although not shown, a protective film is formed on the upper surface of the wiring part 3. This protective film is for preventing the wiring portion 3 from absorbing moisture and adversely affecting the wiring layer 12, and for example, a silicon nitride film is formed by plasma CVD.

  Next, as shown in FIG. 9G, an adhesive layer 34 is formed on one surface of the second support substrate 33, and the second support substrate 33 is bonded onto the wiring portion 3 through the adhesive layer 34. And it adhere | attaches by performing the heat processing of 400 degrees C or less. Since the heat treatment this time is after the wiring layer 12 is formed, the temperature is set to 400 ° C. or lower so as not to affect the wiring layer 12. As the adhesive layer 34 in this case, SOG (spin on glass) or a metal layer capable of metal bonding can be used.

Next, as shown in FIG. 9H, the wafer is inverted again.
Subsequently, the first support substrate 31 and the adhesive layer 32 on the silicon layer 21 are removed by, for example, a back grinding method, a CMP (chemical mechanical polishing) method, wet etching, or the like. Thereby, as shown in FIG. 10I, the silicon layer 21 is exposed.

Next, as shown in FIG. 10J, an antireflection film 28 is formed on the silicon layer 21, and the color filter 5 and the on-chip lens 6 are sequentially formed thereon. Although not shown, pad electrodes for connecting external terminals are also formed.
In this way, a solid-state imaging device having a backside illumination type structure can be manufactured.

In the CMOS sensor such as the solid-state imaging device 1 shown in FIG. 1, a semiconductor chip having the same peripheral circuit unit for driving and controlling the solid-state imaging device 1 as well as the solid-state imaging device 1 constituting the imaging unit. Formed.
Accordingly, although not shown, when the semiconductor region of the light receiving sensor portion is formed, a semiconductor region such as a transistor of the peripheral circuit portion is also formed. Similarly, the wiring of the peripheral circuit portion is also formed as the wiring layer 12.

According to the manufacturing method of the present embodiment described above, the thickness of the solid-state imaging device having the same configuration as that of the solid-state imaging device 1 shown in FIG. 5 μm or less) can be manufactured.
Therefore, according to the manufacturing method of the present embodiment, sufficiently high sensitivity is obtained in the visible light region, and color mixing and shading due to light incident on adjacent pixels, and electrical color mixing with adjacent pixels can be suppressed. Thus, it is possible to manufacture a solid-state imaging device having a configuration that can improve the dynamic range and that does not generate smear.

In this embodiment, since the silicon layer 21 is formed in advance on the SOI substrate 24, the interface of the silicon layer 21 is relatively stable, and the dark current generated at the interface is more than that shown in FIG. Can be reduced.
In addition, since the controllability of the thickness of the silicon layer 21 is good and the spectral characteristics can be stabilized, the manufacturing yield can be improved.
Moreover, for the silicon layer 21, the wiring portion 3 is formed on the front surface side, the first support substrate 31 is bonded to the back surface side, and then the first support substrate 31 is removed, whereby the silicon layer 21 is formed. Since it is not polished, the silicon layer 21 is not mechanically damaged.

  Further, in the present embodiment, since the SOI substrate 24 is used, for example, it is possible to manufacture a solid-state imaging device at a lower cost by using an existing (commercially available) inexpensive SOI substrate 24. Become.

In particular, in the manufacturing method of the present embodiment, the crystallinity at the interface of the active layer of the silicon layer 21 can be improved by heat treatment at a relatively high temperature when the first support substrate 31 is bonded, and noise is generated. A small number of solid-state imaging devices can be manufactured. Further, since the P ⁺ region 19 on the back surface side is formed by ion implantation from the back surface side into the silicon layer 21, it is easy to control the position of the P ⁺ region 19 near the interface on the back surface side of the silicon layer 21.

  Next, as another embodiment of the method for manufacturing a solid-state imaging device of the present invention, another method for manufacturing a solid-state imaging device having a back-illuminated structure having the same configuration as that of the solid-state imaging device 1 in FIG. 1 will be described. .

Also in this embodiment, the SOI substrate 24 whose sectional view is shown in FIG. 6 is used.
However, the total thickness of the SOI substrate 24 is 725 μm, the thickness of the intermediate layer (SiO ₂ film) 22 is 10 μm or less, and the thickness of the silicon layer 21 is 10 μm or less (more preferably 5 μm or less). .

First, as shown in FIG. 11A, an N-type region 17 constituting a photodiode, a P ⁺ region 19 on the back surface side, a P ⁺ region 16 on the front surface side, and a floating diffusion 15 are formed on the silicon layer 21 of the SOI substrate 24. N-type regions are formed by ion implantation. In addition, an alignment mark 26 for positioning the color filter and the on-chip lens is also formed. The N-type region 17 is formed in two steps, for example, ion implantation for forming the lower portion and ion implantation for forming the upper portion because the upper and lower patterns are different.
At this time, when the thickness of the silicon layer 21 is 5 μm or less, ion implantation can be performed using a photoresist (not shown) as a mask, but when the thickness of the silicon layer 21 exceeds 5 μm, It is necessary to perform ion implantation with relatively high energy using a hard mask made of an oxide film or the like.

Next, the gate electrode 14 of the read transistor is formed on the silicon layer 21 through a thin insulating film.
Subsequently, as shown in FIG. 11B, the wiring portion 3 is formed on the silicon layer 21 by forming the multilayer wiring layer 12 via the interlayer insulating layer 11.
Further, although not shown, a protective film is formed on the upper surface of the wiring part 3. This protective film is for preventing the wiring portion 3 from absorbing moisture and adversely affecting the wiring layer 12, and for example, a silicon nitride film is formed by plasma CVD.

  Next, as illustrated in FIG. 11C, an adhesive layer 32 is formed on one surface of the first support substrate 31, and the first support substrate 31 is bonded onto the wiring portion 3 through the adhesive layer 32. And it adhere | attaches by performing the heat processing of 400 degrees C or less. Since this heat treatment is performed after the wiring layer 12 is formed, the heat treatment is performed at a low temperature of 400 ° C. or lower in order not to affect the wiring layer 12. As the adhesive layer 32 in this case, SOG (spin on glass) or a metal layer capable of metal bonding can be used as in the previous embodiment.

Next, as shown in FIG. 12D, the wafer is inverted.
Subsequently, the back side is etched by, for example, a back grinding method, a CMP method, wet etching, or the like, and the silicon substrate 23 and the intermediate layer (SiO ₂ film) 22 of the SOI substrate 24 are removed. Thereby, as shown in FIG. 12E, the silicon layer 21 is exposed.

Next, although not shown, the upper surface of the silicon layer 21 is oxidized to form an oxide film.
Thereafter, as shown in FIG. 12F, an antireflection film 28 is formed on the silicon layer 21, and the color filter 5 and the on-chip lens 6 are sequentially formed thereon. Although not shown, pad electrodes for connecting external terminals are also formed.
In this way, a solid-state imaging device having a backside illumination type structure can be manufactured.

  Also in this case, when the semiconductor region of the light receiving sensor portion is formed, a semiconductor region such as a transistor of the peripheral circuit portion is also formed. Similarly, the wiring of the peripheral circuit portion is also formed as the wiring layer 12.

According to the manufacturing method of the present embodiment described above, the thickness of the solid-state imaging device having the same configuration as that of the solid-state imaging device 1 shown in FIG. 5 μm or less) can be manufactured.
Therefore, according to the manufacturing method of the present embodiment, sufficiently high sensitivity is obtained in the visible light region, and color mixing and shading due to light incident on adjacent pixels, and electrical color mixing with adjacent pixels can be suppressed. Thus, it is possible to manufacture a solid-state imaging device having a configuration that can improve the dynamic range and that does not generate smear.

In this embodiment, since the silicon layer 21 is formed in advance on the SOI substrate 24, the interface of the silicon layer 21 is relatively stable, and the dark current generated at the interface is more than that shown in FIG. Can be reduced.
In addition, since the controllability of the thickness of the silicon layer 21 is good and the spectral characteristics can be stabilized, the manufacturing yield can be improved.
Moreover, since the wiring portion 3 is formed on the front surface side and the silicon substrate 23 and the intermediate layer 22 on the back surface side are removed with respect to the silicon layer 21, the silicon layer 21 is not polished. There is no damage.

  Further, in the present embodiment, since the SOI substrate 24 is used, for example, it is possible to manufacture a solid-state imaging device at a lower cost by using an existing (commercially available) inexpensive SOI substrate 24. Become.

  In particular, in the manufacturing method of the present embodiment, the heat treatment is performed at a relatively low temperature of 400 ° C. or lower, so that heat treatment is performed on impurity regions such as the source / drain of the transistor that are formed in portions other than the photoresist of the silicon layer. Less influence. This makes it possible to reduce the channel length of the transistor by applying the latest design rule, so that miniaturization can be easily achieved.

Note that when the thickness of the silicon layer 21 of the SOI substrate 24 has a variation of, for example, about 10%, the spectral characteristics are hardly affected, but the depth and the back surface of the N-type region 17 are not affected by ion implantation under the same conditions. The position of the P ⁺ region 19 on the side may vary.
If the P ⁺ region 19 on the back side is formed at a position deeper than the interface of the silicon layer 21 on the back side, the effect of suppressing dark current is weakened and noise is generated, which is not preferable. On the other hand, if the P ⁺ region 19 on the back side is formed at a position shallower than the interface of the silicon layer 21, an electric barrier is formed, and the amount of charge that can be read is reduced, resulting in a decrease in sensitivity. End up.
As an effective measure for variation in the thickness of the silicon layer 21, for example, by measuring the thickness of the silicon layer 21 of the wafer of the SOI substrate 24, for example, the thickness of the silicon layer 21 is substantially equal (variation does not become a problem). It is conceivable to select and use a wafer within a certain range, or to control the ion implantation conditions (energy, etc.) depending on the thickness of the silicon layer 21, for example.

In the present embodiment, as shown in FIG. 11A, the N-type region 17 and the P ⁺ region 19 on the back surface side are formed by ion implantation from the surface side of the silicon layer 21, but the temperature is relatively low. After the silicon substrate 23 is removed (after the step of FIG. 12E), ions are implanted from the back surface side and the back surface side portion of the N-type region 17 and P can be activated. It is also possible to form the ⁺ region 19. That is, as in the manufacturing method of the previous embodiment, ion implantation can be performed twice from the front surface side and the back surface side.

In each of the above-described embodiments, the region where photoelectric conversion of the light receiving sensor unit is performed is the N-type region 17, and the P ⁺ regions 16 and 19 are formed on the front side and the back side of the N-type region 17, respectively. However, the present invention can also be applied to a configuration in which each has a reverse conductivity type.

In each embodiment of the manufacturing method described above, the SOI substrate 24 using the SiO ₂ film is used for the intermediate layer 22, but in the manufacturing method of the present invention, the silicon substrate, the intermediate layer, and the silicon layer are laminated. A laminated substrate is used, and it is also possible to use a laminated substrate on which another material, for example, a material that can be easily peeled, such as porous silicon, is formed as an intermediate layer.

  The present invention is not limited to the above-described embodiment, and various other configurations can be taken without departing from the gist of the present invention.

1 is a schematic configuration diagram (cross-sectional view) of a solid-state imaging device according to an embodiment of the present invention. It is sectional drawing of the principal part of the solid-state image sensor of FIG. It is a figure which shows the relationship between the thickness of a silicon layer, and the wavelength dependence of the incident light of the quantum efficiency in a light-receiving sensor part. It is a figure which shows the relationship between the thickness of a silicon layer, and the wavelength dependence of the incident light of the quantum efficiency in a light-receiving sensor part. It is a figure which shows the spectral characteristic of an infrared cut filter. It is sectional drawing of an SOI substrate. 1A to 1C are manufacturing process diagrams illustrating an embodiment of a method for manufacturing a solid-state imaging device of the present invention. DF is a manufacturing process diagram showing an embodiment of a method for manufacturing a solid-state imaging device of the present invention. G and H are manufacturing process diagrams showing an embodiment of a method for manufacturing a solid-state imaging device of the present invention. I, J It is a manufacturing process figure which shows one Embodiment of the manufacturing method of the solid-state image sensor of this invention. A to C are manufacturing process diagrams showing another embodiment of a method for manufacturing a solid-state imaging device of the present invention. DF is a manufacturing process diagram showing another embodiment of the method for manufacturing a solid-state imaging device of the present invention. It is a schematic sectional drawing of a backside illumination type CMOS sensor.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Solid-state image sensor, 2 Support substrate, 3 Wiring part, 4,21 Silicon layer, 5 Color filter, 6 On-chip lens, 12 Wiring layer, 14 Gate electrode, 15 Floating diffusion, 16, 18, 19 P ⁺ area | region, 17 , 25, 27 N-type region, 22 intermediate layer, 23 silicon substrate, 24 SOI substrate, 26 alignment mark, 28 antireflection film, 31 first support substrate, 32, 34 adhesive layer, 33 second support substrate

Claims (5)

Using a laminated substrate in which a silicon substrate, an intermediate layer, and a silicon layer are laminated,
Forming a semiconductor region of a light receiving sensor part in the silicon layer of the multilayer substrate;
Forming a wiring portion having a wiring layer in an insulating layer above the silicon layer;
Thereafter, a step of attaching a support substrate on the wiring portion;
Removing the silicon substrate and the intermediate layer to expose the silicon layer;
The manufacturing method of a solid-state image sensor which has at least. The method for manufacturing a solid-state imaging device according to claim 1 , wherein the silicon substrate and the intermediate layer are removed by back grinding. The method for manufacturing a solid-state imaging device according to claim 1 , wherein the silicon substrate and the intermediate layer are removed by a chemical mechanical polishing method. The method for manufacturing a solid-state imaging device according to claim 1 , wherein the silicon substrate and the intermediate layer are removed by wet etching. The method of manufacturing a solid-state imaging device according to claim 1 , wherein the intermediate layer is a SiO ₂ film or a porous silicon layer.

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