JP4711823B2 - 電子部品収納用パッケージおよび電子装置 - Google Patents
電子部品収納用パッケージおよび電子装置 Download PDFInfo
- Publication number
- JP4711823B2 JP4711823B2 JP2005370988A JP2005370988A JP4711823B2 JP 4711823 B2 JP4711823 B2 JP 4711823B2 JP 2005370988 A JP2005370988 A JP 2005370988A JP 2005370988 A JP2005370988 A JP 2005370988A JP 4711823 B2 JP4711823 B2 JP 4711823B2
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- electronic component
- insulating
- insulating base
- storage package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
2・・・・・・配線導体
3・・・・・・接続パッド
4・・・・・・リード端子
5・・・・・・電子部品
6・・・・・・接合部材
Claims (4)
- 複数の絶縁層からなり、電子部品の搭載部を有する絶縁基体と、前記複数の絶縁層の層間に形成されており、前記電子部品の電極に電気的に接続される配線導体と、前記複数の絶縁層の少なくとも一層を貫通して充填するように設けられており、前記配線導体に電気的に接続されているとともに、表面の一部が前記絶縁基体の側面に露出され、該露出された部位の幅より前記絶縁基体の内部に埋設された部位の幅の方が広い導体と、該導体の前記絶縁基体の前記側面に露出された部位に接合されたリード端子とを備えたことを特徴とする電子部品収納用パッケージ。
- 前記配線導体が、前記複数の絶縁層の異なる層間に複数形成されており、前記導体の上端および下端が、前記複数の配線導体に接続されていることを特徴とする請求項1記載の電子部品収納用パッケージ。
- 前記導体の端部が、前記導体が形成された前記絶縁層の上層の絶縁層または下層の絶縁層に埋設されていることを特徴とする請求項1記載の電子部品収納用パッケージ。
- 請求項1乃至請求項3のいずれかに記載された電子部品収納用パッケージと、該電子部品収納用パッケージの前記絶縁基体に搭載された電子部品とを備えていることを特徴とする電子装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005370988A JP4711823B2 (ja) | 2005-12-22 | 2005-12-22 | 電子部品収納用パッケージおよび電子装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005370988A JP4711823B2 (ja) | 2005-12-22 | 2005-12-22 | 電子部品収納用パッケージおよび電子装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007173629A JP2007173629A (ja) | 2007-07-05 |
JP4711823B2 true JP4711823B2 (ja) | 2011-06-29 |
Family
ID=38299759
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005370988A Active JP4711823B2 (ja) | 2005-12-22 | 2005-12-22 | 電子部品収納用パッケージおよび電子装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4711823B2 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7964945B2 (en) * | 2007-09-28 | 2011-06-21 | Samsung Electro-Mechanics Co., Ltd. | Glass cap molding package, manufacturing method thereof and camera module |
JP5454226B2 (ja) * | 2010-03-01 | 2014-03-26 | パナソニック株式会社 | 放熱基板とその製造方法 |
JP2012089745A (ja) * | 2010-10-21 | 2012-05-10 | Kyocera Corp | リード端子およびそれを備えたリード端子付き絶縁基体ならびに素子収納用パッケージ |
JP7049141B2 (ja) * | 2018-03-07 | 2022-04-06 | 新光電気工業株式会社 | 電子部品用パッケージとその製造方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55107249A (en) * | 1979-02-12 | 1980-08-16 | Mitsubishi Electric Corp | Manufacture of container for semiconductor device |
JP2001345522A (ja) * | 2000-05-31 | 2001-12-14 | Kyocera Corp | 回路基板の製造方法とその回路基板 |
JP2002314257A (ja) * | 2001-02-23 | 2002-10-25 | Fujitsu Ltd | 多層回路基板、その製造方法および電気アセンブリ |
JP2005203487A (ja) * | 2004-01-14 | 2005-07-28 | Denso Corp | 電子装置およびその製造方法 |
-
2005
- 2005-12-22 JP JP2005370988A patent/JP4711823B2/ja active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55107249A (en) * | 1979-02-12 | 1980-08-16 | Mitsubishi Electric Corp | Manufacture of container for semiconductor device |
JP2001345522A (ja) * | 2000-05-31 | 2001-12-14 | Kyocera Corp | 回路基板の製造方法とその回路基板 |
JP2002314257A (ja) * | 2001-02-23 | 2002-10-25 | Fujitsu Ltd | 多層回路基板、その製造方法および電気アセンブリ |
JP2005203487A (ja) * | 2004-01-14 | 2005-07-28 | Denso Corp | 電子装置およびその製造方法 |
Also Published As
Publication number | Publication date |
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JP2007173629A (ja) | 2007-07-05 |
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