JP4783975B2 - MIS semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase a latch-up resistance and to reduce a leakage current at a reverse voltage applying time by improving a trade-off relation between an on voltage and turn-off loss of a MOS semiconductor device such as an IGBT or the like. SOLUTION: A method for manufacturing the semiconductor device comprises the steps of forming a gate electrode 3 on a semiconductor substrate 1 via an insulating film 2, and forming a p-type base region 6 and an n+ type emitter region 7 on a thin film semiconductor layer 11 formed on the electrode 3 via an insulating film 5 through a coupled semiconductor 12 from the surface of the substrate 1. An emitter layer is thinned for microminiaturization of an emitter structure, and a latch-up resistance is increased by remotely separating a hole current in the p-type region 6 from the region 7. Simultaneously, an impurity concentration of the region 6 is lowered, a leakage current at a reverse voltage applying time is reduced, and hence an operation as a bidirectional device can be performed.

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a MIS semiconductor device having a gate structure made of a metal-insulating film-semiconductor, and more particularly to a vertical MIS semiconductor device having an emitter structure using a thin film semiconductor layer and a method for manufacturing the same.
[0002]
[Prior art]
  An insulated gate bipolar transistor (hereinafter referred to as IGBT) is known as a type of high voltage MIS semiconductor device.
  FIG. 15 is a cross-sectional view of a unit cell which is a unit structure of a planar gate type vertical IGBT which is a conventional IGBT. This IGBT is a non-punch through type, and the collector electrode 29, p⁺Collector layer 28, n^-Drift layer 21, p base region 26, p⁺Contact region 26a, n⁺An emitter region 27, a gate insulating film 25, a gate electrode 23, and an emitter electrode 30 are included.
[0003]
  FIG. 16 is a cross-sectional view of a unit cell of a trench gate type vertical IGBT which is another conventional IGBT. This IGBT is a non-punch through type, and collector electrode 39, p from the lower side of the figure.⁺Collector layer 38, n^-Drift layer 31, p base region 36, p⁺Contact region 36a, n⁺An emitter region 37 and an emitter electrode 40 are included. In this IGBT, a gate electrode 33 is embedded in a trench 46 via a gate insulating film 35.
[0004]
[Problems to be solved by the invention]
  However, the conventional IGBT as shown in FIG. 15 has three drawbacks.
  One is that miniaturization is difficult because the gate electrode 23 is formed on the surface of the semiconductor substrate. Therefore, it is difficult to reduce the on-voltage, and it is difficult to improve the trade-off between the on-voltage and the turn-off loss.
[0005]
  The second is n⁺The hole current flows in the p base region 26 around the emitter region 27. Due to the voltage drop due to this hole current, n⁺Emitter region 27, p base region 26, n^-Drift layer 21, p⁺There is a problem that the parasitic thyristor formed of the collector layer 28 is latched up, and the current cannot be controlled by the gate signal.
  Third, when a reverse voltage is applied as a bidirectional device, the p⁺N from contact region 26a^-There is a problem that a large amount of holes are injected into the drift layer 21 and a large leakage current flows. In order to eliminate this third problem, p⁺When the impurity concentration of the contact region 26a is lowered, there is a problem that the parasitic thyristor is more easily latched up.
[0006]
In the trench gate IGBT of FIG. 16, the problem of the parasitic thyristor latching up and the problem of the reverse leakage current described above are the same.⁺Contact regions 36a and n⁺Since the emitter electrode 40 that contacts the emitter region 37 is formed on the surface of the semiconductor substrate, there is a problem that miniaturization is difficult. Therefore, it is difficult to reduce the on-voltage, and it is difficult to improve the trade-off between the on-voltage and the turn-off loss.
[0007]
An object of the present invention is to solve the above problems, improve the trade-off between on-voltage and turn-off loss, prevent parasitic thyristors from latching up, and reduce the leakage current when applying a reverse voltage, and its manufacture It is to provide a method.
[0008]
[Means for Solving the Problems]
  In order to achieve the above object, the MIS semiconductor device of the present invention is such that the emitter portion is thinned and miniaturized. First, a gate electrode formed on the first conductive type semiconductor substrate via an insulating film, an insulating film covering the side surface and upper surface of the gate electrode, and a first conductive type thin film formed on the insulating film on the gate electrode Insulating the side surface of the gate electrode on a part of the thin film semiconductor layer on the gate electrode, a semiconductor layer, a connecting semiconductor portion connecting the semiconductor substrate and the first conductive type thin film semiconductor layer through the insulating film on the side surface of the gate electrode A second conductivity type base region formed across the thin film semiconductor layer at a predetermined distance from the film surface; a first conductivity type emitter region formed at an end of the thin film semiconductor layer far from the connecting semiconductor portion; An emitter electrode provided in contact with both the one conductivity type emitter region and the second conductivity type base region, and a collector electrode formed on the back side of the semiconductor substrate.The part where the gate electrode and the emitter electrode are in contact with the emitter region and the base region through the insulating film is opposed to each other.Shall.
[0009]
  That is, by forming the second conductivity type base region and the first conductivity type emitter region in the thin film semiconductor layer on the gate electrode surrounded by the insulating film, it becomes easy to apply microfabrication. The on-voltage can be loweredThe MaFurther, when the first conductivity type emitter region of the emitter portion is formed in contact with the second conductivity type base region, the base region extends along the boundary between the first conductivity type emitter region and the second conductivity type base region. Since the component of the current flowing inside is reduced, the voltage drop is reduced and the parasitic thyristor is difficult to latch up.
[0010]
  Furthermore, since the parasitic thyristor is difficult to latch up, the impurity concentration of the second conductivity type base region can be lowered. As a result, the amount of the second conductivity type carriers injected from the second conductivity type base region into the first conductivity type semiconductor substrate when the reverse voltage is applied is reduced, and the reverse leakage current can be reduced. The connecting semiconductor portion may be a semiconductor thin film layer or a part of a semiconductor substrate.
[0011]
  If the fourth electrode is provided via an insulating film on the surface of the thin film semiconductor layer close to the connection semiconductor part, the potential of the connection semiconductor part is increased by applying a voltage to the fourth electrode when a forward voltage is applied. Thus, electric field concentration caused by the corners of the gate electrode can be reduced. If the corner of the gate electrode is rounded, electric field concentration caused by the corner of the gate electrode can be avoided.
[0012]
  An emitter electrode formed on the first conductive type semiconductor substrate via an insulating film; an insulating film covering a side surface of the facing emitter electrode; a first conductive type thin film semiconductor layer formed on the emitter electrode; A connecting semiconductor portion for connecting the semiconductor substrate and the first conductive type thin film semiconductor layer through the insulating film on the side surface of the emitter electrode, and insulating the side surface of the emitter electrode from the semiconductor substrate surface to a part of the thin film semiconductor layer on the emitter electrode A second conductivity type base region formed across the thin film semiconductor layer at a predetermined distance from the film surface; a first conductivity type emitter region formed at an end of the thin film semiconductor layer far from the connecting semiconductor portion; A gate electrode provided on the two-conductivity type base region via an insulating film, and a collector electrode formed on the back side of the semiconductor substrateThe part where the gate electrode and the emitter electrode are in contact with the emitter region and the base region through the insulating film is opposed to each other.The MIS semiconductor device is assumed.
[0013]
  That is, even if the second conductive type base region and the first conductive type emitter region are formed in the thin film semiconductor layer on the emitter electrode, and the gate electrode is provided on the thin film semiconductor layer via the insulating film, the microfabrication is also possible. Can be applied more easily and the cell width can be narrowed to reduce the on-voltage.The
  Also in this case, the connecting semiconductor portion may be a thin film semiconductor layer or a part of a semiconductor substrate.
[0014]
If the corner of the emitter electrode is rounded, electric field concentration caused by the corner of the emitter electrode can be avoided. If the width W of the connecting semiconductor portion of the thin film semiconductor layer is 10 μm or less, the cell width can be reduced and the on-voltage can be lowered.
  For the formation of the thin film semiconductor layer, a lateral epitaxial growth technique (hereinafter referred to as ELO) is applied. Specific methods include molecular beam epitaxy (hereinafter referred to as MBE), chemical vapor deposition (hereinafter referred to as CVD), and liquid phase epitaxy (hereinafter referred to as LPE). Can be used.
[0015]
  When using MBE, the straightness of molecular beams with uniform directivity is used. The molecular beam is irradiated at an angle close to horizontal (for example, 10 degrees with respect to the horizontal plane), more molecular beams are irradiated on the side surface of the thin film, and conversely, almost no molecular beam is supplied to the surface of the thin film. Can be epitaxially grown in the lateral direction.
  When CVD or LPE is used, anisotropic growth is used. Depending on the plane orientation of the crystal, there are a plane that is stable and flattened and has a slow growth rate, and a surface that is rough and unstable, and that has a high growth rate where atoms are actively incorporated. Use. Anisotropic growth can also be used in MBE.
[0016]
  The anisotropy of crystal growth varies depending on the material. In the case of silicon, the (111) plane is easily stabilized and the (110) plane is easily roughened. If gallium arsenide is used, the (100) plane is easy to stabilize, and the other planes are easy to rough.
  Therefore, when the first conductivity type semiconductor substrate is silicon, if the surface is the (111) plane, a flat surface can be easily obtained using anisotropy.
[0017]
  If the side surface of the thin film semiconductor layer is the (110) plane, the lateral growth rate is increased. When the first conductive semiconductor substrate is gallium arsenide (GaAs), if the surface is a (100) plane, a flat surface can be easily obtained using anisotropy.
[0018]
[0019]
The impurity concentration of the second conductivity type base region is 10¹⁵Pieces / cm^ThreeIf it is lower, the parasitic thyristor is likely to be latched up due to a voltage drop caused by a current flowing in the base region. Conversely, 10¹⁸Pieces / cm^ThreeIf it is higher, the amount of minority carriers injected from the base region into the semiconductor substrate when a reverse voltage is applied increases, and the leakage current increases.
[0020]
An IGBT having the second conductivity type collector region on the back side of the semiconductor substrate is an IGBT, and an element lacking the IGBT is a MOSFET. The present invention relates to the emitter portion, and the collector structure is arbitrary. As a manufacturing method of the MIS semiconductor device as described above, a connected semiconductor portion and a thin film semiconductor layer are formed on a first conductivity type semiconductor substrate by epitaxial growth.
[0021]
  By epitaxial growth, a linked semiconductor portion and a thin film semiconductor layer with good crystallinity are formed.
  The same applies to the MIS semiconductor device in which the thin film semiconductor layer is formed on the emitter electrode.
  Alternatively, a step of forming a mask on the first conductivity type semiconductor substrate, a step of performing isotropic etching, a step of forming an oxide film, a step of filling the etched recess with polysilicon, and polysilicon If a thin film semiconductor layer is formed by epitaxial growth on the surface of the first conductive type semiconductor substrate that is not etched, a thin film semiconductor layer having good crystallinity is formed on the connected semiconductor portion of the semiconductor substrate. Is done.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
  Embodiments of the present invention will be described below with reference to the drawings.
  [Example 1]
  FIG. 1 is a cross-sectional view of a unit cell which is a unit structure of an IGBT according to the first embodiment of the present invention.
[0023]
  High resistance n^-A gate electrode 3 made of polysilicon is formed on the semiconductor substrate 1 via an insulating film 2 made of an oxide film, for example. The side surface and the upper surface of the gate electrode 3 are covered with, for example, insulating films 4 and 5 of an oxide film. n^-A thin film semiconductor layer 11 is formed from the surface of the semiconductor substrate 1 to the gate electrode 3 through the connecting semiconductor portion 12 on the side of the gate electrode 3, and at the end of the thin film semiconductor layer 11 far from the connecting semiconductor portion 12. p base region 6, n⁺An emitter region 7 is formed. 10 is p base region 6, n⁺This is an emitter electrode provided in common contact with the emitter region 7. n^-On the back side of the semiconductor substrate 1, a p collector region 8 is formed, and a collector electrode 9 is provided. In this IGBT, the insulating film 5 is a gate insulating film.
[0024]
  2A to 2D and FIGS. 3A to 3D are cross-sectional views in order of steps shown for each main manufacturing process of the IGBT according to the first embodiment. In the following description, an n-channel IGBT is exemplified.
  Hereinafter, the manufacturing method of IGBT which concerns on 1st embodiment is demonstrated according to figures. First, high resistance n^-A semiconductor substrate 1 is prepared, and this n^-An insulating film 2 covering the surface of the semiconductor substrate 1 is formed. Next, a polysilicon layer to be the gate electrode 3 is formed on the insulating film 2 [FIG. 2A].
[0025]
  Next, after patterning the insulating film 2 and the gate electrode 3 in a stripe shape using a mask (not shown) [FIG. (B)], the insulating film 4 is formed in the opening by thermal oxidation or CVD [FIG. (C)]. .
  Next, polishing is performed to smooth the surface, and the heights of the gate electrode 3 and the insulating film 4 are made equal [(d)].
[0026]
  Next, an insulating film 5 is formed on the gate electrode 3 and the insulating film 4 [FIG. 3 (a)], and then the central portion of the insulating film 4 is opened in stripes with a mask (not shown). b)].
  Next, n by MBE or CVD or LPE^-Epitaxial growth is performed from the exposed portion of the semiconductor substrate 1, and n^-A shape is formed such that the thin film semiconductor layer 11 extends in the lateral direction through the connecting semiconductor portion 12 of the mold.
[0027]
  When MBE is used for epitaxial growth, a large amount of molecules are supplied only to a specific surface and not supplied to other surfaces using the linearity of a molecular beam with uniform directivity. Selectively grow only the face.
  4A to 4C are perspective sectional views of the substrate surface for explaining the growth process. From the state where the gate electrode 3 is covered with the insulating films 2, 4, 5 [FIG. 4A], MBE is started and the molecular beam x 3 until the connecting semiconductor portion 12 reaches the height of the upper surface of the insulating film 5. Is irradiated perpendicularly to the substrate [FIG. 4B].
[0028]
  When the connecting semiconductor portion 12 reaches the height of the upper surface of the insulating film 5, the molecular beam x4 is incident at a low angle of elevation of 10 degrees or less from the horizontal plane so that the side surface of the thin film semiconductor layer 11 extends [FIG. ]].
  At this time, in the thin film semiconductor layer 11, the molecular beam supply amount per unit area to the side surface is five times or more larger than the supply amount to the upper surface. As a result, the speed at which the thin film semiconductor layer 11 extends in the lateral direction is at least five times the speed at which the thin film semiconductor layer 11 extends in the upward direction.
[0029]
  In FIG. 4 (c), the thin film semiconductor layer 11 extends only in the right direction in the figure, but it is desirable that the thin film semiconductor layer 11 extend in the left-right direction. x4 should be supplied. This may be achieved by constantly rotating the substrate during growth. Alternatively, molecular beam sources may be arranged on both sides of the substrate, and the molecular beam x4 and the molecular beam having a bilaterally symmetric orientation may be supplied simultaneously from two directions.
[0030]
  When silicon is used as the material, the MBE growth conditions are selected as follows.
  Epitaxial growth is 10^-7To 10^-2Performed in a Pa ultrahigh vacuum chamber. Examples of molecular beam sources include the following. There are a method of evaporating solid silicon with an electron gun, a method of heating solid silicon by a Knudsen cell and sublimating and evaporating, a method of supplying with a gas source, and the like. For the gas source, monosilane (SiH_Four), Monochlorosilane (SiH)_ThreeCl), dichlorosilane (SiH₂Cl₂), Trichlorosilane (SiHCl_Three), Tetrachlorosilane (SiCl)_Four), Disilane (Si₂H₆)and so on.
[0031]
The substrate temperature is 300 ° C. to 1000 ° C., and the growth rate is about 0.1 μm / h to 100 μm / h. However, since the region where the reaction process of epitaxial growth is rate-controlled is desirable, the substrate temperature is more preferably in the range of 700 ° C. to 1000 ° C. On the other hand, there is a possibility that polysilicon is deposited on the surface of the insulating film 5, which adversely affects the shape, crystal quality, and device characteristics of the thin film semiconductor layer 11 due to epitaxial growth, and should be avoided. From this point of view, a slower growth rate is desirable because it can suppress the deposition of polysilicon. However, an extremely slow growth rate results in a loss of mass productivity. Therefore, it is considered that the growth rate should be about 1 μm / h to about 2 μm / h.
[0032]
  Even if a minute polysilicon nucleus is formed on the insulating film 5, it can be removed by using an etching action of gas before the polysilicon is enlarged. It is SiH that has a strong etching action._ThreeCl, SiH₂Cl₂, SiHCl_Three, SiCl_FourA gas containing a halogen element such as SiH_FourAnd Si₂H₆Even if a very small amount of hydrochloric acid gas (HCl) is added to and supplied, the deposition of polysilicon can be suppressed by the etching action of HCl.
[0033]
  In the shape control of the thin film semiconductor layer 11 by MBE growth, anisotropic growth can be used in addition to the effect due to the difference in the supply rate of molecules for each surface as described above. This utilizes the fact that the growth rate varies depending on the plane orientation under the same growth environment. Here, a plane orientation that is easy to flatten on the surface of the thin film semiconductor layer 11 and that is stable and has a slow growth rate is selected, and a plane orientation that is easily rough and unstable on the side surface and that has a large amount of atomic incorporation is selected.
[0034]
The stable surface can be further stabilized by using a gas having an etching action. That is, even if a crystal nucleus having a small undesirable orientation is formed, it can be removed by etching to prevent growth. The etching action here is based on the same principle as the etching action on the insulating film, and a gas containing a halogen element is effective.
[0035]
When CVD or LPE is used for epitaxial growth, the anisotropic growth action is mainly used. The principle is the same as that described in the above MBE section.
  For example, when a silicon substrate is used, it is advantageous that the surface is the (111) plane, the stripe direction is the <112> direction, and the (110) plane is exposed on the side surface of the thin film. The reason is that the (111) plane of silicon has the property of being flattened and stable, and it is difficult to form nuclei necessary for growth. On the other hand, since the (110) plane is rough and easily absorbs atoms, the (110) plane has a higher growth rate than the (111) plane. Therefore, in order to form an epitaxial thin film that is long in the lateral direction, it is preferable that the upper surface is the (111) plane, the stripe direction is the <112> direction, and the side surface is the (110) plane as a result.
[0036]
  For the same reason, when using a gallium arsenide substrate, it is preferable to select an orientation in which the top surface is the (100) plane and the (100) plane and (111) plane do not appear on the side surfaces.
  The CVD condition for silicon is SiH at a substrate temperature of 1000 ° C. to 1423 ° C._Four, SiH_ThreeCl, SiH₂Cl₂, SiHCl_Three, SiCl_Four, Si₂ H₆It is preferable to supply a gas such as 0.1 μm / h to 100 μm / h. In particular, the range of 1 μm / h to 10 μm / h seems to be good from the viewpoint of ensuring the mass productivity without depositing polysilicon.
[0037]
  The LPE growth conditions for silicon are as follows: Si is dissolved in a melt of a metal such as Sn or In in the range of 600 ° C. to 1000 ° C. until saturated, and is brought into contact with a substrate at the same temperature and gradually cooled down to 0.1 μm. The growth rate is preferably in the range of / h to 100 μm / h.
  When the thin film semiconductor layer 11 is doped with an impurity during the epitaxial growth, it is performed as follows.
[0038]
In MBE and CVD, arsine (AsH during growth is used to dope the donor impurities._Three) Or phosphine (PH_Three) Supply gas at the same time. To dope the acceptor impurity, diborane (B₂H₆) Supply gas at the same time.
  In LPE, in order to dope a donor impurity, arsenic (As) or phosphorus (P) is dissolved in the melt. To dope the acceptor impurity, boron (B) is dissolved in the melt.
[0039]
  Next, the p base region 6 and n are formed by ion implantation and thermal diffusion.⁺The emitter region 7 is formed [FIG. 3 (c)]. Here, the dose of the p base region 6 is 10¹¹-10¹⁴/cm² And the impurity concentration after thermal diffusion is 10¹⁵-10¹⁸/cm^ThreeIs desirable. N⁺The dose amount of the emitter region 7 is 10¹³/cm²The impurity concentration after thermal diffusion is 10¹⁷/cm^ThreeThe above is desirable.
[0040]
Then n^-P on the back surface of the semiconductor substrate 1 by ion implantation and thermal diffusion.⁺The collector region 8 is formed, and finally the collector electrode 9 and the emitter electrode 10 are formed, thereby completing the n-channel IGBT 13 [(d)].
  The typical dimension range of IGBT13 with a withstand voltage of 600V will be described with reference to FIG. First, the width W of the connecting semiconductor portion 12 is desirably 10 μm or less. Even if W is 1 μm or less, most of the current flows through the accumulation layer formed near the insulating film 5, so the on-resistance does not increase.Yes. ThinThe thickness t of the film semiconductor layer 11 is preferably 10 μm or less, and the values of Wl, W2, and W3 can be reduced as this value decreases. If the thickness t of the thin film semiconductor layer 11 is 1 μm, W1, W2 and W3 can be 2 μm, 2 μm and 1 μm or less, respectively. The unit cell width is 20 μm or less, which can be reduced to less than half of the conventional one.
[0041]
  When the thickness t of the thin film semiconductor layer 11 is 0.1 μm, W1, W2, and W3 can also be 0.2 μm, 0.2 μm, and 0.2 μm, respectively. At this time, the factor that determines the cell width is the design rule or the width W of the connected semiconductor portion 12, and the cells can be further densified.
  The thicknesses tg1, tg2, and tg3 of the insulating film are preferably 0.1 μm, 1 μm, and 1 μm or less, respectively. However, if tg2 and tg3 are too thin, avalanche breakdown is likely to occur due to electric field concentration caused by the corners of gate electrode 3. The thickness tp of the gate electrode 3 is preferably 10 μm or less, but is preferably 0.01 μm or more so that the gate resistance does not become huge.
[0042]
  N for 600V withstand voltage products^-The thickness ts of the semiconductor substrate 1 is about 100 μm, and the thickness of the p collector layer 8 is 0.1 μm or more, and about 300 μm at maximum.
  This IGBT is n⁺The emitter region 7 and the p base region 6 are the thin film semiconductor layer 11 and n⁺Since the emitter region 7 is formed adjacent to the p base region 6, it is easy to apply a microfabrication technique and the cell width can be reduced. For example, the correlation curve between on-state voltage and turn-off loss is improved by about 30% from the conventional one.
[0043]
Since most of the current flows through the accumulation layer formed in the vicinity of the insulating film 4 in the connected semiconductor portion 12, the on-resistance does not increase due to the thinness of the connected semiconductor portion 12.
  Further, when this IGBT is turned on, the hole current flowing through the p base region 6 of the thin film semiconductor layer 11 is n.⁺The parasitic thyristor is difficult to latch up because it passes through a region far from the boundary with the emitter region 7. A simulation that the latch-up resistance is 10 times or more that of the conventional product was almost confirmed with actual devices.
[0044]
Further, in this IGBT, since the parasitic thyristor is difficult to latch up, the impurity concentration of the p base region 6 is set to 10%.¹⁵-10¹⁸Pieces / cm^ThreeCan be lowered. As a result, the p base region 6 is changed to n when a reverse voltage is applied.^-This is characterized in that the amount of holes injected into the drift layer 1 is reduced and the leakage current can be reduced. Impurity concentration of p base region 6 is 10¹⁵Pieces / cm^ThreeIf so, the leakage current can be reduced to about 1/100 of the conventional one. Therefore, the IGBT 13 can be used as a bidirectional device with little leakage current.
[0045]
The present invention relates to the emitter structure, and the collector structure is arbitrary. Therefore, the present invention is applied to MOSFETs and the like in addition to IGBTs.
[Example 2]
  FIG. 6 is a cross-sectional view of an IGBT according to the second embodiment of the present invention. Note that portions corresponding to those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.
[0046]
  The difference from the first embodiment shown in FIG. 1 is that an insulating film 13 and a field plate electrode 14 are formed on the thin film semiconductor layer 11.
  When a positive voltage is applied to the field plate electrode 14 when a forward voltage is applied, the potential of the coupled semiconductor portion 12 is raised, and the electric field concentration caused by the corner of the gate electrode 3 can be relaxed. As a result, avalanche breakdown is less likely to occur and there is an advantage that forward breakdown voltage can be improved. In the case of an IGBT having a withstand voltage of 600V class, an improvement of about 5% of withstand voltage was observed.
[0047]
  [Example 3]
  FIG. 7 is a cross-sectional view of an IGBT according to the third embodiment of the present invention. Portions corresponding to those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.
  This embodiment is different from the IGBT of the first embodiment in that the gate electrode 3 is placed on the p base region 6 and the emitter electrode is placed on the p base region 6 and n.⁺This is that it is arranged below the emitter region 7.
[0048]
  This embodiment has an advantage that the gate electrode 3 can be easily formed as compared with the first embodiment. In addition, the following points are different from the first embodiment in the manufacturing method of the present embodiment.
  n^-After the insulating film 2 is formed on the surface of the semiconductor substrate 1, the insulating film 2 is patterned using a photoetching process, and n is used as a mask.^-The semiconductor substrate 1 is lightly etched, and the emitter electrode 10 is formed in the resulting recess. Next, a window for epitaxial growth is formed in the insulating film 2 and epitaxial growth extending in the lateral direction is performed similarly to the IGBT of the first embodiment, so that the thin film semiconductor layer 11 is formed. Here, unlike the first embodiment, the window opening width W may be as wide as 10 μm or more. Next, the p base region 6 and n⁺An emitter region 7 is formed, and an insulating film 5 and a gate electrode 3 are formed on the upper surface thereof. The other processes are the same as those in the first embodiment. The insulating film 5 becomes a gate insulating film.
[0049]
In order to perform epitaxial growth after the formation of the emitter electrode 10, it is necessary to use polycrystalline silicon or a refractory metal such as tungsten as the emitter electrode 10.
[Example 4]
  FIG. 8 is a cross-sectional view of an IGBT according to the fourth embodiment of the present invention.
[0050]
  In the first embodiment, when the shapes of the gate electrode 3 and the insulating films 2, 4, 5 are rounded as described above, the electric field concentration is relaxed and avalanche breakdown is less likely to occur, and the breakdown voltage is improved. In the case of an IGBT having a withstand voltage of 600 V class, an increase in withstand voltage of about 10% was observed. FIGS. 9A to 9D are cross-sectional views in order of steps showing a manufacturing process for rounding the shapes of the gate electrode 3 and the insulating films 2, 4, 5 according to the third embodiment.
[0051]
n^-For example, a material such as a photoresist is patterned on the semiconductor substrate 1, and isotropic etching is performed with an etching solution of nitric acid, hydrofluoric acid, or acetic acid [FIG. 9A].
  After removing the mask material, the surface is thermally oxidized and a polysilicon layer to be the gate electrode 3 is formed [FIG.
[0052]
  Next, the polysilicon layer is polished and planarized to form an oxide film 5 [FIG.
  A window is opened in the oxide film 5 [FIG.
  In the subsequent steps, the thin film semiconductor layer is deposited by epitaxial growth as in the first embodiment, and the subsequent processes are continued.
[0053]
  In the other second and third embodiments as well, when the gate electrode 3 and the insulating films 2, 4, and 5 are rounded in this way, the electric field concentration is reduced and avalanche breakdown is less likely to occur. improves. When the thin film semiconductor layer is grown by MBE in the examples so far (when anisotropic growth is not used), the plane orientation is not limited, and the pattern of the thin film semiconductor layer is extremely high. FIG. 10 is a perspective sectional view of an example in which a circular thin film semiconductor layer 11a is grown by MBE. Such a pattern shape can also be used.
[0054]
  In the case of CVD or LPE, the plane orientation is important, and it is preferable to adopt a stripe shape with an appropriate orientation selected.
  [Reference Example 1]
  FIG. 11 is a cross-sectional view of an IGBT according to Reference Example 1 of the present invention. Note that portions corresponding to those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.
[0055]
  Hereinafter, the IGBT according to Reference Example 1 will be described according to its manufacturing method.
  n^-A p base region 6 is formed on the surface layer of the semiconductor substrate 1, and n is further formed on the surface layer.⁺An emitter region 7 is formed. N through the p base region 6 from the surface^-A first trench 16 reaching the semiconductor substrate 1 is formed, and a gate electrode 3 made of polysilicon is filled in the first trench 16 via an insulating film 5. Close to the first trench 16 and n from the surface⁺A second trench 17 penetrating the emitter region 7 and reaching the p base region 6 is formed, and the emitter electrode 10 is filled in the second trench 17. n^-On the back side of the semiconductor substrate 1, a p collector region 8 is formed, and a collector electrode 9 is provided.
[0056]
The distance t between the insulating film 2 and the emitter electrode is preferably at least 10 μm and about 1 μm.
  The reference example 1 is different from the first embodiment in that the emitter electrode 10 is embedded in the trench. Not only the gate electrode 3 but also the emitter electrode 10 is embedded in the second trench 17 in which the semiconductor device substrate is dug close to the first trench 14, thereby thinning the p base region 6 of the emitter portion. As a result, the unit cell can be miniaturized as in the first embodiment, the on-voltage is reduced, and the latch-up resistance is increased.
[0057]
  In the semiconductor device described above, a conventionally used technique can be used as the breakdown voltage structure. The example which added the pressure | voltage resistant structure to FIG. The source electrode is omitted.
  FIG. 12 is a perspective sectional view of a guard ring x5 formed around the active part where the thin film semiconductor layer 11 is formed. FIG. 13 shows an example in which a field plate x6 is formed around the active portion, and a conductive material is formed in a stripe shape in the surrounding insulating film. It can be formed simultaneously with the formation of the gate electrode. In FIG. 14, a resistive nitride film x7 is formed as a resistive field plate around the active portion. All of these aim to increase the withstand voltage by relaxing the electric field around the active portion.
[0058]
【The invention's effect】
  As described above, according to the present invention, since the emitter portion of the MIS semiconductor device has a thin film structure, it is easy to apply microfabrication. And turn-off loss trade-off can be improved.
[0059]
[0060]
  The present invention is an important invention that shows that by using a thin film semiconductor layer, a revolutionary performance improvement can be achieved compared to a conventional MIS semiconductor device built in a semiconductor substrate.
[Brief description of the drawings]
FIG. 1 is a sectional view of an IGBT according to a first embodiment of the present invention.
FIGS. 2A to 2D are cross-sectional views for each main manufacturing process of the IGBT of Example 1. FIGS.
FIGS. 3A to 3D are cross-sectional views of the main manufacturing steps of the IGBT according to the first embodiment, following FIG. 2D.
FIGS. 4A to 4C are perspective sectional views illustrating a growth process by MBE.
FIG. 5 is an explanatory diagram of dimensions of each part of the IGBT according to the first embodiment of the present invention.
FIG. 6 is a sectional view of an IGBT according to a second embodiment of the present invention.
FIG. 7 is a cross-sectional view of an IGBT according to a third embodiment of the present invention.
FIG. 8 is a sectional view of an IGBT according to a fourth embodiment of the present invention.
FIGS. 9A to 9D are cross-sectional views showing main manufacturing steps of the IGBT according to the fourth embodiment.
FIG. 10 is a perspective sectional view of an example of a pattern by MBE.
FIG. 11 is a sectional view of an IGBT according to Reference Example 1 of the present invention.
FIG. 12 is a perspective sectional view with a pressure-resistant structure, part 1
FIG. 13 is a perspective sectional view with a pressure-resistant structure, part 2
FIG. 14 is a perspective sectional view with a pressure-resistant structure, part 3
FIG. 15 is a cross-sectional view of a conventional planar gate IGBT.
FIG. 16 is a cross-sectional view of a conventional trench gate IGBT.
[Explanation of symbols]
1, 21, 31 ... n^-Semiconductor substrate
2, 22, 32 ... Insulating film
3, 23, 33 ... Gate electrode
4, 24 ... Insulating film
5, 25, 35 ... Gate insulation film
6, 26, 36 ... p base region
7, 27, 37 ... n⁺Emitter area
8, 28, 38 ... p⁺Collector layer
9, 29, 39 ... Collector electrode
10, 30, 40 ... emitter electrode
11, 11a ... Thin film semiconductor layer
12 ・ ・ ・ Connected semiconductor part
13 ... IGBT
14 ... Insulating film
15 ... Field plate
16 ... First trench
17 ... Second trench
26a, 36a ・ ・ p⁺Contact area
46 ・ ・ ・ Trench
x3, x4 ... molecular beam
x5 ... Guard ring
x6 ... Field plate
x7 ... Resistive field plate

Claims (19)

A gate electrode formed on the first conductive type semiconductor substrate via an insulating film, an insulating film covering a side surface and an upper surface of the gate electrode, and a first conductive type thin film semiconductor layer formed on the insulating film on the gate electrode And a connecting semiconductor portion for connecting the semiconductor substrate and the first conductive type thin film semiconductor layer through the insulating film on the side surface of the gate electrode, and an insulating film surface on the side surface of the gate electrode on a part of the thin film semiconductor layer above the gate electrode A second conductive type base region formed across the thin film semiconductor layer at a predetermined distance from the first conductive type emitter region, a first conductive type emitter region formed at an end of the thin film semiconductor layer far from the connecting semiconductor portion, and a first conductive type an emitter electrode provided in both contact with the type emitter region and a second conductivity type base region, and a collector electrode formed on the back surface side of the semiconductor substrate, a gate electrode and the emitter electrode through the insulating film Emitter region and MIS semiconductor device, wherein a portion together contact with and over scan region are facing. The MIS semiconductor device according to claim 1, wherein the connecting semiconductor portion is a part of a semiconductor substrate. The MIS semiconductor device according to claim 1, wherein the connecting semiconductor portion is formed of a semiconductor thin film layer. 4. The MIS semiconductor device according to claim 2, further comprising a fourth electrode provided on a surface of the thin film semiconductor layer close to the connecting semiconductor portion via an insulating film. 5. The MIS semiconductor device according to claim 2, wherein a corner of the gate electrode is rounded. An emitter electrode formed on the first conductive type semiconductor substrate via an insulating film; an insulating film covering a side surface of the facing emitter electrode; a first conductive type thin film semiconductor layer formed on the emitter electrode; and an emitter electrode A connecting semiconductor portion for connecting the semiconductor substrate and the first conductive type thin film semiconductor layer through the insulating film on the side surface of the semiconductor substrate, and an insulating film surface on the side surface of the emitter electrode from the semiconductor substrate surface to a part of the thin film semiconductor layer on the emitter electrode A second conductive type base region formed across the thin film semiconductor layer at a predetermined distance from the first conductive type emitter region, a first conductive type emitter region formed at an end of the thin film semiconductor layer far from the connecting semiconductor portion, and a second conductive type. a gate electrode provided via an insulating film type base region, and a collector electrode formed on the back surface side of the semiconductor substrate, the gate electrode and the emitter electrode emitter region through an insulating film and the base MIS semiconductor device, wherein a portion together contact with and pass are confronted. The MIS semiconductor device according to claim 6, wherein the connecting semiconductor portion is a part of a semiconductor substrate. The MIS semiconductor device according to claim 6, wherein the connecting semiconductor portion is formed of a semiconductor thin film layer. 9. The semiconductor device according to claim 7, wherein corners of the emitter electrode are rounded. 10. The MIS semiconductor device according to claim 1, wherein a width W of the connecting semiconductor portion is 10 μm or less. 11. The MIS semiconductor device according to claim 1, wherein a thickness t of the thin film semiconductor layer is 10 μm or less. 12. The semiconductor device according to claim 1, wherein the first conductive semiconductor substrate is a silicon substrate, and the surface is a (111) plane. 13. The semiconductor device according to claim 12, wherein the side surface of the thin film semiconductor layer is a (110) plane. 12. The semiconductor device according to claim 1, wherein the first conductive semiconductor substrate is gallium arsenide, and the surface is a (100) plane. The MIS semiconductor device according to claim 1, wherein the impurity concentration of the second conductivity type base region is in a range of 10 ¹⁵ to 10 ¹⁸ / cm ³ . 16. The MIS semiconductor device according to claim 1, further comprising a second conductivity type collector region on a back surface side of the semiconductor substrate. A gate electrode formed on the first conductive type semiconductor substrate via an insulating film, an insulating film covering a side surface and an upper surface of the gate electrode, and a first conductive type thin film semiconductor layer formed on the insulating film on the gate electrode And a connecting semiconductor portion for connecting the semiconductor substrate and the first conductive type thin film semiconductor layer through the insulating film on the side surface of the gate electrode, and an insulating film surface on the side surface of the gate electrode on a part of the thin film semiconductor layer above the gate electrode A second conductive type base region formed across the thin film semiconductor layer at a predetermined distance from the first conductive type emitter region, a first conductive type emitter region formed at an end of the thin film semiconductor layer far from the connecting semiconductor portion, and a first conductive type an emitter electrode provided in both contact with the type emitter region and a second conductivity type base region, and a collector electrode formed on the back surface side of the semiconductor substrate, a gate electrode and the emitter electrode through the insulating film Emitter region and The method of manufacturing a MIS semiconductor device is part of both contact with the over source region are facing, by epitaxial growth and connecting semiconductor portion and the thin film semiconductor layer to the first conductivity type semiconductor substrate formed with the gate electrode and the insulating film A method of manufacturing a MIS semiconductor device, comprising: forming a semiconductor device. An emitter electrode formed on the first conductive type semiconductor substrate via an insulating film, an insulating film covering the side surface of the emitter electrode, a first conductive type thin film semiconductor layer formed on the emitter electrode, and a side surface of the emitter electrode A thin film semiconductor that is separated from the insulating film surface on the side surface of the emitter electrode by a predetermined distance from a connecting semiconductor portion that connects the semiconductor substrate and the first conductive type thin film semiconductor layer through the insulating film; Insulation on the second conductivity type base region formed across the layers, the first conductivity type emitter region formed at the end of the thin film semiconductor layer far from the connecting semiconductor portion, and the second conductivity type base region A gate electrode provided through the film and a collector electrode formed on the back side of the semiconductor substrate, and the gate electrode and the emitter electrode through the insulating film are in contact with the emitter region and the base region together; versus And in the manufacturing method of the MIS semiconductor device is, the MIS semiconductor device, characterized in that the emitter electrode and the connecting semiconductor portion to the first conductivity type semiconductor substrate formed with the insulating film and the thin film semiconductor layer formed by epitaxial growth Production method. An emitter electrode formed on the first conductive type semiconductor substrate via an insulating film, an insulating film covering the side surface of the emitter electrode, a first conductive type thin film semiconductor layer formed on the emitter electrode, and a side surface of the emitter electrode A thin film semiconductor that is separated from the insulating film surface on the side surface of the emitter electrode by a predetermined distance from a connecting semiconductor portion that connects the semiconductor substrate and the first conductive type thin film semiconductor layer through the insulating film; Insulation on the second conductivity type base region formed across the layers, the first conductivity type emitter region formed at the end of the thin film semiconductor layer far from the connecting semiconductor portion, and the second conductivity type base region A gate electrode provided through the film and a collector electrode formed on the back side of the semiconductor substrate, and the gate electrode and the emitter electrode through the insulating film are in contact with the emitter region and the base region together; versus The method of manufacturing a MIS semiconductor device that you are the steps of forming a mask on the first conductivity type semiconductor substrate, a step of performing isotropic etching, and forming an oxide film, poly recess was subjected to etching A MIS semiconductor comprising a step of filling silicon, a step of forming an oxide film on polysilicon, and a step of forming a thin film semiconductor layer by epitaxial growth on the surface of the first conductive type semiconductor substrate that is not etched. Device manufacturing method.

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