JP4624440B2 - Multilayer circuit board, method for manufacturing the same, and method for adjusting characteristic impedance thereof - Google Patents

Description

  The present invention relates to a multilayer circuit board that performs interlayer connection with a conductor filled between layers, a method for manufacturing the same, and a method for adjusting characteristic impedance thereof.

In recent years, with the demand for higher speed and higher performance of computers, there is an increasing demand for high-density mounting of semiconductor elements. In a high-end field such as a supercomputer, a ceramic substrate used for mounting a semiconductor element has a structure in which two wiring layers are sandwiched between ground layers (or power supply layers), thereby reducing crosstalk. Control of characteristic impedance is realized along with high-density mounting.
Japanese Patent Laid-Open No. 5-206678

  In data transfer using a high clock frequency, even if the above-described structure is adopted, sufficient effects cannot be obtained in reducing crosstalk and controlling characteristic impedance.

  Therefore, there is a conventional one disclosed in Patent Document 1. This is because the number of the shield connection bodies is five or more in the multilayer wiring board in which the shield connection bodies are provided around the signal connection bodies. As a result, crosstalk in the interlayer connection portion is reduced and characteristic impedance is stabilized. Even in such a case, since it is necessary to provide a large number of connection bodies on the wiring board, it is not possible to sufficiently cope with recent high-density mounting and increase in the number of pins.

  Therefore, the main object of the present invention is to stabilize the characteristic impedance and increase the density of the signal line connection body with low signal reflection due to the difference in the characteristic impedance between the signal wiring layer and the signal line connection body. It is to achieve both density mounting and compatibility.

  Still another object of the present invention is to reduce the size of the substrate structure required for matching the characteristic impedance.

In order to achieve the above-described object, a multilayer circuit board according to the present invention includes at least two first shield layers disposed to face each other, and a first insulator provided between the first shield layers. And at least two wiring layers disposed in the first insulator substantially parallel to the first shield layer and facing each other, and the first insulator along the facing direction of the wiring layer. A connecting body that is provided through one insulator and connects the wiring layers, and is sandwiched between the connecting bodies at a central position of the connecting body along a facing direction of the wiring layers. An intermediate connection layer that electrically connects the one end side portion and the other end side portion, and a second provided on substantially the same plane of the intermediate connection layer and spaced apart around the intermediate connection layer The intermediate connection layer and the second connection layer. The gap formed between the first and second layers is filled with a second insulator having a relative dielectric constant lower than that of the first insulator, and the diameter when the wiring layer is regarded as substantially circular is m. If the diameter when the intermediate connection layer is considered to be substantially circular is r, r <m when the connection body has a higher characteristic impedance than the wiring layer.
Further, the multilayer circuit board of the present invention, at least two of the first shield layer arranged opposite to each other, a first insulator disposed between the first shield layer, the first insulator And at least two wiring layers arranged substantially parallel to the first shield layer and facing each other, and penetrating the first insulator along a facing direction of the wiring layer. A connection body that is provided to connect the wiring layers, and is sandwiched between the connection bodies at a central position of the connection body along the facing direction of the wiring layers. An intermediate connection layer that electrically connects the portions, and a second shield layer that is provided on substantially the same plane of the intermediate connection layer and is spaced apart from the periphery of the intermediate connection layer Formed between the intermediate connection layer and the second shield layer. The gap is filled with a second insulator having a relative dielectric constant lower than that of the first insulator, the diameter when the wiring layer is regarded as substantially circular is m, and the intermediate connection layer is substantially circular. If the diameter of the connection body is r, r> m when the characteristic impedance of the connection body is lower than that of the wiring layer.

The characteristic impedance adjusting method for a multilayer wiring board according to the present invention includes at least two first shield layers arranged opposite to each other, a first insulator provided between the first shield layers, and the first At least two wiring layers disposed substantially parallel to the first shield layer and facing each other, and the first insulation along a direction in which the wiring layers face each other. A connection body that is provided through the body and connects the wiring layers, and a portion on one end side of the connection body that is sandwiched between the connection bodies at a central position of the connection body along the facing direction of the wiring layers. And an intermediate connection layer that electrically connects the other end portion and a second shield layer that is provided on substantially the same plane of the intermediate connection layer and is spaced apart from the periphery of the intermediate connection layer possess the door, wherein the intermediate connector second A gap formed between the shield layer, a characteristic impedance adjustment method for a multilayer circuit board which is filled with the low first insulator than the dielectric constant second insulator, the wiring layer When the diameter when m is regarded as a substantially circular shape and r when the intermediate connection layer is regarded as a substantially circular shape is r <m, when the characteristic impedance of the connection body is higher than that of the wiring layer, r <m If the characteristic impedance of the connection body is lower than that of the wiring layer, r> m.

  In the method for manufacturing a multilayer circuit board according to the present invention, the lower wiring layer is electrically connected to the lower wiring layer by penetrating the lower wiring layer on the lower surface of the lower insulating layer and passing through the lower insulating layer in the thickness direction. Forming a lower connection body to be connected to each other; an upper surface of the lower insulating layer; an intermediate connection layer electrically connected to the lower wiring layer; and a space around the intermediate connection layer A shield layer formed on the lower insulating layer, and an opening substantially corresponding to the gap between the intermediate connection layer and the shield layer. Forming an insulator having a dielectric constant lower than that of the lower insulating layer on the upper surface of the covering layer, and removing the insulator together with the covering layer except for the insulator on the opening; The upper insulating layer having a relative dielectric constant equivalent to that of the lower insulating layer is formed on the upper surface of the lower insulating layer. A step of forming a layer, a step of forming an upper connecting body that penetrates in the thickness direction of the upper insulating layer and is electrically connected to the intermediate connecting layer, and an upper surface of the upper insulating layer, Forming an upper wiring layer electrically connected to the upper connection body.

  By satisfying this condition, the present invention can match the characteristic impedance of the wiring layer and the characteristic impedance of the connection body to the extent that the signal reflectivity is 0.05 or less.

  As described above, according to the present invention, the characteristic impedance of the wiring layer and the characteristic impedance of the connection body can be matched to the extent that the signal reflectivity is 0.05 or less. Moreover, this characteristic impedance matching can be realized without the need to form an extra via hole. As a result, there is an effect that the signal line via hole having a small signal reflection due to the difference in characteristic impedance between the signal wiring layer and the signal line via hole can be provided with high density and at low cost.

  Preferred embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 shows a configuration according to a reference example of the present invention. In this reference example, the present invention will be described by taking a multilayer circuit board having four layers as an example, but it goes without saying that the present invention can be similarly applied to a multilayer circuit board having a number of layers other than four layers. Absent.

  This multilayer circuit board includes a laminate 101 which is an example of an insulator. The stacked body 101 is configured by stacking and integrating insulating layers 100A, 100B, 100C, and 100D that are stacked in four layers. A wiring layer 102 which is an example of a lower wiring layer is provided on the upper surface of the insulating layer 100 </ b> A located at the lowermost layer of the stacked body 101. The wiring layer 102 is composed of a conductive film patterned into a wiring shape.

  An insulating layer 100B, which is an example of a lower insulating layer, is stacked on the upper surface of the insulating layer 100A. The wiring layer 102 is sandwiched between the insulating layer 100A and the insulating layer 100B. A connection body 103 that is an example of a lower connection body is provided in the insulating layer 100B. The connection body 103 is formed by filling a conductor 105 into a substantially cylindrical connection hole 104 formed through the insulating layer 100B in the thickness direction.

  The connection body 103 is disposed on a connection land 102 a provided in the wiring layer 102. The connection body 103 is electrically connected to the wiring layer 102 by the lower end of the connection body 103 being in contact with the connection land 102a. The connection body 103 is composed of, for example, a conductor filled with a metal filler such as copper, or an insulating body such as a poxy resin having the same shape as the connection hole 104 covered with a conductor such as metal plating. Yes.

  The diameter R of the connection body 103 is set to be slightly smaller than the diameter of the connection land 102a. As a result, an error in alignment (alignment) between the connection body 103 and the connection land 102a is absorbed, and the reliability of the connection between them is increased.

  A via land 106, which is an example of an intermediate connection layer, and a ground layer 107, which is an example of a shield layer, are provided on the upper surface of the insulating layer 100B. Both the via land 106 and the ground layer 107 are made of a conductive film. The via land 106 is patterned in a substantially circular shape in plan view. The via land 106 is provided substantially concentrically with the connection body 103 at the upper end position of the connection body 103. The via land 106 is electrically connected to the connection body 103 by contacting the upper end of the connection body 103. The diameter r of the via land 106 is set to be slightly larger (r> R) than the diameter R of the connection body 103. As a result, an error in alignment (alignment) between the via land 106 and the connection body 103 is absorbed, and the reliability of the connection between the two is improved.

  The ground layer 107 is disposed so as to surround the via land 106. The ground layer 107 is disposed so as to substantially cover the upper surface of the insulating layer 100B. In order to avoid a region where the via land 106 is formed, the ground layer 107 is formed with a circular notch 107a. The notch 107 a is disposed concentrically with the via land 106. The diameter N of the notch 107a is set larger than the diameter r of the via land 106 (N> r). By forming the ground layer 107 in such a shape, a ring-shaped gap 108 having a width L is formed between the via land 106 and the ground layer 107. Via land 106 and ground layer 107 are electrically insulated by gap 108.

  In this specific example, the ground layer 107 is provided around the via land 106, but it goes without saying that a power layer of the same shape may be provided as a shield layer instead. Furthermore, it goes without saying that both the ground layer and the power supply layer may be provided.

  An insulating layer 100C is stacked on the upper surface of the insulating layer 100B. The via land 106 and the ground layer 107 are sandwiched between the insulating layers 100B and 100C. The insulating layer 100B is provided with a connection body 109 which is an example of an upper connection body. The connection body 109 is formed by filling the connection hole 110 with the conductor 111.

  The connection hole 110 penetrates the insulating layer 100C in the thickness direction and is formed in a substantially cylindrical shape. The connection body 109 is disposed on the via land 106. The connecting body 109 is electrically connected to the via land 106 by having its lower end abutted on the via land 106. The connection body 109 is formed and arranged at substantially the same diameter R at a substantially concentric position with the connection body 103. In order to make the electrical characteristics of the connection body 109 the same as that of the connection body 103, the conductor 111 constituting the connection body 109 is made of the same material as the conductor 105 constituting the connection body 103.

  A wiring layer 112 that is an example of an upper wiring layer is provided on the upper surface of the insulating layer 100C. The wiring layer 112 is composed of a conductive film patterned into a wiring shape. A connection land 112 a is formed integrally with the wiring layer 112. The connection land 112a has a circular shape in plan view. The connection land 112 a is provided substantially concentrically with the connection body 109 at the upper end position of the connection body 109. The connection land 112 a is electrically connected to the connection body 109 by contacting the upper end of the connection body 109. The diameter of the connection land 112 a is set to be slightly larger than the diameter R of the connection body 109. As a result, an error in alignment (alignment) between the connection land 112a and the connection body 109 is absorbed, and the reliability of the connection between the two is improved.

  The connection distance between the wiring layer 102 and the wiring layer 112 via the connection body 103, the via land 106, and the connection body 109 is h as shown in FIG.

  An insulating layer 100D is stacked on the upper surface of the insulating layer 100C. The wiring layer 112 is sandwiched between the insulating layer 100C and the insulating layer 100D.

  In this specific example, the width L of the interval 108 satisfies the condition of the following equation (1). As a result, the characteristic impedance of the entire connection body composed of the connection body 103 and the connection body 109 is matched with the characteristic impedance of the wiring layer 102 and the wiring layer 112.

(R · r) / (2 · h) ≦ L ≦ (5 · R · r) / h (1)
R: Diameter of the connecting bodies 103 and 109,
r: diameter of via land 106,
h: connection distance between the wiring layer 102 and the wiring layer 112 via the connection body 103, the via land 106, and the connection body 109;
L: width of the gap 108,
Further, of the range of the conditional expression (1),
(R · r) / h ≦ L ≦ (2 · R · r) / h (2)
If the range satisfies the above, the above-described characteristic impedance matching is further improved, and signal reflection is less likely to occur.

Furthermore, in the range of the conditional expression (1),
L = (1.5 · R · r) / h (3)
It is most preferable to satisfy (best mode).

  Hereinafter, the reason for setting the above-described conditions will be described.

  FIG. 2 shows the result of measuring the variation in the amount of signal reflection that occurs between the connecting bodies 103 and 109 and the wiring layers 102 and 112 under the conditions in which the width L is sequentially changed. The fluctuation of the signal reflection amount is caused by the characteristic impedance mismatch.

  This measurement is performed under the condition that the line width of the wiring layers 102 and 112 is 190 μm, the relative dielectric constant of the insulator layers 100A to 100D is 3.5, and the connection distance h is 200 μm.

  In FIG. 2, the horizontal axis is the value of the width L normalized by (R · r) / h, and the vertical axis is the signal reflection amount.

  As apparent from FIG. 2, the signal reflection amount is 0 in the range α in which the width L satisfies the condition of (R · r) / (2 · h) ≦ L ≦ (5 · R · r) / h. It becomes a sufficiently low value of 05 or less.

  In the range β in which the width L satisfies the condition of (R · r) / h ≦ L ≦ (2 · R · r) / h, the signal reflection amount is a lower value of 0.02 or less.

  When the width L is a point γ that satisfies the condition of L = (1.5 · R · r) / h, the signal reflection amount becomes a minimum value of 0.01.

  In a system that realizes data transfer using a clock frequency of 1 GHz or less, a reflection amount of 5% (= 0.05) or less of an input signal is required. Hereinafter, the reason will be described with reference to FIG.

  Standards such as RANBUS (high-speed bus system proposed by Ranbus, USA) and STL (Stub Series Terminated transceiver Logic) have been proposed and realized for IO interfaces in memory systems using DynamicRAM in recent years. In the electronic machine industry standard SSTL_3 (Stub Series Terminated Logic for 3.3 Volts), the output voltage standard is 3.3 ± 0.3V, the input reference voltage Vref is 1.5 ± 0.2V, and the input voltage is high level. The minimum value VIH (dc) is the input reference voltage Vref + 0.2V, and the input voltage low level maximum value VIL (dc) is the input reference voltage Vref−0.2V.

  The input signal normally satisfies the input levels VIH (ac) and VIL (ac) necessary for satisfying the timing standard. It is the input reference voltage Vref ± 0.4V. The logic of the receiving end is determined High when the input voltage high level minimum value VIH (dc) is equal to or higher. Similarly, when the input voltage is at or below the high level minimum value VIH (dc), it is determined to be Low. At other voltages, it is indeterminate and the logic is not established.

  When the output voltage is 3.3V, the amplitude of the reflected signal is 0.216V when the reflection amount of the signal at the connection bodies 103 and 109 is 0.06. When this reflected signal is added as noise of the input signal, the high level of the added signal becomes the input signal reference voltage Vre + 0.4 ± 0.216V. The low level of the input signal to which noise is added becomes the input signal reference signal Vref−0.4 ± 0.216V. Then, the minimum value of the high level and the maximum value of the low level of the input signal with noise are the input signal reference voltage Vref + 0.184V and the input reference voltage Vref−0.184V of the input signal. In this case, the input reference voltage Vref + 0.2V that is the minimum value VIH (dc) of the input voltage high level and the input reference voltage Vref−0.2V that is the maximum value VIL (dc) of the input voltage low level are not satisfied. That is, the logic is not fixed and malfunction occurs. As described above, when the reflection amount is 0.06 or more, a malfunction occurs. In addition to this, the input signal is also affected by noise other than the reflection signal at the connection bodies 103 and 109, and therefore, it is necessary to suppress the reflection signal at the connection body to be small. For this reason, the signal reflection amount needs to be 5% (= 0.05) or less.

For example, when the connection distance h is set to 400 μm, the diameter R is set to 200 μm, and the diameter r is set to 400 μm (hereinafter referred to as setting 1),
(R · r) / (2 · h) = 100
(5 · R · r) / h = 1000
It becomes. Therefore, equation (1) is
100 ≦ L ≦ 1000 (1) ′
It becomes.

  In setting 1, when the width L is 50 μm or 2 mm (= 2000 μm), the condition of the expression (1) ′ is not satisfied. For this reason, the connection bodies 103 and 109 and the wiring layers 102 and 112 do not match in characteristic impedance, which causes a problem of large signal reflection between them.

  In setting 1, when the width L is 100 μm, 400 μm, and 1000 μm, the condition of the expression (1) ′ is satisfied. Then, the connection bodies 103 and 109 and the wiring layers 102 and 112 are matched in characteristic impedance, and signal reflection hardly occurs between them.

At this time,
(R · r) / h = 200
(2 · R · r) / h = 400
It becomes. Therefore, equation (2) is
200 ≦ L ≦ 400 (2) ′
It becomes.

  Therefore, in setting 1, when the width L is set to a value satisfying the condition of the expression (2) ′ such as 200 μm and 400 μm, the connection bodies 103 and 109 and the wiring layers 102 and 112 have more characteristic impedances. They are matched and no further signal reflection occurs between them.

Furthermore, in setting 1,
(1.5 · R · r) / h = 300
It becomes. Therefore, the above equation (3) is
L = 300 (3) '
It becomes.

  Therefore, when setting the width L to 300 μm in the setting 1 and satisfying the condition of the expression (3) ′, the connection bodies 103 and 109 and the wiring layers 102 and 112 most closely match their characteristic impedances. Signal reflection between the two is minimized.

When the connection distance h is set to 200 μm, the diameter R is set to 200 μm, and the diameter r is set to 300 μm (hereinafter referred to as setting 2),
(R · r) / (2 · h) = 150
(5 · R · r) / h = 1500
It becomes. Therefore, equation (1) is
150 ≦ L ≦ 1500 (1) ″
It becomes.

  In setting 2, when the width L is 50 μm or 2 mm (= 2000 μm), the condition of the expression (1) ″ is not satisfied. Therefore, the connection bodies 103 and 109 and the wiring layers 102 and 112 do not match their characteristic impedances, which causes a problem in that signal reflection increases between them.

  In setting 2, when the width L is set to 150 μm, 800 μm, and 1500 μm, the condition of the expression (1) ″ is satisfied. Therefore, the connection bodies 103 and 109 and the wiring layers 102 and 112 have matching characteristic impedances. There is almost no signal reflection between them.

At this time,
(R · r) / h = 300
(2 · R · r) / h = 600
It becomes. Therefore, equation (2) is
300 ≦ L ≦ 600 (2) ″
It becomes.

  Therefore, in setting 2, when the width L is set to a value satisfying the condition of the expression (2) '' such as 300 μm and 600 μm, the connection bodies 103 and 109 and the wiring layers 102 and 112 have more characteristic impedance. They are matched and no further signal reflection occurs between them.

Furthermore, in setting 2,
(1.5 · R · r) / h = 450
It becomes. Therefore, Equation (3) is
L = 450 (3) ''
It becomes.

  Therefore, in setting 2, when the width L is set to 450 μm and the value satisfies the condition of the expression (3) ″, the connection bodies 103 and 109 and the wiring layers 102 and 112 most closely match their characteristic impedances. The amount of signal reflection between the two is minimized.

  FIG. 4A shows the result of measuring the frequency characteristics (Smith chart) of the characteristic impedance of the connection bodies 103 and 109 satisfying the expression (3) in the present invention.

  Further, FIG. 4B shows the result of measuring the frequency characteristic (Smith chart) of the characteristic impedance of a configuration that does not fall within the scope of the present invention (width L is 1000 μm = 1 mm).

  These measurements are performed under the conditions where the connection distance h is 400 μm, the diameter R is 200 μm, the diameter r is 400 μm, the width is 190 μm, and the relative dielectric constant of each of the insulating layers 100A to 100D is 3.5.

  4A and 4B show S11 of the S parameter in the connection bodies 103 and 109 for signals having a frequency of 100 MHz to 10 GHz.

  The Smith chart is generally used to represent the characteristics of devices used in high-frequency circuits, such as RF filters and amplifier circuits in the field of wireless communication. By using the Smith chart, the impedance and reflection coefficient of the circuit can be read immediately.

In the S parameter, the reflection coefficient describing the state of the traveling wave and the reflected wave toward the port 1 when the port 2 is matched in the 2-port circuit is represented by S11 which is one of the S parameters. On the Smith chart, the distance from the center to the plotted point represents the absolute value of the reflection coefficient. The rotation angle represents the phase angle of the reflection coefficient. When plotted at the center of the Smith chart, the reflection coefficient matches zero. When plotted on the outer circle of the Smith chart, the absolute value of the reflection coefficient matches 1. The relationship between the impedance and the reflection coefficient is that the impedance of the circuit is ZL, the impedance of the signal source is Z0, and the reflection coefficient is Γ.
Γ = (ZL−Z0) / (ZL + Z0)
It is expressed.

  When the circuit impedance is perfectly matched with the signal source impedance (ZL = Z0), the reflection coefficient Γ = 0. When the characteristic is plotted at the center on the Smith chart, the impedance of the circuit of interest matches the impedance of the circuit connected to it, meaning that there is no reflection.

  As shown in FIG. 4A, in the configuration of the present invention, the frequency characteristics are plotted so as to be gathered substantially at the center of the Smith chart. The reflection coefficient is almost zero. The characteristic impedance of the connection bodies 103 and 109 substantially matches the characteristic impedance of the wiring layers 102 and 112.

  As shown in FIG. 4B, a configuration that does not fall within the scope of the present invention is plotted at the center of the Smith chart at 100 MHz. However, it goes away from the center as the frequency increases, and is farthest from the center at 10 GHz. The absolute value of the reflection coefficient at 10 GHz is about 5%.

  As described above, in this reference example, the characteristic impedance can be matched without forming an extra connection body. Therefore, in this reference example, the signal connection body can be formed at a density twice or more per unit area as compared with the conventional case where one signal connection body is provided with five or more ground connection bodies. it can. This reference example can be made smaller than before, and moreover, a multilayer circuit board can be manufactured at a low cost.

  Next, a first preferred embodiment of the present invention will be described with reference to FIG.

  Since the schematic configuration of the multilayer circuit board is the same as that of the reference example described in FIG. 1, the same reference numerals as those in FIG.

  This multilayer circuit board has a laminated body 101 which is an example of a first insulator. The stacked body 101 is configured by stacking and integrating insulating layers 100A, 100B, 100C, and 100D that are stacked in four layers. A wiring layer 102 and a wiring layer 112 are disposed inside the stacked body 101. The wiring layers 102 and 112 are electrically connected via the connection body 103, the via land 106, and the connection body 109. A ground layer 107 is provided on the same plane as the via land 106 inside the stacked body 101. A gap 108 is formed between the ground layer 107 and the via land 106 to electrically insulate them from each other.

  In the gap 108, an insulator 120, which is an example of a second insulator, is disposed. The insulator 120 has a dielectric constant lower than that of the insulator layers 100A to 100D. The insulator 120 fills the entire gap 108. The insulator 120 is formed as follows, for example.

  As shown in FIG. 6A, a via land 106, a ground layer 107, and a gap 108 are patterned on the insulating layer 100B. Next, a resist pattern 121 that is an example of a coating layer is formed over the insulating layer 100B. An opening 121 a is formed in the resist pattern 121 at a portion facing the gap 108.

  As shown in FIG. 6B, an insulating film 120 ′ made of epoxy resin or the like is formed on the formed resist pattern 121. As the insulating film 120 ′, a film having a relative dielectric constant lower than that of the insulating layers 100A to 100D is used. Next, as shown in FIG. 6C, the resist pattern 121 is removed to leave the insulating film 120 ′ only in the gap 108.

  The relative dielectric constant of the insulator 120 is closely related to the matching of the characteristic impedance between the connecting bodies 103 and 109 and the via land 106. This is because the relative dielectric constant of the gap 108 is involved in the amount of capacitance component generated between the via land 106 and the ground layer 107. Compared with the case where an insulator having a relative dielectric constant lower than that of the insulating layers 100A to 100D is arranged in the gap 108, the case where the insulator is arranged reduces the amount of capacitance component generated. For this reason, the width L required to obtain the matching of the characteristic impedance between the connecting bodies 103 and 109 and the via land 106 is smaller when the insulator 120 is disposed in the gap 108 than when it is not.

  Therefore, in this specific example, the width L necessary for matching the characteristic impedance between the connection bodies 103 and 109 and the via land 106 can be reduced. Thereby, in this specific example, the entire structure of the connection bodies 103 and 109 can be reduced in size as compared with a configuration in which the gap 108 is not separately filled with an insulator. High-density mounting is also possible.

  Next, a second preferred embodiment of the present invention will be described with reference to FIG.

  This specific example is basically the same as the configuration of the reference example and the first preferred specific example, and the same reference numerals are given to the same or similar parts.

  This multilayer circuit board includes a laminated body 101 formed by laminating and integrating insulating layers 100A, 100B, 100C, and 100D that are arranged in four layers. A wiring layer 102 and a wiring layer 112 are disposed inside the stacked body 101. The wiring layers 102 and 112 are electrically connected via the connection body 103, the via land 106, and the connection body 109. A ground layer 107 is provided on the same plane as the via land 106 inside the stacked body 101. A gap 108 is formed between the ground layer 107 and the via land 106 to electrically insulate them from each other. The gap 108 is filled with an insulator 130 having a relative dielectric constant lower than that of the insulating layers 100A to 100D.

In this specific example, the width L satisfies the condition of the following expression (4). Thereby, the characteristic impedance of the whole connection body is matched with the characteristic impedance of the wiring layers 102 and 112.
(R · r · √ε ′) / (2 · h · √ε) ≦ L ≦ (5 · R · r · √ε ′) / (h · √ε)
(4)
R: Diameter of the connecting bodies 103 and 109,
r: diameter of via land 106,
h: Connection distance between the wiring layers 102 and 112 via the connection body 103, the via land 106, and the connection body 109,
L: width of the gap 108,
ε: relative dielectric constant of the insulating layers 100A to 100D ε ′: relative dielectric constant of the insulator 130 In the range of the conditional expression (4),
(R · r · √ε ′) / (h · √ε) ≦ L ≦ (2 · R · r · √ε ′) / (h · √ε)
... (5)
If the range satisfies the above, the matching of the characteristic impedance is further improved, and signal reflection is less likely to occur, which is more preferable.

Furthermore, out of the range of the conditional expression (4),
L = (1.5 · R · r · √ε ′) / (h · √ε) (6)
It is most preferable to satisfy (best mode).

  Hereinafter, the reason for setting the above-described conditions will be described.

  FIG. 8 shows the result of measuring the variation in the amount of signal reflection that occurs between the connection bodies 103 and 109 and the wiring layers 102 and 112 under the condition that the width L of the gap 108 is sequentially changed. In this measurement, the line width of the wiring layers 102 and 112 is 190 μm, the relative dielectric constant ε of the insulating layers 100A to 100D is 4.5, the relative dielectric constant ε ′ of the insulator 130 is 3, and the connection distance h is 200 μm. Measured under the following conditions. Furthermore, in FIG. 8, the width L of the gap 108 is normalized by (R · r · √ε ′) / (h · √ε). In FIG. 8, the horizontal axis is the value of the width L, and the vertical axis is the signal reflection amount.

The width L is
(R · r · √ε ′) / (2 · h · √ε) ≦ L ≦ (5 · R · r · √ε ′) / (h · √ε)
In the range α ′ satisfying the above condition, the signal reflection amount is a sufficiently low value of 0.05 or less. As described in the first preferred specific example, in a system that realizes data transfer using a clock frequency of 1 GHz or less, the signal reflection amount needs to be 5% (= 0.05) or less of the input signal. is there.

The width L is
(R · r · √ε ′) / (h · √ε) ≦ L ≦ (2 · R · r · √ε ′) / (h · √ε)
In the range β ′ satisfying the above condition, the signal reflection amount is 0.02 or less, which is an even lower value.

The width L is
L = (1.5 · R · r · √ε ′) / (h · √ε)
When the point γ ′ satisfying the above condition is satisfied, the signal reflection amount becomes a minimum value of 0.01.

For example, the connection distance h is 400 μm, the diameter R of the connection bodies 103 and 109 is 200 μm, the diameter r of the via land 106 is 400 μm, the relative dielectric constant ε of the insulating layers 100A to 100D is 4.5, and the relative dielectric constant of the insulator 130. When ε ′ is set to 3 (hereinafter referred to as setting 3),
(R · r · √ε ′) / (2 · h · √ε) ≈82
5 ・ R ・ r√ε ′ / h ・ √ε ≒ 816
It becomes. Therefore, the above-described equation (4) is
82 ≦ L ≦ 816 (4) ′
It becomes.

  In setting 3, when the width L is 50 μm or 1000 μm, the condition of the expression (4) ′ is not satisfied. For this reason, the connection bodies 103 and 109 and the wiring layers 102 and 112 do not match in characteristic impedance, which causes a problem of large signal reflection between them.

  In setting 3, when the width L is 85 μm, 200 μm, 400 μm, and 800 μm, the condition of the expression (4) ′ is satisfied. Then, the characteristic impedance of the connection bodies 103 and 109 and the characteristic impedance of the wiring layers 102 and 112 are matched, and signal reflection hardly occurs between them.

At this time,
(R · r · √ε ′) / (h · √ε) ≈163
(2 · R · r · √ε ′) / (h · √ε) ≈327
It becomes. Therefore, the above equation (5) is
163 ≦ L ≦ 327 (5) ′
It becomes.

  In setting 3, when the width L is set to a value satisfying the condition of the expression (5) ′ such as 200 μm, 250 μm, and 300 μm, the connection bodies 103 and 109 and the wiring layers 102 and 112 are more matched in their characteristic impedances. In addition, no further signal reflection occurs between the two.

In setting 3,
(1.5 · R · r · √ε ′) / (h · √ε) ≈245
It becomes. Therefore, the above equation (6) is
L≈245 (6) ′
It becomes.

  In setting 3, when the width L is 245 μm and the value satisfies the condition of the expression (6) ′, the connection bodies 103 and 109 and the wiring layers 102 and 112 most closely match the characteristic impedances. The amount of signal reflection between them is minimized.

When the connection distance h is 400 μm, the diameter R is 200 μm, the diameter r is 400 μm, the relative dielectric constant ε is 7.5, and the relative dielectric constant ε ′ is 4,
(R · r · √ε ′) / (2 · h · √ε) ≈73
(5 · R · r · √ε ′) / (h · √ε) ≈730
It becomes. Therefore, equation (4) is
73 ≦ L ≦ 730 (4) ″
It becomes.

  In setting 3, when the width L is 50 μm or 1000 μm, the condition of the expression (4) ″ is not satisfied. For this reason, the connection bodies 103 and 109 and the wiring layers 102 and 112 do not match their characteristic impedances, which causes a problem in that signal reflection increases between them.

  In setting 3, when the width L is set to 75 μm, 150 μm, and 700 μm, the condition of the expression (4) ″ is satisfied. Therefore, the connection bodies 103 and 109 and the wiring layers 102 and 112 have matching characteristic impedances. Signal reflection hardly occurs during this period.

At this time,
(R · r · √ε ′) / (h · √ε) ≈146
(2 · R · r · √ε ′) / (h · √ε) ≈292
It becomes. Therefore, equation (5) is
146 ≦ L ≦ 292 (5) ″
It becomes.

  In setting 3, when the width L is set to a value satisfying the condition of the expression (5) ″ such as 150 μm and 250 μm, the connection bodies 103 and 109 and the wiring layers 102 and 112 are more closely matched in characteristic impedance. In addition, no further signal reflection occurs between the two.

Furthermore, in setting 3,
(1.5 · R · r · √ε ′) / (h · √ε) ≈219
It becomes. Therefore, equation (6) is
L ≒ 219 (6) ''
It becomes.

  In setting 3, when the width L is set to 219 μm and the value satisfying the condition of the expression (6) ″ is satisfied, the connection bodies 103 and 109 and the wiring layers 102 and 112 most closely match their characteristic impedances. The amount of signal reflection between the two is minimal.

  As described above, by providing the configuration of this specific example, matching of characteristic impedance can be performed without forming an extra connection body.

  In this specific example, the signal connection body can be formed at a density twice or more per unit area as compared to the conventional case where one signal connection body is provided with five or more ground connection bodies. Therefore, in this specific example, the size can be reduced as compared with the conventional case, and the multilayer circuit board can be manufactured at a low cost. Further, since the width L can be further reduced, high-density mounting can be achieved.

Next, a specific example according to a reference example of the present invention will be described with reference to FIG.

  This specific example is basically the same as the configuration of the reference example and the first and second preferred specific examples, and the same or similar parts are denoted by the same reference numerals.

  This multilayer circuit board includes a laminated body 101 which is an example of an insulator. The stacked body 101 is configured by stacking and integrating insulating layers 100A, 100B, 100C, and 100D that are stacked in four layers. A wiring layer 102 and a wiring layer 112 are disposed inside the stacked body 101. The wiring layers 102 and 112 are electrically connected via the connection body 103, the via land 106, and the connection body 109. The connection bodies 103 and 109 are examples of connection bodies. The via land 106 is an example of an intermediate connection layer. The wiring layers 102 and 112 are composed of conductive films patterned in a wiring shape. Connection layers 102a and 112a are provided in the wiring layers 102 and 112, respectively. The connection lands 102a and 112a have a circular shape in plan view as shown in FIG. 1B. The connection lands 102 a and 112 a are provided substantially concentrically with the connection bodies 103 and 109 at the lower end position or the upper end position of the connection bodies 103 and 109. The connection lands 102a and 112a are electrically connected to the connection bodies 103 and 109 by contacting the lower ends or upper ends of the connection bodies 103 and 109. The diameters of the connection lands 102 a and 112 a are set to be slightly larger than the diameter R of the connection body 109.

  A ground layer 107 that is an example of a second shield layer is provided in the laminated body 101 on the same plane as the via land 106. A gap 108 is formed between the ground layer 107 and the via land 106 to electrically insulate them from each other. Each outermost layer of the stacked body 101 is provided with a ground layer 140 that is an example of a first shield layer.

In this specific example, when the characteristic impedance of the connection bodies 103 and 109 is higher than that of the wiring layer 102,
r <m (7)
r: diameter of via land 106,
m: The diameter of the wiring layers 102 and 112, specifically the diameter of the connection lands 102a and 112a.

When the characteristic impedance of the connection bodies 103 and 109 is lower than that of the wiring layer 102,
r> m (8)
And In FIG. 9, as an example, r <m.

  Thereby, the characteristic impedance matching between the connection bodies 103 and 106 and the wiring layers 102 and 112 is achieved, and the reflection amount of the signal is suppressed. The reason will be described below.

  The characteristic impedance Z of the connection bodies 103 and 106 can be expressed by Z = √ (I / C) from the equivalent inductance I and the equivalent capacitance C. The equivalent inductance I is an inductance component resulting from the length of the connection bodies 103 and 106 corresponding to the connection distance h described in the above specific example. The equivalent capacitance C is due to the capacitance existing between the connection bodies 103 and 106 and the ground layer 140.

Here, the equivalent capacitance C fluctuates due to the difference between the diameter r of the via land and the diameter m of the connection lands 102a and 112a. When the diameter r is larger than the diameter m (r> m), the capacitance C is
ε · ε0 · [{π · (m / 2)} 2 −π · (r / 2) 2] / (h / 2)
Only increase.

Similarly, when the diameter r is smaller than the diameter m (r <m), the capacitance C is
ε · ε0 · [{π · (r / 2)} 2 −π · (m / 2) 2] / (h / 2)
Only decrease.

ε: relative dielectric constant of insulating layers 100A to 100D ε0: relative dielectric constant in vacuum h / 2: separation distance between connection bodies 103 and 106 and connection lands 102a and 112a, each of insulating layers 100A to 100A Since the thicknesses of 100D are equal to each other, they are half the connection distance h (h / 2). Thus, the capacitance C can be increased by making the diameter m larger than the diameter r. Similarly, the capacitance C can be reduced by making the diameter m smaller than the diameter r.

  When the impedance of the whole connection body is higher than that of the wiring layers 102 and 112, the impedance of both can be matched by making the diameter m larger than the diameter r, and the amount of signal reflection can be suppressed. When the impedance of the whole connecting body is lower than that of the wiring layers 102 and 112, the impedance of both can be matched by making the diameter m smaller than the diameter r, and the amount of signal reflection can be suppressed.

  FIG. 10 shows the characteristics of the reflection amount with respect to the width L of the gap 108 when the connection distance h = 445 μm, the diameter r = 400 μm, the diameter R = 200 μm, and the diameter m = 500 μm (r <m). As apparent from comparison between FIG. 10 and FIG. 2, the range of the width L that can suppress the reflection amount to the upper limit value 0.05 or less shown in the above-described specific example is (r <m). The range of the width L in which the amount of reflection can be suppressed to 0.05 or less is wider in the case of, as compared to the case of not. Specifically, the range on the side where the width L increases is widened.

  As shown in FIG. 11, this specific example exhibits the same effect even when implemented on a multilayer circuit board in which the ground layer 107 as the second shield layer is not provided. In the multilayer circuit board shown in FIG. 11, the width L of the gap 108 in each of the specific examples described above is infinite, and the characteristic impedance cannot be controlled by adjusting the width L. Therefore, in order to control the characteristic impedance of the entire connection body in accordance with the characteristic impedance of the wiring layers 102 and 112, the relationship between the diameter r and the diameter m may be adjusted as in this specific example.

  In each of the specific examples having the above-described configuration and characteristics, a particularly remarkable effect is exhibited when transmitting a signal having a wavelength of 1500 times or less of the connection distance h described above. The reason will be described below.

  When a wiring having a length of 1 mm is formed on a substrate having no ground plane in a medium having a relative dielectric constant ε = 1, the amount of signal reflected by the wiring has the characteristics shown in FIG. 12 depending on the frequency of the signal. Here, if the upper limit value of the signal reflection amount is 5% as described above, the upper limit value of the frequency related to the signal reflection amount is determined, and the upper limit value is 0.2 GHz (= 200 MHz). In terms of wavelength, it is 1.5 m.

  When the wavelength of the signal to be transmitted (1.5 m in the above example) is 1/1500 times or less of the length of the wiring (1 mm in the above example), the reflection of the signal by the wiring exceeds the upper limit (5%). Therefore, it is necessary to control the characteristic impedance of the wiring. Therefore, in this specific example, a remarkable effect is exhibited when a signal having a wavelength equal to or shorter than 1500 times the connection distance h corresponding to the length of the wiring is transmitted.

In general, the wavelength λ of the electromagnetic wave in the medium is
λ = Cv / (f · √ε)
Cv: speed of light f: frequency Since the relative dielectric constant ε of the insulating layers 100A to 100D corresponding to the medium in each specific example is 1 or more, the wavelength of the signal to be transmitted is shorter than that in the above-described condition (ε = 1). . However, it goes without saying that the relationship between the connection distance h and the wavelength is established similarly to the above-described conditions.

  In the above specific examples, the present invention has been described in a multilayer circuit board having a ground layer which is an example of a shield layer. However, the present invention may be applied to a multilayer circuit board in which a power supply layer is provided as a shield layer. Similar effects can be obtained. Furthermore, even if the present invention is applied to a multilayer circuit board having both a ground layer and a power supply layer, the same effect can be obtained.

Furthermore, the multilayer circuit board shown to FIG. 13A-FIG. 13F is illustrated as another reference example of this invention . FIG. 13A shows the connection layers 150A to 150C stacked in three stages, the two layers of via lands 106A and 106B, and the two layers of ground layers 107A and 107B (power supply) in the insulating layers 100A to 100E stacked in five layers. and it may also be) a layer, and a wiring layer 102, 112 is housed and arranged, Ru multilayer circuit board der provided with a ground layer 151 (or a power supply layer) outermost insulating layer 100A, the surface of 100E.

  FIG. 13B shows three layers of connecting members 150A to 150C, two layers of via lands 106A and 106B, two layers of ground layers 107A and 107B (power supply) A multilayer circuit board in which wiring layers 102 and 112 are provided on the surfaces of the outermost insulating layers 100A and 100C. Each invention of the present invention can also be implemented on such a multilayer circuit board.

  FIG. 13C illustrates the connection layers 150A and 150B, two via lands 106, and one ground layer 107 (which may be a power supply layer) stacked in two layers inside the three insulating layers 100A to 100C. This is a multilayer circuit board in which one wiring layer 102 is accommodated, a ground layer 151 is provided on the surface of the outermost insulating layer 100A, and a wiring layer 112 is provided on the surface of the outermost insulating layer 100B. Each invention of the present invention can be carried out also on such a multilayer circuit board.

  In FIG. 13D, three layers of connection bodies 150A to 150C, two layers of via lands 106A and 106B, and one layer of ground layer 107 (a power supply layer may be used) inside the insulating layers 100A to 100E stacked in five layers. ) And wiring layers 102 and 112, and a grounding layer 151 (which may be a power supply layer) is provided on the surface of the outermost insulating layers 100A and 100E. Each invention of the present invention can also be implemented on such a multilayer circuit board.

  In FIG. 13E, three layers of connection bodies 150A to 150C, two layers of via lands 106A and 106B, and one layer of ground layer 107 (which may be a power supply layer) are formed inside the three insulating layers 100A to 100C. ), And the wiring layers 102 and 112 are provided on the surfaces of the outermost insulating layers 100A and 100C. Each invention of the present invention can also be implemented on such a multilayer circuit board.

  FIG. 13F shows the connection layers 150A to 150C stacked in three stages, two layers of via lands 106A and 106B, and two layers of insulating layers 100A to 100E located on the outermost side among the stacked insulating layers. A multilayer circuit board in which the ground layers 107A and 107B (which may be power supply layers) and the wiring layers 102 and 112 are accommodated and the ground layer 151 (which may be power supply layers) is provided on the surface of the outermost insulating layer 100A. It is. Each invention of the present invention can also be implemented on such a multilayer circuit board.

1A is a cross-sectional view showing a schematic configuration of a multilayer circuit board according to a reference example of the present invention, FIG. 1B is a cross-sectional view taken along line AA ′ of FIG. 1A, and FIG. It is sectional drawing. It is a diagram which shows the relationship between the signal reflectivity and the gap | interval L in a reference example. It is a figure where it uses for description of the threshold value of signal reflection amount. 4A is a Smith chart showing the frequency characteristics of the multilayer circuit board of FIGS. 1A to 1C, and FIG. 4B is a Smith chart showing the frequency characteristics of the multilayer circuit board of the conventional example. 5A is a cross-sectional view showing a schematic configuration of a multilayer circuit board according to a first preferred embodiment of the present invention, and FIG. 5B is a cross-sectional view taken along the line CC ′ of FIG. 5A. FIG. 6A is a cross-sectional view illustrating a manufacturing process of the multilayer circuit board of FIGS. 5A and 5B. 7A is a cross-sectional view showing a schematic configuration of a multilayer circuit board according to a second preferred embodiment of the present invention, FIG. 7B is a cross-sectional view along the line DD ′ of FIG. 7A, and EE of FIG. 7A. FIG. FIG. 8 is a diagram showing the relationship between the signal reflectivity and the gap L in the second specific example. It is sectional drawing which shows schematic structure of the multilayer circuit board based on the specific example as a reference example of this invention. It is a diagram which shows the relationship between the signal reflectivity and the gap | interval L in the specific example as a reference example . It is sectional drawing which shows the modification of the specific example as a reference example . It is a diagram which shows the relationship between a frequency and reflection amount. It is sectional drawing which shows each other example of the multilayer circuit board as another reference example of this invention.

Explanation of symbols

100A to 100D Insulating layer 102 Wiring layer
103 Connection 106 Vialand
107 Ground layer 108 Crevice
109 Connector 112 Wiring layer
Diameter of R connector 103
r Diameter of via land 106
N Diameter of notch 107a
L Width of gap 108
h Connection distance between wiring layers 102 and 112

Claims (7)

At least two first shield layers disposed opposite each other;
A first insulator provided between the first shield layers;
At least two wiring layers disposed in the first insulator substantially parallel to the first shield layer and facing each other;
A connection body provided through the first insulator along the facing direction of the wiring layer to connect the wiring layers;
An intermediate connection layer that is sandwiched between the connection bodies at a central position of the connection body along the opposing direction of the wiring layer and electrically connects one end side portion and the other end side portion of the connection body;
A second shield layer provided on substantially the same plane of the intermediate connection layer and spaced apart around the intermediate connection layer;
A gap formed between the intermediate connection layer and the second shield layer is filled with a second insulator having a relative dielectric constant lower than that of the first insulator;
When the diameter when the wiring layer is regarded as substantially circular is m, and the diameter when the intermediate connection layer is regarded as substantially circular is r,
A multilayer circuit board in which r <m when the connection body has a higher characteristic impedance than the wiring layer. At least two first shield layers disposed opposite each other;
A first insulator provided between the first shield layers;
At least two wiring layers disposed in the first insulator substantially parallel to the first shield layer and facing each other;
A connection body provided through the first insulator along the facing direction of the wiring layer to connect the wiring layers;
An intermediate connection layer that is sandwiched between the connection bodies at a central position of the connection body along the opposing direction of the wiring layer and electrically connects one end side portion and the other end side portion of the connection body;
A second shield layer provided on substantially the same plane of the intermediate connection layer and spaced apart around the intermediate connection layer;
A gap formed between the intermediate connection layer and the second shield layer is filled with a second insulator having a relative dielectric constant lower than that of the first insulator;
When the diameter when the wiring layer is regarded as substantially circular is m, and the diameter when the intermediate connection layer is regarded as substantially circular is r,
A multilayer circuit board in which r> m when the connection body has a characteristic impedance lower than that of the wiring layer. The first and second multilayer circuit board according to claim 1 or 2 shielding layer is a ground layer. The first and second multilayer circuit board according to claim 1 or 2 shielding layer is a power layer. Wherein the first and a one ground layer of the second shield layer, multi-layer circuit board according to claim 1 or 2 other is power layer. At least two first shield layers disposed opposite each other;
A first insulator provided between the first shield layers;
At least two wiring layers disposed in the first insulator substantially parallel to the first shield layer and facing each other;
A connection body provided through the first insulator along the facing direction of the wiring layer to connect the wiring layers;
An intermediate connection layer that is sandwiched between the connection bodies at a central position of the connection body along the facing direction of the wiring layer and electrically connects one end side portion and the other end side portion of the connection body;
A second shield layer provided on substantially the same plane of the intermediate connection layer and spaced apart around the intermediate connection layer;
Characteristic impedance adjustment of a multilayer circuit board in which a gap formed between the intermediate connection layer and the second shield layer is filled with a second insulator having a relative dielectric constant lower than that of the first insulator A method,
When the diameter when the wiring layer is regarded as substantially circular is m, and the diameter when the intermediate connection layer is regarded as substantially circular is r,
When the characteristic impedance of the connection body is higher than that of the wiring layer, r <m.
A characteristic impedance adjustment method for a multilayer wiring board in which r> m when the connection body has a characteristic impedance lower than that of the wiring layer. Forming a lower wiring layer on the lower surface of the lower insulating layer, and forming a lower connection body that penetrates in the thickness direction and is electrically connected to the lower wiring layer inside the lower insulating layer; When,
Forming an intermediate connection layer electrically connected to the lower wiring layer on the upper surface of the lower insulating layer, and a shield layer disposed separately from the periphery of the intermediate connection layer;
Forming a coating layer on the upper surface of the lower insulating layer, and forming an opening substantially matching the gap between the intermediate connection layer and the shield layer in the coating layer;
Forming an insulator having a dielectric constant lower than that of the lower insulating layer on the upper surface of the covering layer, and removing the insulator together with the covering layer except for the insulator on the opening;
Forming an upper insulating layer having a dielectric constant equivalent to that of the lower insulating layer on the upper surface of the lower insulating layer;
Forming an upper connection body that penetrates in the thickness direction and is electrically connected to the intermediate connection layer in the upper insulating layer;
Forming an upper wiring layer electrically connected to the upper connector on the upper surface of the upper insulating layer;
A method for manufacturing a multilayer circuit board comprising:

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