JP4617721B2 - Semiconductor device and semiconductor circuit supply voltage control method - Google Patents

Description

  The present invention relates to a semiconductor device having a function of reducing power consumption by controlling a power supply voltage and the like.

  In recent semiconductor integrated circuits (hereinafter referred to as LSI), a method of lowering the power supply voltage is generally used to reduce power consumption. This is because the charge / discharge power of the capacitor, which is the main element of the power consumption of the LSI, is proportional to the square of the power supply voltage, and the charge / discharge power can be greatly reduced by reducing the power supply voltage.

From this point of view, a method has been proposed in which the power supply voltage is dynamically controlled according to the LSI operating frequency, process variation, temperature change, etc., and the lowest power supply voltage capable of operating the LSI is adaptively supplied. (For example, Patent Document 1). In this method, in general, the delay of a critical path is grasped using a delay circuit for monitoring having a delay characteristic equivalent to the critical path of the LSI, and the grasped delay falls within the limit defined by the operation cycle time of the LSI. The power supply voltage is controlled.
JP 2002-1000096 A

  On the other hand, with recent miniaturization of semiconductor processes, leakage power due to subthreshold leakage current (hereinafter referred to as leakage current) has become a major problem in addition to charge / discharge power. For this reason, it is becoming difficult to reduce the entire power consumption including leakage power only by controlling the power supply voltage as in the prior art.

  As a method of reducing the leakage power, a power switch composed of transistors with a high threshold and a small leakage current is inserted on the power supply line for each LSI functional block to supply power to the standby functional block. Is generally cut off by a power switch.

  However, this method can reduce only the leakage power in the standby state, and there is a disadvantage that the leakage power in the active state cannot be reduced.

  The present invention has been made in view of such circumstances, and an object thereof is a semiconductor device capable of reducing power consumption in an active state of a semiconductor circuit including leakage power, and a method for controlling a supply voltage of the semiconductor circuit. Is to provide.

According to a first aspect of the present invention, there is provided a semiconductor device which operates by being supplied with a substrate voltage of a semiconductor substrate and a power supply voltage of the circuit, which are respectively controlled according to a control signal, and monitors a critical path delay of the semiconductor circuit A delay monitor circuit, a power consumption monitor circuit for monitoring the power consumption of the semiconductor circuit, and a condition that the delay monitored in the delay monitor circuit does not exceed a predetermined delay corresponding to the operation cycle time of the semiconductor circuit And outputting a control signal for adjusting the power supply voltage so that the power consumption monitored by the power consumption monitor circuit is minimized based on the monitor value of the delay monitor circuit while keeping the substrate voltage constant. 1 and the power consumption monitor circuit based on the monitor value of the power consumption monitor circuit while keeping the power supply voltage constant. Power to be monitored Te has a control circuit for alternately repeated and a second process of outputting a control signal for adjusting the substrate voltage so as to minimize.

According to the first aspect of the invention, the power consumption is performed under a condition that the delay of the critical path of the semiconductor circuit monitored by the delay monitor circuit does not exceed a predetermined delay corresponding to the operation cycle time of the semiconductor circuit. The substrate voltage and power supply voltage of the semiconductor circuit are controlled so that the power consumption of the semiconductor circuit monitored by the monitor circuit is minimized.
By changing the substrate voltage, the threshold value of the transistor in the semiconductor circuit changes, and the leakage current changes. Further, the charge / discharge power of the capacitor component in the semiconductor circuit is changed by changing the power supply voltage of the circuit. Therefore, by controlling the substrate voltage and the power supply voltage as described above, the ratio between the charge / discharge power of the capacitor component and the leakage power of the transistor in the total power consumption is the smallest. It becomes possible to change to an appropriate ratio.

According to the first invention, the control circuit outputs a control signal for adjusting the power supply voltage while keeping the substrate voltage constant based on a monitor value of the delay monitor circuit. If, based on the monitor value of the power monitor circuit is alternately repeated and a second process of outputting a control signal for adjusting the substrate voltage while maintaining the power supply voltage constant.
Accordingly, in the first process, the power supply voltage is adjusted based on the monitor value of the delay monitor circuit in a state where the substrate voltage is kept constant. In the second process, the power supply voltage is kept constant. In this state, the substrate voltage is adjusted based on the monitor value of the power consumption monitor circuit. Then, the adjustment of the power supply voltage and the adjustment of the substrate voltage are alternately repeated to determine the power supply voltage and the substrate voltage at which the power consumption monitored by the power consumption monitor circuit is minimized.

  In this case, in the first process, for example, the power supply voltage is adjusted to the minimum under the condition that the monitor value of the delay monitor circuit does not exceed a predetermined delay value corresponding to the operation cycle time of the semiconductor circuit. A control signal may be output to obtain a monitor value of the power consumption monitor circuit in a state where the power supply voltage is adjusted to the minimum. In the second process, a series of monitor values of power consumption obtained by repeating the first process and a value of the substrate voltage when each of the series of monitor values is acquired. Thus, a new substrate voltage that can reduce the power consumption of the semiconductor circuit may be determined, and a control signal for changing the currently supplied substrate voltage to the determined substrate voltage may be output.

  In this specification, “operation cycle time” means a time of one cycle when the operation of the semiconductor circuit is periodically executed, and is equal to the time of one cycle defined by the operating frequency of the semiconductor circuit. .

According to the first process, the monitor value of the delay monitor circuit has a predetermined value corresponding to an operation cycle time of the semiconductor circuit (that is, a delay time that hinders the operation of the semiconductor circuit when the monitor value exceeds this). The power supply voltage is adjusted to a minimum under the condition that the delay value is not exceeded. Then, the monitor value of the power consumption monitor circuit in the state adjusted to the minimum is acquired by the control circuit.
According to the second process, based on a series of monitor values of power consumption obtained by repeating the first process, and a value of the substrate voltage when each of the series of monitor values is acquired. Thus, a new substrate voltage that can reduce the power consumption of the semiconductor circuit is determined, and the currently supplied substrate voltage is changed to the determined substrate voltage. For example, if the current power consumption increases compared to the previous time, if the current board voltage is higher than the previous time, the next board voltage is set lower than the current time, and conversely if the current board voltage is lower than the previous time. The next substrate voltage is set higher than this time. Also, for example, when the current power consumption is reduced compared to the previous time, if the current substrate voltage is higher than the previous time, the next substrate voltage is set higher than the current time. Is lower, the next substrate voltage is set lower than this time.

The power consumption monitor circuit includes a leakage current monitor circuit that monitors a leakage current of a transistor of the semiconductor circuit, information on a power supply voltage being supplied to the semiconductor circuit, information on an operating frequency of the semiconductor circuit, An arithmetic circuit that calculates the power consumption of the semiconductor circuit based on the leak current monitored in the leak current monitor circuit may be included.
According to the above configuration, based on the information on the power supply voltage being supplied to the semiconductor circuit, the information on the operating frequency of the semiconductor circuit, and the leak current monitored in the leak current monitor circuit, Power consumption is calculated. As a result, for example, compared with a method of actually measuring power consumption, the temporal fluctuation of the power consumption monitor value is reduced, and it is not necessary to destabilize the control of the power supply voltage and the substrate voltage.

In this case, the leakage current monitoring circuit includes a leakage current monitoring transistor having a structure equivalent to a transistor included in the semiconductor circuit, a capacitor charged or discharged by a leakage current flowing through the leakage current monitoring transistor, A timing circuit for measuring a time required for the voltage of the capacitor to change from the first voltage to the second voltage in response to charging or discharging due to a leakage current, and before starting the timing in the timing circuit, the capacitor And a voltage setting circuit for setting the voltage to the first voltage.
According to the above configuration, the voltage of the capacitor is set to the first voltage before timing is started in the timing circuit. When the timing of the timing circuit is started, the capacitor is charged or discharged by the leakage current of the leakage current monitoring transistor, and the voltage of the capacitor starts to change from the first voltage. The time required for the voltage of the capacitor to change from the first voltage to the second voltage is measured by the time measuring circuit. This measured value has a value corresponding to the leakage current of the transistor in the semiconductor circuit having a structure equivalent to the leakage current monitoring transistor.

The leak current monitor circuit includes a first leak current monitor circuit that monitors a leak current of the first conductivity type transistor of the semiconductor circuit, and a second leak current of the second conductivity type transistor of the semiconductor circuit. The leakage current monitor circuit may be included.
In this case, the arithmetic circuit may calculate the power consumption of the semiconductor circuit using an average value of leak currents monitored in the first leak current monitor circuit and the second leak current monitor circuit, respectively. .
Alternatively, the arithmetic circuit converts the leakage current of a predetermined gate circuit included in the semiconductor circuit based on the leakage current monitored in each of the first leakage current monitoring circuit and the second leakage current monitoring circuit. Then, the power consumption of the semiconductor circuit may be calculated using the conversion result.

  Further, the semiconductor circuit may include a power switch that cuts off the supply of the power supply voltage, and a circuit block to which the power supply voltage is supplied via the power switch. In this case, the arithmetic circuit includes the semiconductor circuit. The power consumption of the semiconductor circuit may be calculated using information on the number of gate circuits that are supplying power supply voltage in the circuit.

The delay monitor circuit may include a signal generation circuit, a delay circuit, and a delay detection circuit.
The signal generation circuit generates a first signal and a second signal having a delay corresponding to the operation cycle time of the semiconductor circuit with respect to the first signal.
The delay circuit inputs and propagates the first signal, gives a delay equivalent to or correlated with the critical path of the semiconductor circuit, and outputs the delayed signal.
The delay detection circuit detects the delay of the output signal of the delay circuit with respect to the first signal with reference to the delay of the second signal with respect to the first signal.

According to the above configuration, the second signal has a delay corresponding to the operation cycle time of the semiconductor circuit with respect to the first signal. The delay of the output signal of the delay circuit with respect to the first signal has a delay equivalent to or correlated with the critical path. In the delay detection circuit, the delay of the output signal of the delay circuit with respect to the first signal is detected with reference to the delay of the second signal with respect to the first signal.
As a result, the delay detection circuit detects the delay according to the margin time of the critical path delay with respect to the operation cycle time of the semiconductor circuit, which is a delay time that hinders the operation of the semiconductor circuit. A value is obtained.

The first invention further includes a clock frequency switching circuit that switches the frequency of the clock signal supplied to the semiconductor circuit and the delay monitor circuit in accordance with processing speed information required for the semiconductor circuit. Also good. The semiconductor circuit operates at a processing speed corresponding to the frequency of the clock signal, and the signal generation circuit of the delay monitor circuit includes the first signal having a delay difference corresponding to the cycle time of the clock signal and The second signal may be generated.
Thus, for example, when a high processing speed is required for the semiconductor circuit, a high frequency clock signal is supplied to the semiconductor circuit, and when a high processing speed is not required for the semiconductor circuit, the semiconductor circuit has a low frequency. It is possible to reduce the power consumption by switching the frequency of the clock signal according to the processing speed, such as by supplying a clock signal.

In this case, the clock frequency switching circuit switches the frequency of the clock signal supplied to the delay monitor circuit when the frequency of the clock signal supplied to the semiconductor circuit and the delay monitor circuit is switched from a low frequency to a high frequency. The frequency of the clock signal supplied to the semiconductor circuit is switched to a high frequency after the switching to a higher frequency, and after the switching, the power supply voltage is adjusted to the minimum by the first processing of the control circuit. desirable. When switching the frequency of the clock signal supplied to the semiconductor circuit and the delay monitor circuit from a high frequency to a low frequency, the frequency of the clock signal supplied to the semiconductor circuit and the delay monitor circuit is set to a low frequency at a common timing. It is desirable to switch to
As a result, when the frequency of the clock signal supplied to the semiconductor circuit and the delay monitor circuit is increased, the frequency of the clock signal is switched after the power supply voltage is increased in advance to a level at which the semiconductor circuit can operate. Is done.
Further, when reducing the frequency of the clock signal supplied to the semiconductor circuit and the delay monitor circuit, the delay monitor circuit maintains a state where the delay of the critical path of the semiconductor circuit can be normally monitored in the delay monitor circuit. Frequency switching is performed.

According to a second aspect of the present invention, there is provided a semiconductor circuit supply voltage control method for controlling a voltage supplied to a semiconductor circuit, comprising a first step and a second step which are executed alternately and repeatedly.
In the first step, the delay of the critical path of the semiconductor circuit is monitored, and the semiconductor circuit under the condition that the value of the monitored delay does not exceed a predetermined delay value corresponding to the operation cycle time of the semiconductor circuit. And a fourth step of monitoring power consumption of the semiconductor circuit in a state where the power supply voltage is adjusted to the minimum in the third step.
In the second step, a series of monitor values of power consumption obtained by repeating the first step and each of the series of monitor values are supplied to the semiconductor substrate of the semiconductor circuit. A new substrate voltage that can reduce the power consumption of the semiconductor circuit is determined based on the substrate voltage value to be changed, and the currently supplied substrate voltage is changed to the determined substrate voltage.

  According to the second aspect, in the first step, the critical path delay of the semiconductor circuit is monitored, and the monitor value does not exceed a predetermined delay value corresponding to the operation cycle time of the semiconductor circuit. Therefore, the power supply voltage of the semiconductor circuit is adjusted to the minimum. The power consumption of the semiconductor circuit in a state where the power supply voltage is adjusted to the minimum is monitored. In the second step, a series of monitor values of power consumption obtained by repeating the first step and each of the series of monitor values are supplied to the semiconductor substrate of the semiconductor circuit. Based on the value of the substrate voltage, a new substrate voltage capable of reducing the power consumption of the semiconductor circuit is determined, and the currently supplied substrate voltage is changed to the determined substrate voltage. For example, if the current power consumption increases compared to the previous time, if the current board voltage is higher than the previous time, the next board voltage is set lower than the current time, and conversely if the current board voltage is lower than the previous time. The next substrate voltage is set higher than this time. Also, for example, when the current power consumption is reduced compared to the previous time, if the current substrate voltage is higher than the previous time, the next substrate voltage is set higher than the current time. Is lower, the next substrate voltage is set lower than this time.

  According to the present invention, the power supply voltage and the substrate voltage are controlled, respectively, and the ratio between the charge / discharge power and the leakage power included in the power consumption in the active state of the semiconductor circuit is set appropriately. It can be changed to a ratio. Thereby, the power consumption in the active state of the semiconductor circuit including the leakage power can be effectively reduced as compared with the method of controlling only the power supply voltage.

  Hereinafter, three embodiments of the present invention will be described with reference to the drawings.

<First Embodiment>
FIG. 1 is a diagram showing an example of the configuration of the semiconductor device according to the first embodiment of the present invention.

  Before describing the semiconductor device shown in FIG. 1, first, the principle of reducing the power consumption of the semiconductor circuit in this embodiment will be described.

  In general, power consumption of a semiconductor circuit is consumed by charge / discharge power consumed by charging / discharging of a capacitor component, leakage power consumed by a transistor leakage current, and a through current of a transistor connected in series between a power source and a ground. It can be expressed by the sum of the power. Of these three components, the power consumption due to through current is small compared to the other two components, so in many cases the power consumption of a semiconductor circuit can be approximated by the sum of charge / discharge power and leakage power. It is.

  As already described, since the charge / discharge power of the capacitor component is proportional to the square of the power supply voltage, reducing the power supply voltage is very effective in reducing the charge / discharge power. However, since the leakage current is becoming larger due to the recent miniaturization of the manufacturing process, it is difficult to reduce the total power consumption including the leakage power only by controlling the power supply voltage as in the conventional technique. ing. In other words, the conventional technology is mainly effective in reducing the charge / discharge power, but is not sufficient in terms of reducing the overall power consumption by combining the charge / discharge power and the leak power, and further reduces the power consumption. There is room for reduction.

2 to 4 show the power consumption of the semiconductor circuit when the substrate voltage V _BS and the power supply voltage V _DD are changed in a state where the delay of the semiconductor circuit is kept constant so as to satisfy the required operation speed. FIG.
The vertical axis of the figure indicates the normalized power consumption of the semiconductor circuit, and the horizontal axis indicates the substrate voltage supplied to the semiconductor substrate.

When the substrate voltage V _BS is changed, the threshold value of the transistor changes, so that the leakage current changes. On the other hand, since the change in the threshold value of the transistor changes the delay of the semiconductor circuit, it is necessary to change the power supply voltage V _DD in order to keep the delay of the semiconductor circuit constant. As a result, the ratio of charge / discharge power and leak power in the total power consumption changes, and the overall power consumption also changes.

In the example under the high temperature condition (FIG. 2), the leakage current increases, so that the ratio of the leakage power to the total power consumption increases. Therefore, a state in which the leakage current is suppressed by applying the substrate voltage V _BS in the reverse direction is a condition for minimizing the overall power consumption. In the example of FIG. 2, the overall power consumption is minimized when the power supply voltage V _DD = 0.9 V and the substrate voltage V _BS = −0.6 V.

On the other hand, in the example under the low temperature condition (FIG. 3), the leakage current decreases, so the ratio of charge / discharge power to the total power consumption increases. Therefore, the state in which the charge / discharge power is suppressed by applying the substrate voltage V _BS in the forward direction to increase the operation speed of the semiconductor circuit and lowering the power supply voltage V _DD is the condition for minimizing the overall power consumption. In the example of FIG. 3, when the power supply voltage V _DD = 0.65 V and the substrate voltage V _BS = 0.4 V, the overall power consumption is minimized.

Finally, in the example under the room temperature condition (FIG. 4), the vicinity of the zero bias condition between the high temperature condition and the low temperature condition is the condition for minimizing the power consumption. In the example of FIG. 4, when the power supply voltage V _DD = 0.8 V and the substrate voltage V _BS = 0 V, the overall power consumption is minimized.

As can be seen from the above examples, it is not sufficient to simply lower the power supply voltage in order to minimize the overall power consumption within the range satisfying the required operating speed. It is necessary to adjust the ratio of the leakage power and the charge / discharge power in the total power consumption to be set appropriately.
In this embodiment, the power supply voltage and the substrate voltage are adaptively controlled in accordance with variations in characteristics due to manufacturing processes and changes in the operating environment, so that the overall power consumption including leakage power and charge / discharge power can be reduced. It is intended to minimize.

Next, the semiconductor device shown in FIG. 1 will be described.
The semiconductor device shown in FIG. 1 includes a target circuit 1, a clock generation circuit 2, a delay monitor circuit 3, a power consumption monitor circuit 4, and a control circuit 5.
The target circuit 1 is an embodiment of the semiconductor circuit of the present invention.
The delay monitor circuit 3 is an embodiment of the delay monitor circuit of the present invention.
The power consumption monitor circuit 4 is an embodiment of the power consumption monitor circuit of the present invention.
The control circuit 5 is an embodiment of the control circuit of the present invention.

[Target circuit 1]
The target circuit 1 is a semiconductor circuit formed on a semiconductor substrate, and can be, for example, a CPU, a DSP, or other logic circuit. The target circuit 1 is supplied with the power supply voltage V _DD of the circuit from the power supply circuit 6 and is supplied with the substrate voltage V _BS of the semiconductor substrate from the substrate voltage supply circuit 7.

[Power supply circuit 6]
The power supply circuit 6 generates a power supply voltage V _DD controlled according to the control signal of the control circuit 5 and supplies it to the target circuit 1.

[Substrate voltage supply circuit 7]
The substrate voltage supply circuit 7 generates a substrate voltage V _BS controlled according to the control signal of the control circuit 5 and supplies it to the target circuit 1.

[Clock generation circuit 2]
The clock generation circuit 2 generates a clock signal CK common to the target circuit 1 and the delay monitor circuit 3.

[Delay monitor circuit 3]
The delay monitor circuit 3 is a circuit that monitors the delay of the critical path of the target circuit 1. For example, as shown in FIG. 1, the delay monitor circuit 3 includes a pulse generation circuit 8, a delay circuit 9, a delay detection circuit 10, and a register 11. Have.
The delay circuit 9 is an embodiment of the delay circuit of the present invention.
The pulse generation circuit 8 is an embodiment of the signal generation circuit of the present invention.
The delay detection circuit 10 is an embodiment of the delay detection circuit of the present invention.

The pulse generation circuit 8 generates a pulse signal S1 and a pulse signal S1A having a delay corresponding to the operation cycle time of the target circuit 1 with respect to the pulse signal S1.
For example, based on the clock signal CK supplied from the clock generation circuit 2, the pulse signal S1 and the pulse signal S1A having a delay difference equal to one cycle of the clock signal CK are generated.
The pulse signal S1 generated in the pulse generation circuit 8 is supplied to the delay circuit 9, and the pulse signal S1A is supplied to the delay detection circuit 10.

  The delay circuit 9 receives and propagates the pulse signal S1 generated in the pulse generation circuit 8, and outputs a delay equivalent to the critical path of the target circuit 1 or having a correlation.

For example, as shown in FIG. 1, the delay circuit 9 is supplied with the power supply voltage V _DD and the substrate voltage V _BS common to the target circuit 1, and the delay characteristics with respect to these voltages are critical path delays of the target circuit 1. It is equivalent to the characteristic or has a correlation. Therefore, the delay of the delay circuit 9 is equivalent to or has a correlation with the delay of the critical path of the target circuit 1 even when the power supply voltage V _DD and the substrate voltage V _BS change.

  The delay circuit 9 is preferably formed on a common semiconductor chip with the target circuit 1. Thereby, the delay characteristic of the delay circuit 9 is equivalent to or has a correlation with the delay characteristic of the critical path of the target circuit 1 even when there is a characteristic variation or a temperature variation caused by the manufacturing process. .

FIG. 5 is a diagram illustrating an example of the configuration of the delay circuit 9.
The delay circuit 9 illustrated in FIG. 5 includes a gate delay circuit 9-1 for simulating the delay of the gate circuit and a wiring delay circuit 9-2 for simulating the delay of the wiring.

  The gate delay circuit 9-1 selects one signal corresponding to the gate delay setting signal S3 from the gate circuits 9-1a to 9-1c connected in cascade and the input signal or output signal of each gate circuit. And a selector circuit 9-1d for outputting.

  The pulse signal S1 is input to the first stage of the cascaded gate circuits 9-1a to 9-1c. The input pulse signal S1 propagates sequentially from the first stage to the subsequent stage of the gate circuits 9-1a to 9-1c, and is output from each gate circuit as a signal having a different delay. One delay signal corresponding to the gate delay setting signal S3 is selected from the plurality of delay signals and output.

  The wiring delay circuit 9-2 receives one signal corresponding to the wiring delay setting signal S4 from the wiring delay elements 9-2a to 9-2c connected in cascade and the input signal or output signal of each wiring delay element. And a selector circuit 9-2d for selecting and outputting.

  A delay signal output from the selector circuit 9-1d of the gate delay circuit 9-1 is input to the first stage of the interconnected delay elements 9-2a to 9-2c. The input delay signal further propagates through the wiring delay elements 9-2a to 9-2c, and is output as a signal having a different delay from each wiring delay element. One delay signal corresponding to the wiring delay setting signal S4 is selected from the plurality of delay signals and is output as the signal S2.

  With such a configuration, the delay component of the gate circuit and the delay component of the wiring can be adjusted independently, so that the delay characteristic of the delay circuit 9 and the delay characteristic of the critical path of the target circuit 1 can be accurately adjusted. They can be combined or have a high correlation between the characteristics of both.

In the example of FIG. 5, the wiring delay circuit 9-2 is connected to the subsequent stage of the gate delay circuit 9-1, but a similar function can be realized even if this order is reversed.
The delay elements constituting the delay circuit 9 are not limited to gate circuits and wiring delay elements, and other delay elements that cause signal delay in the target circuit 1 may be added.

  The register 11 holds the gate delay setting signal S3 and the wiring delay setting signal S4 input to the delay circuit 9. These signals can be arbitrarily rewritten by a control device such as a CPU (not shown).

  The delay detection circuit 10 detects the delay of the output signal S2 of the delay circuit 9 with respect to the pulse signal S1 with reference to the delay of the pulse signal S1A with respect to the pulse signal S1.

FIG. 6 is a diagram illustrating an example of the configuration of the delay detection circuit 10.
The delay detection circuit 10 illustrated in FIG. 6 includes gate circuits 10-1 to 10-5 connected in cascade and flip-flops 10-6 to 10-10 that hold the input signals of the gate circuits in synchronization with the pulse signal S1A. -10 and an encoder 10-11 for converting bit data held in each flip-flop into numerical data.

  The output signal S2 of the delay circuit 9 is input to the first stage of the cascaded gate circuits 10-1 to 10-5. The input signal S2 propagates sequentially from the first stage of the gate circuits 10-1 to 10-5 toward the subsequent stage. When the pulse signal S1A reaches the clock terminal of each flip-flop during the propagation process, the input signal of each gate circuit is held in each flip-flop. The value of the input signal held in each flip-flop is the number of stages of the gate circuits 10-1 to 10-5 that the output signal S2 of the delay circuit 9 reaches until the pulse signal S1A reaches the clock terminal. Indicates whether or not

FIG. 7 is a diagram showing the timing relationship of each signal in the delay detection circuit shown in FIG.
In the example of FIG. 7, the pulse signal S1A has a delay of one cycle of the clock signal CK with respect to the pulse signal S1. That is, after a time of one cycle of the clock signal CK has elapsed since the pulse signal S1 having the value “1” is input to the delay circuit 9, the input signals of the gate circuits 10-1 to 10-5 are changed to the flip-flop 10. -6 to 10-10.
Therefore, as the delay of the delay circuit 9 is smaller than one cycle of the clock signal CK, the signal of the value “1” is held in the flip-flop in the gate circuit whose number of stages is far from the first stage. Conversely, as the delay of the delay circuit 9 approaches one cycle of the clock signal CK, a signal of value “0” is held in the flip-flop in the gate circuit closer to the first stage. When the delay of the delay circuit 9 becomes larger than one cycle of the clock signal CK, the outputs of all the flip-flops become the value “0”.
In this way, the flip-flops 10-6 to 10-10 hold the delay value of the delay circuit 9 detected with reference to the time of one cycle of the clock signal CK.

The signal held in the flip-flop is converted into numerical data by the encoder 10-11. For example, when a signal sequence of “1”, “1”, “1”, “0”,..., “0” is obtained in order from the first stage gate circuit, the encoder 10-11 converts the signal sequence to the value “3”. Converted to numeric data.
The numerical data output from the encoder 10-11 represents a margin time that the critical path delay of the target circuit 1 has for one cycle of the clock signal CK. For example, the larger the value, the longer the margin time, and conversely, the smaller the value, the shorter the margin time.
The numerical data of the encoder is output to the control circuit 5 as critical path delay information of the target circuit 1.

As will be described later, the control circuit 5 controls the power supply circuit 6 so that the delay information output from the delay detection circuit 10 matches a preset target value. For example, when the target value = '3' is set, the power supply circuit 6 is controlled so that the delay information = '3'. As a result, the power supply voltage V _DD is set so that the delay of the output signal S2 of the delay circuit 9 falls within one cycle time of the clock signal CK.

Note that the delay detection circuit 10 is not limited to the configuration shown in FIG. 6. For example, the delay of the output signal S2 of the delay circuit 9 is compared with a reference value determined according to one cycle time of the clock signal CK. It may be configured to output to the control circuit 5 as delay information which state is “large”, “small”, or “match”. In this case, the control circuit 5 may control the power supply circuit 6 so that the delay information is in a “match” state.
The above is the description of the delay monitor circuit 3.

[Power consumption monitor circuit 4]
The power consumption monitor circuit 4 is a circuit that monitors the power consumption of the target circuit 1 and includes, for example, a leakage current monitor circuit 12, an arithmetic circuit 13, and a register 14, as shown in FIG.
The leak current monitor circuit 12 is an embodiment of the leak current monitor circuit of the present invention.
The arithmetic circuit 13 is an embodiment of the arithmetic circuit of the present invention.

The arithmetic circuit 13 is based on the information on the power supply voltage being supplied to the target circuit 1, the information on the operating frequency of the target circuit 1, and the information on the leakage current of the target circuit 1 monitored in the leakage current monitor circuit 12 described later. Thus, the power consumption of the target circuit 1 is calculated.
The power consumption P _C of the target circuit 1 can be calculated by the following equation using the power supply voltage V _DD , the operating frequency F, and the leakage current I _L of the target circuit 1.

Here, the coefficient α _AC is the number of gate circuits included in the target circuit 1 and the average activation rate of the gate circuits (the number of times that the logic value of the gate circuit is actively changed for a predetermined number of operation cycles). Charge / discharge power coefficient determined by the ratio).
The coefficient α _DC is a leak power coefficient determined by the total gate width of the transistors mounted on the target circuit 1.
The coefficients α _AC and α _DC can be determined from the evaluation results of charge / discharge power and leak power.

The register 14 stores information on the coefficient values α _DC and α _AC used for the calculation of the calculation circuit 13, the frequency F of the clock signal CK, and the power supply voltage V _{DD being} set in the control circuit 5. The information stored in the register 14 can be arbitrarily rewritten by a control device such as a CPU (not shown) similarly to the register 11.

  The leak current monitor circuit 12 monitors the leak current of the transistor included in the target circuit 1. For example, when the target circuit 1 has an n-type MOS transistor and a p-type MOS transistor, the leakage current monitor circuit 12 monitors the leakage current of each transistor.

FIG. 8 is a diagram showing an example of the configuration of a circuit that monitors the leak current of the n-type MOS transistor in the leak current monitor circuit 12.
The circuit shown in FIG. 8 includes a capacitor 12-0, an n-type MOS transistor 12-1 for monitoring leakage current, a p-type MOS transistor 12-2 for precharging, a Schmitt trigger circuit 12-3, and an AND circuit. 12-4 and 12-5, a latch circuit 12-6, a counter 12-7, and a flip-flop 12-8.

The n-type MOS transistor 12-1 is an embodiment of the leakage current monitoring transistor of the present invention.
Capacitor 12-0 is an embodiment of the capacitor of the present invention.
A circuit including a Schmitt trigger circuit 12-3, AND circuits 12-4 and 12-5, a latch circuit 12-6, and a counter 12-7 is an embodiment of the timing circuit of the present invention.
The p-type MOS transistor 12-2 is an embodiment of the voltage setting circuit of the present invention.

The capacitor 12-0 is connected between the node N4 and the ground G.
N-type MOS transistor 12-1 has a drain connected to node N 4, a source and a gate connected to ground G, and substrate voltage V _BSN is supplied from substrate voltage supply circuit 7.
In the p-type MOS transistor 12-2, the drain is connected to the node N4, the source is connected to the power supply voltage V _DD , and the precharge signal PCS is input to the gate.

The n-type MOS transistor 12-1 for monitoring leakage current has a structure equivalent to the n-type MOS transistor in the target circuit 1, and the characteristics of the leakage current are equivalent to each other.
For example, the n-type MOS transistor 12-1 is a transistor formed on a common semiconductor chip with the target circuit 1.

  Further, the p-type MOS transistor 12-2 for precharging is, for example, a high threshold transistor, and the magnitude of the leakage current can be ignored as compared with the n-type MOS transistor 12-1.

  The Schmitt trigger circuit 12-3 outputs a high level signal when the voltage at the node N4 is higher than the logical threshold value Vth, and outputs a low level signal when the voltage is lower than the logical threshold value Vth.

The AND circuit 12-4 outputs a logical product of the precharge signal PCS and the output signal of the Schmitt trigger circuit 12-3.
The latch circuit 12-6 outputs the logical product of the AND circuit 12-4 as it is when the clock signal CK is at a low level, and holds the output signal constant when the clock signal CK changes from a low level to a high level. .
The AND circuit 12-5 outputs a logical product of the output signal of the latch circuit 12-6 and the clock signal CK.

The counter 12-7 counts the number of pulses output from the AND circuit 12-5 when the precharge signal PCS is at a high level, and initializes the count result when the precharge signal PCS is at a low level.
The flip-flop 12-8 captures and holds the count result of the counter 12-7 when the precharge signal PCS falls from the high level to the low level.

  FIG. 9 is a diagram showing the timing relationship of each signal in the leak current monitor circuit of the n-type MOS transistor shown in FIG.

During the period when the precharge signal PCS is at the low level, the capacitor 12-0 connected to the node N4 is precharged to the power supply voltage V _DD by the p-type MOS transistor 12-2 for precharging having a high threshold value. .
When the precharge signal PCS transitions from the low level to the high level (time t1), the p-type MOS transistor 12-2 is turned off, and the charge of the capacitor 12-0 is discharged by the leak current of the n-type MOS transistor 12-1. The voltage at the node N4 gradually decreases (FIG. 9B). When the potential of the node N4 reaches the logic threshold value Vth of the Schmitt trigger circuit 12-3 (time t2), the output signal (node N5) transitions from the high level to the low level (FIG. 9C). . In the period from time t1 to t2 when the logical product (FIG. 9D) of the output signal of the Schmitt trigger circuit 12-3 and the precharge signal PCS becomes high level, the output of the latch circuit 12-6 becomes high level. The clock signal CK is input to the counter 12-7 through the AND circuit 12-5 (FIG. 9F), and the number of pulses is counted by the counter 12-7 (FIG. 9G). The count value of the counter 12-7 is held in the flip-flop 12-8 when the precharge signal PCS changes from the high level to the low level (time t3) ((H) in FIG. 9). At this time, the count value of the counter 12-7 is initialized to zero (FIG. 9G).

As described above, in the circuit shown in FIG. 8, after the voltage of the capacitor 12-0 is set to the power supply voltage V _DD , the discharge of the capacitor 12-0 is started by the leakage current of the n-type MOS transistor 12-1. Then, the counter 12-7 counts the pulses of the clock signal CK from the discharge start time to the time when the voltage of the capacitor 12-0 drops to the logic threshold value Vth. As a result, a count value S6 having a magnitude corresponding to the leakage current of the n-type MOS transistor 12-1 is obtained. The count value S6 is output to the arithmetic circuit 13 as a value obtained by monitoring the leakage current of the n-type MOS transistor in the target circuit 1.

FIG. 10 is a diagram showing an example of the configuration of a circuit that monitors the leak current of the p-type MOS transistor in the leak current monitor circuit 12.
9 includes an n-type MOS transistor 12-1 and a p-type MOS transistor 12-2 in the circuit shown in FIG. 8, a p-type MOS transistor 12-9 for monitoring leakage current, and a n-type MOS for precharging. The inverter circuit 12-11 is added to replace the transistor 12-10 and logically invert the precharge signal PCS and input it to the gate of the n-type MOS transistor 12-10. Other configurations are the same as those of the circuit shown in FIG.

In the p-type MOS transistor 12-9, the drain is connected to the node N4, the source and gate are connected to the power supply voltage V _DD, and the substrate voltage V _BSP is supplied from the substrate voltage supply circuit 7.
In the n-type MOS transistor 12-10, the drain is connected to the node N4, the source is connected to the ground G, and the logic inversion signal of the inverter circuit 12-11 is input to the gate.

FIG. 11 is a diagram showing the timing relationship of each signal in the leak current monitor circuit of the n-type MOS transistor shown in FIG.
In the circuit shown in FIG. 10, after the voltage of the capacitor 12-0 is set to the ground level, charging of the capacitor 12-0 is started by the leakage current of the p-type MOS transistor 12-9. The counter 12-7 counts the pulses of the clock signal CK from the charging start time to the time when the voltage of the capacitor 12-0 reaches the logic threshold value Vth. As a result, a count value S7 having a magnitude corresponding to the leakage current of the p-type MOS transistor 12-9 is obtained. The count value S7 is output to the arithmetic circuit 13 as a value obtained by monitoring the leakage current of the p-type MOS transistor in the target circuit 1.

  8 and 10, the Schmitt trigger circuit is used to detect the voltage level change at the node N4. However, the present invention is not limited to this, and an inverter circuit, a comparator, or the like may be used.

The arithmetic circuit 13 converts the leakage current of the target circuit 1 from the n-type MOS transistor and the leakage current monitor values S6 and S7 of the n-type MOS transistor obtained as described above, and uses this conversion result (for example, The power consumption P _c of the target circuit 1 is obtained (by the calculation of equation (1)).
For example, the power consumption P _c may be obtained using the average value of the leakage current monitor values S6 and S7. Alternatively, the leakage current of the gate circuit (NAND circuit or the like) included in the target circuit 1 may be converted based on the leakage current monitor values S6 and S7, and the power consumption _Pc may be obtained using this conversion result.

The power consumption monitored by the power consumption monitor circuit 4 does not have to be an absolute value, and may be a relative value in which the ratio between the charge / discharge power and the leakage power matches the actual ratio of the target circuit 1. .
Therefore, the power consumption monitor circuit 4 actually measures the current consumption value of the target circuit 1, for example, in addition to the method of obtaining the power consumption by calculation using the leakage current monitor value as described above. It is also possible to use a method of calculating based on the measurement result.
In other words, the power consumption monitor circuit 4 can use other monitoring methods as long as it obtains a monitor value of power consumption in which the ratio of charge / discharge power and leak power matches the actual ratio of the target circuit 1. good.
However, in the method of calculating the power consumption using the measured value of the current consumption, the current consumption changes every moment according to the processing content of the circuit, so that the calculation results are likely to vary with time. On the other hand, according to the method of calculating the power consumption using the monitor value of the leakage current, the variation in the calculation result according to the processing content of the circuit is reduced, so that the power supply voltage V _DD and the substrate voltage V _BS are controlled more stably can do.
The above is the description of the power consumption monitor circuit 4.

[Control circuit 5]
The control circuit 5 minimizes the power consumption monitored by the power consumption monitor circuit 4 under the condition that the delay monitored by the delay monitor circuit 3 does not exceed a predetermined delay corresponding to one cycle time of the clock signal CK. Thus, control signals for controlling the power supply voltage V _DD of the power supply circuit 6 and the substrate voltage V _BS of the substrate voltage supply circuit 7 are output.

For example, the control circuit 5 is based on the first process of adjusting the power supply voltage V _DD while keeping the substrate voltage V _BS constant based on the monitor value of the delay monitor circuit 3 and the monitor value of the power consumption monitor circuit 4. The second process of adjusting the substrate voltage V _BS is alternately repeated while keeping the power supply voltage V _DD constant.
In the first process, the power supply voltage V _DD is adjusted to the minimum under the condition that the monitor value of the delay monitor circuit 3 does not exceed a predetermined delay value corresponding to the operation cycle time of the target circuit 1. Then, the monitor value of the power consumption monitor circuit 4 in a state where the power supply voltage V _DD is adjusted to the minimum is acquired.
In the second process, a series of monitor values of power consumption (for example, previous and current monitor values) obtained by repeating the first process, and the substrate voltage V _BS when each of the series of monitor values is acquired. A new substrate voltage that can reduce the power consumption of the target circuit 1 is determined on the basis of the value (for example, the previous and current substrate voltage values), and the currently supplied substrate voltage V _{BS is set} to the determined substrate voltage. change.

Here, in the semiconductor device shown in FIG. 1 having the above-described configuration, the operation for controlling the power supply voltage V _DD and the substrate voltage V _BS so that the power consumption of the target circuit 1 is minimized will be described with reference to the flowchart of FIG. explain.
In the flowchart of FIG. 12, steps ST1 to ST5 are an embodiment of the first step of the present invention.
Steps ST6 to ST11 are an embodiment of the second step of the present invention.

Based on the monitoring result of the delay monitor circuit 3, the control circuit 5 calculates the critical path delay monitor value τ _{monitor of} the target circuit 1 (if the delay circuit 9 has a delay equivalent to the critical path, the delay of the delay circuit 9). Then, it is determined whether or not the following condition 1 is satisfied for one cycle time τ _cycle of the clock signal CK (step ST1).
Condition 1: τ _monitor <τ _cycle −Δτ;
Here, “Δτ” is a constant that gives the convergence condition of the power supply voltage.

  For example, when the delay detection circuit 10 shown in FIG. 6 is included, the control circuit 5 compares the output value S5 of the encoder 10-11 with a predetermined threshold value, and the above condition is satisfied based on the comparison result. It is determined whether or not.

When the condition 1 is satisfied, it can be determined that the delay of the critical path is still sufficient with respect to the upper limit. Therefore, as shown below, the control circuit 5 reduces the power supply voltage V _DD by the value ΔV _DD. The power supply circuit 6 is controlled (step ST3).
V _DD (n + 1) = V _DD (n) −ΔV _DD ;
Note that “V _DD (n)” indicates a value after the nth power supply voltage V _{DD is} changed.
After the power supply voltage V _DD is lowered, the process returns to step ST1 again.

On the other hand, when the condition 1 of step ST1 is not satisfied, the control circuit 5 determines whether the delay monitor value τ _monitor of the critical path satisfies the following condition for one cycle time τ _cycle (step ST2).
Condition 2: τ _monitor > τ _cycle ;

When the condition 2 is satisfied, it can be determined that the critical path delay exceeds the upper limit. Therefore, the control circuit 5 supplies power so as to increase the power supply voltage V _DD by a value ΔV _DD as shown below. The circuit 6 is controlled (step ST4).
V _DD (n + 1) = V _DD (n) + ΔV _DD ;
After increasing the power supply voltage V _DD , the process returns to step ST1 again.

Thus, as <lowering the power supply voltage V _DD if satisfying (τ _cycle -Δτ, condition 2 (tau _monitor conditions 1 τ _monitor)> if it meets the tau _cycle) to increase the power supply voltage V _DD The process is repeated, and as a result, the power supply voltage V _DD converges to a value that satisfies the following condition 3.
Condition 3: τ _cycle −Δτ ≦ τ _monitor ≦ τ _cycle ;
That is, the power supply voltage V _DD converges to the minimum voltage at which the target circuit 1 can operate normally.

In order to converge the power supply voltage V _DD to a constant value, the power supply voltage is set so that the delay change amount of the delay circuit 9 does not exceed a constant Δτ when the power supply voltage is changed by a change amount ΔV _DD in one step. It is necessary to determine the change amount ΔV _DD and the constant Δτ.

When the power supply voltage V _DD converges to the minimum value and the condition 3 is satisfied, the control circuit 5 next acquires the current power consumption P _c (n) of the target circuit 1 monitored by the power consumption monitor circuit 4. (Step ST5).
Note that “P _C (n)” represents the power consumption monitor value after the nth substrate voltage V _BS change.

Next, the control circuit 5 compares the latest power consumption monitor value P _C (n) acquired in step ST5 with the power consumption monitor value P _C (n−1) acquired in the previous loop (step 1). ST6 and ST7). Further, the substrate voltage V _BS (n) when the latest power consumption monitor value P _C (n) is acquired and the substrate voltage V _BS when the power consumption P _C (n−1) is acquired in the previous loop. Comparison with _BS (n-1) is performed (steps ST8 and ST9). Then, based on these comparison results related to the power consumption monitoring value P _C and the substrate voltage V _BS, then determines the substrate voltage to be set (step ST10, ST11, ST12).
A method for determining the substrate voltage V _BS will be described below.

(1) If “P _C (n) <P _C (n−1) −ΔP _C ” and “V _BS (n) ≧ V _BS (n−1)”, the substrate voltage to be set next is set to “V _BS + ΔV _BS ′ (step ST10). That is, if the power consumption is reduced when the substrate voltage V _BS is changed in the forward bias direction, or if the power consumption is reduced even though the substrate bias V _BS is not changed, the substrate voltage V _BS is reduced. Further, the direction is changed in the forward bias direction. Here, “ΔV _BS ” is a step of changing the substrate voltage. 'ΔP _C ' is a constant that gives a convergence condition of power consumption.

(2) If 'P _C (n) <P _C (n-1) -ΔP _C ' and 'V _BS (n) <V _BS (n-1)', the substrate voltage to be set next is set to 'V _BS− ΔV _BS ′ (step ST11). That is, when the power consumption is reduced when changing the substrate voltage V _BS in the reverse bias direction, further varying the reverse bias direction to the substrate voltage V _BS.

(3) If 'P _C (n)> P _C (n-1) + ΔP _C ' and 'V _BS (n)> V _BS (n-1)', the substrate voltage to be set next is set to 'V _BS −ΔV _BS ′ (step ST11). That is, when the power consumption is increased when the substrate voltage V _BS is changed in the forward bias direction, returning the substrate voltage V _BS in the reverse bias direction.

(4) When 'P _C (n)> P _C (n-1) + ΔP _C ' and 'V _BS (n) ≦ V _BS (n-1)', the substrate voltage to be set next is set to 'V _BS It is assumed that + ΔV _BS ′ (step ST10). That is, if the power consumption increases when the substrate voltage V _BS is changed in the reverse bias direction, or if the power consumption increases even though the substrate bias V _BS is not changed, the substrate voltage V _BS is Return to the forward bias direction.

(5) In the case of “P _C (n−1) −ΔP _C ≦ P _C (n) ≦ P _C (n−1) + ΔP _C ′, the current power supply voltage V _DD and substrate voltage V _BS are consumed. Therefore, the substrate voltage V _BS is not changed.

Control circuit 5, after changing or holding a substrate voltage V _BS by the above-described processing, the process returns to step ST1.
(1) When changing the substrate voltage V _BS by the processing to (4), the threshold value is changed in the transistor in the target circuit 1, since the operation speed is changed, it executes the loop process of steps ST1~ST4 described above again As a result, the power supply voltage V _DD converges to a new voltage. After the power supply voltage V _DD converges, the power consumption monitor value is acquired again in step ST5, and the substrate voltage to be set next is determined by any one of the processes (1) to (5).

If the temperature change or the like when the power supply voltage V _DD and the substrate voltage V _BS is in the convergence state occurs, for changing the operating speed of the target circuit 1 by the threshold change of transistor, the convergence voltage of the power supply voltage V _DD Change. Further, the monitor value of the power consumption monitor circuit 4 changes as the leakage current of the transistor changes. Therefore, the control of the power supply voltage V _DD and the substrate voltage V _BS according to the above flow is automatically started, and the combination of the power supply voltage V _DD and the substrate voltage V _BS that minimizes the power consumption under the new conditions is adaptive. It is determined.

As described above, according to the present embodiment, the delay of the critical path of the target circuit 1 monitored by the delay monitor circuit 3 is based on the condition that it does not exceed a predetermined delay corresponding to the one cycle time of the clock signal CK. The power supply voltage V _DD and the substrate voltage V _BS supplied to the target circuit 1 are controlled so that the power consumption of the target circuit 1 monitored by the power consumption monitor circuit 4 is minimized.
This makes it possible to set the ratio between the charge / discharge power of the capacitor component and the leakage power of the transistor in the total power consumption to an appropriate ratio that minimizes the total power consumption. Compared with the method of performing only the above, the power consumption in the active state of the target circuit 1 including the leakage power can be effectively reduced.

<Second Embodiment>
Next, a second embodiment of the present invention will be described.

FIG. 13 is a diagram showing an example of the configuration of the semiconductor device according to the second embodiment of the present invention.
The semiconductor device shown in FIG. 13 has the same configuration as the above-described semiconductor device shown in FIG. 1 and is provided with a clock frequency switching circuit 15.
The clock frequency switching circuit 15 is an embodiment of the clock frequency switching circuit of the present invention.

  The clock frequency switching circuit 15 switches the frequency of the clock signal supplied to the target circuit 1 and the delay monitor circuit 3 according to processing speed information required for the target circuit 1.

  The clock frequency switching circuit 15 includes a clock frequency division / switching circuit 16 and a frequency control circuit 17, for example, as shown in FIG.

  The clock frequency division / switching circuit 16 divides the clock signal CK of the clock generation circuit 2 by the frequency division ratio set by the frequency control circuit 17 and supplies it to the target circuit 1 and the delay monitor circuit 3. Further, switching of the frequency division ratio of the clock signal CK1 supplied to the target circuit 1 and switching of the frequency division ratio of the clock signal CK2 supplied to the delay monitor circuit 3 are performed at independent timings according to the control of the frequency control circuit 17. Do.

  The frequency control circuit 17 determines the frequency of the clock signal supplied to the target circuit 1 and the delay monitor circuit 3 in accordance with the processing speed information supplied from the target circuit 1, and the frequency division ratio corresponding to the determined frequency. Is set in the clock frequency dividing / switching circuit 16. Further, information on the determined frequency is written into the register of the power consumption monitor circuit 4.

  Further, the frequency control circuit 17 controls the division ratio switching timing of the clock signals CK1 and CK2 as follows.

When the frequency of the clock signals CK1 and CK2 is increased from the frequency F1 to the frequency F2 (where F2> F1), the frequency control circuit 17 supplies the clock signal CK2 supplied to the delay monitor circuit 3 to the frequency F2 before the target circuit 1. Switch to. In response to this frequency switching, the power supply voltage control in steps ST1 to ST4 automatically works, and after the power supply voltage V _DD converges to the minimum voltage value corresponding to the frequency F2, the frequency control circuit 17 moves to the target circuit 1. The clock signal CK1 to be supplied is switched to the frequency F2.

  When the frequency of the clock signals CK1 and CK2 is decreased from the frequency F2 to the frequency F1, the frequency control circuit 17 switches the frequencies of the clock signals CK1 and CK2 at a common timing.

According to the above configuration, when the processing speed is increased by increasing the frequency of the clock signal CK1 of the target circuit 1, the clock signal CK1 is increased after the power supply voltage V _DD is increased in advance to a level at which the target circuit 1 can operate. Therefore, the malfunction of the target circuit 1 can be prevented.
Further, when the power consumption is reduced by reducing the frequency of the clock signals CK1 and CK2 of the target circuit 1, before and after the frequency of the clock signal CK1 is switched by switching the frequency of the clock signals CK1 and CK2 at a common timing. Since the delay monitor operation of the delay monitor circuit 3 in FIG. 2 is kept normal, the malfunction of the target circuit 1 can be prevented.
As described above, it is possible to prevent malfunction of the target circuit 1 due to the switching of the clock frequency while reducing the power consumption by switching the frequency of the clock signal in accordance with the processing speed required for the target circuit 1. Further, after the frequency is switched, the power supply voltage and the substrate voltage are automatically adjusted to the minimum power consumption state according to the flow shown in FIG. 12, and the power consumption of the target circuit 1 is further reduced. can do.

<Third Embodiment>
Next, a third embodiment of the present invention will be described.

FIG. 14 is a diagram showing an example of the configuration of a semiconductor device according to the fourth embodiment of the present invention.
The semiconductor device shown in FIG. 14 is obtained by replacing the target circuit 1 and the power consumption monitor circuit 4 with the target circuit 1A and the power consumption monitor circuit 4A in the above-described semiconductor device shown in FIG.

The target circuit 1A includes, for example, a power switch 18 composed of a transistor having a high threshold and a low leakage current, a circuit block 19 to which a power supply voltage V _DD is supplied via the power switch 18, and a power switch 18. And a circuit block 20 to which the power supply voltage V _DD is directly supplied.
When the target circuit 1 executes processing that does not use the circuit block 19, the power switch 18 is turned off, and power supply to the circuit block 19 is cut off. As a result, wasteful power consumption due to leakage current during standby is reduced.

  The power consumption monitor circuit 4A includes a leak current monitor circuit 12, an arithmetic circuit 13A, and a register 14A.

The arithmetic circuit 13A, in addition to the information about the power supply voltage being supplied to the target circuit 1A, the information about the operating frequency of the target circuit 1, and the information about the leak current monitored by the leak current monitor circuit 12, further The power consumption of the target circuit 1 is calculated using information on the number of gates that are supplying the voltage V _DD .
Power P _C of the target circuit 1A, can be calculated for example by the following equation.

Here, “G ₁ ” and “G ₂ ” are coefficients representing the number of gates of the circuit blocks 19 and 20, and “e ₂ ” is “1” when the power switch 18 is on, and “0” when the power switch 18 is off. A flag with a value of '.
The arithmetic circuit 13A calculates the power consumption of the target circuit 1A using, for example, Expression (2).

The register 14A has coefficient values α _DC , α _AC , G ₁ , G ₂ , a flag e ₂ , a frequency F of the clock signal currently selected in the clock frequency switching circuit 15, and is set in the control circuit 5. _Stores the information of the power supply voltage V _DD inside. The information stored in the register 14A can be arbitrarily rewritten by a control device such as a CPU (not shown) as in the register 11.

According to the configuration described above, the static power consumption can be reduced by cutting off the leakage current of the standby circuit by the power switch 18 in the target circuit 1, and appropriate power consumption corresponding to the state of the power switch 18 can be achieved. By calculating the power and controlling the power supply voltage V _DD and the substrate voltage V _BS according to the flow shown in FIG. 12, dynamic power consumption can be reduced.

  As mentioned above, although some embodiment of this invention was described, this invention is not limited only to the form mentioned above, A various variation is included.

  The delay monitor circuit and the power consumption monitor circuit described above are examples for explanation, and the present invention is not limited to this. These circuits may be replaced with circuits of various other configurations that can grasp the delay of the target circuit according to changes in the power supply voltage and the substrate voltage and the changing tendency of the power consumption.

The control flow of the power supply voltage and the substrate voltage described above is an example for explanation, and the present invention is not limited to this. For example, the constants Δτ, ΔPc, and ΔV _DD are not necessarily constant values. By adopting different values depending on the substrate voltage and the power supply voltage, the stability and convergence of the control can be improved. good.

  The delay monitor circuit, power consumption monitor circuit, control circuit, clock frequency switching circuit, power supply circuit, and substrate supply circuit may all be formed on the same semiconductor chip as the semiconductor circuit that is the target for minimizing power consumption. It is also possible to form at least a part on another semiconductor chip.

It is a figure which shows an example of a structure of the semiconductor device which concerns on the 1st Embodiment of this invention. FIG. 6 is a first diagram showing power consumption of a semiconductor circuit when a substrate voltage and a power supply voltage are changed in a state where a delay of the semiconductor circuit is kept constant. FIG. 6 is a second diagram showing power consumption of the semiconductor circuit when the substrate voltage and the power supply voltage are changed while the delay of the semiconductor circuit is kept constant. FIG. 9 is a third diagram showing power consumption of the semiconductor circuit when the substrate voltage and the power supply voltage are changed while the delay of the semiconductor circuit is kept constant. It is a figure which shows an example of a structure of a delay circuit. It is a figure which shows an example of a structure of a delay detection circuit. It is a figure which shows the timing relationship of each signal in the delay detection circuit shown in FIG. It is a figure which shows an example of the structure of the circuit which monitors the leakage current of an n-type MOS transistor. It is a figure which shows the timing relationship of each signal in the circuit shown in FIG. It is a figure which shows an example of the structure of the circuit which monitors the leakage current of a p-type MOS transistor. FIG. 10 is a diagram illustrating a timing relationship of each signal in the circuit. It is a flowchart which shows an example of the control procedure of the power supply voltage and board | substrate voltage in this embodiment. It is a figure which shows an example of a structure of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is a figure which shows an example of a structure of the semiconductor device which concerns on the 3rd Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,1A ... Target circuit, 2 ... Clock generation circuit, 3 ... Delay monitor circuit, 4, 4A ... Power consumption monitor circuit, 5 ... Control circuit, 6 ... Power supply circuit, 7 ... Substrate voltage supply circuit, 8 ... Pulse generation Circuit, 9 ... Delay circuit, 9-1 ... Gate delay circuit, 9-1a to 9-1c, 10-1 to 10-5 ... Gate circuit, 9-1d, 9-2d ... Selector circuit, 9-2 ... Wiring Delay circuit, 9-2a to 9-2c ... wiring delay element, 10 ... delay detection circuit, 10-6 to 10-10 ... flip-flop, 10-11 ... encoder, 11, 14, 14A ... register, 12 ... leak current Monitor circuit, 12-0 ... capacitor, 12-1, 12-10 ... n-type MOS transistor, 12-2, 12-9 ... p-type MOS transistor, 12-3 ... Schmitt trigger circuit, 12-4, 12-5 ... AND times , 12-6 ... latch circuit, 12-7 ... counter, 12-8 ... flip-flop, 12-11 ... inverter circuit, 13, 13A ... arithmetic circuit, 15 ... clock frequency switching circuit, 16 ... clock dividing / switching circuit , 17 ... frequency control circuit

Claims (13)

A semiconductor circuit that operates by being supplied with a substrate voltage of the semiconductor substrate and a power supply voltage of the circuit, each controlled according to a control signal;
A delay monitor circuit for monitoring a critical path delay of the semiconductor circuit;
A power consumption monitor circuit for monitoring the power consumption of the semiconductor circuit;
Based on the monitor value of the delay monitor circuit while maintaining the substrate voltage constant under the condition that the delay monitored in the delay monitor circuit does not exceed a predetermined delay according to the operation cycle time of the semiconductor circuit. The first process of outputting a control signal for adjusting the power supply voltage so that the power consumption monitored in the power consumption monitor circuit is minimized, and the power consumption monitor circuit while maintaining the power supply voltage constant. A control circuit that alternately repeats a second process of outputting a control signal for adjusting the substrate voltage so that the power consumption monitored by the power consumption monitor circuit is minimized based on the monitor value ;
A semiconductor device. The control circuit is
In the first process, a control signal for adjusting the power supply voltage to a minimum is output under the condition that the monitor value of the delay monitor circuit does not exceed a predetermined delay value corresponding to the operation cycle time of the semiconductor circuit. , Obtaining the monitor value of the power consumption monitor circuit in a state where the power supply voltage is adjusted to the minimum,
In the second process, based on a series of monitor values of power consumption obtained by repeating the first process, and a value of the substrate voltage when each of the series of monitor values is acquired, Determining a new substrate voltage that can reduce the power consumption of the semiconductor circuit, and outputting a control signal for changing the currently supplied substrate voltage to the determined substrate voltage;
The semiconductor device according to claim 1 . The power consumption monitor circuit is
A leakage current monitor circuit for monitoring a leakage current of a transistor of the semiconductor circuit;
An arithmetic circuit that calculates power consumption of the semiconductor circuit based on information on the power supply voltage being supplied to the semiconductor circuit, information on the operating frequency of the semiconductor circuit, and leakage current monitored by the leakage current monitor circuit When,
including,
The semiconductor device according to claim 1 or 2. The leakage current monitor circuit is
A leakage current monitoring transistor having a structure equivalent to a transistor included in the semiconductor circuit;
A capacitor that is charged or discharged by a leakage current flowing through the leakage current monitoring transistor;
A time measuring circuit for measuring a time required for the voltage of the capacitor to change from a first voltage to a second voltage in accordance with charging or discharging due to the leakage current;
A voltage setting circuit that sets the voltage of the capacitor to the first voltage before starting the timing in the timing circuit;
including,
The semiconductor device according to claim 3 . The leakage current monitor circuit is
A first leakage current monitor circuit for monitoring a leakage current of a first conductivity type transistor of the semiconductor circuit;
A second leakage current monitor circuit for monitoring a leakage current of the second conductivity type transistor of the semiconductor circuit;
Including
The arithmetic circuit calculates the power consumption of the semiconductor circuit using an average value of leak currents monitored in the first leak current monitor circuit and the second leak current monitor circuit, respectively.
The semiconductor device according to claim 3 . The leakage current monitor circuit is
A first leakage current monitor circuit for monitoring a leakage current of a first conductivity type transistor of the semiconductor circuit;
A second leakage current monitor circuit for monitoring a leakage current of the second conductivity type transistor of the semiconductor circuit;
Including
The arithmetic circuit converts a leakage current of a predetermined gate circuit included in the semiconductor circuit based on leakage currents monitored in the first leakage current monitoring circuit and the second leakage current monitoring circuit, Calculating the power consumption of the semiconductor circuit using the conversion result;
The semiconductor device according to claim 3 . The semiconductor circuit is
A power switch for cutting off the supply of the power supply voltage;
A circuit block to which the power supply voltage is supplied via the power switch;
Including
The arithmetic circuit calculates the power consumption of the semiconductor circuit using information on the number of gate circuits that are supplying power supply voltage in the semiconductor circuit.
The semiconductor device according to claim 3 . The delay monitor circuit is
A signal generation circuit for generating a first signal and a second signal having a delay corresponding to the operation cycle time of the semiconductor circuit with respect to the first signal;
A delay circuit that inputs and propagates the first signal, and outputs a delay equivalent to or correlated with a critical path of the semiconductor circuit;
A delay detection circuit for detecting a delay of an output signal of the delay circuit with respect to the first signal, with reference to a delay of the second signal with respect to the first signal;
including,
The semiconductor device according to claim 1 or 2. A clock frequency switching circuit for switching the frequency of the clock signal supplied to the semiconductor circuit and the delay monitor circuit according to the processing speed information required for the semiconductor circuit;
The semiconductor circuit operates at a processing speed corresponding to the frequency of the clock signal,
A signal generation circuit of the delay monitor circuit generates the first signal and the second signal having a delay difference corresponding to a cycle time of the clock signal;
The semiconductor device according to claim 8 . The clock frequency switching circuit is
When switching the frequency of the clock signal supplied to the semiconductor circuit and the delay monitor circuit from a low frequency to a high frequency, the frequency of the clock signal supplied to the delay monitor circuit is switched to a higher frequency before the semiconductor circuit, and the switching is performed. Then, after the power supply voltage is adjusted to the minimum by the first processing of the control circuit, the frequency of the clock signal supplied to the semiconductor circuit is switched to a high frequency,
When switching the frequency of the clock signal supplied to the semiconductor circuit and the delay monitor circuit from a high frequency to a low frequency, the frequency of the clock signal supplied to the semiconductor circuit and the delay monitor circuit is switched to a low frequency at a common timing. ,
The semiconductor device according to claim 9 . A power supply circuit that generates the power supply voltage according to a control signal output from the control circuit and supplies the power supply voltage to the semiconductor circuit;
The semiconductor device according to claim 1 or 2. A substrate voltage supply circuit that generates the substrate voltage according to a control signal output from the control circuit and supplies the substrate voltage to the semiconductor circuit;
The semiconductor device according to claim 1 or 2. A semiconductor circuit supply voltage control method for controlling a voltage supplied to a semiconductor circuit, comprising:
Having a first step and a second step that are performed alternately and repeatedly,
The first step is
The delay of the critical path of the semiconductor circuit is monitored, and the power supply voltage of the semiconductor circuit is adjusted to the minimum under the condition that the monitored delay value does not exceed a predetermined delay value corresponding to the operation cycle time of the semiconductor circuit. A third step of
A fourth step of monitoring power consumption of the semiconductor circuit in a state where the power supply voltage is adjusted to a minimum in the third step;
Including
In the second step, a series of monitor values of power consumption obtained by repeating the first step, and each of the series of monitor values is acquired and supplied to the semiconductor substrate of the semiconductor circuit. Based on the value of the substrate voltage, a new substrate voltage that can reduce the power consumption of the semiconductor circuit is determined, and the currently supplied substrate voltage is changed to the determined substrate voltage.
Method for controlling supply voltage of semiconductor circuit.

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