WO2010079823A1 - Semiconductor device - Google Patents

Abstract

Provided is a device wherein the accuracy of measuring delay characteristics is improved, while suppressing increase of the circuit area.  The device is provided with: a selection circuit (3) which selects and outputs a plurality of input paths to a plurality of flip-flops (2) in accordance with selection signals; and a delay measuring circuit (4) which measures the delay of the signals outputted from the selection circuit (3).

Description

Semiconductor device

[Description of related applications]
The present invention is based on the priority claims of Japanese patent applications: Japanese Patent Application No. 2009-004046 (filed on Jan. 9, 2009) and Japanese Patent Application No. 2009-281886 (filed on Dec. 11, 2009). The entire contents of this application are incorporated herein by reference.
The present invention relates to a semiconductor device, and more particularly to a configuration and method suitable for grasping delay characteristics.

Recently, as a technique for reducing the power consumption of a semiconductor circuit (LSI), the power supply voltage of the LSI is generally lowered. This is intended to reduce power by applying, for example, the lowest operable voltage as a power supply voltage to an LSI. In order to use this method, it is necessary to know the minimum voltage at which the LSI can operate by some method. Generally, a delay replica circuit (replica) that generates a delay equivalent to the critical path of the core circuit is installed, and the operation clock frequency of the core circuit that is the target of power supply voltage control is compared with the delay value of the replica, By controlling the power supply voltage so that the replica delay value falls within the operation clock cycle, the lowest voltage at which LSI can operate is obtained.

With the recent miniaturization of the manufacturing process, the variation in the operating frequency of LSI is increasing.

In Patent Document 1, data determined by the fuse state of the fuse circuit in the replica control circuit is read, and the delay amount of the replica circuit is adjusted based on the decoding result of the data, whereby the LSI can operate at the minimum. A configuration for adaptively supplying voltage is disclosed.

JP 2004-179320 A

The entire disclosure of Patent Document 1 is incorporated herein by reference.
The following is an analysis of the related art according to the present invention.

According to Patent Document 1, the signal transition timing (edge) in the core circuit is used to observe the critical path delay characteristic of the core circuit.

However, there are a huge number of critical paths in the core circuit. In recent fine processes, the possibility of paths other than the critical path becoming a critical path is increasing due to the influence of manufacturing variations and inter-signal interference.

Therefore, the actual situation is that it is not known which edge of which path can be measured to accurately measure the critical path delay characteristic.

と し て As one proposal for dealing with this problem, a method for more accurately evaluating the characteristics of the core circuit by measuring multiple edges of multiple paths will be examined. In this case, in order to measure a plurality of edges, it is basically necessary to prepare a plurality of edge measurement circuits. As a result, the chip area increases. Furthermore, there is a problem that characteristics cannot be accurately measured due to variations in characteristics among a plurality of edge measuring circuits.

Therefore, an object of the present invention is to provide an apparatus that increases the measurement accuracy of delay characteristics while suppressing an increase in circuit area.

The invention disclosed in the present application is generally configured as follows in order to solve one or more of the above problems.

According to the present invention, a plurality of flip-flops, a selection circuit that selects and outputs input paths to the plurality of flip-flops according to a selection signal, and a delay measurement that measures a delay of a signal output from the selection circuit And a semiconductor device including the circuit.

According to another aspect of the present invention, comprising: a plurality of flip-flops; and a plurality of selection elements arranged in correspondence with the plurality of flip-flops, respectively, the selection elements to the corresponding flip-flops Data input path and clock input path signals are input, and the data signal and clock signal to the flip-flop are output in a time-sharing manner according to the input control signal, and the selection signal is selected from the plurality of selection elements. Therefore, a selection circuit for selecting one,
There is provided a semiconductor device including a delay measurement circuit that measures a delay between a data signal and a clock signal output in a time division manner from the selection element selected by the selection circuit.

According to still another aspect of the present invention, a core circuit responsible for a main function of a semiconductor device, a delay measurement circuit that inputs an internal signal of the core circuit and performs delay measurement, and a power supply control that supplies power to the core circuit A circuit, a storage element that stores a delay measurement result of the delay measurement circuit, and a control element that inputs a value of the storage element and outputs a control signal to the power supply control circuit, and the core circuit includes a plurality of A flip-flop and a selection circuit that selects and outputs an input path to the plurality of flip-flops according to a selection signal, and the delay measurement circuit is a semiconductor device that measures a delay of an output signal of the selection circuit. Provided.

According to the present invention, there is provided a delay measurement method using a semiconductor device including a plurality of flip-flops, wherein a selection circuit selects and outputs an input path to the plurality of flip-flops according to a selection signal, and the delay measurement circuit includes A delay measurement method is provided for measuring a delay of the selected signal.

According to the present invention, there is provided a delay measurement method for creating delay distribution information from measured path delays in the semiconductor device according to the present invention. Further, according to the present invention, there is provided a control method for extracting a feature amount from the delay distribution information and adjusting an operation of the semiconductor device based on the feature amount.

According to the present invention, it is possible to improve the measurement accuracy of delay characteristics while suppressing an increase in circuit area.

According to the present invention, it is possible to operate a semiconductor device in an optimum state by extracting various feature amounts from the created path delay distribution information and controlling the operation of the semiconductor device.

It is a figure which shows the structure of the 1st Example of this invention. It is a flowchart which shows the procedure of the 1st Example of this invention. It is a timing chart which shows the operation example of 1st Example of this invention. It is a figure which shows the structure of the delay measurement circuit of each Example of this invention. It is a figure which shows the structure of the 2nd Example of this invention. It is a figure which shows an example of a structure of FIG. It is a figure which shows an example of a structure of FIG. It is a flowchart which shows the operation | movement procedure of FIG. It is a timing chart explaining the operation of FIG. It is a figure explaining operation | movement of a delay measurement circuit. (A), (B) is a figure which shows the structure and timing operation | movement of the 3rd Example of this invention. It is a figure which shows the structure of the 4th Example of this invention. (A), (B) is a figure which shows the structure and timing operation | movement of FIG. It is a figure which shows the structure of the 5th Example of this invention. It is a figure which shows the structure of the 6th Example of this invention. It is a figure which shows the operation | movement flow of the 6th Example of this invention. (A), (B) is a figure which shows the structural example of FF. It is a figure which shows the operation | movement flow of the 7th Example of this invention. It is a figure explaining the 8th Example of this invention. It is a figure explaining the 9th Example of this invention. It is a figure explaining the 10th Example of this invention.

Embodiments of the present invention will be described below. A semiconductor device according to an embodiment of the present invention includes a selection circuit (selector) (3) that selectively outputs one signal from a plurality of signals of a plurality of paths in a core circuit, and the selected signal And a delay measuring circuit (4) for measuring the delay time. According to the present invention, when performing delay times of a plurality of signals of a plurality of paths, for example, by switching a signal selected by the selection circuit (3) at an arbitrary time interval, the delay of the plurality of signals of the plurality of paths is performed. Time measurements are taken. Further, according to the present invention, it is possible to suppress an increase in circuit area while enabling delay measurement of signals of a plurality of paths.

As described above, when a configuration (comparative example) is provided with a plurality of delay measurement circuits corresponding to a plurality of paths, the circuit area increases.

On the other hand, according to the present invention, it is only necessary to newly add one delay measurement circuit (4) and a selection circuit (3) to a plurality of delay measurement target paths. In general, the delay measurement circuit is constituted by a kind of A / D (analog / digital) conversion circuit that converts a delay time into a digital code. Therefore, the circuit area becomes large, but the selector can be realized with a small area.

Further, according to the present invention, the accurate critical path delay characteristic of the core circuit can be measured by measuring the edges of a plurality of paths. In the present invention, when a plurality of paths are output to the outside of the core circuit via the selection circuit (3), the path is input immediately before being input to the flip-flop (FF) or from the inside of the flip-flop (FF). This is because an accurate edge of the core circuit can be output by branching.

Furthermore, according to the present invention, as described above, even when measuring edges of a plurality of paths, an increase in area can be suppressed, so that not only a plurality of critical paths but also a normal path can be measured. This makes it possible to observe the internal state of the core circuit in detail. Hereinafter, description will be given in accordance with specific examples.

FIG. 1 is a diagram showing a configuration of a semiconductor device according to an embodiment of the present invention. Referring to FIG. 1, the semiconductor device of this embodiment includes a logic circuit 1, a core circuit 10 including a plurality of flip-flops (FF) 2, a selection circuit (selector) 3, and a delay measurement circuit 4. ing. Note that the selection circuit (selector) 3 may be provided in the core circuit 10.

The selection circuit 3 receives input signals to the plurality of FFs 2 (in FIG. 1, data signals (D1, D2, D3...)) And inputs signals to the plurality of FFs 2 according to the values of the input selection signals ( D1, D2, D3, etc.) The selection circuit 3 inputs not only the data signal (D) to FF2 but also the clock signal (CK) to FF2, A configuration may be selected.

The delay measurement circuit 4 measures the delay time of the output (SOUT) from the selection circuit 3, and outputs the result as a digital code.

The semiconductor device of this embodiment has a small circuit overhead. This is because only one delay measurement circuit 4 having a relatively large circuit area is required, and the circuit area of the selection circuit 3 is small.

As the input signal to the selection circuit 3, signals (D1, D2, D3...) Immediately before being input to each FF2 or branched from the inside of the FF2 are used. As a result, the transition timing (edge) of the data signal arriving at FF 2 is output (SOUT) to the outside of the core circuit 10 via the selection circuit 3, and the delay measurement circuit 4 measures the delay.

FIG. 2 is a flowchart showing a procedure for measuring delay characteristics of a plurality of paths in the core circuit 10 of this embodiment. As described above, in the semiconductor device of this embodiment, the selection circuit 3 selectively outputs any one path from a plurality of paths. Therefore, first, the selection signal is controlled, and a signal of an arbitrary path corresponding to the selection signal is output from the selection circuit 3 (step S11).

After outputting an edge of an arbitrary path, the edge is measured by the delay measurement circuit 4 (step S12).

The signal selection (S11) and delay measurement (S12) steps of FIG. 2 are executed for each of a plurality of paths in the core circuit 10, thereby switching the signal input to the selection circuit 3 to time division and delaying. Measurements can be made. As a result, detailed delay characteristics of the input paths to the plurality of FFs 2 in the core circuit 10 can be measured.

FIG. 3 is a timing chart for explaining the timing operation of this embodiment. In the example shown in FIG. 3, the selection circuit 3 selects D2 according to the selection signal and outputs it to SOUT, the delay measurement circuit 4 performs the delay measurement of D2, and then the selection circuit 3 changes the value of the selection signal so that the selection circuit 3 D1 is selected and output to SOUT, the delay measurement circuit 4 measures the delay of D1, and then the selection circuit 3 selects D3 by the selection signal and outputs it to SOUT. The delay measurement circuit 4 measures the delay of D3. In the same manner, the delay measurement circuit 4 measures the delay of the DN selected by the selection circuit 3.

FIG. 4 is a diagram showing an example of the configuration of the delay measurement circuit 4 of FIG. Referring to FIG. 4, the delay measurement circuit 4 includes a delay circuit in which delay elements 12 are cascade-connected in a plurality of stages, a plurality of FFs 42, and a data processing circuit 43.

D terminals (data terminals) of the plurality of FFs 42 are respectively connected to connection points of delay elements 41 connected in series (cascade). Although not particularly limited, a clock signal used in the core circuit 10 is commonly input to the clock terminals (CK) of the plurality of FFs 42. Although not particularly limited, the data processing circuit 43 includes at least three registers and an arithmetic operation circuit not shown. Two of these registers hold the delay measurement result of the clock signal edge and the delay measurement result of the data signal edge, respectively, and the arithmetic operation circuit obtains the delay difference from the delay measurement result of the data edge and the clock edge, The third register stores the delay difference between the data calculated by the arithmetic operation circuit and the clock.

The outputs (Q0, Q1, Q2, Q3,..., Qn) of each FF 42 are input to the data processing circuit 43. The output (SOUT) of the selection circuit 3 is input to the head of the delay element 41, propagates through the group of delay elements 41, and then the effective edge (for example, rising edge) of the clock signal (the clock supplied to the delay measurement circuit 4). Is latched by FF42. At this time, by observing how far the signal SOUT has propagated through the delay circuit, the delay of the signal SOUT can be measured. When the output signal (SOUT) of the selection circuit 3 rises from Low to High, for example, of the outputs Q0 to Qn of (n + 1) FFs 42 commonly sampled at the rising edge of the clock, Q0 to Qi (where i is When the integer of 0 to n is 1 (High) and Qi to Qn are 0 (Low), it can be seen that the propagation has reached the i-th delay element, which is the change point of the output value of the FF. By repeating this delay measurement for a plurality of paths while switching the paths, for example, tens of thousands of core cycles, the edges inside the circuit are comprehensively measured.

Also, in this embodiment, by storing only the value near the minimum timing margin value in the register, it is possible to measure the delay characteristics of the entire circuit with a small amount of memory.

Further, in the present embodiment, it is possible to search for a critical path using the acquired data.

In this embodiment, it is also possible to evaluate the jitter characteristics by measuring the same clock signal a plurality of times.

Furthermore, in this embodiment, this method is not applied to all FFs. For example, on a path or layout that can cause a maximum delay in consideration of deterioration and variation from the path distribution obtained by design. Further area reduction can be achieved by applying to a path that is likely to cause interference or failure.

Next, a second embodiment of the present invention will be described. FIG. 5 is a diagram showing the configuration of the semiconductor device according to the second embodiment of the present invention. In the semiconductor device of this embodiment, a control element 6 that receives a clock signal input to the clock (CK) terminal to the FF2 and a data signal input to the data (D) terminal is disposed adjacent to the corresponding FF2. The output signal of the control element 6 is input to the corresponding input terminal of the selection circuit 3. The FF 2 and the control element 6 constitute a delay measurement FF 5. The control element 6 may be disposed in the vicinity of the input of the FF 2 or may be disposed in the FF 2.

In the present embodiment, the configuration of the selection circuit 3 and the delay measurement circuit 4 and the delay measurement procedure are basically the same as those in the first embodiment described with reference to FIGS. .

In the first embodiment described with reference to FIG. 1, there is a possibility that the measurement accuracy of the delay characteristic may be lowered due to the difference in the propagation characteristic of the path from each FF 2 to the delay measurement circuit 4. In the embodiment shown in FIG. 1, the path to each FF 2 is branched from the node immediately before the input to each FF 2 and directly input to the delay measurement circuit 4 via the selection circuit 3.

However,
(A) Since FF2 is arranged at various positions inside the core, a difference in propagation path due to a difference in path length from FF2 to selection circuit 3;
(B) Difference in delay characteristics from input to output for each input terminal of the selection circuit 3,
For these reasons, the propagation characteristics of the edge path to the delay measurement circuit 4 may be different for each FF2. For this reason, the phase of the signal input to the FF 2 cannot be accurately propagated to the delay measurement circuit 4, and an accurate delay time may not be obtained.

Therefore, in this embodiment, by providing the control element 6, the problem of a decrease in measurement accuracy of the delay characteristic is solved.

In this embodiment, based on the fact that the circuit delay is strictly defined by the difference between the edge of the clock signal input to each FF2 and the edge of the data signal, the signal input to the FF2 is simply directly applied. Instead of branching and inputting to the selection circuit 3, the control element 6 detects the relationship between the clock signal (CK) and the data signal (D) for each FF2, and the detected clock signal (CK) and data signal are detected. The delay measurement circuit 4 measures the relationship (D). With this configuration, it is possible to avoid the influence of the difference in propagation characteristics for each path.

FIG. 6 is a diagram showing an example of the configuration of the control element 6 of FIG. Referring to FIG. 6, in this embodiment, a selection element 7 is provided as the control element 6 of FIG. The selection element 7 selects one of the data signal input to the data terminal (D) of the FF 2 or the clock signal input to the clock terminal (CK) of the FF 2 as it is according to the given control signal. 3 to the corresponding input terminals.

In this embodiment, the data signals (D1, D2,...) Input to the plurality of FFs 2 and the clock signals (CK1, CK2,. The clock signal in the vicinity of the clock input terminal) is output in a time-sharing manner, and the delay measurement circuit 4 performs delay measurement, whereby the relationship between the data signal and the clock signal can be calculated.

FIG. 7 is a diagram illustrating an example of the configuration of FIG. In the example shown in FIG. 7, a 2-input 1-output multiplexer circuit (MUX) that selectively outputs one of the two inputs according to the value (1/0) of the control signal is used as the selection element 7 in FIG. 6. In FIG. 7, the configuration other than the MUX is the same as that in FIG.

FIG. 8 is a flowchart showing the procedure of delay measurement in the present embodiment. FIG. 9 is a timing chart showing an example of the operation of this embodiment.

In this embodiment, the selection signal is first controlled for delay measurement, the measurement target path (S1, S2,... In FIG. 7) is determined (step S21 in FIG. 8), and the control signal in FIG. 7 is set. (Step S22), it is determined whether to propagate the clock signal (CK) or the data signal (D) from the MUX 7 in FIG.

In the example of FIG. 8, the clock signal (CK) is selected in step S22, and the edge delay of the clock signal (CK) is measured in step S23.

In step S24, the data signal (D) is selected, and in step S25, the edge delay of the data signal (CK) is measured. In step S26, the delay is calculated.

In step S22, it is possible to measure the delay characteristics of the entire path in the core circuit 10 by executing the delay measurement of the edges of the data and the clock signal in the plurality of FFs 2 while switching the selection signal.

In measuring the delay of each FF2, the time from the rising transition of the clock signal (CK) to the transition of the data signal (D) is often measured as the delay time. However, a glitch may appear on the data signal (D) due to a transient transition state of the circuit, and measurement by this method is difficult.

Therefore, in this embodiment, the delay time is accurately measured by observing the transition of the clock signal (CK) from the last transition of the data signal (D).

In particular,
(1) Delay measurement of clock signal (CK) (step S23 in FIG. 8),
(2) Delay measurement of data signal (D) (step S25 in FIG. 8),
(3) Calculation of delay characteristics from the difference between the delay of the clock signal (CK) and the delay of the data signal (D) (step S26 in FIG. 8),
The delay measurement is performed by the following three procedures.

For these three procedures, the operation of the delay measurement circuit 4 in FIG. 4 will be described with reference to FIG.

When the control signal is 0 (for example, Low) or 1 (for example, High), the selection element (multiplexer circuit) 7 selects the clock (CK) and data (D), respectively.

When the value of the selection signal input to the selection circuit 3 is “2”, the clock signal CK2 and the data signal D2 are output from the selection circuit 3 in a time division manner according to 0 and 1 of the control signal, respectively, and the delay measurement is performed. The delay of D2 is obtained from the difference between the delay of the clock signal (CK2) and the delay of the data signal (D2).

When the value of the selection signal input to the selection circuit 3 is “1”, the CK1 and D1 are output from the selection circuit 3 in a time-sharing manner according to 0 and 1 of the control signal, the delay measurement is performed, and the clock signal From the difference between the delay of (CK1) and the delay of the data signal (D1), the delay of D2 is obtained.

When the value of the selection signal input to the selection circuit 3 is “3”, the CK3 and D3 are output from the selection circuit 3 in a time-sharing manner according to the control signal 0 or 1, the delay measurement is performed, and the clock signal ( The delay of D3 is obtained from the difference between the delay of CK3) and the delay of the data signal (D3).

FIG. 10 is a diagram for explaining the procedure for calculating the delay characteristic from the difference between the delay of the clock signal (CK) and the delay of the data signal (D) in step 26 of FIG. In the timing diagram of FIG. 10A, SOUT is the output of the selection circuit 3, E1, E2,... En in the delay measurement circuit 4 of FIG. The output signal and clock of the delay element 41 are clock signals input to the clock terminal of the FF 42 of the delay measurement circuit 4 in FIG.

First, the delay of the clock signal (CK) output to the output SOUT of the selection circuit 3 is measured, and the transition point of the output data signal (Q0, Q1, Q2,... Qn) of the FF 42 is set to LSB (Least Significantant). (Bit) side, and the transition point is held in a register (Tck) (not shown) or the like.

The example of FIG. 10B is the case of the clock input path (CK) where SOUT is FF. At the timing of the rising transition of the clock of the delay measurement circuit 4 of FIG. Since the others are 0, the output Q0 = 1, Q1 = 1, Q2 = Q3 =. . . = Qn = 0 (the lower 2 bits are 1) and the input Q = 0. . . The transition point from 1 to 0 is 2 from the LSB side, that is, Tck = 2. *

Next, the delay of the data signal (D) output to the output SOUT of the selection circuit 3 is measured in the same manner, and the transition point from the LSB (Least Significant Bit) side of the data is held in the register (Td) or the like. The example of FIG. 10C is the case of the data input path (D) where SOUT is FF, and the output Q0 = Q1 = Q2 = Q3 = Q4 = 1, Q5 =. . . = Qn = 0 (the lower 2 bits are 1) and the input Q = 0. . . 000011111, and the transition point from 1 to 0 is 5 from the LSB side, that is, Td = 5. *

The transition point of the data signal (D) is closer to the MSB (Most Significant Bit) side than the transition point of the clock signal (CK). This is because the data cannot be correctly sampled by FF2 unless the signal at the data terminal is fixed (transition) at a predetermined time (setup time) before the rising edge of the clock terminal of FF2.

The time difference from the transition (Td) of the data signal (D) to the transition (Tck) of the clock signal (CK) is a delay margin of the path. In the example of FIG. 10, the delay time can be calculated from the delay margin = Td−Tck = 3, that is, the margin value which is a difference.

Next, a third embodiment of the present invention will be described. FIG. 11A is a diagram showing the configuration of the third exemplary embodiment of the present invention. FIG. 11B is a timing chart for explaining the operation of FIG. FIG. 11B shows timing waveforms of Sel_CK1, Sel_D1, S1, Sel_CK2, Sel_D2, and S2 of FIG.

In this embodiment, the selection element 7 shown in FIG. 6 is composed of three NAND circuits, and the selection circuit 3 is composed of an OR circuit. The FF2 and the three NAND circuits constitute a delay measurement FF5.

The selection element has a clock selection signal Sel_CK and a data selection signal Sel_D as control signals.

The clock selection signal (Sel_CK) and the clock signal (CK) are input to the first NAND circuit, and the data selection signal (Sel_D) and the data signal (D) are input to the second NAND circuit. The outputs of the first and second NAND circuits are input to the third NAND circuit at the next stage. When the clock selection signal (Sel_CK) is 1 (High), the data selection signal (Sel_D) is 0 (Low), and the first NAND circuit to which the clock signal (CK) is input is an inversion of the clock signal (CK). And the output of the second NAND circuit is fixed to 1 (High), and the third NAND circuit is an inverted signal of the output of the first NAND circuit (inverted signal of the clock signal (CK)), and accordingly A clock signal (CK) is output.

When the data selection signal (Sel_D) is 1 (High), the clock selection signal (Sel_CK) is set to 0 (Low), and the second NAND circuit that receives the data signal (D) inverts the data signal (D). The first NAND circuit output is fixed to 1 (High), and the third NAND circuit is an inverted signal of the output of the second NAND circuit (inverted signal of the data signal (D)), therefore A data signal (CK) is output.

The output of the delay measurement FF 5 (the output of the third NAND circuit) is input to the selection circuit 3 (OR circuit).

In each delay measurement FF 5, the selection element including the first to third NAND circuits outputs a signal corresponding to the control signal input to each delay measurement FF 5. For example, when the clock selection signal Sel_CK is 1 (High), the clock signal (CK1) is selected and output. When the data selection signal (Sel_D) is 1, the data signal (D1) is output.

In the configuration of FIG. 7, the multiplexer (MUX) always outputs either the clock signal (CK) or the data signal (D). For this reason, electric power is expected to increase.

In the configuration of FIG. 11A, by controlling the control signal (Sel_CK / Sel_D) to be alternatively 1, the signal is propagated only in the path output to the delay measurement circuit 4, It is possible to suppress an increase in power. For example, as shown in FIG. 11B, when only Sel_CK1 is 1 (High) and the remaining Sel_D1, Sel_CK2, Sel_D2,... Are all 0 (Low), CK1 is output to the path S1, and the selection circuit The delay measurement circuit 4 performs delay measurement via the 3 OR circuit. Next, only Sel_D1 is 1, all remaining Sel_CK1, Sel_CK2, Sel_D2,... Are 0, data D1 is output to the path S1, and delay measurement is performed by the delay measurement circuit 4 via the OR circuit of the selection circuit 3. Is called. Further, only Sel_CK2 is 1, all remaining Sel_D2, Sel_CK1, Sel_D1,... Are 0, CK2 is output to the path S2, and the delay measurement circuit 4 performs delay measurement via the OR circuit of the selection circuit 3. . Subsequently, only Sel_D2 is set to 1, the remaining Sel_CK2, Sel_CK1, Sel_D1,... Are set to 0, data D2 is output to the path S2, and the delay measurement circuit 4 performs delay measurement via the OR circuit of the selection circuit 3. .

11A has a configuration in which part of the circuit of the selection circuit 3 is added to the selection element 7 of FIG. As described above, since the logic circuit can have a plurality of configurations in order to realize the same logic, it is also possible to adopt a configuration of another logic circuit for realizing a similar function.

Next, a fourth embodiment of the present invention will be described. FIG. 12 is a diagram showing the configuration of the fourth exemplary embodiment of the present invention. In this embodiment, a processing circuit 8 is used as a control element. The processing circuit 8 outputs a simple logical operation result of the data signal (D) input to the data terminal (D) of the FF2 and the clock signal (CK) input to the clock terminal (CK) of the FF2 (S ) That is, the calculation result of the processing circuit 8 that inputs D1 and CK1 is output as one signal S1, is input to the corresponding input terminal of the selection circuit 3, and the calculation result of the processing circuit 8 that inputs D2 and CK2 is one The signal S2 is output and input to the corresponding input terminal of the selection circuit 3.

In the first embodiment, since the data signal (D) and the clock signal (CK) are output in a time-sharing manner, it takes about twice as much time for delay measurement as in the first embodiment.

In the present embodiment, the processing circuit 8 directly calculates the relationship between the clock signal (CK) and the data signal (D) and outputs the result, so that the clock signal (CK) and the data signal (D) are time-divided. ), The delay can be measured at a higher speed.

FIG. 13A is a diagram showing an example of the configuration of FIG. Referring to FIG. 13A, an XOR (exclusive OR) circuit having a data signal (D) and a clock signal (CK) as inputs is used as the processing circuit 8 in FIG. As shown in the timing chart of FIG. 13B, the phase difference between the data signal (D) and the clock signal (CK) can be converted into a pulse width by using an XOR circuit. The selection circuit 3 propagates the pulse width from the XOR circuit directly to the delay measurement circuit 4. The delay margin can be obtained by measuring the pulse width by the delay measuring circuit 4. Thereby, the delay characteristic can be calculated. The delay measurement circuit 4 is slightly different from the configuration shown in FIG. 4 and measures the width of an arbitrary pulse. This can be easily handled by changing the data processing circuit 43 of the delay measuring circuit 4 of FIG.

Next, a fifth embodiment of the present invention will be described. FIG. 14 is a diagram showing the configuration of the fifth exemplary embodiment of the present invention. In this embodiment, in addition to the core circuit 10 and the delay measurement circuit 4, a setting storage element 21, a control element 22, and a power supply control circuit 23 are provided. The delay measurement circuit 4 measures the characteristic of the critical path of the core circuit 10 and stores it in the setting storage element 21. The core circuit 10 includes the selection circuit 3 of the above embodiment, or the selection circuit 3 and the delay measurement FF 5, and outputs a signal of the selected path to the delay measurement circuit 4. The delay measurement circuit 4 has the configuration of the above-described embodiment described with reference to FIG.

The core circuit 10 has its power supply voltage variably controlled via the control element 22 and the power supply control circuit 23 based on the information stored in the setting storage element 21.

In the present embodiment, the power supply voltage of the core circuit 10 is controlled according to the delay characteristics of the core circuit 10, so that the low voltage operation of the core circuit 10 can be optimized.

Next, a sixth embodiment of the present invention will be described. FIG. 15 is a diagram showing the configuration of the sixth exemplary embodiment of the present invention. Referring to FIG. 15, the semiconductor device of this embodiment includes a core circuit 10, a delay measurement circuit 4, a setting register 34 that stores a delay characteristic result, and a delay that can generate an arbitrary delay according to the value of the setting register 34. The variable replica circuit 33, the frequency comparison circuit 32 that compares the frequency of the delay variable replica circuit 33 and the clock frequency of the core circuit 10, and the core circuit 10 and the peripheral circuits according to the frequency difference between the delay variable replica circuit 33 and the core circuit 10 A power supply control circuit 31 for supplying power.

14 is provided with a variable delay replica circuit 33 and a frequency comparator 32 as the control element 22 of FIG. In FIG. 15, the setting register 34 and the power supply control circuit 31 correspond to the setting storage element 21 and the power supply control circuit 23 of FIG. The core circuit 10 of FIG. 15 has the configuration of the embodiment described with reference to FIG.

In this embodiment, the delay variable replica circuit 33 is corrected for delay by the delay measurement circuit 4 so as to operate with the same delay characteristics as the core circuit 10. Thereby, in the present embodiment, it is possible to perform power supply voltage control optimal for the core circuit 10.

FIG. 16 is a flowchart for explaining the operation of this embodiment.

In the present embodiment, as an initial setting (step S31), the critical path characteristic of the core circuit 10 is measured using the delay measurement circuit 4 during a test before shipment, and the characteristic value is stored in the setting register 34.

Thereafter, the product is shipped, and the core circuit 10 operates normally (step S32: core circuit actual operation start). In this case, for example, the delay measurement circuit 4 is used in a state where the normal operation is not affected, and the delay is selectively measured, for example, for each path (critical path, other path, etc.) in the core circuit 10. The process of signal selection and delay measurement (steps S34 and S35) between the LOOP start and the LOOP end in FIG. 16 is repeated. The delay characteristics of various paths are repeatedly measured for tens of thousands of clocks, and the value of the setting register 34 is updated using the measured delay characteristics (step S37). Specifically, when there is a measured delay characteristic of the core circuit 10 with a small delay margin with the clock, the value of the setting register 34 is set so that the delay of the delay variable replica circuit 33 becomes longer. Correct it. The value of the setting register 34 is corrected by the data processing circuit 43 (see FIG. 4) of the delay measurement circuit 4.

Thereby, it is possible to detect an increase in delay due to an inspection failure at the time of initial setting, a delay deterioration of the core circuit 10, a partial temperature rise of the core circuit 10, and the like. By reflecting the operation characteristics, not only the power supply optimization of the core circuit 10 can be realized, but also the malfunction of the core circuit 10 can be prevented. By continuing this operation after product shipment, for example, it can be operated as a low-power mechanism at the time of shipment, operated for a long period of time, and can be operated as a safety mechanism when circuit deterioration progresses.

It is also possible to set the simulation result directly in the setting register 34 without measuring the critical path during the test.

In the present embodiment, one of the above-described embodiments is used as the delay measurement circuit 4 of the core circuit 10, but the delay measurement of other embodiments may be used.

Also, it is possible to use an FF as shown in FIG. 17 for delay measurement. The flip-flop (FF1) in FIG. 17A is called “Raizor-FF” and latches the same data signal (D) separately using a normal clock (CLK) and a clock signal delayed by a delay circuit. In this way, malfunctions can be detected.

The flip-flop (FF2) in FIG. 17B is called “degradation detection FF”, and the data signal (D) and the delayed data signal are separately latched by the same clock (CLK), so that the core circuit It is possible to detect delay degradation. Although a failure or deterioration can be detected only in the fixed delay region of the data signal or the clock signal, the above-described flow can be performed by using these FFs.

The present invention is suitable for reducing the power consumption of a semiconductor device.

Next, a seventh embodiment of the present invention will be described. FIG. 18 is a diagram for explaining a seventh embodiment of the present invention. In this embodiment, a path delay distribution is created based on a result of performing path delay measurement over a plurality of cycles in the semiconductor device (LSI) having the configuration shown in each of the above embodiments.

The path delay distribution usually indicates the number of activation paths and the delay amount in one cycle of the semiconductor device. Delay information that can be acquired using the present invention is one path in one cycle. That is, for example, as shown in FIG. 1, one delay measurement circuit 4 measures the delay of one path selected by the selection circuit 3 among a plurality of input paths to a plurality of FFs. For this reason, in this embodiment, a path delay distribution in a plurality of cycles is created. If the semiconductor device includes N delay measuring circuits 4 (see FIG. 1), N paths can be measured in parallel in one cycle.

In the present embodiment, the semiconductor device extracts various feature amounts from the delay distribution information of the created path. Then, the operation of the semiconductor device (LSI) is controlled based on the extracted feature amount. As a result, the semiconductor device (LSI) can be operated in an optimum state.

The specific flow of the present embodiment will be described with reference to FIG. In the path delay measurement, which is the base data for creating the delay distribution information, the signal selection phase (S41) for selecting the FF (2 in FIG. 1) that terminates the arbitrary path of the semiconductor device is repeated to the selected FF. The delay measurement phase (S42) for measuring the delay of the input path is executed. Note that the processing of S41 to S42 shows the same processing as S21 to S26 of FIG.

Predetermined conditions such as each instruction set (instruction set of the CPU of the semiconductor device) and each fixed cycle are set for the path delay information acquired by path selection and delay measurement, and delay distribution information is created (S43).

Next, using the created delay distribution information, statistical analysis, critical path delay search, and the like are executed to extract feature values of the statistical information (S44).

The semiconductor device (LSI) is operated in an optimal state by performing control to reflect the extracted feature amount in the operation of the semiconductor device (LSI) (S45). In this embodiment, acquisition of delay distribution information, extraction of feature values, and control of operations are performed in a semiconductor device (LSI), but the present invention is not limited to such a configuration. For example, a semiconductor device (LSI) transmits path delay information acquired by an internal delay measurement circuit 4 (see FIG. 1 and the like) to another device (another semiconductor device, a controller, a tester, or the like), and the other device Of course, the delay distribution information may be acquired and the feature amount may be extracted to control the operation of the semiconductor device (LSI). The operation parameters of the semiconductor device (LSI) are set in a nonvolatile memory element (fuse, wire breakage, etc.) in the semiconductor device (LSI) or in a rewritable nonvolatile memory element. May be.

A series of these operations interferes with the actual operation of the semiconductor device (LSI) not only at the time of the shipping test after the manufacture of the semiconductor device (LSI) but also in the state where it is incorporated in the actual product after the shipment of the semiconductor device (LSI). Can be done without. Therefore, various effects such as long life operation, low power operation, and high reliability operation of the semiconductor device (LSI) can be obtained.

Next, an eighth embodiment of the present invention will be described. FIG. 19 is a diagram for explaining an eighth embodiment of the present invention. FIG. 19 shows an example of the feature amount extracted from the delay distribution information and an example of the operation of the semiconductor device (LSI). Note that steps S41, S42, and S43 in FIG. 19 are the same as the steps in FIG.

In this embodiment, from the delay distribution information created in step S43,
・ Degree of deterioration,
・ Activation rate that can be extracted from the number of measured paths,
・ Current consumption extracted from the activation rate,
-Maximum operating speed extracted from the longest path,
・ Average and variance of distribution extracted from statistical analysis
Are extracted as feature quantities.

Then, the extracted feature amount is used during LSI operation.
·Power-supply voltage,
・ Operating temperature,
・ Operating frequency,
-Optimum operation of the LSI can be realized by reflecting it in at least one of instruction scheduling and the like.

It should be noted that the feature amount to be extracted may be one deterioration amount or a plurality of deterioration amounts, for example. Further, in FIG. 19, characteristic values of deterioration, activation rate, current consumption, maximum operating speed, distribution average, and distribution dispersion are used for power supply voltage control (operating temperature, operating frequency, instruction scheduling). Although an example is shown, it goes without saying that any one feature amount may be used to control the power supply voltage.

Next, a ninth embodiment of the present invention will be described. FIG. 20 is a diagram for explaining a ninth embodiment of the present invention, and shows an example in which current consumption is extracted as the feature amount explained with reference to FIG. That is, in this embodiment, the current consumption tendency is extracted from the delay distribution information acquired in step S43 of FIG.

Specifically, for example, in an environment after shipment of a semiconductor device (LSI) product (for example, in an environment where an actual device is mounted), a plurality of consecutive instruction sequences sequentially executed by a CPU in the semiconductor device (LSI) (FIG. 20A) Corresponding to the instruction sequences B, E, A,..., Respectively, from the path delay information obtained successively by the selection circuit 3 (for example, see FIG. 1) and the delay measurement circuit 4 (for example, see FIG. 1), respectively. Delay distribution information is created (see FIG. 20B).

In addition, when there is one delay measurement circuit (for example, 4 in FIG. 1), delay information of one path is acquired in one cycle. Therefore, in this embodiment, the path delay distribution (the delay and the number of paths) in a plurality of cycles is acquired. ). In the delay distribution of FIG. 20B, the horizontal axis represents delay (time), the vertical axis represents the number of paths, and it can be seen how many paths have a certain delay (the vertical axis may represent the number of times delay information is acquired). The total number of paths in the range from the minimum to the maximum delay is the total number of paths. Note that an instruction executed by the CPU in the semiconductor device (LSI) may be given from the tester side in a test at the time of product shipment (an instruction may be given at random). Under an environment after product shipment, the instructions are executed by the CPU in the semiconductor device (LSI) in accordance with a program stored in a memory (not shown).

The total number of activation paths corresponding to each delay distribution is extracted from the delay distribution information of a plurality of paths acquired corresponding to instructions sequentially executed by the CPU in the semiconductor device (LSI) (FIG. 20C). reference). As shown in FIG. 20C, the time transition of the total number of activation paths is acquired, and the time transition (trend) of the current value is extracted.

In the delay measurement (step S42 in FIG. 19), when the selected path is activated, a delay value smaller than the system clock cycle is acquired by the delay measurement circuit (for example, 4 in FIG. 1) (see FIG. 10). When the path is not activated (when the signal does not transition to the activation level), a delay value larger than the system clock cycle can be obtained, so that the activation path can be easily determined. The number of activation paths is extracted from a plurality of pieces of delay distribution information having different times. As a result, the current consumption of the LSI can be known. This utilizes the fact that there is generally a correlation between the activation rate of the circuit and the current consumption (the current value and the number of activation paths in FIG. 20C change in time in the same phase as the time. ing).

Based on the extracted current consumption, it is possible to reflect on the operation of the semiconductor device (LSI), for example, schedule control of instructions executed in the semiconductor device (LSI) to reduce current consumption (power).

In extracting the total number of activated paths, it is possible to estimate the current consumption more accurately by extracting a value obtained by weighting the delay amount of the activated paths. For example, a delay of a path having a large load capacity is generally increased, and current consumption for charging / discharging the load with, for example, a power supply amplitude is also increased. In this case, for example, a single path having a large delay (a large load capacity) is multiplied by a weighting factor w (w> 1) corresponding to the delay amount, so that one path becomes w. You may make it extract the activation path total number according to consumption.

Next, a tenth embodiment of the present invention will be described. FIG. 21 is a diagram for explaining a tenth embodiment of the present invention. In the present embodiment, the deterioration tendency is extracted as the feature amount extracted from the delay distribution information acquired in step S43 of FIG. Specifically, with respect to an instruction that is randomly (or sequentially) executed by a CPU in the semiconductor device (LSI) in an environment (shipment environment) after the semiconductor device (LSI) is shipped, a predetermined instruction (for example, FIG. Paying attention to the instruction sequence A) of 21 (A), delay distribution information is created based on the path delay information in the instruction. When there is one delay measurement circuit (for example, 4 in FIG. 1), delay information of one path is acquired in one cycle. In this embodiment, path delay distributions in a plurality of cycles are obtained for the same instruction. create.

Next, statistical processing is performed on each of the acquired path delay distributions (delay distributions during the same operation by executing the same instruction) (see FIG. 21B). FIG. 21B shows an example of path delay distribution (horizontal axis: delay, vertical axis: number of paths).

From this delay distribution, for example, a median value, a mean value, a maximum value, a variance, a standard deviation, and the like are obtained as statistical information. At this time, since the acquired path delay distribution is a delay information distribution at the time of execution of the same instruction, the same distribution should theoretically be obtained. However, in reality, the shape of the distribution may be slightly different due to the influence of deterioration. The maximum delay corresponds to the critical path delay. The statistical information may be derived by a CPU or the like in the semiconductor device (LSI).

In this embodiment, this slight change in distribution is extracted using statistical analysis. Generally, in the case of deterioration, the delay in the entire semiconductor device (LSI) increases. For this reason, the median and standard deviation indicating the delay tendency of the entire path are plotted according to the acquired time (the median and standard deviation in FIG. 21C are time-varying). As a result, a tendency of progress of deterioration can be obtained. It should be noted that a series of processing of path delay distribution (FIG. 21B) and statistical information extraction at the same operation by executing the same instruction is performed at a predetermined time interval (for example, hourly, daily, weekly, monthly or yearly). (Any one of the units), the state (trend) of the change over time (aging) of the delay characteristics (median, standard deviation, critical path delay) as shown in FIG. Monitored. This deterioration monitoring can be performed without interfering with the actual operation of the semiconductor device (LSI) in an actual machine mounting environment after product shipment.

Note that, with respect to feature quantities other than deterioration, it is possible to monitor changes over time (aging) while the semiconductor device (LSI) is operating normally. Countermeasures for the operation of the semiconductor device (LSI) are appropriately taken corresponding to the secular change of the monitored semiconductor device (LSI).

It should be noted that the disclosures of the above patent documents are incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

Hereinafter, the contents disclosed in the present invention will be collectively described as additional notes.

Appendix 1

Multiple flip-flops,
A selection circuit that selects an input path according to a selection signal from a plurality of input paths to the plurality of flip-flops;
A delay measuring circuit for measuring a delay of a signal of an input path selected by the selection circuit;
A semiconductor device comprising:

Appendix 2

An input path to the flip-flop is branched in the vicinity of the input terminal to the flip-flop or inside the flip-flop, and is connected to an input terminal corresponding to the flip-flop among a plurality of input terminals of the selection circuit. 2. The semiconductor device according to appendix 1, wherein:

Appendix 3

The semiconductor device according to appendix 1 or 2, wherein the signal of the input path is supplied from the selection circuit to the delay measurement circuit in a time division manner.

Appendix 4

A plurality of selection elements arranged corresponding to each of the plurality of flip-flops;
The selection element selects one path from among branch paths of a plurality of input paths to the flip-flop based on a control signal input to the selection element,
The semiconductor device according to any one of appendices 1 to 3, wherein a signal of a selected path is supplied to a corresponding input terminal of the selection circuit.

Appendix 5

The selection element inputs signals of a data input path and a clock input path to the flip-flop,
The selection element time-divides a data signal and a clock signal to the flip-flop into a path between the output of the selection element and a corresponding input terminal of the selection circuit according to a control signal input to the selection element. 5. The semiconductor device according to appendix 4, wherein

Appendix 6

The selection circuit selects one of the plurality of selection elements corresponding to the plurality of flip-flops based on the selection signal, and a data signal and a clock signal from the selected one selection element are supplied to the delay measurement circuit. 6. The semiconductor device according to appendix 5, wherein the output is performed in a time division manner.

Appendix 7

Any one of Supplementary notes 4 to 6, wherein the plurality of selection elements are configured to selectively operate one of the plurality of selection elements based on a control signal input to each of the plurality of selection elements. A semiconductor device according to claim 1.

Appendix 8

The selection elements are arranged between a branch point of a path from an input path to the flip-flop to an input terminal of the selection circuit and an input terminal of the selection circuit. The semiconductor device according to any one of the above.

Appendix 9

The semiconductor device according to appendix 8, wherein the selection element is disposed in the vicinity of or inside the flip-flop.

Appendix 10

The delay measuring circuit is characterized in that the signal transition time of the data input path and the clock input path to the flip-flop is measured in a time-sharing manner, and a delay amount is calculated from a difference between the measured transition times. The semiconductor device according to any one of appendices 5 to 9.

Appendix 11

The delay measuring circuit calculates a delay amount from a difference between a delay measurement result of a valid edge of a clock signal and a delay measurement result of an edge of a data signal temporally prior to the valid edge. The semiconductor device according to appendix 10.

Appendix 12

12. The semiconductor device according to any one of appendices 1 to 11, wherein a jitter is measured by measuring a delay of the same input path among the plurality of input paths a plurality of times by the delay measurement circuit. .

Appendix 13

A plurality of processing circuits arranged corresponding to each of the plurality of flip-flops;
The processing circuit inputs respective branch paths of a plurality of input paths to the flip-flop, performs a logical operation of the plurality of input paths, and outputs a logical operation result corresponding to the flip-flop of the selection circuit 4. The semiconductor device according to claim 1, wherein the semiconductor device is supplied to a terminal.

Appendix 14

14. The semiconductor device according to appendix 13, wherein the processing circuit includes a 2-input exclusive OR circuit having a clock input and a data input as inputs.

Appendix 15

13. The semiconductor device according to any one of appendices 1 to 12, further comprising a register that holds an output value of the delay measurement circuit.

Appendix 16

The semiconductor device according to any one of appendices 1 to 15, wherein among the plurality of flip-flops, inputs of flip-flops constituting a plurality of critical paths are selected.

Addendum 17

Multiple flip-flops,
A plurality of selection elements arranged corresponding to the plurality of flip-flops, and
And the selection element inputs a data input path and a clock input path signal to the corresponding flip-flop, and time-divides the data signal and the clock signal to the flip-flop according to the input control signal. Output with
A selection circuit that selects one of the plurality of selection elements according to a selection signal;
A delay measurement circuit for measuring a delay between a data signal and a clock signal output in a time-sharing manner from the selection element selected by the selection circuit;
A semiconductor device comprising:

Addendum 18

Item 18. The supplementary note 17, wherein the selection element is disposed between a branch point of a path from an input path to the flip-flop to an input terminal of the selection circuit and an input terminal of the selection circuit. Semiconductor device.

Addendum 19

Item 19. The semiconductor device according to appendix 18, wherein the selection element is disposed in the vicinity of or inside the flip-flop.

Appendix 20

The delay measuring circuit calculates a delay amount from a difference between a delay measurement result of a valid edge of a clock signal and a delay measurement result of an edge of a data signal temporally prior to the valid edge. The semiconductor device according to appendix 17.

Appendix 21

A core circuit responsible for the main function of the semiconductor device;
A delay measuring circuit that inputs an internal signal of the core circuit and performs delay measurement;
A power supply control circuit for supplying power to the core circuit;
A storage element for storing a delay measurement result of the delay measurement circuit;
A control element that inputs a value of the storage element and outputs a control signal to the power supply control circuit;
With
The core circuit includes a plurality of flip-flops,
A selection circuit that selects an input path according to a selection signal from among a plurality of input paths to the plurality of flip-flops, provided inside or outside the core circuit,
The semiconductor device characterized in that the delay measurement circuit measures a delay of an output signal of the selection circuit.

Appendix 22

A delay variable replica circuit in which the control element has an output from the storage element as an input and a delay is set variably;
A frequency comparison circuit for comparing the frequency of the delay variable replica circuit and the clock frequency of the core circuit;
The semiconductor device according to appendix 21, characterized by comprising:

Appendix 23

23. The supplementary note 22, wherein the variable delay replica circuit is set to have the same delay characteristic as that of a critical path of the core circuit based on delay information obtained by the delay measurement circuit. Semiconductor device.

Appendix 24

An input path to the flip-flop is branched in the vicinity of the input terminal to the flip-flop or inside the flip-flop, and is connected to an input terminal corresponding to the flip-flop among a plurality of input terminals of the selection circuit. 24. The semiconductor device according to any one of appendices 21 to 23, wherein:

Appendix 25

25. The semiconductor device according to any one of appendices 21 to 24, wherein the signal of the input path is supplied from the selection circuit to the delay measurement circuit in a time division manner.

Addendum 26

Comprising a selection element arranged corresponding to each of the flip-flops;
The selection element selects one input path based on a control signal input to the selection element from among branch paths of a plurality of input paths to the flip-flop,
26. The semiconductor device according to any one of appendices 21 to 25, wherein a signal of a selected path is supplied to a corresponding input terminal of the selection circuit.

Addendum 27

The selection element inputs signals of a data input path and a clock input path to the flip-flop,
The selection element time-divides a data signal and a clock signal to the flip-flop into a path between the output of the selection element and a corresponding input terminal of the selection circuit according to a control signal input to the selection element. 27. The semiconductor device according to appendix 26, wherein

Addendum 28

The selection circuit selects one of the plurality of selection elements corresponding to the plurality of flip-flops based on the selection signal, and a data signal and a clock signal from the selected one selection element are supplied to the delay measurement circuit. 28. The semiconductor device according to appendix 27, wherein output is performed in a time division manner.

Addendum 29

29. The supplementary note 28, wherein the plurality of selection elements are configured such that one selection element of the plurality of selection elements operates alternatively based on a control signal input to each of the plurality of selection elements. Semiconductor device.

Addendum 30

The delay measuring circuit is characterized in that the signal transition time of the data input path and the clock input path to the flip-flop is measured in a time-sharing manner, and a delay amount is calculated from a difference between the measured transition times. The semiconductor device according to any one of appendices 27 to 29.

Addendum 31

The delay measuring circuit calculates a delay amount from a difference between a delay measurement result of a valid edge of a clock signal and a delay measurement result of an edge of a data signal temporally prior to the valid edge. The semiconductor device according to appendix 30.

Addendum 32

A processing circuit arranged corresponding to each of the flip-flops;
The processing circuit inputs respective branch paths of a plurality of input paths to the flip-flop, performs a logical operation of the plurality of input paths, and outputs a logical operation result corresponding to the flip-flop of the selection circuit 26. The semiconductor device according to any one of appendices 21 to 25, wherein the semiconductor device is supplied to a terminal.

Addendum 33

A delay measurement method using a semiconductor device including a plurality of flip-flops,
A selection circuit that selects and outputs one path from a plurality of input paths to the plurality of flip-flops according to a selection signal;
A delay measurement circuit measures a delay of the signal of the selected path;
A delay measuring method.

Addendum 34

A selection element arranged corresponding to the flip-flop inputs a data input path and a clock input path signal to the flip-flop,
The selection element propagates a data signal and a clock signal to the flip-flop in a time division manner in a path between the output of the selection element and the input terminal of the selection circuit according to a control signal input to the selection element. 34. The delay measuring method according to appendix 33, wherein

Addendum 35

In the semiconductor device according to any one of appendices 1 to 20,
A delay measurement method characterized in that delay distribution information is created from measured path delays.

Addendum 36

Measure the delay of a number of paths less than the total number of paths in the semiconductor device in one cycle,
36. The delay measurement method according to appendix 35, wherein the delay distribution information is created using the measured delay over a plurality of cycles.

Addendum 37

A control method, wherein a feature amount is extracted from the delay distribution information created by the delay measurement method according to attachment 35, and an operation of the semiconductor device is adjusted based on the feature amount.

Addendum 38

A control method characterized in that the number of activated paths is calculated from the delay distribution information created by the delay measurement method according to appendix 35 to obtain a change in current consumption or power consumption of the semiconductor device.

Addendum 39

A control method characterized in that at least one of an average value, a median value, and a variance is calculated from the delay distribution information created by the delay measurement method according to attachment 35, and a tendency of aging deterioration is obtained.

Appendix 40

A control method characterized in that, from the delay distribution information created by the delay measurement method according to attachment 35, the longest delay is calculated from the distribution information to obtain the maximum operating speed of the semiconductor device.

Appendix 41

Multiple flip-flops,
A selection circuit that selects an input path according to a selection signal from a plurality of input paths to the plurality of flip-flops;
A delay measuring circuit for measuring a delay of a signal of an input path selected by the selection circuit;
With
A semiconductor device characterized in that path delay distribution information is created from the delay measured by the delay measuring circuit.

Appendix 42

42. The semiconductor device according to appendix 41, wherein a feature amount is extracted from the delay distribution information, and an operation of the semiconductor device is adjusted based on the feature amount.

1 logic circuit 2 FF
3 Selection circuit (selector)
4 Delay measurement circuit 5 Delay measurement FF
6 Control element 7 Selection element (multiplexer)
8 processing circuit 10 core circuit 11 data processing circuit 12 delay element 21 setting storage element 22 control element 23, 31 power supply control circuit 32 frequency comparison circuit 33 variable delay replica circuit 34 setting register 41 delay element 42 flip-flop 43 data processing circuit

Claims (14)

1. Multiple flip-flops,
   A selection circuit that selects an input path from a plurality of input paths to the plurality of flip-flops according to an input selection signal;
   A delay measuring circuit for measuring a delay of a signal of an input path selected by the selection circuit;
   A semiconductor device comprising:
2. The input path to the flip-flop is branched in the vicinity of the input terminal to the flip-flop or inside the flip-flop and connected to the corresponding input terminal of the selection circuit. Semiconductor device.
3. 3. The semiconductor device according to claim 1, wherein the signal of the input path is supplied from the selection circuit to the delay measurement circuit in a time division manner.
4. A plurality of selection elements arranged corresponding to each of the plurality of flip-flops;
   The selection element selects one path from among branch paths of a plurality of input paths to the flip-flop based on a control signal input to the selection element,
   4. The semiconductor device according to claim 1, wherein a signal of a selected path is supplied to a corresponding input terminal of the selection circuit. 5.
5. The selection element inputs signals of a data input path and a clock input path to the flip-flop,
   The selection element time-divides a data signal and a clock signal to the flip-flop into a path between the output of the selection element and a corresponding input terminal of the selection circuit according to a control signal input to the selection element. 5. The semiconductor device according to claim 4, wherein
6. The selection circuit selects one of the plurality of selection elements respectively corresponding to the plurality of flip-flops based on the selection signal, and the delay measurement circuit receives a data signal and a clock signal from the selected one selection element. 6. The semiconductor device according to claim 5, wherein output is performed in a time division manner.
7. The plurality of selection elements are configured to selectively operate one of the plurality of selection elements based on a control signal input to each of the plurality of selection elements. The semiconductor device according to any one of the above.
8. The selection element is disposed between a branch point of a path from an input path to the flip-flop to an input terminal of the selection circuit and an input terminal of the selection circuit. 8. The semiconductor device according to any one of 7 above.
9. The semiconductor device according to claim 8, wherein the selection element is disposed in the vicinity of or inside the flip-flop.
10. The delay measuring circuit is characterized in that the signal transition time of the data input path and the clock input path to the flip-flop is measured in a time-sharing manner, and a delay amount is calculated from a difference between the measured transition times. The semiconductor device according to claim 5.
11. The delay measuring circuit calculates a delay amount from a difference between a delay measurement result of a valid edge of a clock signal and a delay measurement result of an edge of a data signal temporally prior to the valid edge. The semiconductor device according to claim 10.
12. The jitter is measured by measuring the delay of the same input path among the plurality of input paths a plurality of times by the delay measuring circuit. Semiconductor device.
13. 13. The semiconductor device according to claim 1, wherein inputs of flip-flops constituting a plurality of critical paths are selected from the plurality of flip-flops.
14. 2. The semiconductor device according to claim 1, wherein path delay distribution information is created from the delay measured by the delay measuring circuit.

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