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JP4649792B2 - Semiconductor device - Google Patents

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JP4649792B2
JP4649792B2 JP2001220396A JP2001220396A JP4649792B2 JP 4649792 B2 JP4649792 B2 JP 4649792B2 JP 2001220396 A JP2001220396 A JP 2001220396A JP 2001220396 A JP2001220396 A JP 2001220396A JP 4649792 B2 JP4649792 B2 JP 4649792B2
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lsi chip
wafer
semiconductor device
layer
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JP2003031768A (en
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宏治 古澤
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NEC Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73217—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体装置に関し、特に、ウェハの状態での半導体チップのパッケージ化に適用される半導体装置に関する。
【０００２】
【従来の技術】
従来、半導体装置およびその製造方法は、例えば、半導体装置の１つであるウェハレベルＣＳＰ（Chip Size Package/以下、ＷＬ−ＣＳＰ）へ適用される。ＷＬ−ＣＳＰは、ＬＳＩチップ周辺部に配置されたアルミパッドから、再配線技術を用いて外部端子をＬＳＩチップ表面にエリア状に転換して樹脂封止をすることで、ウェハの状態でパッケージング工程を完了する半導体装置である。
【０００３】
端子の再配線技術には、大きく分けて２種類の方法がある。１つは、再配線をウェハプロセス技術と同じ蒸着・フォトリソグラフィ技術を用いて行う方法である。
【０００４】
図５のように、ウェハプロセスでアルミ配線保護のための窒化膜３１１が形成されたウェハ３１０上に、層間絶縁、ストレスバッファ等の役割をする有機膜層３１２を形成する。ただし、ＬＳＩ上でアルミパッド３１３上の有機膜層３１２は、フォトリソグラフィにより除去される。次に、再配線パターンとしてスパッタ方式などでメタル膜３１４を形成する。それに続き、外部端子の再配置位置に電解めっきでＣｕポスト３１５を形成する。次には樹脂封止で、ウェハ全面に薄い樹脂封止層３４１を形成し、最後に、電解めっきされたＣｕポスト３１５上にはんだボール３４０を供給した後、テスト、分割、梱包を行い、出荷となる。
【０００５】
また、Ｃｕポスト３１５を形成せずにメタル層上に再度有機膜層を形成し、外部端子の再配置位置にフォトリソグラフィを施してメタル層へのコンタクトホールを形成し、そこへ直接はんだボールを供給する方法もある。もう１つの方法は、あらかじめ再配線パターンが形成されたインタポーザを用いる方法である。
【０００６】
図６のように、薄いポリイミド等の有機フィルム３５６上に数十μｍ厚の再配線パターン３５５が形成されており、それを接着剤３５７で窒化膜３５１が形成されたＬＳＩチップ３５０に固着する。インタポーザとＬＳＩチップ上のアルミパッド部３５３との接続は、ワイヤボンド３５８で接続する方法と、シングルポイントボンディングで接続する方法とがある。その後、露出しているボンディング部分を封止樹脂３７１で封止し、はんだボール３７０を供給し、テスト、分割、梱包を行い、出荷となる。
【０００７】
このようにして作られたＷＬ−ＣＳＰの利点としては、ＬＳＩチップと全く同一のパッケージサイズを得ることができる点にある。他のＱＦＰ（quad flat package/クワッドフラットパッケージ）やＢＧＡ（ball grid array/ボールグリッドアレイ）等のように、チップ周辺部のボンディグパッドからリードフレームあるいは基板にワイヤボンディングするエリアが不必要になる。このため、高密度実装が可能となる。
【０００８】
その一方、パッケージ内部に複数のＬＳＩチップを積層することで、高密度実装を可能とするスタックＣＳＰ（Stack Chip Size Package）という半導体装置がある。このスタックＣＳＰにおけるＬＳＩのアルミパッド部とインタポーザとの接続方法には各種あるが、ＬＳＩチップ内部にあらかじめ貫通ビアを形成しておく方法以外は、ワイヤボンドによる接続が必要になる。
【０００９】
従って、ワイヤボンドを使用するスタックＣＳＰのパッケージサイズは、ＷＬ−ＣＳＰのように、ＬＳＩチップと同一サイズにはならない。また、ＬＳＩチップ内部にあらかじめ貫通ビアを形成しておく方法であれば、スタックＣＳＰにおいてもＬＳＩチップと同一のパッケージサイズを得られることになる。
【００１０】
本発明と技術分野の類似する先願発明例１として、特開２０００−２４３７２９号公報の「半導体装置の製造方法」がある。本先願発明例１では、ウェハレベルＣＳＰの製造において、樹脂封止の信頼性を向上させることを課題としている。
【００１１】
先願発明例２の特開２０００−１８８３５２号公報の「チップ・サイズ・パッケージおよびその製造方法」は、感光性絶縁材料を利用して、ウェハプロセス工程（前工程）のみで樹脂封止可能な、ウェハレベルのＣＳＰ技術を開示している。
【００１２】
先願発明例３の特開２０００−２３５９７９号公報の「半導体装置」は、回路素子形成領域上に第１の絶縁膜を介して設けられたバリア層上に第２の絶縁膜を介して再配線や薄膜回路素子を設けている。このバリア層により、クロストークが発生しないようにすることができ、ひいては再配線や薄膜回路素子の配置に制約を受けないようにすることができる、としている。
【００１３】
先願発明例４の特開平０６−２８３６６１号公報の「マルチチップモジュールの構造」は、基板層の上部に配線層を構成し、この配線層の上部に切り替えユニットおよびプロセッサユニットを構成し、信頼性が高く、かつ安価なマルチチップモジュールを提供することを可能としている。
【００１４】
【発明が解決しようとする課題】
しかしながら、上記従来技術では、使用されるＬＳＩチップには内部に貫通ビアを設けるなどして、スタックＣＳＰ専用に設計、製造する必要がある。これは、複数のＬＳＩチップの機能を再設計して１つのチップに集積する方法と比べて、開発に必要な費用や時間、積層するＬＳＩチップの組合せの自由度など、スタックＣＳＰが有利とされている点を損なうことになるという問題点を伴う。
【００１５】
【課題を解決するための手段】
本発明は、経費および時間を削減し、積層するＬＳＩチップの自由度を向上させた半導体装置を提供することを目的とする。
【００１６】
【課題を解決するための手段】
かかる目的を達成するため、請求項１記載の半導体装置は、ウェハレベルＣＳＰであるＷＬ−ＣＳＰへ適用される半導体装置であり、再配線パターンが形成された有機フィルムが固着された第１のＷＬ−ＣＳＰ上に、再配線パターンが形成された有機フィルムが固着された第２のＷＬ−ＣＳＰを、各再配線パターンが同一方向を向くように配置し、ＷＬ−ＣＳＰと同等のチップサイズのスタックＣＳＰの構成を可能とし、第１のＷＬ−ＣＳＰの有機フィルムは所定領域に穴が形成され、穴の領域における第１のＷＬ−ＣＳＰ上に第２のＷＬ−ＣＳＰが接着されていることを特徴としている。
【００２５】
【発明の実施の形態】
次に、添付図面を参照して本発明による半導体装置およびその製造方法の実施形態を詳細に説明する。図１から図４を参照すると、本発明の半導体装置およびその製造方法の一実施形態が示されている。
【００２６】
（第１の実施例）
図１に、本発明を適用した半導体装置の構成例を示す。
図１に示す半導体装置は、第一のＬＳＩチップ１０、窒化膜１１、有機膜層１２、アルミパッド１３、メタル層１４、Ｃｕポスト１５、接着層１６、第二のＬＳＩチップ２０、窒化膜２１、有機膜層２２、アルミパッド２３、メタル層２４、Ｃｕポスト２５、はんだボール４０、封止樹脂４１、を有して構成される。
【００２７】
この半導体装置には、第一のＬＳＩチップ１０と第二のＬＳＩチップ２０との２つのＬＳＩチップが積層されている。
【００２８】
第一のＬＳＩチップ１０のアルミ配線を保護する窒化膜１１の上に、感光性絶縁材料の有機膜層１２が形成されている。この有機膜層１２は、後で再配線層としてメタル層１４を積層した際の層間絶縁の働きと、基板実装後に外部から加わるストレスを緩和する働きとを持つ。また、第一のＬＳＩチップ１０の電極であるアルミパッド１３上の有機膜層１２は、フォトリソグラフィにより除去され、有機膜層１２に積層されるメタル層１４との接続のためのコンタクトホールが形成されている。
【００２９】
有機膜層１２の上には、スパッタ方式によりメタル層１４が形成されている。
このメタル層１４は、第一のＬＳＩチップ１０の電極の再配置を目的としたものであり、コンタクトホールで第一のＬＳＩチップ１０のアルミパッド１３と接続し、第一のＬＳＩチップ１０の電極が所望の位置に再配置されるようにパターン化されている。メタル層１４により再配置された電極位置には、電解めっきでＣｕポスト１５がそれぞれ形成されている。
【００３０】
また、第一のＬＳＩチップ１０の中央部には、接着層１６を介して第二のＬＳＩチップ２０が接着されている。第二のＬＳＩチップ２０も第一のＬＳＩチップ１０と同様に、窒化膜２１上に有機膜層２２とメタル層２４とにより電極位置が再配置され、アルミパッド２３からメタル層２４により再配置された電極位置には、Ｃｕポスト２５が形成されている。
【００３１】
なお、第一のＬＳＩチップ１０と第二のＬＳＩチップ２０とのそれぞれのＣｕポスト１５、２５の先端が同一の高さになるように、第一のＬＳＩチップ１０および第二のＬＳＩチップ２０のそれぞれの有機膜層１２、２２、メタル層１４、２４、Ｃｕポスト１５、２５の高さは、あらかじめ調整されている。
【００３２】
Ｃｕポスト１５、２５の先端には、実装基板との接続用にはんだボール４０が供給されている。またＣｕポスト１５、２５のすき間やメタル層１４、メタル層２４の段差等を埋めるようにして、封止樹脂４１が充填されている。
【００３３】
図２を用いて、本実施例における半導体装置の製造方法を示す。
（ａ）第一のＬＳＩチップを含むウェハ１１０に、アルミパッド１１２を含むアルミ配線を保護するために、表面に窒化膜１１１を形成する。
【００３４】
（ｂ）アルミ配線保護のための窒化膜処理が完了した第一のＬＳＩチップのウェハ１１０上に、感光性絶縁材料層１１３を形成する。次に第一のＬＳＩチップのアルミパッド部へフォトリソグラフィを施して絶縁材料層を除去し、コンタクトホールを形成する。更に再配線パターンとしてスパッタ方式でメタル膜１１４を形成する。
【００３５】
（ｃ）電解めっきで第一のＬＳＩチップの外部端子の位置に、Ｃｕポスト１１５を形成する。この時、Ｃｕポスト１１５の高さは、後で第二のＬＳＩチップ１１６をスタック積層した際に、これのＣｕポストと同一高さになるように決める。
【００３６】
（ｄ）第二のＬＳＩチップのウェハは、スタック積層時のチップ接着のため、あらかじめウェハ裏面に接着フィルムを貼付し、同じように再配線とＣｕポストの形成とまで行う。第二のＬＳＩチップのウェハは、この後ダイシングにより個片化される。個片化された第二のＬＳＩチップ１１６を、先の第一のＬＳＩチップのウェハ１１０の各チップ部位にそれぞれスタック積層して接着する。
【００３７】
（ｅ）ウェハ全面に樹脂封止層１１７を形成する。次に第一のＬＳＩチップおよび第二のＬＳＩチップのポスト上に、はんだボール１１８を供給して、テストを行う。
（ｆ）ダイシングにより第一のＬＳＩチップのウェハ１１０を個片化する。
（ｇ）完成状態となる。
【００３８】
すなわち、図２は、ＬＳＩチップ周辺部のアルミパッドから、再配線技術を用いて外部端子をＬＳＩチップ表面にエリア状に転換して樹脂封止をすることで、ウェハの状態でパッケージング工程を完了させ、完成状態のウェハレベルＣＳＰとする方法を示す。
【００３９】
上記の実施例によれば、ウェハ上に別のＷＬ−ＣＳＰを接着することで、ＷＬ−ＣＳＰと同等サイズのスタックＣＳＰを実現し、ＬＳＩの実装密度を向上させたＷＬ−ＣＳＰが得られる。これにより、ＷＬ−ＣＳＰと同一サイズのスタックＣＳＰの製造が可能となる。
【００４０】
（第２の実施例）
図３に、本発明による半導体装置の別の構成例を示す。
第２の実施例では、第一のＬＳＩチップ５０および第二のＬＳＩチップ６０の再配線層として、感光性絶縁材料による有機膜層とメタル層の代わりに、あらかじめ再配線パターンが形成された有機フィルムを使用する。
【００４１】
第一のＬＳＩチップ５０のアルミ配線を保護する窒化膜５１の上に、あらかじめ再配線パターン５５が形成されたポリイミドフィルム５６が接着剤５７で固着されている。ポリイミドフィルム５６の再配線パターン５５と第一のＬＳＩチップ５０のアルミパッド５３との接続は、ワイヤボンディング５８により接続されている。第二のＬＳＩチップ６０も同様に、再配線パターン６５が形成されたポリイミドフィルム６６が接着剤６７で固着され、再配線パターン６５とアルミパッド６３がワイヤボンディング６８により接続され、端子が再配置されている。
【００４２】
また、第一のＬＳＩチップ５０のポリイミドフィルム５６には、中央に穴があらかじめ空いており、ポリイミドフィルム６６を固着した第二のＬＳＩチップ６０が、接着層６９により固着されている。ポリイミドフィルムによる再配置された各端子には、はんだボール７０が供給されている。第一のＬＳＩチップ５０および第二のＬＳＩチップ６０の露出しているワイヤボンディング部は封止樹脂７１により保護されている。
【００４３】
図４に、第２の実施例における半導体装置の製造方法を示す。
（ａ）第一のＬＳＩチップを含むウェハ２１０に、アルミパッド２１２を含むアルミ配線を保護するために、表面に窒化膜２１１を形成する。
（ｂ）アルミ配線保護のための窒化膜処理が完了した第一のＬＳＩチップのウェハ２１０上に、再配線パターンが形成されたポリイミドフィルム２１３を接着する。
（ｃ）ポリイミドフィルム２１３の再配線パターンとウェハ２１０のアルミパッド２１２とをワイヤボンディング２１４で接続する。
【００４４】
（ｄ）第二のＬＳＩチップのウェハに、スタック積層時のチップ接着のため、あらかじめウェハ裏面に接着フィルムを貼付し、同じように再配線パターンが形成されたポリイミドフィルムを接着し、ワイヤボンディングによりアルミパッドと再配線パターンとを接続し、ダイシングにより個片化する。個片化された第二のＬＳＩチップ２１５を、先の第一のＬＳＩチップのウェハ２１０のポリイミドフィルム２１３のあらかじめ空いている穴に接着する。
【００４５】
（ｅ）露出しているワイヤボンディング部に、封止樹脂２１６を塗布して保護する。次に、第一のＬＳＩチップおよび第二のＬＳＩチップの再配線パターン上に、はんだボール２１７を供給してテストを行う。
（ｆ）ダイシングにより、第一のＬＳＩチップのウェハ２１０を個片化する。
（ｇ）完成状態となる。
【００４６】
なお、上述の実施形態は本発明の好適な実施の一例である。ただし、これに限定されるものではなく、本発明の要旨を逸脱しない範囲内において種々変形実施が可能である。
【００４７】
【発明の効果】
以上の説明より明らかなように、本発明による半導体装置は、ウェハ上において第一のＷＬ−ＣＳＰと第二のＷＬ−ＣＳＰとを相互に接着させてウェハレベルＣＳＰ（ＷＬ−ＣＳＰ）へ適用し、ＷＬ−ＣＳＰと同等のチップサイズのスタックＣＳＰの構成を可能としている。これにより、経費および時間を削減し、積層するＬＳＩチップの自由度を向上させることができる。
【図面の簡単な説明】
【図１】本発明による半導体装置の実施形態を示す半導体装置の断面図である。
【図２】本発明による半導体装置の製造方法の実施形態の手順例を示す図である。
【図３】本発明による半導体装置の他の実施例を示す断面図である。
【図４】本発明による半導体装置の製造方法の他の手順例を示す図である。
【図５】従来の半導体装置の第一の構造例を示す断面図である。
【図６】従来の半導体装置の第二の構造例を示す断面図である。
【符号の説明】
１０、５０ 第一のＬＳＩチップ
１１、２１、５１、１１１、２１１ 窒化膜
１２、２２ 有機膜層
１３、２３、５３、６３、１１２、２１２ アルミパッド
１４、２４ メタル層
１５、２５、１１５ Ｃｕポスト
１６、６９ 接着層
２０、６０、１１６、２１５ 第二のＬＳＩチップ
４０、７０、１１８、２１７ はんだボール
４１、７１、２１６ 封止樹脂
５５、６５ 再配線パターン
５６、６６、２１３ ポリイミドフィルム
５７、６７ 接着剤
５８、６８、２１４ ワイヤボンディング
１１０、２１０ ウェハ
１１３ 感光性絶縁材料層
１１４ メタル膜
１１７ 樹脂封止層[0001]
BACKGROUND OF THE INVENTION
The present invention relates to semiconductor equipment, in particular, relates to a semiconductor equipment to be applied to the packaging of semiconductor chips in a state of the wafer.
[0002]
[Prior art]
Conventionally, a semiconductor device and a manufacturing method thereof are applied to, for example, a wafer level CSP (Chip Size Package / hereinafter, WL-CSP) which is one of semiconductor devices. WL-CSP is packaged in the wafer state by converting the external terminals into an area on the LSI chip surface from the aluminum pads arranged around the LSI chip using resin re-wiring technology and sealing the resin. A semiconductor device that completes a process.
[0003]
There are roughly two types of terminal redistribution techniques. One is a method of performing rewiring by using the same vapor deposition / photolithography technique as the wafer process technique.
[0004]
As shown in FIG. 5, an organic film layer 312 serving as an interlayer insulation, a stress buffer, or the like is formed on a wafer 310 on which a nitride film 311 for protecting aluminum wiring is formed in a wafer process. However, the organic film layer 312 on the aluminum pad 313 on the LSI is removed by photolithography. Next, a metal film 314 is formed as a rewiring pattern by a sputtering method or the like. Subsequently, Cu posts 315 are formed by electrolytic plating at the rearrangement positions of the external terminals. Next, by resin sealing, a thin resin sealing layer 341 is formed on the entire surface of the wafer. Finally, after supplying the solder balls 340 onto the electrolytically plated Cu posts 315, testing, dividing, packing are performed, and the shipment is performed. It becomes.
[0005]
Also, the organic film layer is formed again on the metal layer without forming the Cu post 315, and photolithography is performed at the rearrangement position of the external terminal to form a contact hole to the metal layer, and the solder ball is directly applied to the metal layer. There is also a method of supplying. Another method is a method using an interposer in which a rewiring pattern is formed in advance.
[0006]
As shown in FIG. 6, a rewiring pattern 355 having a thickness of several tens of μm is formed on an organic film 356 made of thin polyimide or the like, and is fixed to an LSI chip 350 on which a nitride film 351 is formed with an adhesive 357. Connection between the interposer and the aluminum pad 353 on the LSI chip includes a connection method using a wire bond 358 and a connection method using single point bonding. After that, the exposed bonding portion is sealed with a sealing resin 371, the solder balls 370 are supplied, tested, divided, packed, and shipped.
[0007]
The advantage of the WL-CSP produced in this way is that it is possible to obtain the exact same package size as the LSI chip. Like other QFP (quad flat package) and BGA (ball grid array), an area for wire bonding from the bonding pad on the periphery of the chip to the lead frame or substrate becomes unnecessary. . For this reason, high-density mounting is possible.
[0008]
On the other hand, there is a semiconductor device called a stack CSP (Stack Chip Size Package) that enables high-density mounting by stacking a plurality of LSI chips inside a package. There are various methods for connecting the LSI aluminum pad portion and interposer in the stack CSP, but connection by wire bonding is required except for a method of forming a through via in the LSI chip in advance.
[0009]
Therefore, the package size of the stack CSP using the wire bond is not the same size as the LSI chip like the WL-CSP. Further, if the through via is formed in advance in the LSI chip, the same package size as that of the LSI chip can be obtained in the stack CSP.
[0010]
Japanese Patent Application Laid-Open No. 2000-243729 discloses a “semiconductor device manufacturing method” as a first invention example 1 in the technical field similar to the present invention. In Invention Example 1 of the prior application, an object is to improve the reliability of resin sealing in the production of a wafer level CSP.
[0011]
The "chip size package and manufacturing method thereof" disclosed in Japanese Patent Application Laid-Open No. 2000-188352 of Invention Example 2 of the prior application can be sealed with a resin only in a wafer process step (previous step) using a photosensitive insulating material. Discloses a wafer level CSP technology.
[0012]
The “semiconductor device” disclosed in Japanese Patent Application Laid-Open No. 2000-235799 of Invention Example 3 of the prior application is re-transmitted via a second insulating film on a barrier layer provided via a first insulating film on a circuit element formation region. Wiring and thin film circuit elements are provided. With this barrier layer, crosstalk can be prevented, and as a result, rewiring and arrangement of thin film circuit elements can be prevented from being restricted.
[0013]
Japanese Patent Application Laid-Open No. 06-283661 of Prior Invention Example 4 discloses a structure of a multi-chip module in which a wiring layer is formed above a substrate layer and a switching unit and a processor unit are formed above the wiring layer. It is possible to provide a multi-chip module that is highly reliable and inexpensive.
[0014]
[Problems to be solved by the invention]
However, in the above prior art, it is necessary to design and manufacture exclusively for the stack CSP by providing a through via inside the LSI chip to be used. This is because the stack CSP is advantageous compared to the method of redesigning the functions of a plurality of LSI chips and integrating them into one chip, such as the cost and time required for development, and the freedom of combination of stacked LSI chips. It is accompanied by the problem that it will damage the point.
[0015]
[Means for Solving the Problems]
The present invention is to reduce costs and time, and an object thereof is to provide a semiconductor equipment with an improved degree of freedom in LSI chips to be stacked.
[0016]
[Means for Solving the Problems]
In order to achieve this object, the semiconductor device according to claim 1 is a semiconductor device applied to a WL-CSP which is a wafer level CSP, and a first WL to which an organic film on which a rewiring pattern is formed is fixed. -A second WL-CSP having an organic film on which a rewiring pattern is formed is fixed on the CSP so that each rewiring pattern faces the same direction, and a stack having a chip size equivalent to that of the WL-CSP. It is possible to configure the CSP, and the organic film of the first WL-CSP has a hole formed in a predetermined region, and the second WL-CSP is adhered on the first WL-CSP in the region of the hole. It is a feature.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of a semiconductor device and a manufacturing method thereof according to the present invention will be described in detail with reference to the accompanying drawings. 1 to 4 show an embodiment of a semiconductor device and a method for manufacturing the same according to the present invention.
[0026]
(First embodiment)
FIG. 1 shows a configuration example of a semiconductor device to which the present invention is applied.
1 includes a first LSI chip 10, a nitride film 11, an organic film layer 12, an aluminum pad 13, a metal layer 14, a Cu post 15, an adhesive layer 16, a second LSI chip 20, and a nitride film 21. , An organic film layer 22, an aluminum pad 23, a metal layer 24, a Cu post 25, a solder ball 40, and a sealing resin 41.
[0027]
In this semiconductor device, two LSI chips of a first LSI chip 10 and a second LSI chip 20 are stacked.
[0028]
An organic film layer 12 of a photosensitive insulating material is formed on the nitride film 11 that protects the aluminum wiring of the first LSI chip 10. The organic film layer 12 has a function of interlayer insulation when the metal layer 14 is laminated as a rewiring layer later, and a function of alleviating stress applied from the outside after mounting on the substrate. Further, the organic film layer 12 on the aluminum pad 13 which is an electrode of the first LSI chip 10 is removed by photolithography, and a contact hole for connection with the metal layer 14 laminated on the organic film layer 12 is formed. Has been.
[0029]
A metal layer 14 is formed on the organic film layer 12 by sputtering.
The metal layer 14 is intended for rearrangement of the electrodes of the first LSI chip 10, and is connected to the aluminum pad 13 of the first LSI chip 10 through a contact hole. Are patterned so as to be rearranged at a desired position. Cu posts 15 are respectively formed by electrolytic plating at electrode positions rearranged by the metal layer 14.
[0030]
The second LSI chip 20 is bonded to the central portion of the first LSI chip 10 via the adhesive layer 16. Similarly to the first LSI chip 10, the second LSI chip 20 is rearranged on the nitride film 21 by the organic film layer 22 and the metal layer 24, and is rearranged by the metal layer 24 from the aluminum pad 23. Cu posts 25 are formed at the electrode positions.
[0031]
The first LSI chip 10 and the second LSI chip 20 have the same height so that the tips of the Cu posts 15 and 25 of the first LSI chip 10 and the second LSI chip 20 have the same height. The heights of the organic film layers 12 and 22, the metal layers 14 and 24, and the Cu posts 15 and 25 are adjusted in advance.
[0032]
Solder balls 40 are supplied to the tips of the Cu posts 15 and 25 for connection to the mounting substrate. Further, the sealing resin 41 is filled so as to fill the gaps between the Cu posts 15 and 25 and the steps of the metal layer 14 and the metal layer 24.
[0033]
A method for manufacturing a semiconductor device according to this embodiment will be described with reference to FIG.
(A) A nitride film 111 is formed on the surface of the wafer 110 including the first LSI chip in order to protect the aluminum wiring including the aluminum pad 112.
[0034]
(B) A photosensitive insulating material layer 113 is formed on the wafer 110 of the first LSI chip on which the nitride film treatment for protecting the aluminum wiring has been completed. Next, photolithography is performed on the aluminum pad portion of the first LSI chip to remove the insulating material layer, and a contact hole is formed. Further, a metal film 114 is formed by sputtering as a rewiring pattern.
[0035]
(C) Cu posts 115 are formed at the positions of the external terminals of the first LSI chip by electrolytic plating. At this time, the height of the Cu post 115 is determined to be the same height as the Cu post when the second LSI chip 116 is stacked and stacked later.
[0036]
(D) For the wafer of the second LSI chip, an adhesive film is pasted on the back surface of the wafer in advance for chip bonding at the time of stack stacking, and the same process up to rewiring and Cu post formation is performed. Thereafter, the wafer of the second LSI chip is separated into pieces by dicing. The separated second LSI chip 116 is stacked and bonded to each chip portion of the wafer 110 of the first LSI chip.
[0037]
(E) A resin sealing layer 117 is formed on the entire surface of the wafer. Next, a test is performed by supplying solder balls 118 onto the posts of the first LSI chip and the second LSI chip.
(F) The wafer 110 of the first LSI chip is separated into pieces by dicing.
(G) Completed state.
[0038]
That is, FIG. 2 shows the packaging process in the wafer state by converting the external terminals from the aluminum pad around the LSI chip into an area shape on the LSI chip surface using a redistribution technique and sealing the resin. A method of completing the wafer level CSP in a completed state will be described.
[0039]
According to the above embodiment, by adhering another WL-CSP on the wafer, a stack CSP having the same size as the WL-CSP can be realized, and a WL-CSP with improved LSI packaging density can be obtained. Thereby, it is possible to manufacture a stack CSP having the same size as the WL-CSP.
[0040]
(Second embodiment)
FIG. 3 shows another configuration example of the semiconductor device according to the present invention.
In the second embodiment, as the rewiring layer of the first LSI chip 50 and the second LSI chip 60, an organic layer in which a rewiring pattern is formed in advance instead of the organic film layer and the metal layer made of a photosensitive insulating material. Use film.
[0041]
On the nitride film 51 that protects the aluminum wiring of the first LSI chip 50, a polyimide film 56 on which a rewiring pattern 55 is formed in advance is fixed with an adhesive 57. The rewiring pattern 55 of the polyimide film 56 and the aluminum pad 53 of the first LSI chip 50 are connected by wire bonding 58. Similarly, in the second LSI chip 60, the polyimide film 66 on which the rewiring pattern 65 is formed is fixed with an adhesive 67, the rewiring pattern 65 and the aluminum pad 63 are connected by wire bonding 68, and the terminals are rearranged. ing.
[0042]
The polyimide film 56 of the first LSI chip 50 has a hole in the center in advance, and the second LSI chip 60 to which the polyimide film 66 is fixed is fixed by an adhesive layer 69. Solder balls 70 are supplied to the terminals rearranged by the polyimide film. The exposed wire bonding portions of the first LSI chip 50 and the second LSI chip 60 are protected by a sealing resin 71.
[0043]
FIG. 4 shows a method for manufacturing a semiconductor device according to the second embodiment.
(A) A nitride film 211 is formed on the surface of the wafer 210 including the first LSI chip in order to protect the aluminum wiring including the aluminum pad 212.
(B) A polyimide film 213 on which a rewiring pattern is formed is bonded onto the wafer 210 of the first LSI chip on which the nitride film treatment for protecting the aluminum wiring has been completed.
(C) The rewiring pattern of the polyimide film 213 and the aluminum pad 212 of the wafer 210 are connected by wire bonding 214.
[0044]
(D) Adhering an adhesive film to the back of the wafer in advance for bonding the stack when stacking the chips to the wafer of the second LSI chip, and then bonding the polyimide film on which the rewiring pattern was formed in the same way, by wire bonding The aluminum pad and the rewiring pattern are connected and separated into pieces by dicing. The separated second LSI chip 215 is bonded to a previously open hole in the polyimide film 213 of the wafer 210 of the first LSI chip.
[0045]
(E) A sealing resin 216 is applied to the exposed wire bonding portion to protect it. Next, a test is performed by supplying solder balls 217 on the rewiring patterns of the first LSI chip and the second LSI chip.
(F) The wafer 210 of the first LSI chip is separated into pieces by dicing.
(G) Completed state.
[0046]
The above-described embodiment is an example of a preferred embodiment of the present invention. However, the present invention is not limited to this, and various modifications can be made without departing from the scope of the present invention.
[0047]
【The invention's effect】
As apparent from the above description, a semiconductor equipment according to the invention, applied a first WL-CSP and a second WL-CSP adhered to each other on the wafer to a wafer level CSP (WL-CSP) In addition, a stack CSP having a chip size equivalent to that of the WL-CSP can be configured. Thereby, cost and time can be reduced, and the degree of freedom of the LSI chips to be stacked can be improved.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a semiconductor device showing an embodiment of a semiconductor device according to the present invention.
FIG. 2 is a diagram showing a procedure example of an embodiment of a semiconductor device manufacturing method according to the present invention;
FIG. 3 is a sectional view showing another embodiment of the semiconductor device according to the present invention.
FIG. 4 is a diagram showing another example of the procedure for manufacturing the semiconductor device according to the present invention.
FIG. 5 is a cross-sectional view showing a first structural example of a conventional semiconductor device.
FIG. 6 is a cross-sectional view showing a second structure example of a conventional semiconductor device.
[Explanation of symbols]
10, 50 First LSI chip 11, 21, 51, 111, 211 Nitride film 12, 22 Organic film layer 13, 23, 53, 63, 112, 212 Aluminum pad 14, 24 Metal layer 15, 25, 115 Cu post 16, 69 Adhesive layer 20, 60, 116, 215 Second LSI chip 40, 70, 118, 217 Solder ball 41, 71, 216 Sealing resin 55, 65 Rewiring pattern 56, 66, 213 Polyimide film 57, 67 Adhesives 58, 68, 214 Wire bonding 110, 210 Wafer 113 Photosensitive insulating material layer 114 Metal film 117 Resin sealing layer

Claims (1)

ウェハレベルＣＰＳであるＷＬ−ＣＳＰへ適用される半導体装置であり、
再配線パターンが形成された有機フィルムが固着された第１のＷＬ−ＣＳＰ上に、再配線パターンが形成された有機フィルムが固着された第２のＷＬ−ＣＳＰを、各再配線パターンが同一方向を向くように配置し、
ＷＬ−ＣＳＰと同等のチップサイズのスタックＣＳＰの構成を可能とし、
前記第１のＷＬ−ＣＳＰの前記有機フィルムは所定領域に穴が形成され、前記穴の領域における前記第１のＷＬ−ＣＳＰ上に前記第２のＷＬ−ＣＳＰが接着されていることを特徴とする半導体装置。It is a semiconductor device applied to WL-CSP which is a wafer level CPS,
The second WL-CSP to which the organic film on which the rewiring pattern is formed is fixed on the first WL-CSP to which the organic film on which the rewiring pattern is formed is fixed. Place it facing the
Enables the configuration of a stack CSP having the same chip size as the WL-CSP ,
The organic film of the first WL-CSP has a hole formed in a predetermined region, and the second WL-CSP is bonded onto the first WL-CSP in the region of the hole. Semiconductor device.
JP2001220396A 2001-07-19 2001-07-19 Semiconductor device Expired - Fee Related JP4649792B2 (en)

Priority Applications (1)

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JP2001220396A JP4649792B2 (en) 2001-07-19 2001-07-19 Semiconductor device

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JP4851794B2 (en) 2006-01-10 2012-01-11 カシオ計算機株式会社 Semiconductor device
JP5337404B2 (en) 2008-05-21 2013-11-06 ローム株式会社 Semiconductor device and manufacturing method of semiconductor device
JP5165006B2 (en) * 2010-01-25 2013-03-21 株式会社テラミクロス Manufacturing method of semiconductor device
JP2012099648A (en) * 2010-11-02 2012-05-24 Fujitsu Semiconductor Ltd Semiconductor device, and method of manufacturing the same
GB2485830A (en) * 2010-11-26 2012-05-30 Cambridge Silicon Radio Ltd Stacked multi-chip package using encapsulated electroplated pillar conductors; also able to include MEMS elements
KR101332916B1 (en) * 2011-12-29 2013-11-26 주식회사 네패스 Semiconductor package and method of manufacturing the same

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