JP4519512B2 - 半導体装置の作製方法、除去方法 - Google Patents
半導体装置の作製方法、除去方法 Download PDFInfo
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- JP4519512B2 JP4519512B2 JP2004132677A JP2004132677A JP4519512B2 JP 4519512 B2 JP4519512 B2 JP 4519512B2 JP 2004132677 A JP2004132677 A JP 2004132677A JP 2004132677 A JP2004132677 A JP 2004132677A JP 4519512 B2 JP4519512 B2 JP 4519512B2
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/01—Manufacture or treatment
- H10D86/021—Manufacture or treatment of multiple TFTs
- H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/02—Electroplating of selected surface areas
- C25D5/022—Electroplating of selected surface areas using masking means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
- H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
- H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
- H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
- H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
- H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
- H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- General Physics & Mathematics (AREA)
- Plasma & Fusion (AREA)
- General Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Electrochemistry (AREA)
- Organic Chemistry (AREA)
- Metallurgy (AREA)
- Drying Of Semiconductors (AREA)
- Thin Film Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Cleaning Or Drying Semiconductors (AREA)
- Electrodes Of Semiconductors (AREA)
Description
本発明の半導体装置の製造方法について、図1(A)〜(G)、図2(A)〜(D)を用いて説明する。
本発明の半導体装置の製造方法について、図3(A)〜(G),図4(A)、(B)を用いて説明する。
本発明の半導体装置の製造方法を用いることによって歩留まり良く集積回路を製造することができる。本形態では、本発明を適用して製造した中央演算処理装置(CPU)について図5(A)を用いて説明する。
本発明の半導体装置の製造方法を用いた集積回路フィルムの作製方法の一態様について図8(A)〜(D)を用いて説明する。
102 絶縁層
103 半導体層
103b 半導体層
104 絶縁層
105 導電層
106 マスク
107 導電層
108 反応生成物
109 マスク
110 サイドウォール
111 マスク
112 絶縁層
113 配線
114 不純物領域
115 不純物領域
116 不純物領域
Claims (9)
- 形状化されたマスクを表面に有する導電層を、前記導電層の側壁に垂直方向に延びるように反応生成物を付着させながら第1のエッチングをし、
液体組成物を用いて処理することによって、前記マスク及び前記反応生成物の一部を除去すると共に、前記反応生成物の一部を水平方向若しくは斜め方向に倒し、
酸素ガスとハロゲン化物ガスとをプロセスガスとして用い且つ前記プロセスガスを励起した活性種を垂直方向に加速させた第2のエッチングによって倒れた前記反応生成物を除去することを特徴とする半導体装置の作製方法。 - 形状化されたマスクを表面に有する導電層を、前記導電層の側壁に垂直方向に延びるように反応生成物を付着させながら第1のエッチングし、
液体組成物を用いて処理することによって、前記マスク及び前記反応生成物の一部を除去すると共に、前記反応生成物の一部を水平方向若しくは斜め方向に倒し、
前記液体組成物を用いた処理の後に音波エネルギーの印加を伴った溶液処理を行い、
酸素ガスとハロゲン化物ガスとをプロセスガスとして用い且つ前記プロセスガスを励起した活性種を垂直方向に加速させた第2のエッチングによって倒れた前記反応生成物を除去することを特徴とする半導体装置の作製方法。 - 形状化されたマスクを表面に有する導電層を、前記導電層の側壁に垂直方向に延びるように反応生成物を付着させながら第1のエッチングし、
液体組成物を用いて処理することによって、前記マスク及び前記反応生成物の一部を除去すると共に、前記反応生成物の一部を水平方向若しくは斜め方向に倒し、
前記液体組成物を用いた処理の後に超音波若しくはメガソニックの印加を伴った溶液処理を行い、
酸素ガスとハロゲン化物ガスとをプロセスガスとして用い且つ前記プロセスガスを励起した活性種を垂直方向に加速させた第2のエッチングによって倒れた前記反応生成物を除去することを特徴とする半導体装置の作製方法。 - 請求項1乃至請求項3のいずれか一において、前記マスクは感光性樹脂であることを特徴とする半導体装置の作製方法。
- 請求項1乃至請求項4のいずれか一において、前記ハロゲン化物ガスは、塩素ガスであることを特徴とする半導体装置の作製方法。
- 請求項1乃至請求項5のいずれか一において、前記第2のエッチングは、誘導結合型プラズマ方式で行うことを特徴とする半導体装置の作製方法。
- 導電膜上にマスクを形成し、
前記マスクを用いて前記導電膜に第1のエッチングをすることによって導電層を形成する際に、前記マスク及び前記導電層の側壁に付着する反応生成物の除去方法であって、
前記マスクと前記導電層と前記反応生成物とが形成された状態において、液体組成物を用いて前記マスク及び前記反応生成物の一部を除去すると共に、前記反応生成物の一部を水平方向若しくは斜め方向に倒し、
前記液体組成物を洗浄する処理を行い、
酸素ガスとハロゲン化物ガスとをプロセスガスとして用い且つ前記プロセスガスを励起した活性種を垂直方向に加速させた第2のエッチングによって倒れた前記反応生成物を除去することを特徴とする除去方法。 - 導電膜上にマスクを形成し、
前記マスクを用いて前記導電膜に第1のエッチングをすることによって導電層を形成する際に、前記マスク及び前記導電層の側壁に付着する反応生成物の除去方法であって、
前記マスクと前記導電層と前記反応生成物とが形成された状態において、液体組成物を用いて前記マスク及び前記反応生成物の一部を除去すると共に、前記反応生成物の一部を水平方向若しくは斜め方向に倒し、
前記液体組成物を洗浄する処理を行い、
超音波若しくはメガソニックの印加を伴う溶液処理を行い、
酸素ガスとハロゲン化物ガスとをプロセスガスとして用い且つ前記プロセスガスを励起した活性種を垂直方向に加速させた第2のエッチングによって倒れた前記反応生成物を除去することを特徴とする除去方法。 - 請求項7又は請求項8に記載の除去方法を用いた工程を含むことを特徴とする半導体装置の作製方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004132677A JP4519512B2 (ja) | 2004-04-28 | 2004-04-28 | 半導体装置の作製方法、除去方法 |
US11/099,628 US7432211B2 (en) | 2004-04-28 | 2005-04-06 | Method for manufacturing semiconductor device |
CN2005100684632A CN1691292B (zh) | 2004-04-28 | 2005-04-28 | 用于制造半导体器件的方法和电子器件 |
Applications Claiming Priority (1)
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JP2004132677A JP4519512B2 (ja) | 2004-04-28 | 2004-04-28 | 半導体装置の作製方法、除去方法 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2005317699A JP2005317699A (ja) | 2005-11-10 |
JP2005317699A5 JP2005317699A5 (ja) | 2007-06-07 |
JP4519512B2 true JP4519512B2 (ja) | 2010-08-04 |
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Application Number | Title | Priority Date | Filing Date |
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JP2004132677A Expired - Fee Related JP4519512B2 (ja) | 2004-04-28 | 2004-04-28 | 半導体装置の作製方法、除去方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7432211B2 (ja) |
JP (1) | JP4519512B2 (ja) |
CN (1) | CN1691292B (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
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JP5352081B2 (ja) | 2006-12-20 | 2013-11-27 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
JP2009033727A (ja) * | 2007-06-22 | 2009-02-12 | Semiconductor Energy Lab Co Ltd | 半導体装置 |
KR101892430B1 (ko) | 2009-10-21 | 2018-08-30 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치 |
CN119096336A (zh) * | 2023-03-29 | 2024-12-06 | 京东方科技集团股份有限公司 | 金属网格的制备方法和天线的制备方法 |
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-
2004
- 2004-04-28 JP JP2004132677A patent/JP4519512B2/ja not_active Expired - Fee Related
-
2005
- 2005-04-06 US US11/099,628 patent/US7432211B2/en not_active Expired - Fee Related
- 2005-04-28 CN CN2005100684632A patent/CN1691292B/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2005317699A (ja) | 2005-11-10 |
CN1691292A (zh) | 2005-11-02 |
CN1691292B (zh) | 2011-01-12 |
US7432211B2 (en) | 2008-10-07 |
US20050241952A1 (en) | 2005-11-03 |
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