JP4552752B2 - Storage element manufacturing method and storage device manufacturing method - Google Patents

Description

  The present invention relates to a method for manufacturing a memory element capable of recording information, and a method for manufacturing a memory device using the memory element.

  In information equipment such as a computer, a high-speed and high-density DRAM is widely used as a random access memory.

However, a DRAM has a higher manufacturing cost because a manufacturing process is more complicated than a general logic circuit LSI or signal processing used in an electronic device.
The DRAM is a volatile memory in which information disappears when the power is turned off, and it is necessary to frequently perform a refresh operation, that is, an operation of reading, amplifying, and rewriting the written information (data).

Thus, for example, FeRAM (ferroelectric memory), MRAM (magnetic memory element), and the like have been proposed as nonvolatile memories whose information does not disappear even when the power is turned off.
In the case of these memories, it is possible to keep the written information for a long time without supplying power.
In addition, in the case of these memories, it is considered that by making them non-volatile, the refresh operation is unnecessary and the power consumption can be reduced accordingly.

However, with the above-described nonvolatile memory, it is difficult to ensure characteristics as a memory element as the memory elements constituting each memory cell are reduced.
For this reason, it is difficult to reduce the element to the limit of the design rule and the limit of the manufacturing process.

Therefore, a new type of storage element has been proposed as a memory having a configuration suitable for downsizing.
This memory element has a structure in which an ionic conductor containing a certain metal is sandwiched between two electrodes.
And by including the metal contained in the ionic conductor in one of the two electrodes, when a voltage is applied between the two electrodes, the metal contained in the electrode becomes an ion in the ionic conductor. Due to the diffusion, this changes the electrical properties such as resistance or capacitance of the ionic conductor.
A memory device can be configured using this characteristic (see, for example, Patent Document 1 and Non-Patent Document 1).

  Specifically, the ionic conductor is made of a solid solution of chalcogenide and metal, more specifically, a material in which Ag, Cu, Zn is dissolved in AsS, GeS, GeSe, and one of the two electrodes. One electrode contains Ag, Cu, and Zn (see Patent Document 1).

Special Table 2002-536840 Publication Nikkei Electronics 2003.1.20 (page 104)

However, the configuration of the memory element described above has a problem that it changes to a low resistance state in a high temperature environment or during long-term storage.
Therefore, a configuration in which the oxide layer is used as a solid electrolyte layer adjacent to a solid solution of chalcogenide and metal is conceivable.
According to this configuration, the information retention characteristic is greatly improved.

  However, the configuration of the memory element described above causes not only the above-described problem of data retention characteristics that change to a low resistance state in a high-temperature environment or during long-term storage, but also other problems.

For example, when manufacturing a large-capacity memory having a large-scale cell array, in order to prevent erroneous recording, a threshold value of a so-called “write” operation for transitioning from a high-resistance state to a low-resistance state or vice versa The threshold value of the so-called “erase” operation for transitioning from the state to the high resistance state needs to be kept within a certain range.
These threshold values vary even in the same memory element due to repeated writing / erasing, or the threshold voltage changes with each repetition, or the threshold voltage for writing is different for each memory element (that is, for each memory cell of the memory). If there are variations in threshold values, such as different values, stable memory operation becomes difficult.
In addition, when the threshold voltage is too high, high-speed operation becomes difficult, or the voltage drive range of the selection MOS transistor for selecting the memory cell is exceeded, and the operation becomes impossible. Exists.

  In order to solve the above-described problems, the present invention makes it possible to manufacture a storage element and a storage device having appropriate characteristics by suppressing variation in characteristics such as threshold voltage in recording, reading, and writing of information. The present invention provides a method for manufacturing a memory element and a method for manufacturing a memory device.

The method for manufacturing a memory element according to the present invention includes a memory thin film sandwiched between a first electrode and a second electrode, the memory thin film including an oxide layer, and the memory thin film. The inner layer or the layer in contact with the memory thin film contains any element selected from Ag, Cu, and Zn. By applying a voltage pulse or a current pulse to the memory thin film, the memory thin film When a memory element having a configuration in which information is recorded by changing the impedance of the Gd film is formed, after the Gd film is formed, the Gd film is exposed to a plasma containing oxygen to thereby form an amorphous Gd oxide film. An oxide layer is formed, and a laminated film constituting the memory element is formed without exposing the interface of the memory thin film to the atmosphere.
A method for manufacturing a memory device according to the present invention includes the memory element, a wiring connected to the first electrode side, and a wiring connected to the second electrode side, and a large number of memory elements are arranged. When manufacturing the memory device, the memory element is manufactured by the method for manufacturing the memory element of the present invention.

  In the memory element according to the manufacturing method of the present invention, a memory thin film is sandwiched between the first electrode and the second electrode, and the memory thin film includes an oxide layer. Utilizing the fact that the resistance state of the memory thin film changes due to the constitution in which any element selected from Ag, Cu, and Zn is contained in the thin film or the layer in contact with the memory thin film Information can be recorded.

Specifically, for example, when a positive potential is applied to one electrode side and a voltage is applied to the memory element, Ag, Cu and Zn are ionized and diffused into the memory thin film, and at the other electrode side part The resistance value of the memory thin film is lowered by being deposited in combination with electrons or by forming an impurity level in the insulating film that remains in the memory thin film, so that information can be written. become.
Further, from this state, when a negative potential is applied to one electrode side and a negative voltage is applied to the memory element, Ag, Cu, Zn deposited on the other electrode side is ionized again to return to the original state. By returning, the resistance value of the memory thin film returns to its original high state, and the resistance value of the memory element also increases, so that the recorded information can be erased.

  And since the memory thin film comprises an oxide layer, the resistance value in the high resistance state can be made relatively high.

According to the method for manufacturing a memory element of the present invention described above, the memory thin film including the oxide layer is formed by forming the laminated film constituting the memory element without exposing the interface of the memory thin film to the atmosphere. The change in the oxide layer that occurs when the interface is exposed to the atmosphere can be suppressed. Thereby, the nonuniformity of the oxide layer of the memory thin film can be reduced.
And, in the memory element according to the present invention, the threshold voltage when the resistance value is changed by the ionization behavior excited by the applied voltage and the operation of the ions greatly depends on the thickness and the oxidation state of the oxide layer. By reducing the non-uniformity of the oxide layer of the memory thin film, it is possible to suppress variations in threshold voltage during writing and erasing of the memory element.

According to the present invention described above, it is possible to suppress variations in threshold voltage in writing and erasing to the storage element by reducing non-uniformity of the oxide layer of the memory thin film. A memory element and a memory device having characteristics can be manufactured stably and with high yield.
In addition, since it becomes possible to reduce variations in threshold voltage, it is possible to reduce the occurrence of errors in writing and erasing information, so that a storage device capable of stable memory operation can be realized. It becomes possible.

Furthermore, the memory element according to the present invention can be manufactured by materials and manufacturing methods used in a normal MOS logic circuit manufacturing process.
Therefore, according to the present invention, a storage element and a storage device having appropriate characteristics can be manufactured at a low cost, and an inexpensive storage device can be provided.

FIG. 1 shows a schematic configuration diagram (cross-sectional view) of an embodiment of a memory element according to the manufacturing method of the present invention.
In this memory element 10, for example, a lower electrode 2 is formed on a silicon substrate 1, a layer 3 containing Ag, Cu, and Zn is formed on the lower electrode 2, and a memory thin film 4 is formed thereon, An upper electrode 5 is formed on the memory thin film 4.
An insulating layer 6 is embedded around the laminated film of these layers 2, 3, 4, and 5.

For the lower electrode 2, a wiring material used in a semiconductor process, for example, TiW, Ti, W, Cu, Al, Mo, Ta, silicide, or the like can be used.
For example, when a W film is used for the lower electrode 2, the film thickness may be in the range of 10 nm to 100 nm, for example.

The layer 3 on the lower electrode 2 includes at least one of Ag, Cu, and Zn, that is, a metal element that serves as an ion source to be described later. Hereinafter, the layer 3 is referred to as an ion source layer 3.
The ion source layer 3 includes, for example, a film having a composition in which Ag, Cu, Zn is added to GeSbTe, GeTe, GeSe, GeS, SiGeTe, SiGeSbTe, or the like containing a chalcogenide element of Te, Se, or S, an Ag film, or an Ag alloy. A film, a Cu film, a Cu alloy film, a Zn film, a Zn alloy film, or the like can be used.
For example, when a GeTeCu film is used for the ion source layer 3, the film thickness may be set to 5 nm to 50 nm, for example. Moreover, it is good also as a composition containing the rare earth elements used for the oxide layer mentioned later other than said composition, for example, CuGeTeGd.

  Further, the ion source layer 3 may have a laminated structure of the chalcogenide element layer and a layer that supplements an element serving as a necessary ion source. For example, when an Ag, Cu, Zn filling layer is provided, the film thickness may be 2 nm to 30 nm, for example.

The memory thin film 4 is one or more kinds of rare earth elements selected from La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Yb, and Y among rare earth elements. A thin film made of the above oxide (hereinafter referred to as a rare earth oxide thin film) is used.
Since this rare earth oxide thin film 4 is usually an insulating material, it is thinned to a thickness of 0.5 nm to 3 nm, for example, so that a current can flow.
The composition of oxygen in the rare earth oxide thin film 4 is usually an RE ₂ O ₃ composition with respect to the rare earth element (RE). Here, the composition is an amorphous film having an electrical conductivity lower than the conductivity of the semiconductor region. Since it is sufficient if it has properties, it is not necessarily limited to such a composition. For example, REOx (0.5 <x ≦ 1.5) may be used.

  Further, the rare earth oxide thin film 4 includes, for example, Ge, Si, Te, S, Se, Sb, Ti, W, Cu, Ag, Zn, Fe, Co, P, N, H, and the like other than rare earth elements. An element may be contained in advance.

  The rare earth oxide thin film 4 made of the above-described material has a characteristic that the impedance changes when a voltage pulse or a current pulse is applied.

As with the lower electrode 2, a normal semiconductor wiring material is used for the upper electrode 5.
The insulating layer 6 includes, for example, a hard-cured photoresist, SiO ₂ or Si ₃ N ₄ commonly used in semiconductor devices, and other materials such as SiON, SiOF, Al ₂ O ₃ , Ta ₂ O ₅ , Inorganic materials such as HfO ₂ and ZrO ₂ , fluorine organic materials, aromatic organic materials, and the like can be used.

  The storage element 10 can be operated as follows to store information.

First, for example, a positive potential (+ potential) is applied to the ion source layer 3 containing Ag, Cu, and Zn, and a positive voltage is applied to the memory element 10 so that the upper electrode 5 side becomes negative. . As a result, Ag, Cu, Zn is ionized from the ion source layer 3 and diffuses in the rare earth oxide thin film 4, and is combined with electrons on the upper electrode 5 side to be deposited, or the rare earth oxide thin film 4 It stays diffused inside.
Then, a current path containing a large amount of Ag, Cu, Zn is formed inside the rare earth oxide thin film 4 or a large number of defects due to Ag, Cu, Zn are formed inside the rare earth oxide thin film 4, thereby The resistance value of the oxide thin film 4 becomes low. Each layer other than the rare earth oxide thin film 4 originally has a lower resistance value than the resistance value of the rare earth oxide thin film 4 before recording. The resistance value can also be lowered.

  After that, when the positive voltage is removed and the voltage applied to the memory element 10 is eliminated, the resistance value is kept low. This makes it possible to record information. When used in a storage device that can be recorded only once, so-called PROM, the recording is completed only by the recording process.

On the other hand, an erasing process is necessary for application to an erasable storage device, so-called RAM or EEPROM. In the erasing process, the ion source layer 3 containing Ag, Cu, Zn, for example, is negatively charged. A negative voltage is applied to the memory element 10 by applying a potential (−potential) so that the upper electrode 5 side becomes positive. As a result, Ag, Cu, Zn constituting the current path or impurity level formed in the rare earth oxide thin film 4 is ionized, moves in the rare earth oxide thin film 4, and returns to the ion source layer 3 side. .
Then, current paths or defects due to Ag, Cu, and Zn disappear from the rare earth oxide thin film 4, and the resistance value of the rare earth oxide thin film 4 increases. Since each layer other than the rare earth oxide thin film 4 originally has a low resistance value, by increasing the resistance value of the rare earth oxide thin film 4, the resistance value of the entire memory element 10 can also be increased.
After that, when the negative voltage is removed and the voltage applied to the memory element 10 is eliminated, the resistance value is kept high. As a result, the recorded information can be erased.

  By repeating such a process, it is possible to repeatedly record (write) information on the storage element 10 and erase the recorded information.

  For example, if a state with a high resistance value is associated with information “0” and a state with a low resistance value is associated with information “1”, the information recording process by applying a positive voltage changes from “0” to “ It can be changed from “1” to “0” in the process of erasing information by applying a negative voltage.

  The rare earth oxide thin film 4 is preferably made of a material that exhibits a high resistance value in an initial state before recording and a state after erasing.

The resistance value after recording depends on the recording conditions such as the voltage pulse or current pulse width and current amount applied during recording rather than the cell size of the memory element 10 and the material composition of the rare earth oxide thin film 4, and the initial resistance. When the value is 100 kΩ or more, the range is approximately 50Ω to 50 kΩ.
In order to demodulate the recorded data, it is sufficient that the ratio of the initial resistance value and the resistance value after recording is approximately twice or more. Therefore, the resistance value before recording is 100Ω, and after recording, It is sufficient if the resistance value is 50 Ω, or the resistance value before recording is 100 kΩ and the resistance value after recording is 50 kΩ, and the initial resistance value of the rare earth oxide thin film 4 satisfies such a condition. Set to The resistance value of the rare earth oxide thin film 4 can be adjusted by, for example, oxygen concentration, film thickness, area, and addition of impurity materials.

  According to the configuration of the memory element 10 of the above-described form, the ion source layer 3 containing Ag, Cu, and Zn, the rare earth oxide thin film 4 made of oxygen and rare earth elements are provided between the lower electrode 2 and the upper electrode 6. For example, when a positive voltage (+ potential) is applied to the ion source layer 3 side containing Ag, Cu, and Zn so that the upper electrode 5 side becomes negative, the rare earth element By forming a current path containing a large amount of Ag, Cu, Zn in the oxide thin film 4 or by forming many defects due to Ag, Cu, Zn in the rare earth oxide thin film 4, the rare earth oxide The resistance value of the thin film 4 becomes low, and the resistance value of the entire memory element 10 becomes low. Then, by stopping the application of the positive voltage so that no voltage is applied to the memory element 10, the state in which the resistance value is low is maintained, and information can be recorded. Such a configuration can be used for a storage device capable of recording only once, such as a PROM.

  Since information is stored by utilizing the change in resistance value of the memory element 10, particularly the change in resistance value of the rare earth oxide thin film 4, even when the memory element 10 is miniaturized, the information Recording and storing of recorded information becomes easy.

  Further, for example, when used in a storage device that can be erased in addition to recording such as RAM or EEPROM, the storage element 10 in the state after recording described above includes, for example, ions containing Ag, Cu, and Zn. A negative voltage (−potential) is applied to the source layer 3 so that the upper electrode 5 side becomes positive. As a result, the current path or defect due to Ag, Cu, Zn formed in the rare earth oxide thin film 4 disappears, the resistance value of the rare earth oxide thin film 4 increases, and the resistance value of the entire memory element 10 increases. Becomes higher. Then, by stopping the application of the negative voltage so that no voltage is applied to the memory element 10, the state in which the resistance value is increased is maintained, and the recorded information can be erased.

Furthermore, according to the memory element 10 of this embodiment, the lower electrode 2, the ion source layer 3, the rare earth oxide thin film 4, and the upper electrode 5 can all be made of a material that can be sputtered. For example, sputtering may be performed using a target having a composition suitable for the material of each layer.
In addition, it is possible to continuously form a film by exchanging the target in the same sputtering apparatus.

The rare earth oxide thin film 4 is formed by a method in which a rare earth metal film is formed in advance and then formed by plasma oxidation using oxygen plasma or plasma of a mixed gas containing oxygen, or an oxide sputtering target is used. It is possible to use a method, a method of introducing oxygen together with an inert gas such as argon as an introduction gas during sputtering using a metal target, a method such as so-called reactive sputtering.
Further, in addition to sputtering, the rare earth oxide thin film 4 can be formed by a CVD method, a vapor deposition method, or the like. In addition, the film is in a metal state at the time of film formation, and is then subjected to thermal oxidation or chemical treatment. It is also possible to form the rare earth oxide thin film 4 by such a method.

  In the memory element 10 of the above-described form, the ion source layer 3 contains Ag, Cu, Zn and is not included in the upper electrode 5. However, only the lower electrode 2 contains Ag, Cu, Zn of the ion source. Alternatively, the lower electrode 2 and the upper electrode 5 may include an ion source of Ag, Cu, or Zn. Further, the ion source layer 3 can be used as it is as the lower electrode 2.

A memory device (memory device) can be configured by arranging a large number of the memory elements 10 in the above-described form in a matrix.
For each storage element 10, a wiring connected to the lower electrode 2 side and a wiring connected to the upper electrode 5 side are provided. For example, each storage element 10 is arranged near the intersection of these wirings. What should I do?

  Specifically, for example, the lower electrode 2 is formed in common in the memory cell in the row direction, the wiring connected to the upper electrode 5 is formed in common in the memory cell in the column direction, and a current is applied by applying a potential. By selecting the lower electrode 2 and the wiring to be flown, a memory cell to be recorded is selected, and a current is passed through the memory element 10 of this memory cell to record information or erase the recorded information. it can.

The memory element 10 having the above-described form can easily record and read information, and has an excellent characteristic that variation in write and erase voltage thresholds is particularly small.
Further, even when the memory element 10 having the above-described form is miniaturized, it becomes easy to record information and hold recorded information.
Therefore, by configuring the memory device using the memory element 10 having the above-described form, the memory device can be integrated (densified) or downsized.

  Next, a method for manufacturing the memory element 10 having the configuration shown in FIG. 1 will be described as an embodiment of the method for manufacturing the memory element of the present invention.

First, a lower electrode 2, for example, a W film is deposited on the substrate 1.
Next, an ion source layer 3, for example, a Cu film is formed.

Thereafter, a rare earth oxide thin film 4, for example, a Gd ₂ O ₃ film, which becomes a memory thin film is formed. In order to form the rare earth oxide film 4, first, a rare earth metal film is formed by DC magnetron sputtering or the like, and then oxidized by oxygen plasma or plasma of a mixed gas of oxygen and argon.

  Next, as the upper electrode 5, for example, a W film is formed. Thereby, a laminated film of the lower electrode 2, the ion source layer 3, the rare earth oxide thin film (memory thin film) 4, and the upper electrode 5 is formed.

Thereafter, the laminated film from the lower electrode 2 to the upper electrode 5 is patterned by, for example, plasma etching. Besides plasma etching, patterning can be performed using an etching method such as ion milling or RIE (reactive ion etching).
Further, an insulating layer 6 is embedded around the patterned laminated film.
In this way, the memory element 10 shown in FIG. 1 can be manufactured.

In the present embodiment, in particular, the laminated film from the lower electrode 2 to the upper electrode 5 is made such that the interface of the rare earth oxide thin film 4 is not exposed to the atmosphere until the upper electrode 5 is formed. For example, a film is continuously formed in a film forming apparatus having a vacuum inside, and a laminated film from the lower electrode 2 to the upper electrode 5 is formed.
By manufacturing the memory element 10 in this way, changes in the rare earth oxide thin film 4 can be suppressed. Thereby, the nonuniformity of the rare earth oxide thin film 4 of the memory thin film can be reduced.

  In the memory element 10 according to the present embodiment, the threshold voltage when the resistance value changes due to the ionization behavior excited by the applied voltage and the operation of the ions is large depending on the thickness and oxidation state of the rare earth oxide thin film 4. Therefore, by reducing the non-uniformity of the rare earth oxide thin film 4, it is possible to suppress variations in threshold voltage during writing and erasing of the memory element 10.

Further, the memory element 10 according to the present embodiment can be manufactured by a material or a manufacturing method used in a normal MOS logic circuit manufacturing process.
Therefore, with the manufacturing method of this embodiment, a storage element and a storage device with appropriate characteristics can be manufactured at low cost, and an inexpensive storage device can be provided.

  Accordingly, it becomes possible to suppress variation in threshold voltage in writing and erasing of the memory element 10, and thus the memory element 10 and the memory device having appropriate characteristics can be manufactured stably and with high yield.

More preferably, a rare earth metal film (Gd film or the like) for forming the rare earth oxide thin film 4 is formed with a film thickness in the range of 0.5 nm to 3.0 nm.
As a result, variation in thresholds of the write voltage and the erase voltage can be greatly reduced.
Although the film thickness of the rare earth oxide thin film 4 obtained varies depending on the oxidation conditions, the rare earth oxide thin film 4 having a film thickness of 10 nm or less is formed by forming the Gd film with a film thickness within the above range. can do.

In particular, in order to operate the memory element 10 at high speed, it is advantageous to reduce the threshold voltage for writing and erasing.
Therefore, the threshold voltage is reduced by reducing the thickness of the memory thin film. For example, the film thickness is set to several nm or less. Accordingly, since the operating voltage can be reduced, the power consumption of the memory element 10 and the memory device can be reduced, and the heat generated by the operation can be reduced, so that the memory device having high reliability can be obtained. Can be realized.
Further, since power consumption of each memory element 10 can be reduced, integration (high density) and miniaturization of a memory device having a large number of memory elements 10 can be achieved.

  In addition, when the thickness of the rare earth oxide thin film 4 constituting the memory thin film is reduced (thinned) in this way, the element characteristics are more sensitively affected by non-uniformity of impurities and the like. In addition, when the stacked film of the memory elements 10 is formed so that the interface of the rare earth oxide thin film 4 is not exposed to the atmosphere, the memory elements 10 with a small threshold voltage variation and a sufficiently low threshold voltage can be stably obtained with a high yield. Can be manufactured.

Instead of patterning the laminated film up to the interface between the lower electrode 2 and the substrate 1 as in the memory element 10 shown in FIG. 1, only a part of the laminated film may be patterned.
For example, it is possible to pattern only the upper layer interface of the lower electrode 2 or the upper part of the lower electrode 2 so that the lower electrode 2 also serves as a wiring.
Further, for example, only the upper electrode 5 is patterned, and the lower electrode 2, the ion source layer 3, and the rare earth oxide thin film (memory thin film) 4 are shared by the memory elements of a plurality of memory cells. ) Can also be configured.

In the memory element 10 of the above-described form, the memory thin film 4 is composed of an oxide of a rare earth element. However, in the present invention, other oxides can be used for the memory thin film 4.
Examples thereof include oxides such as tantalum oxide, niobium oxide, and aluminum oxide.
Even when these oxides are used for the memory thin film 4, a stacked film from the lower electrode to the upper electrode including the memory thin film 4 is continuously formed in a vacuum film forming apparatus, so that a write voltage and an erasure can be obtained. Variation in voltage threshold can be reduced.

(Example)
Next, the memory element 10 having the above-described configuration was actually manufactured and the characteristics were examined.

<Sample 1 to Sample 9; Examples>
First, a W film having a thickness of 20 nm was deposited as a lower electrode 2 on a silicon substrate on which a 300 nm thermal oxide film was formed as a substrate 1 by sputtering.
Next, using a magnetron sputtering apparatus, a Cu film was formed to a thickness of 4 nm, and a CuGeTeGd film was deposited to a thickness of 20 nm to form an ion source layer 3 composed of these laminated films.
Subsequently, after forming the Gd film, plasma oxidation with oxygen plasma with an input power of 500 W and an oxygen pressure of 1 mTorr is performed for 30 seconds to oxidize the Gd film to form an amorphous gadolinium oxide film (amorphous Gd oxide film), and memory Thin film 4 was obtained.
Next, a W film having a thickness of 20 nm was formed as the upper electrode 5.
That is, the laminated film which comprises the memory element 10 was produced by making the material and film thickness of each layer into the following structure (film structure 1).
Film configuration 1: W (20 nm) / Cu (4 nm) / CuGeTeGd (20 nm) / GdO / W (20 nm)

Subsequently, a memory element having a cross-sectional structure shown in FIG.
First, heat treatment was performed at 160 ° C. for 4 hours in a heat treatment furnace.

  Next, after masking the portion of the word line WL which also serves as the lower electrode by photolithography, selective etching is performed by Ar plasma on the laminated film other than the word line WL, whereby the word line WL (of the lower electrode 2) W film) was formed. At this time, except for the word line WL portion, the substrate was etched to a depth of 5 nm.

  Then, the memory element 10 was formed by forming a mask of the pattern of the memory element 10 and performing patterning by performing selective etching on the laminated film. Except for the memory element 10 portion, the lower electrode 2 was etched to a depth of 10 nm. That is, in the W film, the upper layer portion patterned by selective etching was used as the lower electrode 2, and the lower layer portion was used as the word line WL.

Next, an insulating layer 6 was formed by depositing Al ₂ O ₃ having a thickness of about 100 nm by sputtering except for the portion of the memory element 10 to insulate the stacked film of the memory element 10.
Thereafter, a contact on the upper surface of the memory element 10 was formed by lift-off.
Next, Cr (20 nm) / Cu (100 nm) / Au (100 nm) were sequentially deposited by a sputtering method to form the wiring layer 11 connected to the upper electrode 5.
The wiring layer 11 was patterned using photolithography to form the bit line BL and a measurement pad portion.
In this way, a sample of the memory element 10 was produced.

And each sample of the memory element 10 of Sample 1 to Sample 9 was manufactured by changing the film thickness of the Gd film that becomes an amorphous gadolinium oxide film by oxidation in the above film configuration 1.
In sample 1, the thickness of the Gd film was 0.4 nm.
In sample 2, the thickness of the Gd film was 0.6 nm.
In sample 3, the thickness of the Gd film was 1.0 nm.
In Sample 4, the thickness of the Gd film was 1.4 nm.
In Sample 5, the thickness of the Gd film was 1.8 nm.
In Sample 6, the thickness of the Gd film was 2.2 nm.
In Sample 7, the thickness of the Gd film was 2.8 nm.
In Sample 8, the thickness of the Gd film was set to 3.0 nm.
In Sample 9, the thickness of the Gd film was 3.2 nm.

<Sample 10; Comparative Example>
As a comparative example for the present invention, a memory element 50 having the configuration shown in the cross-sectional view of FIG. 3 was produced.
First, a W film having a thickness of 20 nm was deposited as the lower electrode 2 on the silicon substrate 1 on which the 300 nm thermal oxide film was formed by sputtering.
Next, using a magnetron sputtering apparatus, a Cu film was formed to a thickness of 4 nm, and a CuGeTeGd film was deposited to a thickness of 20 nm to form an ion source layer 3 composed of these laminated films.
Subsequently, after forming a Gd film with a thickness of 1.4 nm, plasma oxidation with oxygen plasma at an input power of 500 W and an oxygen pressure of 1 mTorr is performed for 30 seconds to oxidize the Gd film to form an amorphous gadolinium oxide film (amorphous Gd oxide). Film) to form a memory thin film 4.

Next, a photoresist was formed so as to cover the memory thin film 4, and thereafter, exposure and development were performed by a photolithography technique to form an opening (through hole) in the photoresist on the memory thin film 4.
In developing, since the sample is taken out of the film forming apparatus, the portion of the memory thin film 4 facing the opening is exposed to the atmosphere.

Thereafter, annealing was performed at 280 ° C. in vacuum to alter the photoresist, and the insulating layer 6 was formed as a hard cure resist that is stable with respect to temperature and etching.
Next, a W film having a thickness of 20 nm was formed as the upper electrode 5 so as to fill the opening of the insulating layer 6 and connect it to the memory thin film 4.
Thereafter, the W film deposited on the insulating layer 6 made of a hard-cure resist was patterned by a photolithography technique using a plasma etching apparatus to form a bit line and a pad portion for measurement.
In this way, a sample of the memory element 50 of Sample 10 was manufactured.

  That is, the film configuration of the laminated film in the memory element 50 portion of the sample 10 is the same as the film configuration 1 of the memory element 10 of the sample 1 to the sample 9, and the film thickness of the Gd film is the same as that of the sample 4. It has become.

(Characteristic evaluation)
First, with respect to the sample of the memory element of Sample 4, the lower electrode 2 connected to the word line WL was grounded to the ground potential, and a negative potential was applied to the upper electrode 5 connected to the bit line BL.
Then, the negative potential applied to the upper electrode 5 was decreased from 0V to −1.5V, and the change in current was measured.
Further, from the state where the negative potential applied to the upper electrode 5 reached −1.5 V, the negative potential applied to the upper electrode 5 was decreased to 0 V, and the change in current was measured.
Subsequently, this time, conversely, a positive potential is applied to the upper electrode 5, and the application of the positive voltage is increased until the voltage between the upper electrode 5 and the lower electrode 2 becomes a voltage of 1.0 V. The operation to return to was performed.
This recording / erasing operation was repeated three times in total.
FIG. 4 shows the measurement results of the IV characteristics of the sample of the memory element of Sample 4 obtained in this way.

As shown in FIG. 4, the resistance value is initially high, the memory element is in the OFF state, and the voltage increases in the negative direction, so that the current increases rapidly at a certain threshold voltage (Vth) or higher.
That is, it can be seen that the resistance value decreases and the memory element transitions to the ON state. Thereby, information is recorded.
On the other hand, even if the voltage is decreased thereafter, a constant resistance value is maintained. That is, it can be seen that the storage element is kept in the ON state and the recorded information is held. The same operation is performed even if the recording / erasing is performed twice (total three times) thereafter.

Further, as shown in the figure, a voltage V having a polarity opposite to that described above, that is, a positive potential (+ potential) is applied to the upper electrode 5, and the lower electrode 2 side is connected to a ground potential (ground potential). It was confirmed that the resistance value of the memory element 10 returned to the initial high-resistance state by turning it back to 0 V after applying a positive potential of V = 0.3 V or more.
That is, it can be seen that the information recorded in the memory element 10 can be erased by applying a negative voltage.

Next, for each of Samples 1 to 10, the same measurement was performed on 10 elements formed on the same substrate.
First, as an example of the measurement results, the measurement results of the IV characteristics of 10 elements of the sample 4 are superimposed and shown in FIG.

Next, the initial write voltage threshold and the erase voltage threshold were obtained from the initial IV characteristic loop, and the respective variations were obtained.
Similarly, the second write voltage threshold and the erase voltage threshold were obtained from the second IV characteristic loop, and the respective variations were obtained.
Then, the standard deviation of the threshold value of the voltage of 10 elements was obtained, and the value obtained by dividing the standard deviation was defined as the variation value (%). Table 1 shows values of variations in thresholds of the write voltage and the erase voltage. Table 2 shows the measured values of each threshold.

First, as shown in Table 1, the sample 10 which is the configuration of the comparative example (FIG. 3) of the present invention has a large variation in the threshold voltage.
In the sample 10, after the memory thin film 4 made of the Gd oxide film is formed, the atmosphere, photoresist, and developer are touched to form contact holes.
On the other hand, Sample 1 to Sample 9 having the configuration shown in FIGS. 1 and 2 and having the configuration according to the present invention have significantly smaller variations in voltage threshold than sample 10.
Therefore, it is desirable to form a stacked film of memory elements without being exposed to the atmosphere or the like as in samples 1 to 9.

Further, among the samples (sample 1 to sample 9) having the configuration shown in FIGS. 1 and 2, in samples 2 to 8, the variation in threshold voltage is 10% or less, and good variation characteristics are obtained. ing.
On the other hand, in Sample 1 in which the thickness of the Gd film is reduced to 0.4 nm, the variation is larger than those in Samples 2 to 8.
Similarly, in sample 9 in which the thickness of Gd is as thick as 3.2 nm, the variation is larger than in samples 2 to 8. Since the initial write threshold voltage exceeds −1.0 V, it is difficult to operate at high speed.
Therefore, it can be seen that it is desirable that the thickness of the Gd film is within the range of 0.5 nm to 3.0 nm as described above, including Sample 2 to Sample 8.

A memory device (memory device) can be configured by arranging a large number of memory elements, for example, in a column shape or a matrix shape, using the memory element according to the present invention as shown in the above-described embodiments and the like. it can.
At this time, a memory cell is configured by connecting a MOS transistor or a diode for selecting the element to each memory element as necessary.
Further, if necessary, the storage element is connected to a sense amplifier, an address recorder, a recording / erasing / reading circuit, etc. via a wiring.

  The memory element according to the present invention can be applied to various memory devices. For example, a so-called PROM (programmable ROM) that can be written only once, an electrically erasable EEPROM (electrically erasable ROM), or a so-called RAM (random access memory) that can be recorded / erased / reproduced at high speed. It is possible to apply any memory form such as (memory).

  The present invention is not limited to the above-described embodiments, and various other configurations can be taken without departing from the gist of the present invention.

It is a schematic block diagram (sectional drawing) of one form of the memory element which concerns on the manufacturing method of this invention. It is a schematic sectional drawing of the sample of the produced memory element. It is a schematic block diagram (sectional drawing) of the memory element of a comparative example. 4 is a measurement result of IV characteristics of a sample of a memory element of Sample 4. It is the figure which superimposed the IV characteristic curve of 10 elements of the sample of the memory | storage element of the sample 4. FIG.

Explanation of symbols

1 substrate, 2 lower electrode, 3 ion source layer, 4 memory thin film (rare earth oxide thin film), 5 upper electrode, 6 insulating layer, 10 memory element, WL word line, BL bit line

Claims (4)

A memory thin film is sandwiched between the first electrode and the second electrode,
The memory thin film comprises an oxide layer;
Any element selected from Ag, Cu, Zn is contained in the memory thin film or in the layer in contact with the memory thin film ,
A method of manufacturing a memory element having a configuration in which information is recorded by changing the impedance of the memory thin film by applying a voltage pulse or a current pulse to the memory thin film ,
After forming the Gd film, the Gd film is exposed to plasma containing oxygen to form the oxide layer made of an amorphous Gd oxide film,
A method for manufacturing a memory element, comprising forming a laminated film constituting the memory element without exposing an interface of the memory thin film to the atmosphere. The method for manufacturing a memory element according to claim 1 , wherein the Gd film is formed in a thickness range of 0.5 nm to 3.0 nm. A memory thin film is sandwiched between the first electrode and the second electrode, and the memory thin film includes an oxide layer, and the memory thin film or the memory thin film The contacting layer contains any element selected from Ag, Cu, and Zn, and the impedance of the memory thin film is changed by applying a voltage pulse or a current pulse to the memory thin film. A storage element that is configured to record information ;
Wiring connected to the first electrode side;
A wiring connected to the second electrode side,
A method of manufacturing a storage device in which a large number of the storage elements are arranged,
After forming the Gd film, the Gd film is exposed to plasma containing oxygen to form the oxide layer made of an amorphous Gd oxide film,
A method for manufacturing a memory device, comprising forming a laminated film constituting the memory element without exposing an interface of the memory thin film to the atmosphere. The method for manufacturing a memory device according to claim 3, wherein the Gd film is formed in a thickness range of 0.5 nm to 3.0 nm.

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