JP2007165474A - Storage element and storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a storage element capable of stably holding the contents recorded. <P>SOLUTION: A storage layer 3, having a resistance that varies due to the application of a voltage, is held between a first electrode 2 and a second electrode 6, and the storage element 10 with a formed insulating layer 11 having pores is constituted between either of the first electrode 2 or the second electrode 6 and the storage layer 3. Since a place can be prescribed, where a conductive path in the storage layer 3 is formed by pores, dispersion of the resistance value of the storage layer 3 suppressed, and the resistance value can be stabilized. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a memory element capable of recording information and a memory device using the memory element.

  In information equipment such as a computer, a high-speed and high-density DRAM is widely used as a random access memory.

However, a DRAM has a higher manufacturing cost because a manufacturing process is more complicated than a general logic circuit LSI or signal processing used in an electronic device.
The DRAM is a volatile memory in which information disappears when the power is turned off, and it is necessary to frequently perform a refresh operation, that is, an operation of reading, amplifying, and rewriting the written information (data).

Thus, for example, flash memories, FeRAMs (ferroelectric memories), MRAMs (magnetic storage elements), and the like have been proposed as nonvolatile memories whose information does not disappear even when the power is turned off.
In the case of these memories, it is possible to keep the written information for a long time without supplying power.
In addition, in the case of these memories, it is considered that by making them non-volatile, the refresh operation is unnecessary and the power consumption can be reduced accordingly.

However, with the above-described nonvolatile memory, it is difficult to ensure characteristics as a memory element as the memory elements constituting each memory cell are reduced.
For this reason, it is difficult to reduce the element to the limit of the design rule and the limit of the manufacturing process.

Therefore, a new type of storage element has been proposed as a memory having a configuration suitable for downsizing.
This memory element has a structure in which an ionic conductor containing a certain metal is sandwiched between two electrodes.
And by including the metal contained in the ionic conductor in one of the two electrodes, when a voltage is applied between the two electrodes, the metal contained in the electrode becomes an ion in the ionic conductor. The diffusion changes the electrical characteristics such as resistance or capacitance of the ionic conductor.
A memory device can be configured using this characteristic (see, for example, Patent Document 1 and Non-Patent Document 1).

  Specifically, the ionic conductor is made of a solid solution of chalcogenide and metal, and more specifically, made of a material in which Cu, Ag, Zn is dissolved in AsS, GeS, GeSe, and is one of the two electrodes. One electrode contains Cu, Ag, and Zn (see Patent Document 1).

  In addition, as a method for manufacturing this memory element, an ion conductor made of chalcogenide is deposited on a substrate, and then an electrode containing a metal is deposited on the ion conductor, so that light having an energy larger than the optical gap of the ion conductor is obtained. There has been proposed a method of forming an ionic conductor containing a metal by a method in which a metal is diffused into an ionic conductor to form a solid solution by irradiating or heat.

Furthermore, various non-volatile memories using crystalline oxide materials have been proposed. For example, Cr-doped SrZrO ₃ crystalline material is sandwiched between a lower electrode made of SrRuO ₃ or Pt and an upper electrode made of Au or Pt. In a device having an elliptical structure, a memory is reported in which resistance is reversibly changed by application of voltages having different polarities (see Non-Patent Document 2). However, the details such as the principle are unknown.
Special Table 2002-536840 Publication Nikkei Electronics 2003.1.20 (page 104) A. Beck et al., Appl. Phys. Lett., 77, (2000), p. 139

  However, in the above-described memory element in which either the upper electrode or the lower electrode contains Cu, Ag, Zn and GeS or GeSe amorphous chalcogenide material is sandwiched between the electrodes, the upper electrode and the lower electrode face each other. The movement of the metal ions occurs at an unspecified portion of the portion to be moved, and the amount of the moving metal ions is not constant.

For this reason, it is difficult to control the resistance value of the memory element to be substantially constant when a voltage is applied to the memory element to change from the high resistance state to the low resistance state.
Therefore, for example, the resistance value may fluctuate in a high-temperature environment or during long-term storage, and recorded information cannot be stably held.

  In order to solve the above-described problems, the present invention provides a storage element that can stably hold recorded contents and a storage device using the storage element.

The memory element of the present invention is configured by sandwiching a memory layer whose resistance is changed by voltage application between a first electrode and a second electrode, and stores either the first electrode or the second electrode. An insulating layer having pores is formed between the layers.
A memory device of the present invention includes the memory element of the present invention, a wiring connected to the first electrode side, and a wiring connected to the second electrode side, and a large number of memory elements are arranged. Is.

According to the configuration of the memory element of the present invention described above, an insulating layer having a pore is formed between one of the first electrode and the second electrode and the memory layer. Since the position where the conductive path is formed in the storage layer can be defined, it is possible to stabilize the resistance value by suppressing the variation in the resistance value of the storage layer after recording information.
As a result, the resistance value of the storage layer can be stably held, so that recorded information can be stably held.
In addition, since a conductive path is formed at a specified position in the storage layer (that is, a partial region in the storage layer), the resistance value of the storage layer can be changed with a small amount of current, The current required for recording can be reduced.

  According to the configuration of the memory device of the present invention described above, the memory element of the present invention, the wiring connected to the first electrode side, and the wiring connected to the second electrode side, Since a large number of are arranged, information can be recorded by flowing current from the wiring to the storage element.

According to the present invention described above, the recorded information can be stably held, so that the recorded information can be stably held even when used in a high temperature environment or when storing long-term data. can do.
Therefore, the reliability of the memory element can be improved.
Furthermore, since information is recorded by utilizing a change in the resistance value of the memory element, in particular, a change in the resistance value of the memory layer, even when the memory element is miniaturized, the information is recorded or recorded information. It has the advantage that the holding | maintenance of becomes easy.

  Further, according to the present invention described above, it is possible to reduce the current required for recording in the storage element, and thus it is possible to reduce the power consumption when recording information. In addition, it is possible to easily record information by reducing the amount of current during recording.

Therefore, according to the present invention, a highly reliable storage device can be configured.
In addition, the storage device can be highly integrated (high density) and downsized, and the power consumption of the storage device can be reduced.

As an embodiment of the present invention, a schematic configuration diagram (cross-sectional view) of a memory element is shown in FIG.
In the memory element 10, a lower electrode 2 is formed on a substrate 1 having a high electrical conductivity, for example, a (P ⁺⁺ ) silicon substrate 1 doped with a P-type high concentration impurity. A memory thin film (memory layer) 3 having a relatively high resistance value and an ion source layer 4 containing any element of Cu, Ag, and Zn are formed on the ion source layer 4. An upper electrode 6 is formed and configured to connect to the ion source layer 4 through an opening formed in the insulating layer 5.

For the lower electrode 2, a wiring material used in a semiconductor process, for example, TiW, Ti, W can be used.
When TiW is used for the lower electrode 2, for example, the film thickness may be in the range of 20 nm to 100 nm.

For the memory thin film (memory layer) 3, rare earth oxides (for example, gatrinium oxide), other oxides (SiO ₂ or oxides of transition metal elements) and the like can be used.

  The ion source layer 4 includes CuTe, GeSbTe, CuGeTe, AgGeTe, AgTe, ZnTe, ZnTeTe, CuS containing at least one of Cu, Ag, Zn, and at least one of Te, Se, S chalcogenide elements. , CuGeS, CuSe, CuGeSe, etc., and boron or a rare earth element and silicon can be used to form the ion source layer 4.

The insulating layer 5 includes, for example, a hard-cured photoresist, SiO ₂ or Si ₃ N ₄ commonly used in semiconductor devices, and other materials such as SiON, SiOF, Al ₂ O ₃ , Ta ₂ O ₅ , HfO. ₂ , inorganic materials such as ZrO ₂ , fluorine-based organic materials, aromatic organic materials, and the like can be used.
As with the lower electrode 2, a normal semiconductor wiring material is used for the upper electrode 6.

  In the memory element 10 of the present embodiment, an insulating layer 11 having pores is provided between the lower electrode 2 and the memory thin film (memory layer) 3.

For the insulating layer 11 having pores (pores), for example, SiO ₂ , Si ₃ N ₄ , other materials such as SiON, SiOF, Al ₂ O ₃ , Ta ₂ O ₅ , HfO ₂ , ZrO _2, etc. Materials, fluorine organic materials, aromatic organic materials, and the like can be used.

As a method for forming the insulating layer 11 having pores, for example, there is a method in which Al is anodized to form Al ₂ O ₃ and pores are simultaneously formed during the anodic oxidation. By performing anodization, as shown in a schematic configuration diagram in FIG. 2, pores 12 substantially perpendicular to the film surface are formed in an insulating layer (Al ₂ O ₃ layer) 11 having cellular grains. .
As another method of forming the insulating layer 11 having pores, there is a method of forming pores by a nanodot stamp or the like after forming a continuous (uniform) insulating layer 11 in advance. Further, an electron beam drawing method may be used. When these forming methods are employed, the cellular grains as shown in FIG. 2 are not formed, and pores are formed in the uniform insulating layer 11.

  The position of the current path formed in the memory thin film (memory layer) 3 can be regulated by the pores of the insulating layer 11 having pores, as will be described in detail later.

  The storage element 10 of this embodiment can be operated as follows to store information.

First, for example, a positive potential (+ potential) is applied to the ion source layer 4 containing Cu, Ag, and Zn, and a positive voltage is applied to the memory element 10 so that the upper electrode 6 side becomes positive. . As a result, Cu, Ag, Zn is ionized from the ion source layer 4 and diffuses in the memory thin film 3, and is combined with electrons on the lower electrode 2 side to deposit, or in the memory thin film 3. Stays diffuse.
Then, a current path containing a large amount of Cu, Ag, Zn is formed inside the memory thin film 3, or a large number of defects due to Cu, Ag, Zn are formed inside the memory thin film 3, whereby the memory thin film The resistance value of 3 becomes low. Each layer other than the memory thin film 3 originally has a lower resistance value than the resistance value of the memory thin film 3 before recording. Therefore, by reducing the resistance value of the memory thin film 3, the resistance value of the memory element 10 as a whole is reduced. Can also be lowered.

  After that, when the positive voltage is removed and the voltage applied to the memory element 10 is eliminated, the resistance value is kept low. As a result, information can be recorded (written) (recording process).

On the other hand, for example, a negative potential (−potential) is applied to the ion source layer 4 containing Cu, Ag, and Zn, and a negative voltage is applied to the memory element 10 so that the upper electrode 6 side becomes negative. . As a result, Cu, Ag, and Zn constituting the current path or impurity level formed in the memory thin film 3 are ionized, move in the memory thin film 3, and return to the ion source layer 4 side.
Then, current paths or defects due to Cu, Ag, and Zn disappear from the memory thin film 3, and the resistance value of the memory thin film 3 increases. Since each layer other than the memory thin film 3 originally has a low resistance value, the resistance value of the memory element 10 as a whole can be increased by increasing the resistance value of the memory thin film 3.
After that, when the negative voltage is removed and the voltage applied to the memory element 10 is eliminated, the resistance value is kept high. This makes it possible to erase the recorded information (erase process).

  By repeating such a process, it is possible to repeatedly record (write) information on the memory element 10 and erase the recorded information.

  For example, if a state with a high resistance value is associated with information “0” and a state with a low resistance value is associated with information “1”, the information recording process by applying a positive voltage changes from “0” to “ It can be changed from “1” to “0” in the process of erasing information by applying a negative voltage.

  The memory thin film 3 generally has a high resistance in the initial state before recording. However, the memory thin film 3 exhibits a low resistance in the initial recording state by plasma treatment, annealing treatment, or the like in the process step. It doesn't matter.

  According to the configuration of the memory element 10 of the above-described embodiment, by adopting a configuration in which the memory thin film 3 and the ion source layer 4 are sandwiched between the lower electrode 2 and the upper electrode 6, for example, When a positive voltage (+ potential) is applied to the ion source layer 4 side so that the upper electrode 6 side becomes positive, a current path containing a large amount of Cu, Ag, and Zn is formed in the memory thin film 3. In addition, by forming a large number of defects due to Cu, Ag, and Zn in the memory thin film 3, the resistance value of the memory thin film 3 is lowered, and the resistance value of the entire memory element 10 is lowered. Then, by stopping the application of the positive voltage so that no voltage is applied to the memory element 10, the state in which the resistance value is lowered is maintained, and information can be recorded.

  Further, for example, a negative voltage (−potential) is applied to the ion source layer 4 with respect to the storage element 10 in the state after recording, so that the upper electrode 6 side becomes negative. As a result, current paths or defects due to Cu, Ag, and Zn formed in the memory thin film 3 disappear, the resistance value of the memory thin film 3 increases, and the resistance value of the entire memory element 10 increases. Become. Then, by stopping the application of the negative voltage so that no voltage is applied to the memory element 10, the state in which the resistance value is increased is maintained, and the recorded information can be erased.

  Since information is stored by utilizing a change in the resistance value of the memory element 10, particularly a change in the resistance value of the memory thin film 3, even when the memory element 10 is miniaturized, information recording is performed. And storage of recorded information becomes easy.

Furthermore, according to the memory element 10 of the present embodiment, the position of the current path formed in the memory thin film (memory layer) 3 can be defined by the pores of the insulating layer 11 having pores. Therefore, it is possible to stabilize the resistance value by suppressing variations in the resistance value of the memory thin film (memory layer) 3 after information recording.
Thereby, it is possible to stably hold the recorded information by stably holding the resistance value of the memory thin film (memory layer) 3. For example, when used in a high temperature environment or when storing long-term data Also, the recorded information can be stably held.
Therefore, the reliability of the memory element 10 can be improved.

Further, since the position of the current path formed in the memory thin film (memory layer) 3 can be defined as described above, the defined position in the memory thin film (memory layer) 3 (that is, the memory thin film). 3), a current path is formed. Thereby, the resistance value of the memory thin film (memory layer) 3 can be changed with a small amount of current, and the current required for recording in the memory element 10 can be reduced.
As described above, the current required for recording in the memory element 10 can be reduced, so that power consumption when recording information can be reduced. In addition, it is possible to easily record information by reducing the amount of current during recording.
Since the current required for recording in the storage element 10 can be reduced, for example, the time required for recording can be shortened, and the amount of current when reading information can be reduced to read information. Can be easily performed.

Further, according to the memory element 10 of the present embodiment, the lower electrode 2, the memory thin film 3, the ion source layer 4, and the upper electrode 6 can all be made of a material that can be sputtered. For example, sputtering may be performed using a target having a composition suitable for the material of each layer.
In addition, it is possible to continuously form a film by exchanging the target in the same sputtering apparatus.

That is, the memory element 10 can be manufactured by a material or a manufacturing method (film formation by sputtering of an electrode material, a normal etching process such as plasma or RIE) used in a normal MOS logic circuit manufacturing process. .
Therefore, the memory element 10 can be easily manufactured by a relatively simple method.

The memory element 10 of FIG. 1 can be manufactured as follows, for example.
First, a lower electrode 2 such as a TiW film is deposited on a substrate 1 having a high electrical conductivity, such as a silicon substrate doped with a high concentration of P-type impurities.
Next, an Al film is formed so as to cover the lower electrode 2, and anodization is performed to change Al to Al ₂ O ₃ to form the insulating layer 11, and at the same time, pores 12 are formed in the insulating layer 11. To do.
Next, the oxidized surface of the lower electrode 2 is etched through the pores 12 to remove the thin oxide film and obtain an electrically good surface.
Subsequently, a memory thin film 3, for example, a gadolinium oxide (Gd ₂ O ₃ ) film is formed, and then an ion source layer 4, for example, a CuTeGe film is formed.
Thereafter, the insulating layer 5 is formed so as to cover the ion source layer 4, but a part of the insulating layer 5 is removed by photolithography to form a contact portion to the ion source layer 4.
Subsequently, for example, a W film is formed as the upper electrode 6 by, for example, a magnetron sputtering apparatus.
Thereafter, the W film is patterned by, for example, plasma etching. Besides plasma etching, patterning can be performed using an etching method such as ion milling or RIE (reactive ion etching).
In this way, the memory element 10 shown in FIG. 1 can be manufactured.

A storage device (memory device) can be configured by arranging a large number of the memory elements 10 of the above-described embodiment in a matrix.
For each memory element 10, a wiring connected to the lower electrode 2 side and a wiring connected to the upper electrode 6 side are provided. For example, each memory element 10 is arranged near the intersection of these wirings. What should I do?

  Specifically, for example, the lower electrode 2 is formed in common in the memory cell in the row direction, the wiring connected to the upper electrode 6 is formed in common in the memory cell in the column direction, and a potential is applied. A memory cell to be recorded is selected by selecting the lower electrode 2 and wiring through which a current flows, and a current is passed through the memory element 10 of this memory cell to record information and erase the recorded information. be able to.

The memory element 10 according to the above-described embodiment can easily record information and read information, reduce power consumption, and shorten the time required for recording.
Therefore, by configuring a storage device using this storage element 10, it is possible to easily record information and read information, reduce the power consumption of the entire storage device, and reduce the power consumption of the storage device. Can be configured.
Further, even when the memory element 10 according to the above-described embodiment is miniaturized, it is easy to record information and hold the recorded information. Therefore, the storage device is integrated (high density) and downsized. Can be achieved.

  Furthermore, since the memory element 10 of the above-described embodiment can be easily manufactured by a simple method, the manufacturing cost of the memory device can be reduced and the manufacturing yield can be improved.

In the memory element 10 of the above-described embodiment, the ion source layer 4 is laminated on the memory thin film 3, but the memory thin film is laminated on the ion source layer by reversing the lamination order. It doesn't matter.
In the memory element 10 of the above-described embodiment, the insulating layer 11 having pores is provided between the electrode 2 and the memory thin film (memory layer) 3, but the ion source layer and the memory thin film ( It may be provided between the storage layer and the storage layer.
Note that the insulating layer having pores is preferably in contact with the memory thin film (memory layer) regardless of the lower layer or the upper layer of the memory thin film (memory layer). Even if it is not in contact with the memory thin film (memory layer), when the film between them is thin, the effect of defining the conductive path in the memory thin film is obtained by the pores, but the effect is inferior to that in contact with the memory thin film Because.

Furthermore, in the insulating layer having pores, the inside of the pores can be left hollow, but the resistance value can be reduced by putting a conductive material in the pores.
As the conductive material put into the pores in this way, for example, an electrode material used for the lower electrode 2 can be used.

By using the memory element of the present invention and arranging a large number of memory elements, for example, in a column shape or a matrix shape, a memory device (memory device) can be configured.
In addition, a memory cell is configured by connecting a MOS transistor or a diode for selecting an element to each memory element as necessary.
Further, it is connected to a sense amplifier, an address recorder, a recording / erasing / reading circuit, etc. via wiring.

  The memory element of the present invention can be applied to various memory devices. For example, a so-called PROM (programmable ROM) that can be written only once, an electrically erasable EEPROM (electrically erasable ROM), or a so-called RAM (random access memory) that can be recorded / erased / reproduced at high speed. It is possible to apply any memory form such as (memory).

Subsequently, as another embodiment of the present invention, FIG. 3 shows a schematic configuration diagram (a cross-sectional view of a main part) of a memory device (memory device) using a memory element.
This memory device (memory device) is configured by arranging a large number of memory elements 20 constituting memory cells in an array.
A memory element 20 of each memory cell is configured by laminating an insulating layer 11 having pores, a memory thin film (memory layer) 3, and an ion source layer 4 between a lower electrode 2 and an upper electrode 6. 1 has the same laminated structure as the memory element 10 shown in FIG.
The lower electrode 2 is constituted by a plug layer formed by being embedded in the insulating layer 8.

  In the present embodiment, in particular, the memory element 20 constituting each memory cell shares each layer of the insulating layer 11 having pores, the memory thin film (memory layer) 3, the ion source layer 4, and the upper electrode 6. ing. In other words, each memory element 20 is composed of the insulating layer 11 having pores, the memory thin film (memory layer) 3, the ion source layer 4, and the upper electrode 6 in the same layer.

The upper electrode 6 formed in common is the plate electrode PL. Through the plate electrode PL, the same potential can be applied to the memory element 20 of each memory cell.
On the other hand, the lower electrode 2 is individually formed for each memory cell, and each memory cell is electrically isolated. The memory element 20 of each memory cell is defined at a position corresponding to each lower electrode 2 by the lower electrode 2 formed individually for each memory cell.

Here, FIGS. 4A to 4C show one embodiment of a method for forming the insulating layer 11 having pores in this embodiment.
FIG. 4A shows a state in which the lower electrode 2 made of a plug layer embedded in the insulating layer 8 is formed. Such a lower electrode 2 can be formed by a conventionally known method.
If necessary, the oxidized surface of the lower electrode 2 is etched to remove the thin oxide film and obtain an electrically good surface.
Next, as shown in FIG. 4B, an Al film 21 is formed on the surface by sputtering or the like.
Further, by performing an anodic oxidation process on the Al film 21, the insulating layer 11 having pores can be formed as shown in FIG. 4C.

  In the present embodiment, the base of the insulating layer 11 having pores is the insulating layer 8 and the lower electrode 2, but the insulating layer 11 having pores is also in good condition on the insulating layer 8. Can be formed.

According to the configuration of the memory device (memory device) of the present embodiment described above, the insulating layer 11, the memory thin film (memory layer) 3, the ion source layer 4, and the upper electrode 6 of the memory element 20 constituting each memory cell. Is formed in common, and in the process of patterning each of the layers 11, 3, 4 and 6 in manufacturing the memory device, the entire portion to be formed may be processed so as to remain in the state of the art. There is no need to use the ultra-fine processing technology.
As a result, it is not necessary for the ground of each layer 11, 3, 4, 6 to be a highly flat surface such as the surface of a semiconductor substrate, and each layer 11, 3, 4, 6 can be easily manufactured by a conventional manufacturing technique. Thus, the memory device can be easily manufactured with a high yield.
Therefore, even if the size of the memory cell is reduced, the memory device can be easily manufactured with a high yield, so that the density of the memory cell can be increased. As a result, the storage capacity of the storage device can be increased or downsized.

In addition, even when using new materials that are inexperienced in conventional semiconductor processes, it is possible to manufacture memory devices easily and with high yield, so the time required to develop processing technology can be significantly reduced. It is.
Furthermore, even when a new material is used, it is possible to cope with an inexpensive old-generation lithography apparatus and manufacturing process, so that the manufacturing cost of the storage device can be greatly reduced.

  The factors that determine the density of memory cells and the manufacturing yield of the memory device are determined by the materials, lithography process, etching process, and polishing process used in conventional semiconductor mass production technology, regardless of the configuration of the memory element 20. Therefore, the conventional technique can be easily used.

In the present invention, the memory element is not limited to the configuration of the memory element 10 shown in FIG. 1 or the memory element 20 shown in FIG. 3, and other configurations are possible.
For example, a configuration in which the ion source layer also serves as an electrode, a configuration in which an element (Cu, Ag, Zn) used in the ion source layer is included in the memory thin film instead of providing the ion source layer, and the like are conceivable.
In addition to the memory element having a memory element made of a metal element (Cu, Ag, Zn) that is easily ionized and an oxide or the like, there are various configurations as a memory element in which the resistance value of the memory layer changes.
The present invention can be applied to memory elements having other configurations.

  Next, the memory element of the present invention was actually manufactured and the characteristics were examined.

(Example)
The memory element 10 of the embodiment shown in FIG. 1 was produced.
First, a TiW film having a thickness of 100 nm was deposited as a lower electrode 2 on a substrate 1 having high electrical conductivity, for example, a silicon substrate doped with a high concentration of P-type impurities by sputtering.

Next, an Al film is deposited to a thickness of 15 nm by sputtering covering the lower electrode 2, and anodization is performed to change the Al to Al ₂ O ₃ to form the insulating layer 11 and simultaneously to the insulating layer. The pores 12 were formed in 11.

Specifically, the anodizing treatment was performed as follows.
First, about half of pure water was put into a 500 ml beaker, 15 g of phosphoric acid and 0.5 g of sulfuric acid were added, and further pure water was added to make a treatment solution of 500 ml. The treatment liquid was stirred using a rotary stirring device.
Next, a wafer having an Al film deposited on the outermost surface and a high-purity aluminum plate were each immersed in the treatment liquid.
Further, a direct current power source was connected so that the wafer became an anode and the aluminum plate became a cathode.
Electrolysis was performed for 20 minutes by applying a voltage of 10 V with a DC power source. Thereby, an anodic oxide film was formed on the surface of the anode wafer.
Thereafter, the power was turned off, the wafer was taken out and thoroughly washed with pure water.
In this way, an insulating layer (aluminum oxide layer) 11 having pores 12 was formed.

Next, a gadolinium oxide layer having a thickness of 25 nm is formed as the memory thin film 3 on the insulating layer 11 having pores, and a Cu ₅₀ Te ₃₅ Ge ₁₅ film is formed as the ion source layer 4 with a thickness of 20 nm. did.

Next, a photoresist was formed so as to cover the ion source layer 4, and then exposure and development were performed by photolithography to form an opening (through hole) in the photoresist. The size of the opening (through hole) was 0.7 μm in length and 0.7 μm in width.
Thereafter, annealing was performed in vacuum at 270 ° C. to alter the photoresist, and the insulating layer 5 was formed as a hard-cure resist that is stable with respect to temperature, etching, and the like. Note that the hard-cure resist is used for the insulating layer 5 because it can be easily formed experimentally. In the case of manufacturing a product, another material (such as a silicon oxide film) is used for the insulating layer 5. May be good.

Further, an upper electrode 6 connected to the ion source layer 4 through the opening formed in the insulating layer 5 was formed by depositing a W film with a thickness of 100 nm on the insulating layer 5.
Thereafter, the upper electrode 6 deposited on the insulating layer 5 made of a hard-cure resist was patterned by a photolithography technique using a plasma etching apparatus.
In this way, the memory element 10 having the structure shown in FIG. 1 was produced and used as the memory element 10 of the example.

(Comparative example)
As a comparative example for the present invention, a memory element 50 having the configuration shown in FIG. 5 was produced.
The memory element 50 shown in FIG. 5 has a memory thin film (memory layer) 3 directly formed on the lower electrode 2 without providing the insulating layer 11 having pores in the configuration of the memory element 10 shown in FIG. It is the formed structure.
The method of forming each layer of the memory element 50 was made the same as each layer of the memory element 10 of the example, and the memory element 50 of the comparative example was manufactured.

  By the above-described manufacturing method, a large number of memory elements 10 of the example were formed on the wafer, and a large number of memory elements 50 of the comparative example were formed on another wafer.

(Measurement of resistance change due to heat treatment)
In order to evaluate the characteristics, the change in resistance value due to heat treatment was measured.
First, four memory elements were selected from the memory element 10 of the example and the memory element 50 of the comparative example formed on each wafer.
For these memory elements, a voltage of 1.5 V is applied between the lower electrode 2 and the upper electrode 6 so that the upper electrode 6 is at a positive potential, so that a write process, that is, a high resistance state to a low resistance state is applied. A record of transition to the state was made.
Then, the resistance value of the memory element after the writing process was measured.
Subsequently, each wafer was heat-treated at 140 ° C. for 12 hours in a vacuum.
And the resistance value of the memory element after this heat treatment was measured.

  Table 1 shows the ratio of the resistance value before and after the heat treatment of each memory element as the measurement result.

From Table 1, in the case of the memory element 50 of the comparative example, the resistance value in the low resistance state is changed to high resistance by the heat treatment.
On the other hand, in the case of the memory element 10 of the example, it was confirmed that almost no change in the resistance value due to the heat treatment occurred and the record was retained.
That is, with the configuration of the present invention, it is possible to improve the retention characteristics of recorded information.

  The present invention is not limited to the above-described embodiment, and various other configurations can be taken without departing from the gist of the present invention.

It is a schematic block diagram (sectional drawing) of the memory element of one embodiment of this invention. It is a schematic block diagram of the insulating layer which has a pore. It is a schematic block diagram (sectional drawing) of the memory | storage device of other embodiment of this invention. FIGS. 4A to 4C are manufacturing process diagrams illustrating a method for forming an insulating layer having pores when the memory device of FIG. 3 is manufactured. It is a schematic block diagram (sectional drawing) of the memory element of a comparative example.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Substrate, 2 Lower electrode, 3 Memory thin film (memory layer), 4 Ion source layer, 5, 8 Insulating layer, 6 Upper electrode, 10, 20 Memory element, 11 (having pores) Insulating layer, 12 pores

Claims (7)

A memory layer whose resistance is changed by voltage application is sandwiched between the first electrode and the second electrode,
A memory element, wherein an insulating layer having pores is formed between one of the first electrode and the second electrode and the memory layer.   The memory element according to claim 1, wherein the insulating layer is made of aluminum oxide.   The memory element according to claim 2, wherein the insulating layer is formed by anodization of aluminum.   The memory element according to claim 1, wherein the insulating layer is in contact with the memory layer.   The memory element according to claim 1, wherein the pores of the insulating layer are filled with a conductive material.   The memory element according to claim 1, wherein an ion source layer containing any element selected from Cu, Ag, and Zn is provided in contact with the memory layer. A memory layer whose resistance is changed by voltage application is sandwiched between the first electrode and the second electrode,
A memory element in which an insulating layer having pores is formed between any one of the first electrode and the second electrode and the memory layer;
Wiring connected to the first electrode side;
A wiring connected to the second electrode side,
A storage device comprising a large number of the storage elements.

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