JP4543071B2 - Delay device - Google Patents

Description

  The present invention relates to a delay device, and more particularly to a delay device having an additional circuit that applies a predetermined voltage to the output of a delay element.

  FIG. 1 shows a form of a conventional delay device D12. The delay device D12 includes a plurality of delay elements DL connected in series. The input transmission signal is delayed by each delay element DL. Td indicates a delay time delayed by the delay device D12.

FIG. 2 shows the form of the power supply current flowing through the delay device D12 of FIG. When a single pulse signal is input to the delay device D12 as shown in A, the power supply current applied to the delay element DL fluctuates, and a bursty power supply current as shown in B flows. The time during which the power supply current flows is equal to the delay time Td. When a continuous pulse signal is input to the delay device D12 as shown in C, the burst power supply current flows through the delay device D12 by the pulse signal first input as shown in D, and the next A new burst-shaped power supply current flows to the delay device D12 by the pulse signal. Thus, even when the power supply voltages of two or more delay elements DL change simultaneously, the magnitude of the power supply current flowing through the entire delay device D12 changes as indicated by E. Due to the fluctuation of the power supply current, the power supply voltages V _DD and V _SS of the delay device D12 fluctuate, which causes a decrease in the accuracy of the delay time of the delay device D12.

  FIG. 3 shows another form of the conventional delay device D12. The delay device D12 includes a plurality of selectors SEL connected in series, and a delay element DL that delays a transmission signal input to the delay device D12 and applies the signal to the selector SEL. The delay element DL has one or a plurality of inverters INV connected in series. The selector SEL selects and outputs one of the signal that has passed through the delay element DL and the signal that has not passed through the delay element DL. Depending on the selection of the selector SEL, the timing at which the power supply power is consumed in the delay device D12 varies. For example, when the output from the delay element DL is selected in all the selectors SEL, since the transmission signal passes through the delay device D12 at a slow speed, the most output side selector SEL consumes the power supply power. The selector SEL also consumes power. That is, the power supply is consumed at two or more places of the delay device D12. Therefore, since the power supply voltage of the delay device D12 differs between when the power supply current fluctuates at two or more places and when the power supply current fluctuates at one place, the accuracy of the delay time is lowered.

  FIG. 4 shows a circuit electrically equivalent to the delay element DL of FIG. A wiring capacitance CL is generated in the signal line LIN connecting the drive circuit DR and the driven circuit RC, and an input capacitance CG is formed at the input end of the driven circuit RC. The input capacitance CG is proportional to the number of driven circuits RC to be connected, and the wiring capacitance CL is proportional to the length of the signal line LIN. As the input capacitance CG and the wiring capacitance CL increase, a larger current is required to pass a signal through the delay device D12. If a larger current is used, the change in the power supply current shown in E of FIG. 2 increases, and the accuracy of the time for which the delay device D12 delays decreases.

Accordingly, an object of the present invention is to provide a delay device that can solve the above-described problems. This object is achieved by a combination of features described in the independent claims. The dependent claims define further advantageous specific examples of the present invention.

In order to solve the above problems, one aspect of the present invention is a delay device that delays an input transmission signal, and is connected to a delay element that delays the input transmission signal and an output of the delay element There is provided a delay device including an additional circuit having a logic inversion function, in which an input and an output are connected to a wiring . In one aspect of this embodiment, the delay element is driven by two power supply voltages V _SS and V _DD (V _DD > V _SS ), and the additional circuit has a voltage output from the delay element that is higher than the power supply voltage V _SS . When the voltage is higher than a predetermined voltage that is larger than the power supply voltage V _DD, an increase in the voltage output from the delay element is suppressed, and when the voltage output from the delay element is lower than the predetermined voltage, a decrease in the voltage output from the delay element is suppressed. The additional circuit, when the voltage delay element outputs is higher than the predetermined voltage, the power supply voltage V _DD of the delay elements to the power supply voltage V _SS of the additional circuit flowing a supply current, the output of the delay element is predetermined from the power supply voltage V _DD of the additional circuit if voltage lower than to the power supply voltage V _SS of the delay element may by flowing supply current. In another aspect of the present embodiment, the additional circuit includes a logic gate having a logic inversion function, in which the shorted input / output is connected to the wiring connected to the output of the delay element. In another aspect of the present embodiment, the delay device further includes a plurality of delay elements connected in series and a plurality of additional circuits respectively connected to the outputs of the plurality of delay elements.

In another aspect of the present embodiment, in the delay device, the delay device includes a digital circuit that outputs one of the binary output voltages in accordance with the input voltage, and the additional circuit is an output of the digital circuit. Outputs a voltage that substantially matches the threshold voltage that reverses from one of the binary output voltages to the other. In another aspect of the present embodiment, in the delay device, the additional circuit outputs a voltage approximately at the midpoint between the power supply voltages V _SS and V _DD . In still another aspect of this embodiment, in the delay device, the additional circuit has an output impedance lower than the output impedance of the drive circuit. In still another aspect of the present embodiment, in the delay device, the output impedance of the additional circuit is 1/2 to 1/4 of the output impedance of the drive circuit.

  In still another aspect of the present embodiment, in the delay device, the first logic gate that inverts and outputs the signal input by the additional circuit, and the feedback that connects the input terminal and the output terminal of the first logic gate. It has a circuit. In yet another aspect of the present embodiment, in the delay device, the delay element includes a second logic gate having a logically inverted output, and the first logic gate is substantially equal to the second logic gate. Has a ratio. In still another aspect of this embodiment, in the delay device, the first logic gate includes an inverter, a NAND gate, or a NOR gate. In still another aspect of the present embodiment, in the delay device, the delay element includes a second inverter, and the first inverter has a beta ratio substantially equal to that of the second inverter. In still another aspect of the present embodiment, the delay device further includes a switch unit that selects and outputs one of the outputs of the plurality of delay elements, and the additional circuit has a predetermined voltage with respect to the output of the switch unit. Is output.

In still another aspect of the present embodiment, the delay device includes a plurality of delay elements connected in series, and a selection circuit that selects which of the plurality of delay elements receives the input transmission signal. The additional circuit outputs a predetermined voltage higher than the power supply voltage V _{SS and} lower than the power supply voltage V _{DD with} respect to the input transmission signal. In still another aspect of the present embodiment, in the delay device, a plurality of capacitors that accumulate charges of transmission signals output from the delay elements, and a plurality of capacitors that disconnect or connect each of the plurality of capacitors and the output of the delay elements. The switch is further provided.

In still another aspect of the present embodiment, in the delay device, the capacitor includes a P-type FET, the power supply voltage V _DD is applied to the gate of the P-type FET, and at least one of the drain or the source of the P-type FET is Connected to the gate and the other to the switch. In still another aspect of this embodiment, in the delay device, the capacitor includes an N-type FET, the power supply voltage V _SS is applied to the gate of the N-type FET, and at least one of the drain or the source of the N-type FET is Connected to the gate and the other to the switch.

In still another aspect of the present embodiment, in the delay device, the capacitor includes a P-type FET, the power supply voltage V _DD is applied to the gate of the P-type FET, and the switch includes the drain and source of the P-type FET. Connect or disconnect the delay element. In still another aspect of the present embodiment, in the delay device, the capacitor includes an N-type FET, the power supply voltage V _SS is applied to the gate of the N-type FET, and the switch includes the drain and the source of the N-type FET. Connect or disconnect the delay element. In still another aspect of the present embodiment, in the delay device, the capacitor includes an N-type FET, the power supply voltage V _SS is applied to the drain and source of the N-type FET, and the gate of the N-type FET is connected to the switch. Is done.

In still another aspect of the present embodiment, in the delay device, the capacitor includes an N-type FET, the power supply voltage V _SS is applied to the gate and the substrate of the N-type FET, and the switch is the drain of the N-type FET. And the source and the output of the delay element are connected or disconnected. In still another aspect of the present embodiment, in the delay device, the capacitor includes a P-type FET, the power supply voltage V _DD is applied to the gate and the substrate of the P-type FET, and the switch is the drain of the P-type FET. And the source and the output of the delay element are connected or disconnected. In still another aspect of the present embodiment, in the delay device, the capacitor includes an N-type FET, the power supply voltage V _SS is applied to the drain, source, and substrate of the N-type FET, and the gate of the N-type FET Is connected to the switch.

In still another aspect of the present embodiment, in the delay device, the capacitor has a P-type FET, the power supply voltage V _DD is applied to the drain, source, and substrate of the P-type FET, and the gate of the P-type FET Is connected to the switch. In still another aspect of this embodiment, in the delay device, the additional circuit includes a P-type FET and an N-type FET, and a forward bias voltage is applied to each of the gates of the P-type FET and the N-type FET. The In still another aspect of the present embodiment, in the delay device, the additional circuit includes a voltage source that outputs a predetermined voltage that is higher than the power supply voltage V _{SS and} lower than the power supply voltage V _DD .

  In still another aspect of the present embodiment, in the delay device, the additional circuit further includes a low impedance buffer circuit that lowers the output impedance of the voltage output from the voltage source. In still another aspect of the present embodiment, the delay device includes a blocking unit that blocks a current flowing between the signal line and the additional circuit. In still another aspect of the present embodiment, in the delay device, the additional circuit includes a NAND gate and a feedback circuit in which one input terminal and an output terminal of the NAND gate are connected. In still another aspect of the present embodiment, in the delay device, the NAND gate has a control terminal to which a control signal for cutting off a current flowing between the signal line and the additional circuit is input.

  In still another aspect of the present embodiment, in the delay device, the additional circuit includes a NOR gate and a feedback circuit in which one input terminal and an output terminal of the NOR gate are connected. In still another aspect of the present embodiment, in the delay device, the NOR gate has a control terminal to which a control signal for cutting off a current flowing between the signal line and the additional circuit is input. In still another aspect of the present embodiment, in the delay device, the additional circuit is connected to the end of the signal line. In one aspect of the present invention, the additional circuit has an output impedance that is lower than the output impedance of the drive circuit.

  The above summary of the invention does not enumerate all the necessary features of the present invention, and sub-combinations of these feature groups can also be the invention.

FIG. 5 shows the configuration of the delay device D10 of the present invention. The delay device D10 of the present invention includes a plurality of delay elements DL connected in series as shown in FIG. 5 and a plurality of additional circuits ADC respectively connected to the outputs of the plurality of delay elements DL. The additional circuit ADC can be configured by connecting the full feedback circuit NF to an inverter INV (polarity inverting circuit) formed of a CMOS circuit. The delay element DL outputs one of two power supply voltages V _SS and V _DD (V _DD > V _SS ) according to the input voltage. The additional circuit ADC outputs a voltage approximately at the midpoint between the power supply voltages V _SS and V _DD to the output of the delay element DL. Therefore, when the voltage output from the delay element DL is higher than the midpoint voltage Vc output from the additional circuit ADC, the midpoint voltage Vc is added to the voltage output from the delay element DL, thereby suppressing an increase in voltage. . On the other hand, when the voltage output from the delay element DL is lower than the midpoint voltage Vc output from the additional circuit ADC, the voltage drop is suppressed by adding the midpoint voltage Vc to the voltage output from the delay element DL. . In this way, the midpoint voltage Vc output from the additional circuit ADC reduces fluctuations in the voltage output from the delay element DL.

FIG. 6 shows the waveform of the power supply current flowing through the delay device D10. When a single pulse signal is input to the delay device D10 as shown in A, a burst-like power supply current flows to the delay device D10 as shown in B. Further, since the additional circuit ADC supplies the midpoint voltage Vc to the delay element DL, the through current Ihl flows from the power supply voltage V _DD to the V _{SS of the} delay element DL and the additional circuit ADC. As shown in B, the total power supply current is the sum of the through current Ihl plus the drive current flowing through the delay element DL by the input signal. When the midpoint voltage Vc output from the additional circuit ADC is added to the voltage output from the delay element DL, the variation in the signal voltage is reduced. Smaller than. Even if a continuous pulse signal is input as shown in C, the amplitude of the power supply current consumed by each pulse is small as shown in D, so that the amplitude of the power supply current is smaller than in the conventional case as shown in E. For this reason, since the fluctuation of the power supply voltage of the delay device D10 is reduced, the accuracy of the delay time is increased.

  FIG. 7 shows an embodiment of a delay device D10 according to the present invention. DR, RC, LIN, CL, and CG shown in FIG. 7 respectively indicate a drive circuit, a driven circuit, a signal line, a wiring capacitance, and an input capacitance. The drive circuit DR and the driven circuit RC correspond to the delay element DL shown in FIG. In the present invention, the additional circuit ADC is connected to the signal line LIN. The additional circuit ADC can be configured by connecting the entire feedback circuit NF to an inverter INV (polarity inverting circuit) formed of, for example, a CMOS circuit. When high-speed signal transmission is performed, a signal propagated through the signal line LIN is reflected by the driven circuit RC, and overshoot and undershoot may occur in the signal waveform captured by the driven circuit RC. In order to reduce such overshoot and undershoot, the additional circuit ADC may be connected to the end of the signal line LIN.

FIG. 8 shows an example of a specific circuit structure of the delay device D10. In this example, the drive circuit DR and the driven circuit RC also use an inverter INV configured by a CMOS circuit. The additional circuit ADC can also be configured by connecting the full feedback circuit NF to the inverter INV having a CMOS circuit structure. According to the circuit structure of the additional circuit ADC, the potential of the common connection point J of the input terminal and the output terminal of the inverter INV can be stabilized at the substantially midpoint potential of the power supply voltage V _DD -V _SS . The reason will be described with reference to FIG.

In FIG. 9, a curve Y indicates the DC transfer characteristic (relationship of the output voltage with respect to the input voltage) of the inverter INV. Since the inverter INV has a logic inversion (negative) function, the inverter INV exhibits a right downward characteristic in the vicinity of the logical threshold. Here, in order to constitute the additional circuit ADC according to the present invention, when the input and output terminals are short-circuited (or connected by an element such as a resistor) and the total feedback is applied, the input and output voltages are equal. Therefore, when a straight line X of Vin = Vout is drawn over the curve Y, the output voltage of this circuit becomes equal to the intersection of the straight line X and the curve Y. This intersection is just the point where the output voltage is inverted in the DC transfer characteristic, that is, equal to the logical threshold value of the inverter INV. When the on-resistances of the P-type FET Q _P and the N-type FET Q _N constituting the inverter INV are equal, this intersection point is exactly the midpoint between the power supply voltages V _SS and V _DD .

  Here, for simplicity, the term on-resistance is used, but it actually has non-linearity. In order to express it more accurately, the drain coefficient β is used as an index representing the ease of flow of the drain current of the FET. The drain current coefficient β is a proportional constant determined by the size, aspect ratio, etc. of the MOSFET.

If β of the N-type FET Q _N and P-type FET Q _P is βn and βp, respectively,
βn = (W / Leff) · (εox / Tox) · μn, eff
βp = (W / Leff) · (εox / Tox) · μp, eff

W: gate width, Leff: effective gate length, Tox: gate oxide film thickness, εox: gate oxide film dielectric constant, μn, eff: effective electron mobility, μp, eff: effective hole mobility

If this β is used, the drain current of the MOSFET can be simply expressed as follows.
Id = β {(Vgs−Vt) Vds− (1/2) (Vds ² )}
(Vds ≦ Vgs−Vt)
Id = (1/2) β (Vgs−Vt) ² (Vds> Vgs−Vt)

In the case of silicon, the mobility of holes is about half of the mobility of electrons, so if N-type FET Q _N and P-type FET Q _P are made in the same shape (assuming that the threshold voltages are equal), N-type FET Q _N has A current twice that of P-type FET Q _P flows. The on-resistance of the N-type FET Q _N is half that of the P-type FET Q _P.

In a normal element, it is common that β of the N-type FET Q _N and the P-type FET Q _P are equal or the shapes (W, H) are equal. The ratio of .beta.n of P-type FETs Q _P of .beta.p and N-type _{FETQ N (βR = βn / βp} , beta ratio) when changing 10 times, and generally will change the order of the curve of the curve Y1 and Y2 shown in FIG. 9 . However, Y1 can be, for example, βn> βp, (βR = 10), and Y2 can be βn <βp, (βR = 0.1) (βn, βp are respectively N-type FET Q _N and P-type FET Q _P. Drain current coefficient). In this case, the inverter INV constituting the driven circuit RC also sets the beta ratio of the N-type FET Q _N and the P-type FET Q _{P in} the same manner as the additional circuit ADC, thereby setting the threshold voltage at which the driven circuit RC is inverted to the power supply voltage. It can be matched with the midpoint voltage Vc of V _DD -V _SS . Accordingly, by setting the relationship between the inverter INV constituting the additional circuit ADC and the inverter INV constituting the driven circuit RC to the above-described relationship (generally said to have the same beta ratio), the driven circuit RC is set. Receives a signal sent from the drive circuit DR around its threshold voltage.

FIG. 10 shows the power supply current Ih or Il flowing in the drive circuit DR and the additional circuit ADC in the delay device D10 of FIG. 8, and the through current Ihl flowing in the drive circuit DR. FIG. 10A shows a state where the input voltage Vin of the drive circuit DR is lower than the midpoint voltage Vc. When the input voltage Vin of the drive circuit DR is less than the midpoint voltage Vc, the power supply current Ih flows from the power supply voltage V _DD of the drive circuit DR to supply voltage V _SS of the addition circuit ADC. Further, a through current Ihl flows from the power supply voltage V _DD of the drive circuit DR to the power supply voltage V _SS of the drive circuit DR. FIG. 10B shows a state where the input voltage Vin of the drive circuit DR is higher than the midpoint voltage Vc. When the input voltage Vin of the drive circuit DR is higher than the midpoint voltage Vc, the power supply current Il flows from the power supply voltage V _DD of the addition circuit ADC to the power supply voltage V _SS of the drive circuit DR. Further, a through current Ihl flows from the power supply voltage V _DD of the drive circuit DR to the power supply voltage V _SS of the drive circuit DR.

FIG. 11 shows the power supply currents Ih and Il and the through current Ihl flowing through the delay device D10 shown in FIG. Figure 11 (A) shows the relationship between the through current Ihl from the power supply voltage V _DD at the input voltage Vin and the driving circuit DR of the drive circuit DR to supply voltage V _SS. On the other hand, FIG. 11B shows the relationship between the input voltage Vin of the drive circuit DR, the power supply current Ih, and the power supply current Il. In FIG. 11A, when the input voltage Vin of the drive circuit DR is the midpoint voltage Vc, the midpoint voltage Vc is applied to the gates G of the two FETs of the drive circuit DR, so that the through current Ihl becomes the maximum value. Further, since the input voltage Vin of the drive circuit DR and the midpoint voltage Vc output from the additional circuit ADC are equal, no current flows between the drive circuit DR and the additional circuit ADC as shown in FIG.

Further, when the input voltage Vin of the drive circuit DR is less than the midpoint voltage Vc in FIG. 11 (A) the reverse bias voltage is applied to the gate G of the N-type FETs Q _N of the drive circuit DR, P-type of the driving circuit DR A forward bias voltage is applied to the gate G of the FET Q _P. Since high reverse bias voltages, the gate G of the N-type FETs Q _N of the drive circuit input voltage Vin is the midpoint voltage Vc from as low driving circuit DR of the DR is applied through current Ihl decreases. The input voltage voltage Vin is output from the P-type FETQ drive circuit DR and a high forward bias voltage is applied to the gate G of the _P driving circuit DR as lower than the midpoint voltage Vc of the drive circuit DR is higher than the midpoint voltage Vc Get higher. Therefore, the power supply current Ih flowing from the power supply voltage V _DD of the drive circuit DR to supply voltage V _SS of the addition circuit ADC increases.

Further, when the input voltage Vin of the drive circuit DR is higher than the midpoint voltage Vc in FIG. 11 (A) the reverse bias voltage is applied to the gate G of the P-type FETs Q _P of the drive circuit DR, N of the driving circuit DR forward bias voltage is applied to the gate G of the type FETs Q _N. Since high reverse bias voltages, the gate G of the P-type FETs Q _P of the input voltage Vin is the midpoint voltage Vc higher driving circuit than DR of the driver circuit DR is applied through current Ihl decreases. The input voltage Vin is the midpoint voltage Vc from higher driving circuit DR N-type FETs Q _N midpoint voltage Vc addition circuit ADC with high forward bias voltage is applied to the gate G to the output of the drive circuit DR driver circuit DR becomes higher than the output voltage. Therefore, the power supply current Il flowing from the power supply voltage V _DD of the additional circuit ADC to the power supply voltage V _SS of the drive circuit DR increases.

  FIG. 11C shows the relationship between the input voltage Vin of the drive circuit DR and the sum of the through current Ihl and the power source current Ih or Il. The sum of the through current Ihl and the power supply current Ih and the sum of the through current Ihl and the power supply current Il are substantially constant with respect to the input voltage Vin of the drive circuit DR. Therefore, when the additional circuit ADC outputs the midpoint voltage Vc with respect to the output of the drive circuit DR, the fluctuation of the power supply current is reduced.

FIG. 12 shows an equivalent circuit of the delay device D10 shown in FIG. The drive circuit DR can be equivalently represented by a switch SW. R _OUT represents the output impedance of the drive circuit DR. In FIG. 9, the DC resistance of the signal line LIN is omitted. RM represents an equivalent resistor equal to the output impedance of the additional circuit ADC. That is, the additional circuit ADC can be represented as a circuit connected to the midpoint voltage V _C through the equivalent resistor RM having a resistance value R _T. When the switch SW is switched to the contact A side in the drive circuit DR, the power supply voltage V _DD is applied to the signal line LIN through the output impedance R _OUT . At this time, a current I ₁ flows through the impedance _RT of the equivalent resistor RM, and a voltage higher than the midpoint voltage V _C is generated at the common connection point J. When this voltage Vc + _{E 1,} the voltage _{E 1} is
E ₁ = (V _DD −V _C ) R _T / (R _T + R _OUT )

It is represented by On the other hand, when the switch SW is switched to the contact B side in the drive circuit DR, the power supply voltage V _SS is applied to the signal line LIN. Therefore, at this time, the current I ₂ flows through the impedance _RT of the additional circuit ADC, and the voltage at the common connection point J swings to the negative side by E ₂ from the midpoint potential V _C. This voltage E ₂ is E ₂ = (V _SS −V _C ) R _T / (R _T + R _OUT )
It is represented by

FIG. 13 shows the outputs of the additional circuit ADC and the driven circuit RC shown in FIG. The resistance value R _T of the equivalent resistor RM of the additional circuit ADC shown in FIG. 12 is a small value and R _T << R _OUT . Therefore, the amplitudes E ₁ and E ₂ of the signal generated at the common connection point J are very small values (FIG. 13A). However, since the driven circuit RC operates using the midpoint potential V _C as the threshold value for the inversion operation, the voltages E _A and E _B existing within the amplitude range of the voltages E ₁ and E ₂ generated at the common connection point J. The reversing operation is reliably performed (FIG. 13B). Therefore, the driven circuit RC inverts as soon as the potential at the common connection point J slightly crosses the midpoint voltage V _C , the sum of the wiring capacitance CL and the input capacitance CG is large, and is delayed from the potential change of the signal line LIN. Even if there is, the output of the driven circuit RC can be transmitted with a waveform with almost no waveform distortion, as shown in FIG. 13C.

The voltages E ₁ and E ₂ are a function of R _T and R _OUT as shown in the above equation. The smaller the value of R _T, the voltage _{E 1} and _{E 2} is small. However, the driven circuit RC has a threshold voltage, and the value of _RT must be determined within the sensitivity range of the signal of the driven circuit RC. The maximum input voltage at which the driven circuit RC can output a stable L or H value when the input is L is V _thL, and when the input is H, the driven circuit RC is stable H or Let V _thH be the minimum input voltage that can output the value of L. When the input is gradually increased from L, the input voltage when the output of the driven circuit RC starts to change substantially is V _thL, and when the input is gradually decreased from H, the output of the driven circuit RC is The input voltage when V substantially starts to change may be V _thH . For example, the input voltage V _thH of the driven circuit RC is about V _C + (V _DD −V _C ) × 0.2, and similarly the input voltage V _thL is about V _C + (V _SS −V _C ) × 0.2. , The ratio of R _T and R _OUT is preferably (1) :( 4 or less) from the equations of voltages E ₁ and E ₂ . The value obtained by dividing _RT by _ROUT is more preferably between 1/2 and 1/4.

In this specification, the term “midpoint voltage” does not necessarily mean only the central voltage between the power supply voltages V _DD and V _SS . As described with reference to FIG. 9, the midpoint voltage Vc means any voltage between the power supply voltages V _DD and V _SS depending on the value of the beta ratio, and may vary from the center voltage.

  FIG. 14 shows another embodiment of the delay device D10. FIG. 14A shows the configuration of the delay device D10, and FIG. 14B shows the waveform of the power supply current flowing through the delay device D10. The delay device D10 includes a plurality of delay elements DL connected in series, a switch unit SU that selects and outputs one of the outputs of the delay element DL according to the selection signal SLS, and a midpoint with respect to the output of the switch unit SU The circuit includes an additional circuit ADC that outputs the voltage Vc, and an inverter INV that outputs the output of the switch unit SU to the outside of the delay device D10. The switch unit SU includes a plurality of switches SW that connect or disconnect each output of the delay element DL to the inverter INV. The delay element DL delays the input transmission signal and supplies it to the next delay element DL. The transmission signal can be delayed for a desired time by supplying the selection signal SLS to the switch unit SU and selecting one of the outputs of the delay element DL. Further, since the additional circuit ADC outputs the midpoint voltage Vc with respect to the output of the switch unit SU, the fluctuation of the power supply voltage can be reduced and the accuracy of the delay time can be increased. The transmission signal selected by the switch unit SU is output to the outside of the delay device D10 through the inverter INV.

  FIG. 14B shows a waveform of the power supply current when a pulse signal is input to the delay device D10 at an interval of 4 ns when the time during which the power supply current flows through the delay device D10 by one pulse is 4 ns. Since the input interval of the pulse signal is equal to the time during which the power supply current flows through the delay device D10, the power supply current flows continuously without overlapping each other. Therefore, the waveform of the power supply current does not change. The delay device D10 can generate a desired clock because the delay time of the pulse signal can be changed by connecting or disconnecting a desired switch SW of the switch unit SU. Since a large number of switches SW are commonly connected to the output side of the switch unit SU, the load capacity is large. Therefore, the power supply voltage of the delay device D10 varies when the switch SW and the inverter INV are driven. When the additional circuit ADC outputs the midpoint voltage Vc, the amplitude of the signal voltage output from the switch unit SU is reduced. Therefore, when the signal changes, the change in the power supply current flowing through the delay device D10 becomes small, and the change in the power supply voltage becomes small. This increases the accuracy of the delay time. In the example shown here, the load circuit ADC is added only to the output of the switch unit SU. However, the additional circuit ADC is connected to each output side of the delay element DL and each input side of the plurality of switches SW. Therefore, the fluctuation of the power supply current can be further reduced.

  FIG. 15 shows yet another embodiment of the delay device D10. The delay device D10 receives a plurality of delay elements DL that delay the transmission signal IN, a plurality of OR gates that give the input transmission signal IN to the delay element DL provided in the subsequent stage, and a selection signal SLS. A plurality of AND gates AND that provide transmission signals to an OR gate OR provided in a subsequent stage, an inverter INV that supplies transmission signals input from the outside of the delay device D10 to the plurality of AND gates, and a transmission signal output from the inverter INV And an additional circuit ADC that outputs the midpoint voltage Vc.

  The plurality of delay elements DL are connected in series via an OR gate OR, and delay the input transmission signal by a predetermined time. The delay time of the entire delay device D10 is determined by the number of delay elements DL through which the transmission signal passes. Therefore, the delay time can be adjusted by selecting which delay element DL is supplied with the selection signal SLS. For example, when the selection signal SLS is given to the uppermost AND gate AND, the AND gate AND gives a transmission signal to the uppermost OR gate provided in the subsequent stage. Next, the OR gate OR supplies a transmission signal to the uppermost delay element DL provided in the subsequent stage. This transmission signal passes through all the delay elements DL and is output to the outside of the delay device D10. Therefore, the time delayed by the delay device D10 is the longest.

  On the other hand, when a selection signal is given to the lowermost AND gate AND, the AND gate AND gives a transmission signal to the lowermost OR gate provided in the subsequent stage. Since the delay element DL is not provided on the output side of the lowermost OR gate to which the transmission signal is given, the transmission signal is output to the outside of the delay device D10 without passing through any delay element DL. When the selection signal is given to the lowermost AND gate AND in this way, the transmission signal is output from the delay device D10 most quickly without being delayed by the delay element DL. Thus, the delay time can be adjusted by selecting the delay element DL to which the selection signal SLS is applied. Since many AND gates AND are connected to the output side of the inverter INV, the load capacity when the inverter INV is driven increases. For this reason, when the inverter INV and the AND gate AND are driven by the input transmission signal, the power supply voltage of the delay device D10 varies. When the additional circuit ADC outputs the midpoint voltage Vc, the amplitude of the signal voltage output from the inverter INV is reduced. Therefore, when the signal changes, the change in the power supply current flowing through the delay device D10 becomes small, and the change in the power supply voltage becomes small. This increases the accuracy of the delay time. In the example shown here, the additional circuit ADC is connected only to the output of the inverter INV. However, by connecting the additional circuit ADC to the output side of the AND gate AND and the output side of the OR gate OR, the fluctuation of the power supply current is further increased. Can be small.

  FIG. 16 shows another embodiment of the delay device D10. When a number of driven circuits RC are connected to the signal line LIN, the wiring capacitance CL and the input capacitance CG on the signal line LIN are increased. For this reason, when the signal level changes, a large power supply current flows and the power supply voltage fluctuates greatly. Therefore, the delay time varies greatly. By connecting the additional circuit ADC to the signal line LIN to which a large number of driven circuits RC that cause a large fluctuation in the power supply voltage is connected, the fluctuation in the power supply voltage of the delay device D10 is effectively reduced, and the delay time Can be reduced.

  FIG. 17 shows a modified embodiment of FIG. The additional circuit ADC may be connected to any position of the signal line LIN.

FIG. 18 shows yet another embodiment of the delay device D10. The delay device D10 includes a plurality of delay elements DL connected in series, capacitors C10 and C12 that store charges of transmission signals output from the delay elements DL, and outputs of each of the plurality of capacitors C10 and C12 and the delay element DL. And switches SW10 and SW12, and an additional circuit ADC that outputs a midpoint voltage Vc with respect to the output of each delay element DL. In FIG. 18, the capacitor C10 and the capacitor C12 are connected to the power supply voltage V _SS , but may be connected to the power supply voltage V _DD .

  For example, the switch signal SW-CNT1 is supplied to the switch SW10 so that the switch SW10 connects the output of the delay element DL and the capacitor C10. Further, a switch signal SW-CNT2 is supplied to the switch SW12 so that the switch SW12 connects the output of the delay element DL and the capacitor C12. The input transmission signal is delayed by the delay element DL and then given to the next delay element DL. The capacitor C10 and the capacitor C12 delay the transmission signal by accumulating the charge of the transmission signal input from the delay element DL. The delay time can be adjusted by selecting whether the switches SW10 and SW12 are connected or disconnected. For example, when the switch SW10 is connected and the switch SW12 is disconnected, the charge of the transmission signal is accumulated only in the capacitor C10. Therefore, the charge of the transmission signal is accumulated in the capacitors C10 and C12 by connecting the switch SW10 and the switch SW12. Compared to the case, the delay time becomes shorter.

  By driving the plurality of delay elements DL, the power supply voltage of the delay device D10 varies. By accumulating the output charge of the delay element DL in the capacitor C10 and the capacitor C12, the fluctuation of the power supply voltage of the delay device D10 is further increased. However, since the additional circuit ADC outputs the midpoint voltage Vc, the fluctuation of the power supply voltage of the delay device D10 is reduced, so that the accuracy of the delay time can be improved.

FIG. 19 shows an example of a specific circuit of the switches SW10 and SW12 and the capacitors C10 and C12 of FIG. Capacitor C10 has a P-type FETs Q _P that connects the switch SW10 and the power supply voltage V _DD, and a N-type FETs Q _N that connects the switch SW10 and the power supply voltage V _SS. In the P-type FETs Q _P, the power supply voltage V _DD is applied to the gate G, the source S is connected to the gate G, drain D is connected to the switch SW10. In the N-type FET Q _N of the capacitor C10, the power supply voltage V _SS is applied to the gate G, the source S is connected to the gate G, and the drain D is connected to the switch SW10.

The capacitor C12 has three P-type FETs Q _P and one N-type FET Q _N. In these P-type FETs Q _P , the power supply voltage V _DD is applied to each gate G, and the switch SW12 connects the drains D and sources S of these P-type FETs Q _P and the output of the delay element DL. Or cut. In the N-type FET Q _N of the capacitor C12, the power supply voltage V _SS is applied to the gate G, the source S is connected to the gate G, and the drain D is connected to the switch SW12. Since the gates G of the P-type FET Q _P and the N-type FET Q _{N included in} the capacitors C10 and C12 are insulated from the channel by the gate oxide film, the drain D and the source S are reverse-biased with respect to the substrate SUB. It is insulated from the substrate SUB. Therefore, a capacitor can be configured using an FET. Further, by changing the number and arrangement of the P-type FET Q _P and the N-type FET Q _N of the capacitors C10 and C12, it is possible to change the capacity for storing charges.

FIG. 20 shows yet another embodiment of the delay device D10. The delay device D10 includes a plurality of delay elements DL, a plurality of capacitors C14, C16, C18, and C20 that store charges of transmission signals output from the delay elements DL, one of the capacitors C14 and C16, and an output of the delay element DL. A switch SW20 that disconnects or connects the output of the delay element DL with one of the capacitors C18 and C20, and an additional circuit ADC that outputs a midpoint voltage Vc to the output of the delay element DL With. In FIG. 20, capacitors C14, C16, C18, and C20 are connected to the power supply voltage V _SS , but may be connected to the power supply voltage V _DD .

  For example, the switch signal SW-CNT3 is supplied to the switch SW20 so that the switch SW20 connects the output of the delay element DL and the capacitor C14. Further, a switch signal SW-CNT4 is supplied to the switch SW22 so that the switch SW22 connects the output of the delay element DL and the capacitor C18. The input transmission signal is delayed by the delay element DL and then given to the next delay element DL. Then, the capacitor C14 and the capacitor C18 delay the transmission signal by accumulating the charge of the transmission signal input from the delay element DL. The switch SW20 and the switch SW22 can adjust the time for delaying the transmission signal by connecting one of the capacitors C14 or C16 and one of the capacitors C18 or C20 arranged in parallel to the output of the delay element DL. it can. Further, the switch SW20 can select neither of the capacitors C14 and C16. Switch SW22 can select neither capacitor C18 nor C20.

  By driving the plurality of delay elements DL, the power supply voltage of the delay device D10 varies. By accumulating the output charge of the delay element DL in the capacitors C14, C16, C18, and C20, the fluctuation of the power supply voltage of the delay device D10 is further increased. However, since the additional circuit ADC outputs the midpoint voltage Vc, the fluctuation of the power supply voltage of the delay device D10 is reduced, so that the accuracy of the delay time can be improved.

FIG. 21 shows an example of a specific circuit of the switches SW20 and SW22 and the capacitors C14, C16, C18, and C20 of FIG. Capacitor C14 has a P-type FETs Q _P connecting the switch SW20 and the power supply voltage V _DD, and a N-type FETs Q _N connecting switches SW20 and the power supply voltage V _SS. In the P-type FETs Q _P, the power supply voltage V _DD is applied to the gate G, the source S is connected to the gate G, drain D is connected to the switch SW20. In the N-type FET Q _N of the capacitor C14, the power supply voltage V _SS is applied to the gate G, and the switch SW20 connects or disconnects the drain D and source S of the N-type FET Q _N and the output of the delay element DL. Capacitor C16 is one have the N-type FETQ _N. In the N-type FET Q _N , the power supply voltage V _SS is applied to the drain D and the source S, and the gate G is connected to the switch SW20.

The capacitor C18 has two P-type FETs Q _P that connect the switch SW22 and the power supply voltage V _DD and two N-type FETs Q _N that connect the switch SW22 and the power supply voltage V _SS . In one of the two P-type FETs Q _P , the power supply voltage V _DD is applied to the gate G, the source S is connected to the gate G, and the drain D is connected to the switch SW22. In the other P-type FET Q _P , the power supply voltage V _DD is applied to the gate G, and the switch SW22 connects or disconnects the drain D and source S of the P-type FET Q _P and the output of the delay element DL. To do. In one of the two N-type FETs Q _N of the capacitor C18, the power supply voltage V _SS is applied to the gate G, the source S is connected to the gate G, and the drain D is connected to the switch SW22. In the other N-type FET Q _N , the power supply voltage V _SS is applied to the gate G, and the switch SW22 connects or disconnects the drain D and source S and the output of the delay element DL. Capacitor C20 is one have the N-type FETQ _N. In the N-type FET Q _N , the power supply voltage V _SS is applied to the drain D and the source S, and the gate G is connected to the switch SW22.

Since the gates G of the P-type FET Q _P and the N-type FET Q _{N included in} the capacitors C14 and C18 are insulated from the channel by the gate oxide film, the drain D and the source S are reverse-biased with respect to the substrate SUB. It is insulated from the substrate SUB. Therefore, a capacitor can be configured using an FET. In the case of the capacitor C16 and the capacitor C20, since the gate G is connected to the switches SW20 and SW22, the charge is charged when a transmission signal that applies a reverse bias voltage to the gate G of the capacitor C16 and the capacitor C20 is input. accumulate. Also it is possible to vary the capacity of storing charges by changing the number and arrangement of the capacitors C14, C16, C18, and C20 of P-type FETs Q _P and N-type FETs Q _N.

FIG. 22 shows an example of another embodiment of the capacitors C10, C12, C14, C16, C18, and C20 shown in FIGS. (A) is an example of a capacitor using the N-type FETs Q _N. The N-type FETs Q _N supply voltage V _SS to the gate G and the substrate SUB of is applied, the switch SW connects or disconnects the output of the drain D and the source S and the delay element DL of the N-type FETs Q _N. (B) is an example of a capacitor using the P-type FETs Q _P. The P-type FETQ power supply voltage V _DD to the gate G and the substrate SUB of the _P is applied, the switch SW connects or disconnects the output of the drain D and the source S and the delay element DL of the P-type FETQ _P. (C) is an example of a capacitor using the N-type FETs Q _N. A power supply voltage V _SS is applied to the drain D, source S and substrate SUB of the N-type FET Q _N , and a switch SW is connected to the gate G. (D) is an example of a capacitor using the P-type FETs Q _P. The drain D of the P-type FETs Q _P, the power supply voltage V _DD is applied to the source S and substrate SUB, the switch SW is connected to the gate G.

The gates G of the P-type FET Q _P and N-type FET Q _N of the capacitors shown in FIGS. 22A and 22B are insulated from the channel by a gate oxide film, and the drain D and the source S are connected to the substrate SUB. Since it is reverse biased, it is insulated from the substrate SUB. Therefore, a capacitor can be configured using an FET. Since the gates G of the P-type FET Q _P and N-type FET Q _N of the capacitors shown in FIGS. 22C and 22D are connected to the switch SW, there is a transmission signal that applies a reverse bias voltage to the gate G. Accumulate charge when input.

23 and 24 show a modified embodiment of the additional circuit ADC. Addition circuit ADC shown in FIG. 23 shows a case of a structure giving to the gates G of the P-type FETs Q _P and N-type FETs Q _N a forward bias voltage directly. With this configuration, the P-type FET Q _P and the N-type FET Q _N are always kept on, and the potential of the common connection point J can be maintained at the midpoint voltage Vc with low impedance.

FIG. 24 shows a case where the additional circuit ADC is configured by combining the low impedance buffer circuit LOW and the midpoint voltage source EJV. In the low impedance buffer circuit LOW, the drain D of the N-type FET Q _N is connected to the power supply voltage V _DD side, the drain D of the P-type FET Q _P is connected to the power supply voltage V _SS side, and the gate G and the source S are common. The midpoint voltage V _C is applied to the common connection point J of the gate G from the midpoint voltage source EJV.

FIG. 25 shows an equivalent circuit of the additional circuit ADC shown in FIG. The N-type FET Q _N and the P-type FET Q _P constituting the low impedance buffer circuit LOW shown in FIG. 24 can be viewed as a voltage buffer with a gain of 1. The additional circuit ADC includes a midpoint voltage source EJV and a low impedance buffer circuit LOW. When the drive circuit DR outputs the L logic, current I ₁ flows to the signal line LIN from the equivalent resistor RM, the potential at the common junction J is slightly smaller from the middle point potential. Therefore, at this time, the driven circuit RC outputs H logic. On the other hand, when the drive circuit DR outputs a logical H, a current flows I ₂ flows from the signal line LIN in addition circuit in equivalent resistor RM. The potential of the common connection point J by the current I ₂ flows is slightly smaller from the middle point potential V _C. Therefore, the driven circuit RC outputs L logic. In the resistance value R _U is small value of the equivalent resistor RM, the output impedance R _OUT of the driver circuit DR, can be reduced potential change of the R _OUT >> R _U next common connection point J. Therefore, fluctuations in the power supply voltage can be reduced.

FIG. 26 shows an embodiment in which an additional circuit ADC is used for the midpoint voltage source EJV. In the embodiment shown in FIG. 24, the midpoint voltage source EJV is configured by a resistor divider circuit. However, the additional circuit ADC shown in FIG. 8 or FIG. 23 can be used as the midpoint voltage source EJV. When the additional circuit ADC is configured by the midpoint voltage source EJV and the low impedance buffer circuit LOW, the midpoint voltage V _C is applied to a plurality of low impedance buffer circuits LOW by one midpoint voltage source EJV, and a plurality of signal lines An additional circuit ADC may be connected to.

  Incidentally, the delay device D10 having the CMOS structure consumes almost no current when the active element is in a stationary state. Therefore, when testing the delay device D10, the current at rest is measured to test whether the current value is equal to or less than a specified value. On the other hand, if the additional circuit ADC described above is incorporated in the delay device D10, the additional circuit ADC consumes current even in a stationary state. As a result, it becomes difficult for the delay device D10 incorporating the additional circuit ADC to measure the quiescent current.

  In the embodiment shown in FIG. 27 to FIG. 30, in order to eliminate this inconvenience, a cutoff means CUT is added to the additional circuit ADC, a control signal is given to this cutoff means CUT, and the current flowing through the additional circuit ADC is cut off as necessary. The quiescent current measurement was made possible.

FIG. 27 shows an example in which a blocking means CUT is added to the additional circuit ADC. The blocking means CUT has a control terminal CT. When the logic H is applied to the control terminal CT, the additional circuit ADC is maintained in the operating state, and when the logic L is applied, the additional circuit ADC is switched to the non-operating state and is controlled so as not to consume any current. That is, when H logic is applied to the control terminal CT, the FETs Q ₁ and Q ₃ are controlled to be off and Q ₂ and Q ₄ are controlled to be on. FETs Q ₂ is turned on, _{since Q 1} is controlled to the OFF state, FETs Q ₅ is turned on, _{Q 6} is controlled to the OFF state. As a result, FETs Q ₄ and _{Q 5} are controlled to ON-state, the gate G mutual FETs Q _P and Q _N through these FETs Q ₄ and _{Q 5} is operated as an additional circuit ADC are maintained in the connected state.

When L logic is applied to the control electron CT, the FETs Q ₁ and Q ₃ are controlled to be on and the FETs Q ₂ and Q ₄ are controlled to be off. FETs Q ₁ is turned on, since the FETs Q ₂ is controlled to the OFF state, FETs Q ₅ is turned off, _{Q 6} is controlled to the ON state. That, FETs Q ₄ and _{Q 5} are controlled to the OFF state, since FETs Q ₃ and _{Q 6} are controlled to ON-state, FETs Q _P and Q _N are controlled in the OFF state. Here, the FETs Q ₁ , Q ₃ , and Q ₆ are controlled to be in an on state, but the FETs Q ₂ , Q ₄ , and Q ₅ connected in series to these are controlled to be in an off state. The power supply current will not flow. Therefore, the quiescent current measurement can be performed if the control terminal CT is in a state where L logic is applied.

The embodiment shown in FIG. 28 shows a case where the blocking means CUT is configured by a switch element ANS generally called an analog switch or the like. By controlling the switch element ANS to be in an OFF state, the FETs Q _P and Q _N constituting the additional circuit ADC are controlled to be in an OFF state.

FIG. 29 shows a case where a blocking means CUT is added to the additional circuit ADC shown in FIG. Controlling the FETs Q ₄ and _{Q 5} on state by applying a logical H to the control terminal CT, the gate G of the gate G and the N-type FETs Q _N of P-type FETs Q _P applied forward bias voltage V _SS and V _DD Then, the P-type FET Q _P and the N-type FET Q _N are controlled to be in an on state, and operate as an additional circuit ADC. When the control terminal CT give L logic, FETs Q ₄ and _{Q 5} are turned off, _{Q 3} and _{Q 6} are controlled to ON-state, P-type FETs Q _P and N-type FETs Q _N in this state is controlled to the OFF state The current consumption is controlled to be almost zero.

FIG. 30 shows a configuration in which the cutoff means CUT is added when the additional circuit ADC is configured by combining the low impedance buffer circuit LOW and the midpoint voltage source EJV. In this embodiment, the additional circuit ADC shown in FIG. 8 is used as the midpoint voltage source EJV. CUT1 is a cutoff means for controlling the P-type FET Q _P1 and N-type FET Q _N1 constituting the midpoint voltage source EJV to be in a cutoff state, and CUT ₂ is an N-type FET Q _N2 and P-type FET Q _P2 constituting the low impedance buffer circuit LOW. The shut-off means for controlling to a shut-off state is shown. When logic H is applied to the control terminal CT, the FET Q _4-1 and Q _5-1 are controlled to be turned on in the cutoff means CUT ₁ , and each of the P-type FET Q _P1 and N-type FET Q _N1 constituting the midpoint voltage source EJV is controlled. gate G is connected through these _{FETs Q 4-1} and _{Q 5-1.} As a result, the midpoint voltage Vc is output to the connection point J1.

On the other hand, by the H logic is supplied to the blocking means CUT2 the control terminal CT, _{FETs Q 4-2} and _{FETs Q 5-2} are controlled to ON-state. As a result, the N-type FET Q _N2 and the P-type FET Q _P2 constituting the low-impedance buffer circuit LOW are commonly connected to the gate G through the FET Q _4-2 and the FET Q _5-2 , and the midpoint voltage source is connected to the common connection point J2. A midpoint voltage Vc is given from EJV. Therefore, in this state, the N-type FET Q _N2 and the P-type FET Q _P2 have the same circuit structure as the low-impedance buffer circuit LOW shown in FIG. 24, and the signal potential is applied to the connection point J2 from the drive circuit DR. It operates in the same way as described in. When L logic is applied to the control terminal CT, _{FETs Q 3-1} and _{Q 6-1} in blocking means CUT1 is _{on, Q 4-1} and _{Q 5-1} constitute an intermediate voltage source EJV from being controlled to be off The P-type FET Q _P1 and the N-type FET Q _N1 are controlled to be off. Since _{FETs Q 4-2} and _{FETs Q 5-2} in blocking means CUT2 _{off, Q 3-2} and _{Q 6-2} are controlled to ON-state, N-type FETs Q _N2 and the P-type constituting the low-impedance buffer circuit LOW The FET Q _P2 is controlled to be in an off state. Therefore, even in the additional circuit ADC shown in FIG. 30, when L logic is applied to the control terminal CT, all currents are cut off, and quiescent current measurement can be performed.

  In the embodiments so far, the configuration using the inverter INV as the additional circuit ADC has been described. Hereinafter, an embodiment in which the additional circuit ADC is formed using a circuit other than the inverter INV, for example, a NAND gate or a NOR gate will be described.

  FIG. 31 shows another embodiment of a delay device D10 according to the present invention. The additional circuit ADC according to the present embodiment has a NAND gate. The additional circuit ADC is configured by connecting a total feedback circuit NF to a NAND gate. Since the NAND gate has a plurality of input terminals, as shown in the figure, one terminal can be used as the control terminal CT.

FIG. 32 shows an example of a specific configuration of the additional circuit ADC using a NAND gate. In this circuit configuration, the operation of the additional circuit ADC can be turned on / off by switching the input signal of the control terminal CT between H logic and L logic. In this embodiment, when the logic H is applied to the control terminal CT, the additional circuit ADC is maintained in the operating state and can output a midpoint potential. When the logic L is applied to the control terminal CT, the additional circuit ADC is It is switched to the non-operating state and the output is set to H. Given a logical H to the control terminal CT, FETs Q ₁ is turned on, FETs Q ₄ is controlled to the OFF state. Therefore, it is maintained in the drain D mutual FETs Q ₂ and FETs Q ₃ is connected, the additional circuitry ADC is maintained in the operating state, and outputs a midpoint potential.

On the other hand, given a logic L to the control terminal CT, FETs Q ₁ is off, FETs Q ₄ is controlled to ON-state. Therefore, the potential of the common connection point J is always H. At the time of a leakage current test (static current test) of a semiconductor integrated circuit element, it is necessary to set the output of the transmission side (drive circuit DR) equal to the potential at the common connection point J. In this way, by controlling the input of the control terminal CT, the operation of the additional circuit ADC configured using the NAND gate can be turned on / off.

  FIG. 33 shows yet another embodiment of a delay device D10 according to the present invention. The additional circuit ADC according to the present embodiment has a NOR gate. The additional circuit ADC is configured by connecting the entire feedback circuit NF to the NOR gate. Since the NOR gate has a plurality of input terminals, one terminal can be used as the control terminal CT as shown in the figure.

FIG. 34 shows an example of a specific configuration of the additional circuit ADC using the NOR gate. In this circuit configuration, the operation of the additional circuit ADC can be turned on / off by switching the input signal of the control terminal CT between H logic and L logic. In this embodiment, when the logic L is applied to the control terminal CT, the additional circuit ADC is maintained in the operating state and can output a midpoint potential. When the logic H is applied to the control terminal CT, the additional circuit ADC is The mode is switched to the non-operating state, and the output is set to L. Given a logic L to the control terminal CT, FETs Q ₁ is off, FETs Q ₂ is controlled to the ON state. Since the drain D of the FET Q ₃ is connected to the source S of the FET Q _{2 and} the FET Q ₂ is turned on, the drain D of the FET Q ₃ and the FET Q ₄ is maintained in a connected state, and the additional circuit ADC Is maintained in the operating state, and a midpoint potential is output.

On the other hand, given a logical H to the control terminal CT, FETs Q ₁ is turned on, FETs Q ₂ is controlled to the OFF state. Since FETs Q ₁ is turned on, the potential of the common connection point J becomes always L. At the time of a leakage current test (static current test) of a semiconductor integrated circuit element, it is necessary to set the output of the transmission side (drive circuit DR) equal to the potential at the common connection point J. As described above, by controlling the input of the control terminal CT, the operation of the additional circuit ADC configured using the NOR gate can be turned on / off.

FIG. 35 shows still another embodiment of the additional circuit ADC. The additional circuit ADC has control terminals CT and XCT as the cutoff means CUT. When the logic H is applied to the control terminal CT and the logic L is applied to the control element XCT, the additional circuit ADC enters an operating state. Further, when L logic is applied to the control terminal CT and H logic is applied to the control element XCT, the additional circuit ADC is switched to a non-operating state and does not consume current. That is, when H logic is applied to the control terminal CT and L logic is applied to the control element XCT, the FETs Q ₁ and Q ₄ are controlled to be in an ON state. Then, the power supply voltage V _DD is applied from the FETQ ₁ to the FETQ _2, and the power supply voltage V _SS is applied from the FETQ ₄ to the FETQ ₃ . Midpoint voltage Vc is applied to the common connection point J of gate G of the order FETs Q ₂ and QQ _3. When L logic is applied to the control terminal CT and H logic is applied to the control element XCT, the FETs Q ₁ and Q ₄ are turned off. Then, since the power supply voltages V _DD and V _SS are not applied to the FETs Q ₁ and Q ₄ , no power supply current flows through the additional circuit ADC. Therefore, the quiescent current of the delay device D10 can be measured by setting the control terminal CT to L logic and the control element XCT to H logic.

The term “midpoint voltage” has been used to describe embodiments of the present invention, but “middle point voltage” does not necessarily mean only the central voltage between the power supply voltages V _DD and V _SS. is not. The midpoint voltage Vc means any voltage between the power supply voltage V _DD and V _SS depending on the value of the beta ratio, and may vary from the center voltage. For example, the “midpoint voltage source” shown in FIG. 24 does not necessarily output only the central voltage between the power supply voltage V _DD and V _SS , but outputs a voltage corresponding to the threshold voltage of the driven circuit RC. Can be output.

It should be noted that according to the present embodiment, the following delay device is provided.

(1) A delay device for delaying an input transmission signal, which is driven by two power supply voltages V _SS and V _DD (V _DD > V _SS ), and a delay element for delaying the input transmission signal And an additional circuit that outputs a predetermined voltage that is larger than the power supply voltage V _{SS and} smaller than the power supply voltage V _{DD with} respect to the output of the delay element, and the additional circuit includes a P-type FET and an N-type FET. And a forward bias voltage is applied to each of the gates of the P-type FET and the N-type FET.

(2) a delay device for delaying an input transmission signal, which is driven by two power supply voltages V _SS and V _DD (V _DD > V _SS ) and delays the input transmission signal; An additional circuit that outputs a predetermined voltage that is larger than the power supply voltage V _{SS and} smaller than the power supply voltage V _{DD with} respect to the output of the delay element, and the additional circuit is larger than the power supply voltage V _SS , A delay device comprising a voltage source that outputs a predetermined voltage lower than the power supply voltage V _DD .

(3) The delay device according to (2), wherein the additional circuit further includes a low impedance buffer circuit that lowers an output impedance of the voltage output from the voltage source.
(4) The delay device according to any one of (1) to (3), further including a cutoff unit that cuts off a current flowing between the delay element and the additional circuit.
(5) a delay device for delaying an input transmission signal, which is driven by two power supply voltages V _SS and V _DD (V _DD > V _SS ), and delaying the input transmission signal; And an additional circuit that outputs a predetermined voltage that is larger than the power supply voltage V _{SS and} smaller than the power supply voltage V _{DD with} respect to the output of the delay element, the additional circuit comprising: a NAND gate; A delay device comprising a feedback circuit having one input terminal connected to an output terminal.

(6) The NAND gate has a control terminal to which a control signal for cutting off a current flowing between the delay element and the additional circuit and a current in the additional circuit are input. The described delay device.
(7) a delay device for delaying an input transmission signal, which is driven by two power supply voltages V _SS and V _DD (V _DD > V _SS ), and delaying the input transmission signal; And an additional circuit that outputs a predetermined voltage that is larger than the power supply voltage V _{SS and} smaller than the power supply voltage V _{DD with} respect to the output of the delay element, and the additional circuit includes a NOR gate, a NOR gate, A delay device comprising a feedback circuit having one input terminal connected to an output terminal.

(8) The NOR gate has a control terminal to which a current flowing between the delay element and the additional circuit and a control signal for cutting off a current in the additional circuit are input. The described delay device.
(9) a delay device for delaying an input transmission signal, the delay device being driven by two power supply voltages V _SS and V _DD (V _DD > V _SS ) for delaying the input transmission signal; And an additional circuit that outputs a predetermined voltage that is larger than the power supply voltage V _{SS and} smaller than the power supply voltage V _DD with respect to the output of the delay element, and the additional circuit is connected to a terminal of the delay element. A delay device characterized by that.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the description of the scope of claims that embodiments with such changes or improvements can be included in the technical scope of the present invention.

As described above, according to the present embodiment, by connecting the additional circuit ADC to the delay element DL, the fluctuation of the power supply voltage of the delay device D10 is reduced, so that the accuracy of the delay time by the delay device D10 is increased. Further, the midpoint voltage V _C of addition circuit ADC outputs, even if the voltage fluctuates, since changes following to the change to follow the threshold of the delay element DL, it is always possible to operate normally. The additional circuit ADC has a beta ratio equal to the beta ratio of the delay element DL and includes a full feedback circuit. The additional circuit ADC can automatically generate a voltage that matches the logical threshold voltage of the delay element DL.

  Further, in the above embodiment, a cutoff terminal CUT is attached to the circuit such as the additional circuit ADC and the midpoint voltage source EJV, and the current flowing through the circuit such as the additional circuit ADC and the midpoint voltage source EJV is cut off by this cutoff means. Therefore, even if the additional circuit ADC and the midpoint voltage source EJV are circuits that consume idling current even when they are in a stationary state, the idling current can be removed by controlling the circuit to the cut-off state. As a result, when the delay device D10 incorporating the additional circuit ADC or the midpoint voltage source EJV is manufactured, and when the delay device D10 is further tested, an advantage that the quiescent current measurement can be easily performed is obtained.

  As is clear from the above description, according to the present invention, the accuracy of the delay time of the delay device can be increased by reducing the fluctuation of the power supply voltage of the delay device.

It is a figure of the form of the conventional delay device D12. It is a figure of the waveform of the power supply current which flows into delay device D12. It is a figure of other forms of conventional delay device D12. It is a figure of a circuit electrically equivalent to the delay device D12. The structure of the delay device D10 of this invention is shown. The waveform of the power supply current which flows into delay device D10 is shown. It is a block diagram of delay device D10. It is the connection figure which showed delay device D10 concretely. It is a graph for demonstrating operation | movement of the delay device D10. It is a figure explaining through current Ihl and power supply currents Ih and Il which flow into delay device D10. It is a figure explaining the relationship between the input voltage Vin which flows into the delay device D10, the penetration current Ihl, the power supply currents Ih, and Il. FIG. 10 is an equivalent circuit diagram for explaining the operation of the delay device D10. It is a wave form diagram which shows the waveform of the voltage of each part of a circuit equivalent to delay device D10. FIG. 11 is a diagram of another embodiment of a delay device D10. FIG. 14 is a diagram of yet another embodiment of a delay device D10. It is a block diagram for demonstrating the practical form of delay device D10. It is a block diagram for demonstrating the other practical form of the delay device D10. FIG. 14 is a diagram of yet another embodiment of a delay device D10. It is a figure of the concrete circuit of delay device D10. FIG. 14 is a diagram of yet another embodiment of a delay device D10. It is a figure of the concrete circuit of delay device D10. It is a figure of other embodiment of the capacitor | condenser used for delay device D10. It is a connection diagram for demonstrating other embodiment of additional circuit ADC used for this invention. FIG. 10 is a connection diagram for explaining still another embodiment of the additional circuit ADC used in the present invention. It is an equivalent circuit diagram of the additional circuit ADC. It is a block diagram for demonstrating embodiment of additional circuit ADC. It is a connection diagram for demonstrating embodiment which added the interruption | blocking means CUT to the additional circuit ADC used for this invention. It is a connection diagram of other embodiment of interception means CUT. FIG. 6 is a connection diagram for explaining a configuration in which a blocking means CUT is added to an additional circuit ADC. FIG. 6 is a connection diagram for explaining a configuration in which a cutoff means CUT is added to an additional circuit ADC and a midpoint voltage source EJV. FIG. 6 is a block diagram illustrating another embodiment of a delay device D10 according to the present invention. An example of a specific configuration of the additional circuit ADC using a NAND gate is shown. FIG. 7 is a block diagram showing still another embodiment of a delay device D10 according to the present invention. An example of a specific configuration of the additional circuit ADC using the NOR gate is shown. 6 shows still another embodiment of the additional circuit ADC.

Explanation of symbols

ADC Additional circuit ANS Switch element DR Drive circuit RC Driven circuit LIN Signal line CL Wiring capacitance CG Input capacitance CT Control terminal NF All feedback circuit J Common connection point J1 Connection point J2 Connection point RM Equivalent resistor EJV Midpoint voltage source CUT Cut off Means DL Delay element D10 Delay device D12 of the present invention Conventional delay device Il Power supply current Ih Power supply current Ihl Through current SU Switch unit AND gate OR OR gate NAND NAND gate NOR NOR gate INV Inverter SEL Selector SW switch SW10 switch SW12 switch SW20 switch SW22 switch C10 capacitor C12 capacitor C14 capacitor C16 capacitor C18 capacitor C20 capacitor SLS selection signal SW-CNT1 switch signal SW- NT2 switch signal SW-CNT3 switch signal SW-CNT4 switch signal G gate - DOO S source - scan D drain SUB substrate LOW low impedance buffer circuit Q _P P-type FET
Q _N Q-type FET
βn N-type FET drain current coefficient βp P-type FET drain current coefficient Vin Input voltage Vout Output voltage Vc Midpoint voltage V _DD Power supply voltage _VSS Power supply voltage

Claims (26)

A delay device for delaying an input transmission signal,
A delay element that is driven by two power supply voltages V _SS and V _DD (V _DD > V _SS ) to delay the input transmission signal;
An additional circuit having a logic inversion function, wherein an input and an output are connected to a wiring connected to the output of the delay element ;
A blocking means for blocking the current flowing through the additional circuit when measuring the quiescent current;
A delay device comprising: The additional circuit suppresses an increase in the voltage output from the delay element when the voltage output from the delay element is higher than a predetermined voltage that is greater than the power supply voltage V _{SS and} lower than the power supply voltage V _DD. The delay device according to claim 1, wherein when the output voltage is lower than the predetermined voltage, a decrease in the voltage output from the delay element is suppressed. The additional circuit, when the voltage the delay element output is higher than the predetermined voltage, the the flow of supply current from the power supply voltage V _DD of the delay elements to the power supply voltage V _SS of the addition circuit, the delay element delay device of claim 2, output flow power and supply current to the voltage V _SS of the delay element from the power supply voltage V _DD of the adding circuit is lower than the predetermined voltage.   2. The delay device according to claim 1, wherein the additional circuit includes a logic gate having a logic inversion function to which a shorted input / output is connected to a wiring connected to an output of the delay element. The delay device is:
A plurality of the delay elements connected in series;
The delay device according to claim 1, further comprising a plurality of the additional circuits respectively connected to the outputs of the plurality of delay elements. The delay element includes a digital circuit that outputs one of binary output voltages according to an input voltage,
The delay device according to claim 1, wherein the additional circuit outputs a voltage that substantially matches a threshold voltage at which an output of the digital circuit is inverted from one of the binary output voltages to the other. The delay device according to claim 4, wherein the additional circuit outputs a voltage approximately at a midpoint between the power supply voltages V _SS and V _DD .   The delay device according to claim 1, wherein the additional circuit has an output impedance lower than an output impedance of the delay element.   9. The delay device according to claim 8, wherein the output impedance of the additional circuit is 1/2 to 1/4 of the output impedance of the delay element.   2. The additional circuit includes a first logic gate that inverts and outputs an input signal, and a feedback circuit that connects an input terminal and an output terminal of the first logic gate. The described delay device.   The delay device of claim 10, wherein the delay element comprises a second logic gate, the first logic gate having a beta ratio substantially equal to the second logic gate.   The delay device of claim 10, wherein the first logic gate comprises an inverter, a NAND gate, or a NOR gate. 13. The delay device according to claim 12 , wherein the delay element includes a second inverter, and an inverter included in the first logic gate has a beta ratio substantially equal to the second inverter. A switch unit for selecting and outputting one of the outputs of the plurality of delay elements;
The delay device according to claim 5, wherein the additional circuit outputs a predetermined voltage that is greater than the power supply voltage V _{SS and} less than the power supply voltage V _{DD with} respect to an output of the switch unit. A plurality of the delay elements connected in series;
A selection circuit that selects which of the plurality of delay elements inputs the input transmission signal; and
2. The delay device according to claim 1, wherein the additional circuit outputs a predetermined voltage larger than the power supply voltage V _{SS and} smaller than the power supply voltage V _{DD with} respect to the input transmission signal. .   A plurality of capacitors for accumulating charges of the transmission signal output by the delay element; and a plurality of switches for disconnecting or connecting each of the plurality of capacitors and the output of the delay element. The delay device according to claim 1. The capacitor has a P-type FET, the power supply voltage V _DD is applied to the gate of the P-type FET, at least one of the drain or source of the P-type FET is connected to the gate, and the other is the switch The delay device according to claim 16, wherein the delay device is connected to the delay device. The capacitor includes an N-type FET, the power supply voltage V _SS is applied to a gate of the N-type FET, at least one of a drain or a source of the N-type FET is connected to the gate, and the other is the switch The delay device according to claim 16, wherein the delay device is connected to the delay device. The capacitor has a P-type FET, the power supply voltage V _DD is applied to the gate of the P-type FET, and the switch connects or disconnects the drain and source of the P-type FET and the output of the delay element. The delay device according to claim 16, wherein: The capacitor includes an N-type FET, the power supply voltage V _SS is applied to the gate of the N-type FET, and the switch connects or disconnects the drain and source of the N-type FET and the output of the delay element. The delay device according to claim 16, wherein: 17. The capacitor includes an N-type FET, the power supply voltage V _SS is applied to a drain and a source of the N-type FET, and a gate of the N-type FET is connected to the switch. The delay device described in. The capacitor has an N-type FET, the power supply voltage V _SS is applied to the gate and the substrate of the N-type FET, and the switch has a drain and a source of the N-type FET and an output of the delay element. The delay device according to claim 16, wherein the delay device is connected or disconnected. The capacitor has a P-type FET, the power supply voltage V _DD is applied to the gate and the substrate of the P-type FET, and the switch has a drain and a source of the P-type FET and an output of the delay element. The delay device according to claim 16, wherein the delay device is connected or disconnected. The capacitor includes an N-type FET, the power supply voltage V _SS is applied to the drain, source, and substrate of the N-type FET, and the gate of the N-type FET is connected to the switch. The delay device according to claim 16. The capacitor includes a P-type FET, the power supply voltage V _DD is applied to the drain, source, and substrate of the P-type FET, and the gate of the P-type FET is connected to the switch. The delay device according to claim 16. A delay device for delaying an input transmission signal,
A delay element that is driven by two power supply voltages V _SS and V _DD (V _DD > V _SS ) and delays the input transmission signal;
An additional circuit connected to the output of the delay element;
With
The additional circuit, a voltage in which the delay element is outputted, wherein, when the power supply voltage greater higher than the power supply voltage V _DD is less than a predetermined voltage than V _SS, power of the additional circuit from the power supply voltage V _DD of the delay element and passing a power supply current to the voltage V _SS, the delay device output flow supply current to the power supply voltage V _SS of the delay element from the power supply voltage V _DD of the adding circuit is lower than the predetermined voltage of the delay element.

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