JP4452726B2 - memory - Google Patents

Description

  The present invention relates to a memory, and more particularly to a memory including a memory material film such as a ferroelectric film or a giant magnetoresistive (CMR) film.

  Conventionally, since an element having a ferroelectric film has characteristics such as ferroelectricity, it is expected to be applied in many fields such as electronics. For example, a nonvolatile ferroelectric memory using a polarization hysteresis phenomenon has been studied (for example, see Patent Document 1). Conventionally, a non-volatile memory using a giant magnetoresistive material whose resistance changes greatly by applying a pulse of voltage has been proposed. In the nonvolatile memory using the giant magnetoresistive material, data is retained by utilizing the difference in resistance value of the giant magnetoresistive material film sandwiched between the upper electrode and the lower electrode.

  In a nonvolatile memory using a ferroelectric film, data is retained by spontaneous polarization of a ferroelectric material sandwiched between an upper electrode and a lower electrode. As such a ferroelectric memory, a one-transistor one-capacitor type ferroelectric memory in which one memory cell is constituted by one ferroelectric capacitor and one switching transistor is known. However, such a one-transistor one-capacitor type ferroelectric memory has a disadvantage that it is difficult to improve the degree of integration because a switching transistor needs to be arranged in each memory cell. In view of this, a nonvolatile memory composed of a simple matrix type (cross-point type) ferroelectric memory in which one memory cell is composed of only one ferroelectric capacitor has been proposed. In this simple matrix type ferroelectric memory, since one memory cell is composed of only one ferroelectric capacitor, the area of the memory cell can be made very small. As a result, the degree of integration can be improved.

  FIG. 16 is a cross-sectional view showing the structure of a conventional simple matrix ferroelectric memory. Referring to FIG. 16, in a conventional simple matrix ferroelectric memory, a lower electrode 102 is formed on a substrate 101. An upper electrode 104 is formed in a predetermined region on the lower electrode 102 via a ferroelectric film 103. The lower electrode 102 is connected to a word line (not shown), for example, and the upper electrode 104 is connected to a bit line (not shown), for example. The lower electrode 102, the ferroelectric film 103, and the upper electrode 104 constitute a ferroelectric capacitor 110. Only one ferroelectric capacitor 110 constitutes one memory cell.

  17 and 18 are cross-sectional views for explaining a manufacturing process of the conventional simple matrix ferroelectric memory shown in FIG. Next, a manufacturing process of a conventional simple matrix ferroelectric memory will be described with reference to FIGS.

  First, as shown in FIG. 17, a lower electrode 102, a ferroelectric film 103, and an upper electrode 104 are sequentially deposited on a substrate 101. Thereafter, a photoresist film 105 is formed in a predetermined region on the upper electrode 104. Then, the lower electrode 102 is exposed by etching the upper electrode 104 and the ferroelectric film 103 using the photoresist film 105 as a mask. Thus, the upper electrode 104 and the ferroelectric film 103 are patterned as shown in FIG. Thereafter, the photoresist film 105 is removed to form a conventional simple matrix ferroelectric memory as shown in FIG.

Japanese Patent Laid-Open No. 2001-210795

  In the conventional simple matrix ferroelectric memory shown in FIG. 16, since the upper electrode 104 and the ferroelectric film 103 are patterned in the same shape, the ferroelectric film 103 exists only below the upper electrode 104. Then, the ferroelectric film 103 does not exist obliquely below the upper electrode 104. In this case, this structure has a disadvantage that the contribution of the component of the ferroelectric film 103 polarized by the electric field that extends in the lateral direction from the upper electrode 104 is lost. When the contribution of the component of the ferroelectric film 103 polarized by the electric field that leaks from the upper electrode 104 in this way is eliminated, the residual polarization amount of the ferroelectric film 103 is reduced. The strength of the read signal is reduced. As a result, there is a problem that it is difficult to improve the detection accuracy of the read signal.

  The above problem also occurs when a giant magnetoresistive material is used instead of the ferroelectric film 103. In other words, the contribution of the resistance component of the giant magnetoresistive material due to the electric field flowing in the lateral direction from the upper electrode 104 is eliminated, so that the signal detection accuracy is lowered.

  Therefore, in order to solve the above-described problem, it may be considered that only the upper electrode 104 is etched and the ferroelectric film 103 is not etched in the step shown in FIG. However, if only the upper electrode 104 is patterned by etching only the upper electrode 104 using the photoresist film 105 as a mask in the step shown in FIG. 18, for example, chlorine-based etching when the upper electrode 104 made of Pt or the like is etched. A new problem arises in that the exposed surface of the ferroelectric film 103 is corroded by the gas. When the exposed surface of the ferroelectric film 103 is corroded in this way, the corroded portion does not function as the ferroelectric film 103. Therefore, the ferroelectric film polarized by the electric field that is laterally separated from the upper electrode 104 is eventually obtained. It becomes difficult to obtain the components of the body membrane 103. This problem is the same when a giant magnetoresistive material is used instead of the ferroelectric film 103. As a result, it is difficult to improve the read signal detection accuracy.

  One object of the present invention is to provide a memory capable of improving the signal reading accuracy by increasing the intensity of the signal read from the memory cell.

Means for Solving the Problems and Effects of the Invention

The memory according to one aspect of the present invention is formed on the first electrode film and the first electrode film, and is smaller than the thickness of the storage unit and the storage unit, and is 15% or more of the thickness of the storage unit on average. A memory material film having a thin film portion having a thickness of 2 mm, a second electrode film formed on the memory portion of the memory material film, a simple matrix type having a first electrode film, a memory material film, and a second electrode film A memory cell array region including a plurality of memory cells, a memory formed in a region different from the memory cell array region in plan view, a peripheral circuit region including a transistor, and a memory for storing a plurality of memory cells in the memory cell array region The insulating film is formed so as to cover substantially the entire region above the material film and suppresses diffusion of hydrogen that is not formed in the peripheral circuit region including the transistor.

  In the memory according to the one aspect, as described above, the memory material film including the memory portion and the thin film portion having a thickness smaller than the thickness of the memory portion is formed, for example, on the memory portion. Even when the surface of the memory material film is corroded by the chlorine-based etching gas at the time of etching the second electrode film, if the thin film portion is formed by removing the surface of the memory material film, Since the thin film portion can have memory characteristics with respect to a horizontal electric field, the intensity of a signal read from the memory cell can be improved. Thereby, the signal reading accuracy can be improved. Further, when the thin film portion is formed by etching a part of the memory material film by forming the thin film portion so that the average value is about 15% or more of the thickness of the memory material film, It is possible to prevent the first electrode film from being exposed by removing all the thin film portions due to the variation in the deposited film thickness of the memory material film and the variation in the etching rate. As a result, when the first electrode film is exposed and etched, the inconvenience that the etching compound adheres to the side surface of the memory material film to cause a short circuit between the first electrode film and the second electrode film is suppressed. can do. In this case, the insulating film preferably includes a film having a function of suppressing hydrogen diffusion. According to this structure, hydrogen can be prevented from diffusing from above into the memory material film, so that deterioration of memory characteristics due to hydrogen diffusing into the memory material film can be suppressed.

  In the memory according to the aforementioned aspect, preferably, the thin film portion has a thickness of about 95% or less of the storage portion of the storage material film on average. With this configuration, even when the surface of the memory material film is corroded by the chlorine-based etching gas when etching the second electrode film formed on the memory part, the surface of the memory material film is reduced by about 5%. Since it can be removed as described above, the corroded surface of the memory material film can be reliably removed.

  In the memory according to the above aspect, it is preferable to further include an insulating film that is formed so as to cover the second electrode film and the thin film portion of the memory material film, and against an etching mask when the thin film portion of the memory material film is processed. If comprised in this way, it can prevent that an etching mask and a memory material film contact by forming an etching mask on the insulating film, and patterning the thin film part of an insulating film and a memory material film . Thus, for example, even when using a photoresist film as an etching mask and a ferroelectric film that makes it difficult to remove the photoresist film when it comes into contact with the photoresist film as a memory material film, after patterning the thin film portion, The photoresist film can be easily removed.

  The memory according to the above aspect preferably further includes a connection wiring for connecting the memory cell array region and the peripheral circuit region, at least in the vicinity of the connection region between the upper surface of the first electrode film in the memory cell array region and the connection wiring. The memory material film is patterned so that there is no thin film portion of the memory material film. With this configuration, for example, even when a ferroelectric film that is difficult to etch is used as the memory material film, the memory material film is formed when the contact hole is formed in the connection region between the memory cell array region and the connection wiring. Since there is no need to etch, a contact hole can be easily formed.

  In the memory according to the above aspect, the first electrode film includes a first lower electrode film and a second lower electrode film formed on the first lower electrode film, and the first lower electrode film is a diffusion of oxygen. It is preferable to have a function of suppressing the above. With this configuration, the first lower electrode film can function as an oxygen barrier film that suppresses oxygen diffusion.

  In the memory according to the above aspect, the memory material film may be formed so as to cover the upper surface and the side surface of the first electrode film. If comprised in this way, it can prevent that an etching damage is added to a 1st electrode film at the time of the etching of a memory | storage material film | membrane.

  The memory according to the above aspect further includes a transistor having a pair of source / drain regions and a conductive plug connected to one of the source / drain regions of the transistor, wherein the first electrode film is in contact with the conductive plug. It may be formed so as to. If comprised in this way, a favorable electrical characteristic can be acquired compared with the case where a conductive plug and a 1st electrode film are connected via wiring.

  In the invention according to the above aspect, the following configuration may be adopted.

  In the memory in which the first electrode film in the memory cell array region and the connection wiring are connected, preferably, the memory cell array region further includes an interlayer insulating film that covers at least the vicinity of the connection region and has an opening, and the memory via the opening. The first electrode film in the cell array region and the connection wiring are connected. With this configuration, the memory cell array region and the connection wiring can be easily connected.

  In the memory according to the above aspect, the memory material film may be one of a ferroelectric film and a giant magnetoresistive film.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments embodying the present invention will be described below with reference to the drawings.

(First embodiment)
FIG. 1 is a cross-sectional view showing a simple matrix ferroelectric memory according to a first embodiment of the present invention.

  Referring to FIG. 1, the simple matrix ferroelectric memory according to the first embodiment includes a memory cell array region 50 and a peripheral circuit region 60. An element isolation region 2 having an STI (Shallow Trench Isolation) structure is formed in a predetermined region on the surface of the p-type silicon substrate 1.

  In the peripheral circuit region 60, a pair of high-concentration impurity regions 8 are formed in the element formation region surrounded by the element isolation region 2 with a predetermined interval. An extension region (low concentration impurity region) 6 is formed on the channel region side of the high concentration impurity region 8. The high concentration impurity region 8 and the extension region (low concentration impurity region) 6 constitute a source / drain region. A gate electrode 4 made of a doped polysilicon film having a thickness of about 200 nm is formed on the channel region via a gate insulating film 3 made of a silicon oxide film having a thickness of about 5 nm. A silicon oxide film 5 having a thickness of about 150 nm is formed on the gate electrode 4. A sidewall insulating film 7 made of a silicon oxide film is formed on the side surfaces of the gate electrode 4 and the silicon oxide film 5.

  Further, an interlayer insulating film 9 formed by sequentially laminating a silicon oxide film, a BPSG film, and a silicon oxide film is provided so as to cover the entire surface. Contact holes 9 a reaching the pair of high concentration impurity regions 8 are formed in the interlayer insulating film 9. A barrier film made of a Ti film 10 having a thickness of about 10 nm and a TiN film 11 having a thickness of about 15 nm is formed in the contact hole 9a. A tungsten plug 12 is embedded in a region surrounded by the TiN film 11.

  Further, an IrSiN film 13 having a thickness of about 100 nm is formed in a region corresponding to the memory cell array region 50 of the interlayer insulating film 9. The IrSiN film 13 functions as an oxygen barrier film that suppresses oxygen diffusion. A Pt film 14 having a thickness of about 100 nm is formed on the IrSiN film 13. The IrSiN film 13 and the Pt film 14 constitute a lower electrode of the ferroelectric capacitor. This lower electrode is an example of the “first electrode film” in the present invention. On the tungsten plug 12 in the peripheral circuit region 60, an IrSiN film 13a and a Pt film 14a formed by patterning the same layer as the IrSiN film 13 and the Pt film 14 in the memory cell array region 50 are formed.

On the Pt film 14 in the memory cell array region 50, a ferroelectric film 15 made of an SBT (SrBi ₂ Ta ₂ O ₉ ) film is formed. On the ferroelectric film 15, an upper electrode 16 made of a Pt film having a thickness of about 200 nm is formed. The ferroelectric film 15 is an example of the “memory material film” in the present invention, and the upper electrode 16 is an example of the “second electrode film” in the present invention.

  Here, in the first embodiment, the ferroelectric film 15 is located under the upper electrode 16 and has a storage portion 15a having a thickness of about 200 nm, and is located in a region other than the storage portion 15a, and the storage portion has an average value. The thin film portion 15b has a thickness of about 15% to about 95% of the thickness of 15a.

  The lower electrode composed of the IrSiN film 13 and the Pt film 14, the storage portion 15a of the ferroelectric film 15, and the upper electrode 16 constitute one ferroelectric capacitor constituting one memory cell.

  In the first embodiment, the silicon nitride film 17 is formed so as to cover the upper electrode 16 and the thin film portion 15 b of the ferroelectric film 15. The silicon nitride film 17 is provided to prevent the photoresist film and the thin film portion 15b from contacting each other in the patterning process of the thin film portion 15b described later. The silicon nitride film 17 also has a function as a hydrogen diffusion barrier that suppresses diffusion of hydrogen. The silicon nitride film 17 is an example of the “insulating film” in the present invention.

  An interlayer insulating film 18 made of a silicon oxide film is formed so as to cover the entire surface of the memory cell array region 50 and the peripheral circuit region 60. Via holes 18 a and 18 b are formed in the interlayer insulating film 18. TiN film 19 having a thickness of about 15 nm is formed in via hole 18a and via hole 18b so as to be in contact with Pt film 14a in peripheral circuit region 60 and Pt film 14 in memory cell array region 50, respectively. An Al film 20 having a thickness of about 200 nm is formed on the TiN film 19. The TiN film 19 and the Al film 20 constitute a connection wiring for connecting the memory cell array region 50 and the peripheral circuit region 60.

  In the first embodiment, the thin film portion 15b of the ferroelectric film is patterned so as not to exist in the vicinity of the via hole 18b for connecting the memory cell array region 50 and the connection wiring.

  Next, the relationship between the thickness of the thin film portion 15b of the ferroelectric film 15 and the amount of remanent polarization will be described with reference to FIG. The horizontal axis of FIG. 2 shows the ratio of the thickness of the thin film portion 15b when the thickness of the storage portion 15a of the ferroelectric film 15 is 100%. The vertical axis shows the rate of increase in the amount of remanent polarization when there is no thin film portion 15b (conventional case). FIG. 2 shows the rate of increase in the amount of remanent polarization when the line width of the upper electrode 16 is 1 μm. As shown in FIG. 2, it can be seen that the rate of increase in the amount of remanent polarization increases as the film thickness of the thin film portion 15b increases. Specifically, when the film thickness of the thin film portion 15b is 50% (100 nm) of the film thickness (200 nm) of the storage portion 15a, the increase rate of the residual polarization amount is about 3%. Further, when the thickness of the thin film portion 15b of the ferroelectric film 15 is the same as the thickness of the storage portion 15a (in the case of 100%), the increase rate of the residual polarization amount is about 14%. From the graph shown in FIG. 2, it can be seen that as the thickness of the thin film portion 15 b is increased, the thin film portion 15 b can have a larger amount of remanent polarization with respect to a lateral electric field from the upper electrode 16. Further, from the result of FIG. 2, the proportion of the thin film portion 15b having a larger amount of remanent polarization with respect to the electric field in the lateral direction of the upper electrode 16 is further increased when the line width of the upper electrode 16 is 1 μm or less. Become. For this reason, the line width of the upper electrode 16 is preferably 1 μm or less.

On the other hand, when the thin film portion 15b is formed with the same thickness as the memory portion 15a of the ferroelectric film 15, the surface of the thin film portion 15b is formed by a chlorine-based etching gas (Cl ₂ / Ar-based gas) when the upper electrode 16 is patterned. Is corroded, the corroded surface of the thin film portion 15b remains without being removed. In that case, since the corroded surface of the thin film portion 15b does not function as a ferroelectric material, it becomes difficult to function the thin film portion 15b as a ferroelectric material with respect to a lateral electric field from the upper electrode 16. Therefore, an increase in the amount of remanent polarization cannot be obtained. When such a corroded portion on the surface of the thin film portion 15b is removed by etching, it is necessary to etch and remove the surface of the thin film portion 15b by a thickness of about 5% or more of the film thickness of the thin film portion 15b. Therefore, the thickness of the thin film portion 15b is preferably about 95% or less of the thickness of the storage portion 15a on average.

  Further, if the thickness of the thin film portion 15b is smaller than 15% of the thickness of the storage portion 15a, the deposited film thickness of the ferroelectric film 15 in the wafer plane is reduced when the thin film portion 15b is formed by etching. Due to the variation and the variation in the etching rate, the thin film portion 15b may be completely removed in a part of the region, and the Pt film 14 constituting the lower electrode may be exposed. In this case, since the exposed Pt film 14 is etched, the etching compound adheres to the side surface of the storage portion 15a, causing a disadvantage that the lower electrode and the upper electrode 16 are short-circuited. Hereinafter, this problem will be described in detail with reference to FIGS.

First, it is very difficult in the process to leave the ferroelectric material in the range of 0 to 15% over the entire area of the wafer surface. FIG. 3 shows the film thickness distribution when a ferroelectric film is deposited on a 6-inch wafer, and FIG. 4 shows the etching rate when the ferroelectric film is etched with a CF ₄ / Ar-based gas. It is the figure which showed the internal variation. As shown in FIG. 3, when a ferroelectric film is deposited on a 6-inch wafer, a variation of about 5% occurs in the wafer surface. Further, as shown in FIG. 4, there is about 10% variation in etching rate. Therefore, from FIG. 3 and FIG. 4, if it is attempted to leave the thin film portion of the ferroelectric film with a thickness smaller than about 15% in the central portion of the wafer, the Pt film 14 constituting the lower electrode is etched in the peripheral portion of the wafer. An area that ends up occurs. In that region, the etching compound of the Pt film adheres to the side surface of the storage portion 15a of the ferroelectric film, which causes a disadvantage that the ferroelectric capacitor is easily short-circuited. Therefore, in consideration of variations in the deposited film thickness and etching rate of the ferroelectric film shown in FIGS. 3 and 4, the thickness of the thin film portion 15b is about 15% or more of the thickness of the storage portion 15a on average. It needs to be thick.

  From the above results, it is preferable that the thin film portion 15b of the ferroelectric film 15 has an average thickness of about 15% to about 95% of the storage portion 15a.

  In the first embodiment, as described above, the ferroelectric film 15 having the memory portion 15a and the thin film portion 15b having a thickness smaller than the thickness of the memory portion 15a is formed, and thus formed on the memory portion 15a. Even when the surface of the thin film portion 15b is corroded by a chlorine-based etching gas when the upper electrode 16 is etched, if the thin film portion 15b is formed by etching and removing the surface of the thin film portion 15b, the upper electrode 16 The thin film portion 15b can function as a ferroelectric with respect to the horizontal electric field. Thereby, the strength of the signal read from the memory cell can be improved, so that the signal reading accuracy can be improved.

  In the first embodiment, as described above, a part of the ferroelectric film 15 is etched by forming the thin film portion 15b so as to have an average value of about 15% or more of the thickness of the storage portion 15a. Thus, when the thin film portion 15b is formed, all of the thin film portion 15b is removed to form the lower electrode due to variations in the deposited film thickness of the ferroelectric film 15 and variations in the etching rate within the wafer surface. Exposure of the Pt film 14 can be suppressed. As a result, when the Pt film 14 constituting the lower electrode is exposed and etched, the etching compound adheres to the side surface of the memory portion 15a, thereby causing a short circuit between the lower electrode and the upper electrode 16. Can be suppressed.

  Further, as shown in FIG. 1, by forming a silicon nitride film 17 as an insulating film so as to cover the surface of the thin film portion 15b, a photoresist is formed on the silicon nitride film 17 during patterning of the thin film portion 15b described later. Since a film (etching mask) can be formed and patterned, the contact between the photoresist film and the thin film portion 15b can be prevented. Thus, even when the ferroelectric film 15 that makes it difficult to remove the photoresist film when in contact with the photoresist film is used, the photoresist film can be easily removed after the patterning of the thin film portion 15b.

  Further, since the silicon nitride film 17 has a function of suppressing the diffusion of hydrogen, it is possible to suppress the diffusion of hydrogen into the ferroelectric film 15 from above. As a result, it is possible to easily suppress the deterioration of the characteristics due to the penetration of hydrogen into the ferroelectric film 15 made of oxide.

  In the first embodiment, as shown in FIG. 1, patterning is performed so that the thin film portion 15b of the ferroelectric film 15 does not exist in the vicinity of the via hole 18b for connection between the memory cell array region 50 and the connection wiring. This eliminates the need to etch the ferroelectric film 15, which is a material that is difficult to etch, when forming the via hole 18 b, so that the via hole 18 b can be easily formed.

  5 to 13 are cross-sectional views for explaining a manufacturing process of the simple matrix ferroelectric memory according to the first embodiment shown in FIG. A manufacturing process for the ferroelectric memory according to the first embodiment is now described with reference to FIGS.

  First, as shown in FIG. 5, an element isolation region 2 having an STI structure is formed in a predetermined region on a p-type silicon substrate 1. Thereafter, ion implantation for forming an n well and a p well and ion implantation for adjusting a threshold value of the n channel transistor and the p channel transistor are performed. Thereafter, a silicon oxide film 3a is formed with a thickness of about 5 nm using a thermal oxidation method. On the silicon oxide film 3a, a doped polysilicon film 4a is formed with a thickness of about 200 nm by CVD. A silicon oxide film 5a is formed on the doped polysilicon film 4a with a thickness of about 150 nm by using a low pressure CVD method (LPCVD: Low Pressure Chemical Vapor Deposition). Then, a photoresist film 21 is formed in a predetermined region on the silicon oxide film 5a.

Then, by etching the silicon oxide film 5a, the doped polysilicon film 4a and the silicon oxide film 3a using the photoresist film 21 as a mask, as shown in FIG. 6, the gate insulating film 3 made of a silicon oxide film, the doped film is formed. A gate electrode 4 and a silicon oxide film 5 made of a polysilicon film are formed. Thereafter, using the photoresist film 21 as a mask, arsenic (As) ions are ion-implanted under conditions of implantation energy: about 10 keV and dose amount: about 1 × 10 ¹⁴ cm ⁻² . Thereby, an n-type extension region (low concentration impurity region) 6 is formed. Thereafter, the photoresist film 21 is removed.

Next, as shown in FIG. 7, a silicon oxide film (not shown) having a thickness of about 200 nm is formed on the entire surface by LPCVD, and then the silicon oxide film is anisotropically etched to form a gate. A sidewall insulating film 7 is formed on the side surfaces of the insulating film 3, the gate electrode 4 and the silicon oxide film 5. Then, using this sidewall insulating film 7 as a mask, arsenic (As) ions are ion-implanted under the conditions of implantation energy: about 30 keV and dose: about 1 × 10 ¹⁵ cm ⁻² , thereby providing a high concentration impurity region. 8 is formed. The extension region 6 and the high concentration impurity region 8 constitute a source / drain region. Thereafter, in order to activate the implanted impurities, a heat treatment is performed at about 850 ° C. for about 30 minutes in a nitrogen atmosphere.

  Next, a LPCVD method is used to form a silicon oxide film with a thickness of about 200 nm so as to cover the entire surface, and then a BPSG film is deposited on the silicon oxide film with a thickness of about 800 nm. Then, the BPSG film is reflowed by performing heat treatment at about 850 ° C. for about 30 minutes in an oxygen atmosphere. Thereafter, the BPSG film is etched or polished by dry etching or CMP (Chemical Mechanical Polishing) until the BPSG film has a desired thickness. Then, a silicon oxide film is deposited with a thickness of about 100 nm on the BPSG film using LPCVD. Thereby, an interlayer insulating film 9 having a three-layer structure of a silicon oxide film, a BPSG film, and a silicon oxide film is formed. Then, a contact hole 9 a reaching the high concentration region 8 is formed in the interlayer insulating film 9 by using a photolithography technique and a dry etching technique.

  Then, a Ti film 10 having a thickness of about 10 nm and a TiN film 11 having a thickness of about 15 nm are sequentially deposited in the contact hole 9a and on the upper surface of the interlayer insulating film 9 by sputtering. Thereafter, a tungsten film 12 is deposited with a thickness of about 400 nm. Then, by removing the excess tungsten film 12, TiN film 11 and Ti film 10 formed in the region other than the contact hole 9a by using the CMP method, a shape as shown in FIG. 7 is obtained.

Next, an IrSiN film (not shown) having a thickness of about 100 nm and a Pt film (not shown) having a thickness of about 100 nm are sequentially deposited so as to cover the entire surface by sputtering, and then photolithography is performed. The Pt film and the IrSiN film are patterned using a technique and dry etching using a Cl ₂ / Ar-based gas. As a result, as shown in FIG. 8, the IrSiN film 13 and the Pt film 14 constituting the lower electrode are formed in the memory cell array region 50, and the IrSiN film 13a and the Pt film 14a are formed in the peripheral circuit region 60.

  Thereafter, as shown in FIG. 9, a solution for SBT (SBT solution) is applied to the entire surface at about 2000 rpm for about 30 seconds using a spin coating method. Then, a solvent component (ethanol, ethylhexane, etc.) is evaporated by performing a heat treatment at about 200 ° C. for about 15 minutes in the atmosphere. Thereafter, a baking process at about 650 ° C. for about 1 hour is performed in an oxidizing atmosphere. The spin coating and heat treatment of these SBT solutions are repeated until the ferroelectric film 15 has a thickness of about 200 nm. Thereafter, a Pt film 16a is formed with a thickness of about 200 nm by sputtering. Then, a photoresist film 22 is formed in a predetermined region on the Pt film 16a.

Thereafter, by using the photoresist film 22 as a mask, the Pt film 16a is etched using dry etching with a Cl ₂ / Ar-based gas, thereby forming the upper electrode 16 made of the patterned Pt film as shown in FIG. Is done. In this state, the surface of the ferroelectric film 15 is in a state of being corroded by a Cl ₂ / Ar-based gas when the Pt film 16a is etched.

From this state, in this embodiment, as shown in FIG. 11, the ferroelectric film 15 (thin film) is used by dry etching with CF ₄ / Ar-based gas not containing chlorine-based gas using the photoresist film 22 as a mask. The surface of the ferroelectric film 15 is etched away by a predetermined thickness so that the thickness of the portion 15b) is about 15% or more and about 95% or less. As a result, the corroded portion of the surface of the ferroelectric film 15 is removed, and the storage portion 15a and the thin film portion 15b of the ferroelectric film 15 are formed. Thereafter, the photoresist film 22 is removed.

Next, as shown in FIG. 12, after a silicon nitride film 17 is deposited to a thickness of about 10 nm to about 50 nm by sputtering, a photoresist film (etching mask) 23 is formed in a predetermined region on the silicon nitride film 17. Form. Then, using the photoresist film 23, first, the silicon nitride film 17 is etched by dry etching with CF ₄ based gas, a thin film portion 15b made of SBT film by dry etching with _CF 4 / Ar-based gas etching To do. Thereby, the ferroelectric film 15 having the patterned storage portion 15a and thin film portion 15b is obtained. In the first embodiment, patterning is performed so that the thin film portion 15b of the ferroelectric film does not exist in the vicinity of the via hole 18b for connecting the memory cell array region 50 and the connection wiring. Thereafter, the photoresist film 23 is removed.

  Next, as shown in FIG. 13, a silicon oxide film 18 is deposited with a thickness of about 400 nm by plasma CVD so as to cover the entire surface. Then, after forming a photoresist film 24 in a predetermined region on the silicon oxide film 18, the silicon oxide film 18 is etched using the photoresist film 24 as a mask, thereby forming via holes 18 a and 18 b in the silicon oxide film 18. At this time, since the thin film portion 15b of the ferroelectric film 15 does not exist in the vicinity of the via hole 18b serving as a connection region between the memory cell array region 50 and the connection wiring, the SBT which is difficult to be etched during the formation of the via hole 18b It is not necessary to etch the ferroelectric film 15 made of a film. Thereby, the via hole 18b can be easily formed. Thereafter, the photoresist film 24 is removed.

  Finally, as shown in FIG. 1, after depositing a TiN film 19 having a thickness of about 15 nm and an Al film 20 having a thickness of about 200 nm using a sputtering method, a photolithography technique and a dry etching technique are performed. To pattern. Thereby, a connection wiring made of the TiN film 19 and the Al film 20 for connecting the memory cell array region 50 and the peripheral circuit region 60 is formed. In this way, the simple matrix ferroelectric memory according to the first embodiment is formed.

(Second Embodiment)
FIG. 14 is a cross-sectional view showing a non-volatile memory using a cross-point type giant magnetoresistive material according to a second embodiment of the present invention. Referring to FIG. 14, in the second embodiment, unlike the first embodiment, an example in which the present invention is applied to a nonvolatile memory using a giant magnetoresistive material as a memory material film will be described.

Specifically, in the nonvolatile memory according to the second embodiment, PCMO (Pr ₀₎ as a giant magnetoresistive material film is used instead of the ferroelectric film 15 made of the SBT film of the first embodiment shown in FIG. _.7 Ca _0.3 MnO ₃ ) film 25 is used. The PCMO film 25 is an example of the “memory material film” in the present invention. The PCMO film 25 includes a memory portion 25a having a thickness of about 200 nm located under the upper electrode 16 and a thin film portion 25b having a thickness of about 15% to about 95% of the thickness of the memory portion 25a. . The lower electrode composed of the IrSiN film 13 and the Pt film 14, the PCMO film 25, and the upper electrode 16 composed of the Pt film constitute a resistance element for storing data. Specifically, in the nonvolatile memory using the giant magnetoresistive material film (PCMO film 25) according to the second embodiment, the difference in resistance value of the PCMO film 25 sandwiched between the upper electrode 16 and the lower electrode. Is used to hold the data.

  In the second embodiment, as described above, the giant magnetoresistive material film (PCMO film) 25 has the storage unit 25a located under the upper electrode 16 and the thin film unit 25b having a smaller thickness than the storage unit 25a. Even when the surface of the thin film portion 25b is corroded by the chlorine-based etching gas when the upper electrode 16 is etched, the thin film portion 25b is removed by etching the surface of the thin film portion 25b. If formed, the thin film portion 25b can function as a resistance component with respect to a horizontal electric field from the upper electrode 16. Thereby, the strength of the signal read from the memory cell can be improved, so that the signal reading accuracy can be improved.

  The remaining effects of the second embodiment are similar to those of the first embodiment.

(Third embodiment)
FIG. 15 is a sectional view showing a simple matrix ferroelectric memory according to a third embodiment of the present invention. Referring to FIG. 15, in the third embodiment, the structure of the simple matrix ferroelectric memory according to the first embodiment is configured such that the lower electrode is directly connected to the tungsten plug and the ferroelectric film is lower. An example of changing the structure to cover the upper surface and side surfaces of the electrode will be described.

  Specifically, the simple matrix ferroelectric memory according to the third embodiment includes a memory cell array region 90 and a peripheral circuit region 95 as shown in FIG. The p-type silicon substrate 1, the element isolation region 2, the gate insulating film 3, the gate electrode 4, the silicon oxide film 5, the extension region (low concentration impurity region) 6, the side wall insulating film 7, the high concentration impurity region 8, and the interlayer The insulating film 9, the Ti film 10, the TiN film 11, and the tungsten plug 12 have the same structure (composition and film thickness) as in the first embodiment.

  In the third embodiment, an IrSiN film 73 having a thickness of about 100 nm is formed on a region corresponding to the memory cell array region 90 of the interlayer insulating film 9. The IrSiN film 73 is formed so as to extend onto the tungsten plug 12 and is in direct contact with the tungsten plug 12. The IrSiN film 73 functions as an oxygen barrier film that suppresses oxygen diffusion. On this IrSiN film 73, a Pt film 74 having a thickness of about 100 nm is formed. The IrSiN film 73 and the Pt film 74 constitute the lower electrode of the ferroelectric capacitor. This lower electrode is an example of the “first electrode film” in the present invention. On the tungsten plug 12 in the peripheral circuit region 95, an IrSiN film 73a and a Pt film 74a formed by patterning the same layer as the IrSiN film 73 and the Pt film 74 in the memory cell array region 90 are formed.

Here, in the third embodiment, a ferroelectric film made of an SBT (SrBi ₂ Ta ₂ O ₉ ) film so as to cover the upper surface and side surfaces of the lower electrode made of the IrSiN film 73 and the Pt film 74 in the memory cell array region 90. 75 is formed. In a predetermined region on the upper surface of the ferroelectric film 75, an upper electrode 76 made of a Pt film having a thickness of about 200 nm is formed. The ferroelectric film 75 is an example of the “memory material film” in the present invention, and the upper electrode 76 is an example of the “second electrode film” in the present invention.

  In the third embodiment, the ferroelectric film 75 is located in a region on the Pt film 74 other than the storage unit 75a and the storage unit 75a having a thickness of about 200 nm positioned below the upper electrode 76, and has an average value. The thin film portion 75b has a thickness of about 15% to about 95% of the thickness of the storage portion 75a.

  The lower electrode composed of the IrSiN film 73 and the Pt film 74, the storage portion 75a of the ferroelectric film 75, and the upper electrode 76 constitute one ferroelectric capacitor constituting one memory cell.

  In the third embodiment, the silicon nitride film 77 is formed so as to cover the upper electrode 76 and the thin film portion 75 b of the ferroelectric film 75. The silicon nitride film 77 is provided to prevent the photoresist film and the thin film portion 75b from contacting each other in the patterning process of the thin film portion 75b. The silicon nitride film 77 also has a function as a hydrogen diffusion barrier that suppresses diffusion of hydrogen. The silicon nitride film 77 is an example of the “insulating film” in the present invention.

  An interlayer insulating film 78 made of a silicon oxide film is formed so as to cover the entire surface of the memory cell array region 90 and the peripheral circuit region 95. A via hole 78 a is formed in a region corresponding to the peripheral circuit region 95 of the interlayer insulating film 78. A TiN film 79 having a thickness of about 15 nm is formed in the via hole 78a so as to be in contact with the Pt film 74a in the peripheral circuit region 95. On the TiN film 79, an Al film 80 having a thickness of about 200 nm is formed.

In the third embodiment, as described above, a ferroelectric film made of an SBT (SrBi ₂ Ta ₂ O ₉ ) film so as to cover the upper surface and side surfaces of the lower electrode made of the IrSiN film 73 and the Pt film 74 in the memory cell array region 90. By forming the body film 75, it is possible to prevent the etching damage to the lower electrode (Pt film 74) of the ferroelectric capacitor (memory cell) when the insulating film 77 and the ferroelectric film 75 are etched. . Therefore, when the IrSiN film 73 constituting the lower electrode of the dielectric capacitor (memory cell) is formed so as to be in direct contact with the tungsten plug 12, the lower electrode and the tungsten plug 12 are connected via the wiring. Compared to the above, it is possible to obtain better electrical characteristics (resistance of the lower electrode, etc.).

  Etching damage is applied to the Pt film 74a in the peripheral circuit region 95 when the insulating film 77 and the ferroelectric film 75 are etched. However, since the TiN film 79 / Al film 80 is connected to the Pt film 74a after the insulating film 77 and the ferroelectric film 75 are etched, the Pt film 74a is electrically connected to the tungsten plug 12 in the peripheral region 95. The effect of etching damage on electrical characteristics is small.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the scope of claims for patent, and further includes all modifications within the meaning and scope equivalent to the scope of claims for patent.

  For example, in the above embodiment, the Pt film is used as the upper layer of the lower electrode. However, the present invention is not limited to this, and instead of the Pt film, an Ir film, a Pd film, a Co film, an Rh film, a Re film, Mo A film or a Ru film can be used.

In the above embodiment, the IrSiN film is used as the lower layer of the lower electrode. However, the present invention is not limited to this, and instead of the IrSiN film, a TiO ₂ film, a CoSiN film, a RuSiN film, a Ti film, or a Pt / TiO film is used. _Two films, a TaSiN film, a Pt film, an IrO ₂ film, or a TiN film may be used.

In the above embodiment, an SBT (Sr _x Bi _y Ta ₂ O ₉ ) film is used as the ferroelectric film. However, the present invention is not limited to this, and the SBTN (Sr _x Bi _y (Nb, Ta) _{2 is used.} O ₉ ) film, PZT (Pb (Zr, Ti) O ₃ ) film, PLZT ((Pb, La) (Zr, Ti) O ₃ ) film, BLT ((Bi, La) ₄ Ti ₃ O ₁₂ ) film, etc. It is also possible to use an organic ferroelectric film such as a ferroelectric film or a vinylidene fluoride / trifluoride ethylene copolymer.

  In the above embodiment, the PCMO film is used as the giant magnetoresistive material film. However, the present invention is not limited to this, and a giant magnetoresistive material film other than the PCMO film may be used.

In the above embodiment, the ferroelectric material film or the giant magnetoresistive material film is used as the memory material film positioned between the upper electrode and the lower electrode. However, the present invention is not limited to this, and other materials are used. A memory material film may be used. For example, a resistance change film made of an organic material or a memory material film made of a chalcogenide film (for example, Ge ₂ Sb ₂ Te ₅ ) may be used.

In the above embodiment, the silicon nitride film (SiN film) is formed as the insulating film covering the surface of the thin film portion. However, the present invention is not limited to this, and the insulating film covering the surface of the thin film portion is not limited thereto. _Two films may be used. Also in this case, the insulating film can prevent the thin film portion and the photoresist film from contacting each other during patterning of the thin film portion. The SiON film has a function of suppressing hydrogen diffusion, like the SiN film, while the SiO ₂ film does not have a function of suppressing hydrogen diffusion.

  In the above-described embodiment, the simple matrix type ferroelectric memory or the nonvolatile memory has been described. However, the present invention is not limited to this and can be applied to a one-transistor one-capacitor type ferroelectric memory.

  In the above embodiment, the tungsten plug is used as an example of the conductive plug. However, the present invention is not limited to this, and another conductive plug such as a conductive polysilicon plug is used instead of the tungsten plug. Also good.

1 is a cross-sectional view showing a simple matrix ferroelectric memory according to a first embodiment of the present invention. It is the correlation figure which showed the relationship between the film thickness of the thin film part of a ferroelectric film, and the amount of remanent polarization. FIG. 6 is a characteristic diagram for explaining variations in the thickness of a ferroelectric film within a wafer surface. It is a characteristic view for demonstrating the dispersion | variation in the etching rate within a wafer surface. FIG. 7 is a cross-sectional view for explaining a manufacturing process of the simple matrix ferroelectric memory according to the first embodiment shown in FIG. 1. FIG. 7 is a cross-sectional view for explaining a manufacturing process of the simple matrix ferroelectric memory according to the first embodiment shown in FIG. 1. FIG. 7 is a cross-sectional view for explaining a manufacturing process of the simple matrix ferroelectric memory according to the first embodiment shown in FIG. 1. FIG. 7 is a cross-sectional view for explaining a manufacturing process of the simple matrix ferroelectric memory according to the first embodiment shown in FIG. 1. FIG. 7 is a cross-sectional view for explaining a manufacturing process of the simple matrix ferroelectric memory according to the first embodiment shown in FIG. 1. FIG. 7 is a cross-sectional view for explaining a manufacturing process of the simple matrix ferroelectric memory according to the first embodiment shown in FIG. 1. FIG. 7 is a cross-sectional view for explaining a manufacturing process of the simple matrix ferroelectric memory according to the first embodiment shown in FIG. 1. FIG. 7 is a cross-sectional view for explaining a manufacturing process of the simple matrix ferroelectric memory according to the first embodiment shown in FIG. 1. FIG. 7 is a cross-sectional view for explaining a manufacturing process of the simple matrix ferroelectric memory according to the first embodiment shown in FIG. 1. It is sectional drawing which showed the non-volatile memory using the cross point type | mold giant magnetoresistive material by 2nd Embodiment of this invention. 6 is a cross-sectional view showing a simple matrix ferroelectric memory according to a third embodiment of the present invention; FIG. It is sectional drawing which showed the structure of the conventional simple matrix type ferroelectric memory. FIG. 17 is a cross-sectional view for explaining a manufacturing process of the conventional simple matrix ferroelectric memory shown in FIG. 16. FIG. 17 is a cross-sectional view for explaining a manufacturing process of the conventional simple matrix ferroelectric memory shown in FIG. 16.

Explanation of symbols

13, 73 IrSiN film (first electrode film)
14, 74 Pt film (first electrode film)
15, 75 Ferroelectric film (memory material film)
15a Memory unit 15b Thin film unit 16, 76 Upper electrode (second electrode film)
17, 77 Silicon nitride film (insulating film)
19, 79 TiN film (connection wiring)
20, 80 Al film (connection wiring)
18b Via hole (connection area)
25 Giant magnetoresistive material film (memory material film)
25a, 75a Storage unit 25b, 75b Thin film unit

Claims (5)

A first electrode film;
A memory formed on the first electrode film and having a memory portion and a thin film portion having a thickness smaller than the thickness of the memory portion and having an average value of 15% to 95% of the thickness of the memory portion. A material film,
A second electrode film formed on the storage portion of the storage material film,
A memory cell array region including a plurality of simple matrix memory cells having the first electrode film, the memory material film, and the second electrode film;
A peripheral circuit region including a transistor, formed in a region different from the memory cell array region in plan view;
The memory cell array region is formed so as to cover substantially the entire region above the memory material film in the region where the plurality of memory cells are formed, and is not formed in the peripheral circuit region including the transistor. A memory comprising an insulating film for suppressing diffusion. A connection wiring for connecting the memory cell array region and the peripheral circuit region;
The memory material film is patterned so that a thin film portion of the memory material film does not exist at least in the vicinity of a connection region between the upper surface of the first electrode film and the connection wiring in the memory cell array region. The memory according to 1 . The first electrode film includes a first lower electrode film and a second lower electrode film formed on the first lower electrode film,
The first lower electrode layer has a function of suppressing the diffusion of oxygen, the memory according to any one of claims 1 and 2. Wherein the storage material film, the first electrode layer is formed to cover the upper and side surfaces of the memory according to any one of claims 1 and 3. A conductive transistor having a pair of source / drain regions;
And a conductive plug connected to one of the source / drain regions of the transistor,
The first electrode layer is formed to contact the conductive plug, the memory according to any one of claims 1, 3 and 4.

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