JP4442703B2 - Sample hold circuit, multiplying D / A converter and A / D converter - Google Patents

Description

  The present invention is a sample hold circuit suitable for an A / D converter or its pre-circuit, and a multiple D / A converter and A / D using the same, which hold an input voltage and perform differential output. Concerning the converter.

  For each stage of the pipeline A / D converter and the cyclic A / D converter, a multiplying D / A converter is used. This multiplying D / A converter amplifies the voltage obtained by subtracting the reference voltage Vref from the input voltage Vin, and amplifies the voltage determined according to the A / D conversion value (digital value) of the input voltage Vin. The residual voltage subtracted from the voltage is held. Patent Document 1 discloses this multiplying D / A converter and a differential output type sample-and-hold circuit used therefor.

  In the sample and hold circuit of Patent Document 1, a plurality of inversion-side capacitors and non-inversion-side capacitors are connected in pairs to an inverting input terminal and a non-inverting input terminal of an operational amplifier. In the sampling operation, a predetermined charge is set for each capacitor, and an input voltage is applied to at least one capacitor. In the hold operation, at least a pair of inverting and non-inverting capacitors are connected between the input / output terminals of the operational amplifier, and an input voltage is applied to at least one capacitor.

  The single-end input sample and hold circuit disclosed in Patent Document 1 satisfies the predetermined first to third conditions so that the input voltage (common-mode input voltage) of the operational amplifier during the hold operation is the input voltage during the sampling operation. The sampled voltage is kept accurately even if the input voltage changes during the hold operation. Since the op-amp is operated with an optimal common-mode input voltage, the gain and slew rate can be set large, and a stable operating state can be ensured. However, this Patent Document 1 clearly discloses a sample-and-hold circuit having an input voltage range (input dynamic range) from 0 V to a power supply voltage and a multiplying D / A converter using the sample-hold circuit. Therefore, for example, when used in the first stage of a pipeline type A / D converter, only a voltage within the above input voltage range can be input.

On the other hand, Patent Documents 2 and 3 disclose A / D converters capable of converting a voltage exceeding the input voltage range. The device described in Patent Document 2 includes a voltage dividing unit that divides an input voltage, and is configured to input a divided voltage signal to an A / D converter. According to the method described in Patent Document 3, when it is detected that the A / D conversion value matches the upper limit value or the lower limit value that can be expressed by the number of A / D conversion bits, the bias control circuit switches the bias voltage of the amplifier circuit to amplify The output voltage of the circuit is shift controlled. The output digital conversion value is corrected by correction data set according to the bias voltage.
Japanese Patent Laid-Open No. 2007-159087 JP 2006-024975 A JP 2006-115027 A

  If a voltage divider circuit or bias control circuit using a resistor ladder is provided to expand the input voltage range, problems such as a decrease in conversion accuracy due to errors in the voltage divider circuit, an increase in layout area, and an increase in external components occur. .

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a sample-and-hold circuit having an expanded input voltage range, and a multiplying D / A converter and an A / D converter using the sample-and-hold circuit. .

  The present invention is an improved invention obtained by conducting a new analysis from the viewpoint of expanding the input voltage range based on the invention disclosed in Patent Document 1 (hereinafter referred to as a patented invention). The actions and effects provided by the above-mentioned patented invention, and the conditions necessary for that, are maintained as they are. The first condition to the third condition, the fourth condition, and the fifth condition in the above-mentioned patented invention are the first condition to the third condition, the fifth condition (the fifth A and 5B conditions), and the sixth condition in the present invention, respectively. Equivalent to.

  According to the means described in claim 1, since the total capacitance value of the inverting capacitor to which the input voltage is applied during the sampling operation and the total capacitance value of the non-inverting capacitor are substantially different (third condition), the hold The sampled voltage appears in the voltage.

  When N is a positive value, the capacitance values of at least a pair of the inverting side capacitor and the non-inverting side capacitor connected to the non-inverting output terminal and the inverting output terminal of the operational amplifier at the time of the hold operation are (the input voltage during the sampling operation). -The total capacitance value of the inverting side capacitor to which the input voltage is applied-The total capacitance value of the non-inverting side capacitor to which the input voltage is applied during the sampling operation-The total capacitance value of the inverting side capacitor to which the input voltage is applied during the holding operation + Since it is set to be substantially equal to the total capacitance value of the non-inversion side capacitors to which the input voltage is applied) × (N / 2) (fourth condition), the input voltage is multiplied by 1 / N. Is sampled and held.

  According to this means, the input voltage can be divided by 1 / N times (N> 1) or amplified to 1 / N times (0 <N <1), so that the input voltage range (input dynamic range) can be increased. For example, an input voltage exceeding the power supply voltage can be directly sampled and held and applied to A / D conversion or the like. Since circuits for amplification and voltage division are not required, problems such as a decrease in conversion accuracy, an increase in layout area, and an increase in external parts do not occur.

  According to the means described in claim 2, since the total capacitance value of the inverting side capacitor to which the input voltage is applied during the hold operation is substantially equal to the total capacitance value of the non-inverting side capacitor (second condition), Even if the input voltage changes during operation, the sampled voltage is maintained accurately.

  According to the third aspect, the total capacitance value of the capacitor to which the input voltage is applied during the sampling operation is substantially equal to the total capacitance value of the capacitor to which the input voltage is applied during the hold operation (first Condition), the input voltage of the operational amplifier during the hold operation does not depend on the input voltage during the sampling operation. Therefore, regardless of the magnitude of the input voltage during the sampling operation, the input voltage of the operational amplifier during the hold operation can be maintained at a predetermined common-mode input voltage, and the operational amplifier can be operated at a desired gain and slew rate.

  According to the fourth aspect of the present invention, since the circuit configuration is the same as that of the first aspect of the invention and the first condition is satisfied, the input voltage of the operational amplifier during the hold operation is equal to the input voltage during the sampling operation. Do not depend. Therefore, the input voltage of the operational amplifier during the hold operation can be maintained at a predetermined common-mode input voltage, and the operational amplifier can be operated at a desired gain and slew rate.

  Also, the input voltage is applied during the sampling operation and the sum of the total capacitance value of the inverting capacitor to which the input voltage is applied during the sampling operation and the total capacitance value of the non-inverting capacitor to which the input voltage is applied during the hold operation. Since the sum of the total capacitance value of the non-inverting capacitor and the total capacitance value of the inverting capacitor to which the input voltage is applied during the hold operation is substantially different (fifth condition), the voltage sampled as the hold voltage is appear. In this means, the hold voltage is affected by the change ΔV of the input voltage during the hold period, but the bandwidth of the input voltage is limited and the coefficient of the change ΔV can be set to be small. It is possible to realize a hold characteristic without any problem.

  Furthermore, since the fourth condition is satisfied, the input voltage is sampled and held after being multiplied by 1 / N. According to this means, the input voltage range (input dynamic range) can be expanded or reduced, and the input voltage exceeding the power supply voltage can be directly sampled and held and applied to A / D conversion or the like.

  According to the means described in claim 5, the first condition and the fourth condition are satisfied. Further, the total capacitance value of the inverting side capacitor to which the input voltage is applied during the sampling operation and the total capacitance value of the inverting side capacitor to which the input voltage is applied during the holding operation are set to be substantially different (Condition 5A). The total capacitance value of the non-inverting side capacitor to which the input voltage is applied during the sampling operation is set to be substantially different from the total capacitance value of the non-inverting side capacitor to which the input voltage is applied during the holding operation (Condition 5B) )ing. When these 5A and 5B conditions are combined, a condition equivalent to the fifth condition is obtained. Therefore, substantially the same operation and effect as the means described in claim 4 can be obtained.

  According to the means described in claims 6 and 7, the third condition is established for each of the inverting input voltage and the non-inverting input voltage. In addition, the inverting input voltage is applied by subtracting the total capacitance value of the non-inverting capacitor to which the non-inverting input voltage is applied from the total capacitance value of the inverting capacitor to which the non-inverting input voltage is applied during the sampling operation. Since the value obtained by subtracting the total capacitance value of the inverting side capacitor to which the inverting input voltage is applied from the total capacitance value of the non-inverting side capacitor is substantially equal (sixth condition), the differential input voltage sampled to the hold voltage is appear.

  Further, since the seventh condition, which extends the fourth condition to the differential input voltage, is satisfied, the differential input voltage is sampled and held after being multiplied by 1 / N. According to this means, the input voltage can be divided by 1 / N times (N> 1) or amplified to 1 / N times (N <1), so that the input voltage range (input dynamic range) is expanded or The differential input voltage exceeding the power supply voltage can be directly sampled and held and applied to A / D conversion or the like. As long as the sixth condition is satisfied, the seventh condition described in claims 6 and 7 is equivalent.

  According to the eighth aspect of the invention, since the second condition is satisfied for each of the inverting input voltage and the non-inverting input voltage, the sampled voltage is accurately held even if the input voltage changes during the hold operation. to continue.

  According to the means described in claim 9, since the first condition is established for each of the inverting input voltage and the non-inverting input voltage, the input voltage of the operational amplifier during the hold operation does not depend on the input voltage during the sampling operation. .

  According to the means described in claim 10, since the operational amplifier is operated as a voltage follower during the sampling operation of the input voltage, the inverting input terminal and the non-inverting input terminal of the operational amplifier are biased to a predetermined voltage. Thus, a bias voltage supply circuit to the non-inverting input terminal is not necessary. Moreover, the influence of the offset voltage of the operational amplifier can be eliminated by setting appropriate conditions.

  According to the means described in claim 11, during the hold operation, the at least one pair of inverting and non-inverting capacitors respectively connected to the non-inverting output terminal and the inverting output terminal of the operational amplifier keep the capacitance values equal to each other. However, the capacitance value can be changed. Therefore, for example, when applied to a pipeline type A / D converter, the input voltage is multiplied by 1 / N in the first stage to which an external voltage is input, and the second stage and thereafter after the voltage within the power supply voltage range is input. Then, it can be configured to sample and hold the input voltage as it is. When applied to a cyclic A / D converter, the input voltage can be multiplied by 1 / N in the first round, and the input voltage can be sampled and held as it is in the second and subsequent rounds.

  According to the means described in claim 12, during the sampling operation, the input voltage is applied to at least one of the inverting side capacitor and the non-inverting side capacitor, and the other at least one capacitor according to the input digital value. A set DAC voltage is applied. As described above, the DAC voltage is applied only during the hold operation in the conventional configuration, but this means is characterized in that the DAC voltage is applied during the sampling operation. In addition, since an input voltage exceeding the power supply voltage can be directly input, a dividing circuit, a bias control circuit, and the like are not required. For this reason, problems such as a decrease in conversion accuracy, an increase in layout area, and an increase in external parts do not occur.

  According to the means described in claim 13, the A / D converter inputs again the residual voltage output from the unit conversion circuit composed of the sub A / D converter and the multiplying D / A converter to the unit conversion circuit. By executing the operation as many times as necessary, an A / D conversion code of the A / D conversion target voltage input to the A / D converter is generated. In this case, when at least the A / D conversion target voltage is input to the unit conversion circuit to obtain the first residual voltage, the input voltage is multiplied by 1 / N and the residual voltage is output. For example, an input voltage exceeding the power supply voltage or the reference voltage range can be directly sampled and held for A / D conversion.

  According to the means described in claim 14, a pipeline type A / D converter can be configured by connecting a plurality of unit conversion circuits in series.

  According to the means described in the fifteenth aspect, a cyclic A / D converter can be configured by including one or more unit conversion circuits and sequentially circulating the residual voltage in the unit conversion circuits.

  According to the means described in claim 16, only when the A / D conversion target voltage is input to the unit conversion circuit to obtain the first residual voltage, the residual voltage is output after multiplying the input voltage by 1 / N. . The pipeline type A / D converter has the first stage, and the cyclic type A / D converter has the first stage (the first stage in the case of a plurality of stages).

(First embodiment)
Hereinafter, a first embodiment in which a sample-and-hold circuit with a single end input is applied to a multiplying D / A converter (hereinafter referred to as MDAC) will be described with reference to FIGS.

  FIG. 1 is a configuration diagram of a sample and hold circuit including three capacitors on each of the inverting side and the non-inverting side, and using one capacitor as a feedback capacitor. The operational amplifier OP has a configuration for differentially outputting the hold voltage. One end of each of three capacitors Cs1, Cs2, and Cf1 (corresponding to the inverting side capacitor) is connected to the inverting input terminal of the operational amplifier OP, and the same number (three) of capacitors Cs3 and Cs4 are also connected to the non-inverting input terminal. , Cf2 (corresponding to a non-inversion side capacitor) are connected to one end. Capacitors Cs1 and Cs3, capacitors Cs2 and Cs4, and capacitors Cf1 and Cf2 are paired, and have the same capacitance value, that is, xC, yC, zC (x, y, z are positive values, and C is a unit capacitance value). have. The operational amplifier OP is assumed to have a sufficiently large open loop gain. The control circuit 2 determines the connection state of the capacitors Cs1, Cs2, Cf1, Cs3, Cs4, and Cf2 and the voltages Va, Vb, Vc, Vd, Ve, Vf, Vg, Vh, Vi, and Vj during the sampling operation and the holding operation. Control the application state.

  FIG. 2 is a basic circuit used for an A / D conversion stage of a pipelined A / D converter, a cyclic A / D converter, and the like. The unit conversion circuit 3 includes a sample hold circuit 1 (denoted as MDAC in the figure), a sub A / D converter 4 (denoted as sub ADC in the figure), and a multiplexer 5 (denoted as MPX in the figure). Yes. Among them, the sub A / D converter 4 performs a so-called 1.5-bit A / D conversion on the input voltage Vin, and a ternary (+1, 0, −1) A / D conversion value (corresponding to an input digital value). ) Is output.

  The multiplexer 5 outputs one or a plurality of analog voltages to the sample and hold circuit 1 according to the A / D conversion value by the sub A / D converter 4. The sample hold circuit 1 receives the input voltage Vin and the analog voltage from the multiplexer 5 and supplies the voltage Va so that these voltages satisfy the following expressions (1) to (4) and the first condition to the fourth condition. , Vb, Vc, Vd, Ve, Vf, Vg, Vh, Vi, Vj. The entire multiplexer 5 and sample hold circuit 1 may be referred to as a multiplying D / A converter.

  Ideally, the sample hold circuit 1 subtracts the reference voltage Vref from the value obtained by multiplying the input voltage Vin by 1 / N (N> 0) as shown in the equation (1), and amplifies it twice (first). Term), a value corresponding to the A / D conversion value is subtracted (second term), and the differential output voltage Vop1-Vom1 is obtained and held. Specifically, equations (2), (3), and (4) are obtained according to the A / D conversion values +1, 0, and −1, respectively. These equations are equivalent to outputting the residual voltage by doubling the difference voltage between the value obtained by multiplying the input voltage Vin by 1 / N and the value corresponding to the A / D conversion value (D / A conversion value). is there.

  FIG. 3 is an input / output characteristic diagram of the unit conversion circuit 3 when the power supply voltage = 5 V and N = 4. Since the input voltage Vin is input by multiplying the input voltage Vin by 1 / N according to the equation (1), the voltage Vin within the input voltage range (input dynamic range) from 0 V to 20 V (= 5 × N [V]). Can be directly input. In this case, when 0 ≦ Vin <7.5V, the A / D conversion value is +1, when 7.5V ≦ Vin <12.5V, the A / D conversion value is 0, and when 12.5V ≦ Vin <20V The A / D conversion value is -1.

Assuming that the input voltage during the sampling operation is Vin and the input voltage during the hold operation is Vin + ΔV, the characteristics desired to be realized by the sample hold circuit 1 of the present embodiment are as follows. The voltage ΔV represents a subsequent change with respect to the input voltage Vin when the sampling operation is shifted to the hold operation. However, the latter stage (second sentence) and characteristic (1D) of characteristic (1C) may be realized as necessary.
(1A) Single-ended input and differential output.
(1B) The input voltage Vin is applied to at least one capacitor during the sampling operation, and the input voltage Vin + ΔV is applied to at least one capacitor during the hold operation.
(1C) The sampled input voltage Vin multiplied by 1 / N is amplified twice and held. The hold voltage (differential output voltage Vop1-Vom1) does not depend on the input voltage Vin + ΔV during the hold operation.
(1D) The input voltage Vx1 (in-phase input voltage) of the operational amplifier OP during the hold operation does not depend on the input voltage Vin during the sampling operation.

  FIG. 1A shows a connection form during the sampling operation. The operational amplifier OP is connected as a voltage follower, and the voltages Vop and Vom output from the non-inverting output terminal and the inverting output terminal of the operational amplifier OP are both the common voltage Vcm0. In order to derive the general formula, it is assumed that voltages Va, Vb, Vc, Vd, Ve, and Vf for charge setting are input to the capacitors Cs1, Cs2, Cf1, Cs3, Cs4, and Cf2, respectively. At least one of the voltages Va, Vb, Vc, Vd, Ve, and Vf is the input voltage Vin, and the others are constant voltages.

  FIG. 1B shows a connection form during the hold operation. In this case, at least the pair of capacitors, here the other ends of the capacitors Cf1 and Cf2, are connected to the non-inverting output terminal and the inverting output terminal of the operational amplifier OP, respectively. However, not all capacitors Cs1, Cs2, Cf1, Cs3, Cs4, and Cf2 can be feedback capacitors. In order to derive the general formula, the voltages Vop and Vom output from the non-inverting output terminal and the inverting output terminal of the operational amplifier OP are Vop1 and Vom1, respectively, and the capacitors Cs1, Cs2, Cs3, and Cs4 have voltages Vg, Vh, and Vi, respectively. , Vj are input. At least one of the voltages Vg, Vh, Vi, and Vj is the input voltage Vin + ΔV, and the others are constant voltages.

The requirements for obtaining the sample and hold circuit 1 of the present embodiment having the above-described characteristics are the following four. However, the second requirement corresponding to the subsequent stage of the characteristic (1C) and the first requirement corresponding to the characteristic (1D) may be satisfied as necessary.
[First requirement]
The term of the input voltage Vin does not exist in the expression of the input voltage Vx1 of the operational amplifier OP during the hold operation (ΔV may remain).
[Second requirement]
The term ΔV does not exist in the differential output voltage Vop1−Vom1 expression during the hold operation.
[Third requirement]
The Vin term remains in the differential output voltage Vop1-Vom1 equation during the hold operation.
[Fourth requirement]
The coefficient of the term of the input voltage Vin is 2 / N in the differential output voltage Vop1-Vom1 expression during the hold operation.

  As shown in Patent Document 1, the differential output voltage Vop1−Vom1 at the time of the hold operation is expressed by equation (5), and the input voltage Vx1 of the operational amplifier OP is expressed by equation (6). Here, Vcm0 is the common voltage of the output voltages Vop and Vom during the sampling operation, and Vcm1 is the common voltage of the output voltages Vop1 and Vom1 during the hold operation.

Total capacitance value of inversion side capacitor to which input voltage Vin is applied during sampling operation = αC
Total capacitance value of non-inversion side capacitor to which input voltage Vin is applied during sampling operation = βC
Total capacitance value of the inverting-side capacitor that applies the input voltage Vin + ΔV during the hold operation = γC
Total capacitance value of the non-inversion side capacitor to which the input voltage Vin + ΔV is applied during the hold operation = ηC
Then, in order to satisfy the first to third requirements, the following first to third conditions are required, respectively.

[First condition]
α + β = γ + η (7)
[Second condition]
γ = η (8)
[Third condition]
α ≠ β (9)

Next, a fourth condition for satisfying the fourth requirement is derived. In equation (5), the voltages Va, Vb, Vc input to the inverting side during the sampling operation and the voltages Vi, Vj input to the non-inverting side during the holding operation are added, and input to the non-inverting side during the sampling operation. The subtracted voltages Vd, Ve, Vf and the voltages Vg, Vh input to the inversion side during the hold operation are subtracted. From this, the coefficient of Vin in the differential output voltage Vop1−Vom1 shown in the equation (5) is expressed by the equation (10) using the α, β, γ, and η.
Vin coefficient = (α−β−γ + η) / z (10)

On the other hand, the coefficient of Vin is 2 / N in the differential output voltage Vop1−Vom1 expressed by the equations (1) to (4). Accordingly, the fourth condition for satisfying the fourth requirement is the following expression (11).
[Fourth condition]
(Α−β−γ + η) / z = 2 / N
z = (α−β−γ + η) × (N / 2) (11)

  If there are two or more pairs of feedback capacitors, the capacitance values of each pair are z1C, z2C,... (Where z1, z2,... Are positive values, and C is a unit capacitance value). Z on the left side is z1 + z2 +... That is the addition of each pair. Further, the first condition to the fourth condition are theoretical conditional expressions derived analytically, and deviations due to manufacturing variations inevitably occurring in actual products are not excluded from the conditions. The error due to the manufacturing variation will be examined in the sixth embodiment.

  4, 5, and 6 are results of verifying whether or not the first condition to the fourth condition are satisfied for case 1 to case 9 shown in Patent Document 1. FIG. FIG. 4 shows, in the sample hold circuit 1 shown in FIG. 1, black dot marks that indicate the places where the input voltage Vin is applied during the sampling operation and the hold operation. FIG. 5 shows α, β, γ, η, α + β, and γ + η for each case. FIG. 6 shows, for each case, whether or not the first condition to the third condition are satisfied, α−β−γ + η for the fourth condition, the coefficient of Vin shown in the equation (10), and the input voltage Vin. The capacity ratio x: y: z necessary for dividing the voltage to / N is shown. Here, “OK” means that the condition is satisfied, and “NG” means that the condition is not satisfied.

(Case 1)
The voltage Vc is the input voltage Vin, the voltages Vg and Vi are the input voltage Vin + ΔV, z = 2x
(Case 2)
The voltage Vc is the input voltage Vin, the voltages Vg, Vi, Vh, and Vj are the input voltage Vin + ΔV, z = 2x + 2y
(Case 3)
Voltage Va is input voltage Vin, voltages Vh, Vj are input voltage Vin + ΔV, x = 2y
(Case 4)
The voltages Va and Vb are the input voltage Vin, the voltages Vg and Vj are the input voltage Vin + ΔV, and x = y
(Case 5)
The voltages Va and Vd are the input voltage Vin, and the voltages Vg and Vi are the input voltage Vin + ΔV.
(Case 6)
The voltages Va and Vc are the input voltage Vin, the voltages Vh and Vj are the input voltage Vin + ΔV, and x + z = 2y.
(Case 7)
The voltages Vc and Vd are the input voltage Vin, the voltages Vh and Vj are the input voltage Vin + ΔV, and x + z = 2y.
(Case 8)
The voltages Va, Vc, Vd are the input voltage Vin, and the voltages Vh, Vj are the input voltages Vin + ΔV, 2x + z = 2y.
(Case 9)
The voltages Va, Vc, and Vd are the input voltage Vin, and the voltages Vg, Vi, Vh, and Vj are the input voltage Vin + ΔV, z = 2y.

  Case 5 in which the coefficient of Vin in the differential output voltage Vop1−Vom1 = (α−β−γ + η) / z is 0 does not satisfy the fourth condition. In cases 1, 2, 8, and 9 in which (α−β−γ + η) / z is 1, the input voltage Vin can be divided and input (1/2), but otherwise Cannot be obtained. Arbitrary voltage division ratios can be obtained in cases 3, 4, 6, and 7. The capacity ratio necessary for this is as follows.

(Case 3) x: y: z = 2: 1: N
(Case 4) x: y: z = 1: 1: N
(Case 6) x: y: z = 2−N: 1: N
(Case 7) x: y: z = N-2: N-1: N

  As described above, the sample-and-hold circuit 1 according to the present embodiment has the inverting side capacitors Cs1, Cs2, and Cf1 and the non-inverting side capacitors Cs3, Cs4, and Cf2 paired with the inverting input terminal and the non-inverting input terminal of the operational amplifier OP. Is connected. In the sampling operation, the operational amplifier OP operates as a voltage follower to set the charge, and the input voltage Vin is applied to at least one capacitor. Further, at the time of the hold operation, at least a pair of inverting and non-inverting capacitors are connected as feedback capacitors between the input and output of the operational amplifier OP, and the input voltage Vin + ΔV is applied to at least one capacitor.

  By satisfying the fourth condition in this configuration, the sample-and-hold circuit 1 can perform the sample-and-hold operation by dividing the input voltage Vin by 1 / N, so that the input voltage range (input dynamic range) can be expanded. it can. For example, when used in an in-vehicle device or a motor control device, a battery voltage or a motor voltage exceeding the power supply voltage can be directly input. Since there is no need to provide a separate voltage dividing circuit for dividing the input voltage Vin, the layout area in the case of being configured as an IC can be reduced, or external parts are not required. Further, since the capacitance ratio of the capacitor is generally more accurate than the resistance ratio, the sample and hold circuit 1 can perform voltage division with high accuracy.

  Further, by satisfying the first condition, the input voltage Vx1 of the operational amplifier OP can be maintained at a predetermined common-mode input voltage (bias voltage), and the operational amplifier OP can be operated at a desirable gain and slew rate. Further, by satisfying the second condition and the third condition, the sampled single-ended voltage Vin is changed to the differential output voltage Vop1−Vom1 even if the input voltage changes during the hold operation (that is, ΔV is not 0). Can be converted and kept accurate. The first condition and the second condition may be satisfied as necessary. This is because the sample-and-hold operation can be performed by dividing the input voltage Vin by 1 / N if at least the third condition and the fourth condition are satisfied.

(Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to FIGS. The sample and hold circuit of the present embodiment has a circuit configuration similar to that of the sample and hold circuit 1 of the first embodiment. However, the method of applying the input voltages Vin and Vin + ΔV and the setting of the capacitance value of the capacitor are different.

The characteristics desired to be realized by the sample and hold circuit 1 of the present embodiment are as follows. A characteristic that replaces the characteristic (1C) included in the sample and hold circuit 1 of the first embodiment is (2C).
(2A) Single-ended input and differential output.
(2B) The input voltage Vin is applied to at least one capacitor during the sampling operation, and the input voltage Vin + ΔV is applied to at least one capacitor during the hold operation.
(2C) The sampled input voltage Vin multiplied by 1 / N is doubled and held. However, the hold voltage (differential output voltage Vop1-Vom1) depends on the change ΔV of the input voltage Vin during the hold operation.
(2D) The input voltage Vx1 of the operational amplifier OP during the hold operation does not depend on the input voltage Vin during the sampling operation.

  The characteristic (2C) is not a complete hold operation in that the influence of the change ΔV of the input voltage Vin appears on the differential output voltage Vop1−Vom1 during the hold operation. However, when the band of the input voltage Vin is limited, the coefficient of the term of ΔV remaining in the differential output voltage Vop1−Vom1 can be set as small as possible so that it can be sufficiently used as a sample hold circuit.

There are three requirements for obtaining the sample and hold circuit 1 of the present embodiment: the first requirement, the fourth requirement, and the new fifth requirement described in the first embodiment.
[First requirement]
The term of the input voltage Vin does not exist in the expression of the input voltage Vx1 of the operational amplifier OP during the hold operation (ΔV may remain).
[Fourth requirement]
The coefficient of the term of the input voltage Vin is 2 / N in the differential output voltage Vop1-Vom1 expression during the hold operation.
[Fifth requirement]
The terms Vin and ΔV remain in the differential output voltage Vop1−Vom1 equation during the hold operation.

In order to satisfy the first requirement and the fourth requirement, the first condition and the fourth condition may be satisfied as described above. On the other hand, in order to satisfy the fifth requirement, the following fifth condition is required.
[Fifth condition]
α + η ≠ β + γ (12)

By the way, when the addition and subtraction of the equations (12) and (7) are performed, the following equations (13) and (14) are obtained, respectively.
[Condition 5A, Condition 5B]
α ≠ γ (13)
β ≠ η (14)
Therefore, the fifth condition can be expressed by the expression (13) as the fifth A condition and the expression (14) as the fifth B condition instead of the above expression (12). Note that these conditions are derived analytically, and deviations due to manufacturing variations are not excluded from the conditions.

  7, 8, and 9 are results of verifying whether or not the first condition, the fourth condition, and the fifth condition are satisfied for case 10 to case 17 shown in Patent Document 1. FIG. FIG. 7 corresponds to FIG. FIG. 8 shows α, β, γ, η, α + η, and β + γ for each case. FIG. 9 shows whether or not the first condition and the fifth condition are satisfied for each case, and α−β−γ + η for the fourth condition, the coefficient of Vin shown in the equation (10), and the input voltage Vin. The capacity ratio x: y: z necessary for dividing the voltage to / N is shown.

(Case 10)
The voltage Vc is the input voltage Vin, the voltages Vi and Vj are the input voltage Vin + ΔV, z = x + y
(Case 11)
The voltage Vc is the input voltage Vin, the voltage Vi is the input voltage Vin + ΔV, and z = x
(Case 12)
The voltage Va is the input voltage Vin, and the voltage Vi is the input voltage Vin + ΔV.
(Case 13)
The voltages Va and Vb are the input voltage Vin, and the voltages Vi and Vj are the input voltage Vin + ΔV.
(Case 14)
The voltages Va and Vb are the input voltage Vin, and the voltages Vi and Vh are the input voltage Vin + ΔV.
(Case 15)
The voltages Va and Vd are the input voltage Vin, the voltage Vj is the input voltage Vin + ΔV, and 2x = y
(Case 16)
The voltages Va and Vc are the input voltage Vin, the voltage Vj is the input voltage Vin + ΔV, and x + z = y.
(Case 17)
The voltages Vc and Vd are the input voltage Vin, the voltage Vj is the input voltage Vin + ΔV, and x + z = y.

  In the cases 10, 11, and 17 where the coefficient of Vin in the differential output voltage Vop1−Vom1 = (α−β−γ + η) / z is 2, the input voltage Vin is inputted as it is (N = 1), so that the voltage is divided. I can't. Arbitrary voltage division ratios can be obtained in cases 12 to 16, and the capacity ratio necessary for this is as follows.

(Case 12) x: y: z = 1: 1: N
(Case 13) x: y: z = 1: 1: 2N
(Case 14) x: y: z = 1: 1: N
(Case 15) x: y: z = 1: 2: N
(Case 16) x: y: z = 1-N: 1: N

  As described above, the sample and hold circuit 1 of the present embodiment can perform the sample and hold operation by dividing the input voltage Vin by 1 / N, as in the first embodiment. Further, by satisfying the first condition, the operational amplifier OP can be operated at a desirable gain and slew rate as in the first embodiment. Furthermore, by satisfying the fifth condition, the sampled voltage can be held almost accurately under the condition that the band of the input voltage Vin is limited and the influence of ΔV on the differential output voltage Vop1−Vom1 is set to be small. Can do.

(Third embodiment)
Next, a third embodiment in which a differential input sample hold circuit is applied to a multiplying D / A converter (MDAC) will be described with reference to FIGS.

  The configuration of the sample and hold circuit 10 is the same as that in FIG. 1, and a differential input voltage is applied. In the following description, the common-mode voltage is Vref, the non-inverting input voltage during sampling is Vinp, the inverting input voltage is Vinm, the non-inverting input voltage during the hold operation is Vinp ', the inverting input voltage is Vinm', and the differential component The voltage is Vin + ΔV, and the in-phase voltage is Vref + ΔVref.

  FIG. 10 shows a basic circuit used for an A / D conversion stage of a pipelined A / D converter, a cyclic A / D converter, and the like. The unit conversion circuit 7 includes a sample hold circuit 10 (MDAC), a sub A / D converter 8 (sub ADC), and a multiplexer 9 (MPX). Of these, the sub A / D converter 8 performs a so-called 1.5-bit A / D conversion on the differential input voltages Vinp and Vinm, and outputs a ternary (+1, 0, -1) A / D conversion value. To do. The entire multiplexer 9 and sample hold circuit 10 may be referred to as a multiplying D / A converter.

  The multiplexer 9 outputs one or a plurality of analog voltages to the sample and hold circuit 10 according to the A / D conversion value by the sub A / D converter 8. The sample and hold circuit 10 receives the differential input voltages Vinp and Vinm and the analog voltage from the multiplexer 9, and the voltages Va, Vb, Vc, Vd, Ve, Vf, Any of Vg, Vh, Vi, and Vj.

  The sample hold circuit 10 ideally amplifies the differential input voltage Vinp−Vinm to 2 / N times (N> 0) (first term) as shown in the equation (15), and the A / D conversion value Is subtracted (second term) to obtain and hold the differential output voltage Vop1-Vom1. Specifically, equations (16), (17), and (18) are obtained according to the A / D conversion values +1, 0, and −1, respectively. These equations output the residual voltage by doubling the difference voltage between the value obtained by multiplying the differential input voltage Vinp−Vinm by 1 / N and the value corresponding to the A / D conversion value (D / A conversion value). Is equivalent to

The characteristics desired to be realized by the sample and hold circuit 10 of the present embodiment are as follows. However, the latter stage (second sentence) and the characteristic (3D) of the characteristic (3C) may be realized as necessary.
(3A) Differential input and differential output.
(3B) The inverting input voltage Vinm and the non-inverting input voltage Vinp are respectively applied to at least one capacitor during the sampling operation, and the inverting input voltage Vinm ′ and the non-inverting input voltage Vinp ′ are respectively applied to at least one capacitor during the holding operation. ing.
(3C) The differential input voltage Vinp−Vinm sampled by 1 / N times is amplified twice and held. The hold voltage (differential output voltage Vop1−Vom1) does not depend on the inverting input voltage Vinm ′ and the non-inverting input voltage Vinp ′ (the differential voltage Vin + ΔV and the common-mode voltage Vref + ΔVref) during the holding operation.
(3D) The input voltage Vx1 of the operational amplifier OP during the hold operation does not depend on the inverting input voltage Vinm and the non-inverting input voltage Vinp (the differential voltage Vin and the common-mode voltage Vref) during the sampling operation.

  Even in the case of a differential input, if the inverting input voltage Vinm and the non-inverting input voltage Vinp are considered separately, the same requirements (conditions) as those in the first embodiment relating to the single-ended input are necessary. That is, when based on the first embodiment, the first condition to the third condition are necessary for each of the inverting input voltage Vinm and the non-inverting input voltage Vinp, and when based on the second embodiment, the inverting input The first condition and the fifth condition (fifth A and fifth B conditions) are required for each of the voltage Vinm and the non-inverting input voltage Vinp. However, when based on 1st Embodiment, what is necessary is just to satisfy | fill 1st condition and 2nd condition as needed.

Further, in the case of differential input, it is necessary that the term of the differential input voltage Vinp-Vinm remains in the differential output voltage Vop1-Vom1 expression during the hold operation. For this purpose, in the equation (5), it is necessary that the coefficient of the inverting input voltage Vinm and the coefficient of the non-inverting input voltage Vinp are equal and the signs are reversed. In order to satisfy this requirement, the following sixth condition is necessary.
[Sixth condition]
αp−βp = βm−αm (19)

Here, it is defined as follows.
Total capacitance value of the inverting capacitor that applies the non-inverting input voltage Vinp during the sampling operation = αpC
Total capacitance value of the non-inverting side capacitor to which the non-inverting input voltage Vinp is applied during the sampling operation = βpC
Total capacitance value of the inverting-side capacitor to which the non-inverting input voltage Vinp ′ is applied during the holding operation = γpC
Total capacitance value of the non-inversion side capacitor to which the non-inversion input voltage Vinp ′ is applied during the hold operation = ηpC
Total capacitance value of inverting-side capacitor that applies inverting input voltage Vinm during sampling operation = αmC
Total capacitance value of non-inversion side capacitor to which inverting input voltage Vinm is applied during sampling operation = βmC
The total capacitance value of the inverting side capacitor that applies the inverting input voltage Vinm ′ during the hold operation = γmC
Total capacitance value of the non-inversion side capacitor to which the inverting input voltage Vinm ′ is applied during the holding operation = ηmC

Further, the fourth requirement in the present embodiment is that the coefficient of the term of the differential input voltage Vinp−Vinm is 2 / N in the differential output voltage Vop1−Vom1 expression during the hold operation. In the differential output voltage Vop1−Vom1 shown in the equation (5), the coefficients of Vinp and Vinm are expressed by the equations (20) and (21) using α, β, γ, and η, respectively.
The coefficient of Vinp = (αp−βp−γp + ηp) / z (20)
Vinm coefficient = (αm−βm−γm + ηm) / z (21)

If the sixth condition is satisfied, the term of the differential input voltage Vinp−Vinm in the differential output voltage Vop1−Vom1 becomes as shown in equation (22).
Vinp−Vinm term = (αp−βp−γp + ηp) / z
=-(Αm-βm-γm + ηm) / z (22)

On the other hand, in the differential output voltage Vop1−Vom1 shown in the equations (15) to (18), the coefficient of the differential input voltage Vinp−Vinm is 2 / N. Accordingly, the seventh condition for satisfying the fourth requirement is the following equation (23). Note that these conditions are derived analytically, and deviations due to manufacturing variations are not excluded from the conditions.
[Seventh condition]

  FIG. 11 to FIG. 14 show the results of verifying whether the first condition to the third condition and the fifth condition to the seventh condition are satisfied for the case 18 to the case 20 shown in Patent Document 1. FIG. 11 shows the application location of the non-inverted input voltage Vinp in the sampling hold circuit 10 during the sampling operation and the hold operation with black circles, and the application location of the inverted input voltage Vinm with white circles. FIG. 12 shows the result of verifying the first condition to the third condition, the fifth condition, and the sixth condition for the non-inverting input voltage Vinp. FIG. 13 shows the results of verifying the first condition to the third condition and the fifth condition for the inverting input voltage Vinm.

  FIG. 14 shows the result of verifying the seventh condition. In FIG. 14, for the non-inverted input voltage Vinp, αp−βp−γp + ηp, the Vinp coefficient shown in the equation (20), the Vinp−Vinm coefficient, and the capacity required to divide Vinp−Vinm into 1 / N. The ratio x: y: z is shown. For the inverting input voltage Vinm, αm−βm−γm + ηm, the coefficient of Vinm shown in the equation (21) is shown.

(Case 18)
The voltage Vf is the inverting input voltage Vinm, the voltage Vc is the non-inverting input voltage Vinp, the voltage Vg is the inverting input voltage Vinm ′, the voltage Vi is the non-inverting input voltage Vinp ′, and x = z.
(Case 19)
The voltage Vf is the inverting input voltage Vinm, the voltage Vc is the non-inverting input voltage Vinp, the voltages Vg and Vi are the inverting input voltage Vinm ', and the voltages Vh and Vj are the non-inverting input voltage Vinp', 2x = 2y = z.
(Case 20)
The voltage Vd is the inverting input voltage Vinm, the voltage Va is the non-inverting input voltage Vinp, the voltage Vh is the inverting input voltage Vinm ′, the voltage Vj is the non-inverting input voltage Vinp ′, and x = y.

  In case 18, since the coefficient of the differential input voltage Vinp−Vinm is 2 under the condition of x = z for satisfying the first condition, N = 1 and cannot be divided. In case 19, since the coefficient of the differential input voltage Vinp−Vinm is 1 under the condition of 2y = z for satisfying the first condition, N = 2 and the voltage can be divided and input by 1/2. Any other partial pressure ratio cannot be obtained. In the case 20, since the coefficient of the differential input voltage Vinp−Vinm is 2x / z under the condition of x = y that satisfies the first condition, the differential input voltage Vinp−Vinm is divided by 1 / N. The required capacity ratio is x: y: z = 1: 1: N.

  As described above, according to the present embodiment, the first condition to the third condition are satisfied for each of the inverting input voltage Vinm and the non-inverting input voltage Vinp, and the sixth condition and the seventh condition are further satisfied. Thus, a sample and hold circuit that divides and inputs the differential input voltage Vinp−Vinm to 1 / N is obtained. However, the first condition and the second condition may be satisfied as necessary. Even when the fifth (5A, 5B) condition is satisfied instead of the second and third conditions, the band of the differential input voltage Vinp−Vinm is limited and the influence of ΔV on the differential output voltage Vop1−Vom1 is small. Under the set conditions, the sampled voltage can be held almost accurately. As a result, operations and effects similar to those of the first and second embodiments can be obtained.

(Fourth embodiment)
Next, the single-end input case 4 described above will be specifically described with reference to FIG.
FIG. 15A shows a connection form during the sampling operation, and FIG. 15B shows a connection form during the hold operation. The capacitance values of the capacitors Cs1, Cs2, Cs3, and Cs4 are C. The capacitor Cf1 is configured by paralleling capacitors Cf1a and Cf1b having a capacitance value of 2C, and the capacitor Cf1b can be electrically disconnected by the switches S1a and S1b. Similarly to the capacitor Cf1, the capacitor Cf2 is also connected in parallel with the capacitors Cf2a and Cf2b via the switches S2a and S2b. The control circuit 2 switches the switches S1a, S1b, S2a, S2b and the voltage applied to each input terminal.

  When Va = Vb = Vg = Vj = Vin and x: y: z = 1: 1: N, the differential output voltage Vop1−Vom1 during the hold operation is expressed by equation (24), and the input voltage Vx1 of the operational amplifier OP is ( 25). When N = 4 when the switches S1a, S1b, S2a, and S2b are turned on, the expressions (24) and (25) become the expressions (26) and (27), respectively.

  When this sample-and-hold circuit 1 is applied to the unit conversion circuit 3 shown in FIG. 2, in order to adapt the expression (26) to the expressions (2) to (4) at N = 4, the voltages Vc to Vf, Vh, Set Vi as follows. Here, Vrefp = 5V (power supply voltage), Vref = 2.5V (median value of power supply voltage), and Vrefm = 0V. Further, Vcm0 = Vcm1 = Vref = 2.5V.

<When A / D conversion value is +1>
In order to establish the formula (2), the following is set.
Vd = Ve = Vrefp, Vc = Vf = Vh = Vi = Vrefm
At this time, the input voltage Vx1 of the operational amplifier OP is expressed by equation (28).

<When A / D conversion value is 0>
In order to satisfy the equation (3), the following is set.
Vf = Vrefp, Vc = Vd = Ve = Vh = Vi = Vrefm
At this time, the input voltage Vx1 of the operational amplifier OP is expressed by equation (29).

<When A / D conversion value is -1>
In order to establish the equation (4), the following is set.
Vd = Ve = Vf = Vrefp, Vc = Vh = Vi = Vrefm
At this time, the input voltage Vx1 of the operational amplifier OP is expressed by equation (30).

  This embodiment is a case 4 of single-ended input set to x: y: z = 1: 1: 4, and all the first to fourth conditions are satisfied as shown in FIG. Therefore, the sample hold operation (MDAC operation) can be performed by dividing the input voltage Vin by ¼. Further, since the capacitance values of the capacitors Cf1 and Cf2 can be changed, for example, when used in an A / D conversion stage of a pipeline type A / D converter, the switch S1a to S1a is applied when applied to the first stage. When S2b is turned on, the divided voltage input is used, and when applied to the second stage and thereafter, the switches S1a to S2b are turned off to make the same magnification input.

(Fifth embodiment)
Next, the differential input case 20 will be described in detail with reference to FIG.
FIG. 16A shows a connection form during the sampling operation, and FIG. 16B shows a connection form during the hold operation. The circuit configuration relating to the capacitors Cs1, Cs2, Cf1, Cs3, Cs4, Cf2 and the operational amplifier OP of the sample hold circuit 10 is the same as that of the sample hold circuit 1 shown in FIG.

  When Va = Vinp, Vd = Vinm, Vj = Vinp + ΔVinp, Vh = Vinm + ΔVinm, x: y: z = 1: 1: N, the differential output voltage Vop1−Vom1 during the hold operation becomes the equation (31) and the operational amplifier OP The input voltage Vx1 is given by equation (32). When N = 4 when the switches S1a, S1b, S2a, and S2b are turned on, the expressions (31) and (32) become the expressions (33) and (34), respectively.

  When this sample and hold circuit 10 is applied to the unit conversion circuit 7 shown in FIG. 10, in order to adapt the equation (33) to the equations (16) to (18) at N = 4, the voltages Vb, Vc, Ve˜ Vg and Vi are set as follows. Here, Vrefp = 5V (power supply voltage), Vref = 2.5V (median value of power supply voltage), and Vrefm = 0V. Further, Vcm0 = Vcm1 = Vref = 2.5V.

<When A / D conversion value is +1>
In order to hold the equation (16), set as follows.
Vg = Ve = Vrefp, Vb = Vc = Vf = Vi = Vrefm
At this time, the input voltage Vx1 of the operational amplifier OP is expressed by equation (35).

<When A / D conversion value is 0>
In order to establish equation (17), the following is set.
Vb = Vc = Ve = Vf = Vg = Vi = Vrefm
At this time, the input voltage Vx1 of the operational amplifier OP is expressed by equation (36).

<When A / D conversion value is -1>
In order to establish equation (18), the following is set.
Vb = Vi = Vrefp, Vc = Ve = Vf = Vg = Vrefm
At this time, the input voltage Vx1 of the operational amplifier OP is expressed by equation (37).

  This embodiment is a differential input case 20 in which x: y: z = 1: 1: 4 is set. As shown in FIGS. 12 to 14, the first condition, the fifth condition, the sixth condition, Seven conditions are met. Therefore, the sample and hold operation (MDAC operation) can be performed by dividing the differential input voltage Vinp−Vinm by ¼. In addition, since the capacitance values of the capacitors Cf1 and Cf2 can be changed, the same operation and effect as those of the fourth embodiment can be obtained.

(Sixth embodiment)
Next, considering the configuration shown in the first embodiment, the effect of mismatch of conditions in the case where there is variation in the capacitance of the capacitor due to manufacturing variation will be examined. In the first embodiment, since the sample hold circuit 1 realizes the characteristics (1A) to (1D), the first condition to the fourth condition are required.

(A) First Condition When Expression (6) indicating the input voltage Vx1 of the operational amplifier OP is expressed using the above α, β, γ, and η, Expression (38) is obtained.

  In order to eliminate the term Vin from the equation (38), the first condition shown by the equation (7) described above is required. If the condition of equation (7) is not satisfied, the input voltage Vx1 of the operational amplifier OP during the hold operation varies under the influence of the input voltage Vin. When the allowable variation range of Vx1 due to the input voltage Vin is ± Vk [V], the allowable range of variation in the capacitance ratio is expressed by equations (39) and (40).

(B) Second condition and third condition The input voltage during the sampling operation is Vin, the input voltage during the hold operation is Vin + ΔV, and the differential output voltage Vop1-Vom1 during the hold operation is expressed by the above equation (5) as α , Β, γ, and η, the equation (41) is obtained.

  In order to eliminate the ΔV term from the equation (41), the second condition shown in the above equation (8) is necessary, and in order to leave the Vin term, the third condition shown in the above equation (9). Is required. If the condition of the equation (8) is not satisfied, the differential output voltage Vop1−Vom1 at the time of the hold operation varies under the influence of the variation ΔV of the input voltage Vin after the shift to the hold operation. Assuming that the allowable variation range of the differential output voltage Vop1−Vom1 is ± Vk [V], the allowable range of variation in the capacitance ratio is expressed by equations (42) and (43).

  Further, when the second condition expressed by the equation (8) is substantially satisfied, the differential output voltage Vop1−Vom1 held and output becomes very small if α and β are slightly different, and the hold circuit Cannot function as.

(C) Regarding the fourth condition In order to increase the term of the input voltage Vin in the equation (41) by 2 / N times (divided by 1 / N and doubled), the above-mentioned fourth condition expressed by the equation (11) is Necessary. When the target value (design center value) of the voltage division ratio is 2 / N and the allowable error of the voltage division ratio is ± k [%], the allowable range of variation in the capacitance ratio is expressed by equation (44).

  Based on the above consideration, the first condition, the second condition, and the fourth condition are substantially within the allowable ranges shown in the expressions (40), (43), and (44), taking into account the above-described allowable errors. It only has to satisfy. In other words, the equality relationships shown in the equations (7), (8), and (11) may be substantially equal within a range that does not completely coincide with each other but is within an allowable error. The third condition is that the Vin term should remain substantially in the differential output voltage Vop1−Vom1 equation during the hold operation. The inequality relationship shown in equation (9) is practically large. It is necessary to be substantially different so that the hold voltage is output.

  Next, the occurrence of an error due to a deviation in conditions will be described with reference to FIG. 17 taking the case 4 described in the first and fourth embodiments as an example. FIG. 17A shows a connection form during the sampling operation, and FIG. 17B shows a connection form during the hold operation.

  Substituting Va = Vb = Vg = Vj = Vin, Vf = Vrefp, Vc = Vd = Ve = Vh = Vi = Vrefm, x = 1, y = 1, z = 4 into the equation (5), N = 4 Thus, Expression (45) corresponding to Expression (3) when the A / D conversion value is 0 is obtained. Here, when x, which is the capacity ratio, is shifted by +1 [%] due to manufacturing variations and becomes x = 1.01, y = 1, z = 4, the equation (46) is obtained, and the ideal voltage dividing ratio 1 / +0.5 [%] with respect to 4.

(Seventh embodiment)
Next, a seventh embodiment of the present invention will be described with reference to FIG.
FIG. 18 shows a configuration of a pipeline type A / D converter using the unit conversion circuits 3 and 7 described above. The A / D converter 11 is configured by connecting N (N ≧ 2) unit conversion circuits in series. The first stage (first stage) is constituted by the unit conversion circuit 3 shown in FIG. 2, and the second to Nth stages (second stage to Nth stage) are constituted by the unit conversion circuit 7 shown in FIG. . The unit conversion circuit 3 outputs the differential output voltage Vop1−Vom1 which is a residual voltage after the input voltage Vin (A / D conversion target voltage Vs) is multiplied by 1 / N (N> 0). The unit conversion circuit 7 outputs a differential output voltage Vop1-Vom1 that is a residual voltage from the input voltage Vin (differential output voltage Vop1-Vom1 of the previous stage).

  According to the A / D converter 11 of the present embodiment, the input dynamic range capable of A / D conversion can be expanded without adding a preprocessing circuit (voltage dividing circuit, bias control circuit), and a conventional A / D converter Thus, A / D conversion target voltage Vs exceeding a reference voltage range (for example, 0 V to 5 V) that could not be converted can be A / D converted.

(Eighth embodiment)
Next, an eighth embodiment of the present invention will be described with reference to FIG.
FIG. 19 shows a configuration of a cyclic A / D converter using the unit conversion circuit 7 described above. The A / D converter 12 selects one unit conversion circuit 7 and selects either the A / D conversion target voltage Vs or the differential output voltage Vop−Vom of the unit conversion circuit 7 in the unit conversion circuit 7. And a switch 13 for switching for input.

  The A / D converter 12 first switches the switch 13 to the A / D conversion target voltage Vs side, inputs the A / D conversion target voltage Vs from the outside, and outputs a residual voltage. In this first round, the unit conversion circuit 7 increases the differential input voltage Vinp−Vinm (A / D conversion target voltage Vs) by 1 / N times (N> 0) and then the differential output voltage Vop1 which is a residual voltage. -Vom1 is output.

  Subsequently, the A / D converter 12 switches the switch 13 to the output voltage side and inputs the differential output voltage Vop1−Vom1 (the first remaining voltage) of the unit conversion circuit 7 without multiplying by 1 / N. The remaining voltage of the second round is output. The operation after the third round is the same as the second round described above. Thus, the digital output code is generated by adding the code obtained by circulating the residual voltage to the unit conversion circuit 7 while shifting the code by a predetermined bit from the MSB.

  According to the A / D converter 12 of this embodiment, the input dynamic range capable of A / D conversion can be expanded without adding a preprocessing circuit (voltage dividing circuit, bias control circuit), and a conventional A / D converter can be expanded. Thus, A / D conversion target voltage Vs exceeding a reference voltage range (for example, 0 V to 5 V) that could not be converted can be A / D converted. Further, the circuit type and the layout area in the IC can be reduced by employing the cyclic type as compared with the pipeline type A / D converter.

(Other embodiments)
The present invention is not limited to the embodiments described above and shown in the drawings, and can be modified or expanded as follows, for example.
Although the fourth condition and the seventh condition for dividing the input voltage Vin and the differential input voltage Vinp−Vinm to 1 / N have been described, a voltage dividing action is obtained when N> 1, and amplification is performed when N <1. The effect is obtained. For example, when the voltage input from the outside is very small, it can be amplified with high accuracy by setting N <1.

As shown in each embodiment and each case, as long as the necessary conditions among the first condition to the seventh condition are satisfied, the number and position of the input voltage Vin, the number of all capacitors, the number of feedback capacitors, The capacitance value and the like can be set as appropriate. Further, during the hold operation, the pair of inversion-side capacitors and non-inversion-side capacitors (feedback capacitors) connected to the non-inversion output terminal and the inversion output terminal of the operational amplifier OP have constant capacitance values (that is, FIG. 15). Unlike FIG. 16, the capacitors Cf1 and Cf2 may each be composed of only one capacitor). The feedback capacitor during the hold operation is not limited to a pair.
The sample hold circuit described above is not limited to application to an A / D converter.

FIG. 2 is a configuration diagram of (a) sampling operation and (b) hold operation of the sample and hold circuit according to the first embodiment of the present invention. The figure which shows the basic circuit used with the A / D converter Basic circuit input / output characteristics The figure which shows the application location of input voltage about cases 1-9 Diagram showing α, β, γ, η, α + β, γ + η for cases 1-9 The figure which shows the verification result of 1st thru | or 4th condition about cases 1-9 FIG. 4 equivalent view of the cases 10 to 17 according to the second embodiment of the present invention. Diagram showing α, β, γ, η, α + η, β + γ for cases 10 to 17 The figure which shows the verification result of 1st condition, 4th condition, and 5th condition about cases 10-17 FIG. 2 equivalent view showing the third embodiment of the present invention FIG. 4 equivalent view of the cases 18 to 20 The figure which shows the verification result of 1st condition-3rd condition, 5th condition, and 6th condition about Vinp of cases 18-20 The figure which shows the verification result of 1st condition-3rd condition, and 5th condition about Vinm of cases 18-20 The figure which shows the verification result of 7th conditions about cases 18-20 FIG. 1 equivalent view showing a fourth embodiment of the present invention FIG. 1 equivalent view showing a fifth embodiment of the present invention FIG. 1 equivalent view showing a sixth embodiment of the present invention The block diagram of the pipeline type A / D converter which shows the 7th Embodiment of this invention The block diagram of the cyclic | annular A / D converter which shows the 8th Embodiment of this invention

Explanation of symbols

  In the drawing, 1 and 10 are sample hold circuits (multiple D / A converters), 2 is a control circuit, 3 and 7 are unit conversion circuits, 11 and 12 are A / D converters, and OP is an operational amplifier.

Claims (16)

An operational amplifier that differentially outputs the held voltage;
A plurality of inverting capacitors connected to the inverting input terminal of the operational amplifier;
A plurality of non-inverting capacitors connected to the non-inverting input terminal of the operational amplifier and having the same capacitance value as each of the inverting capacitors that form a pair;
At the time of an input voltage sampling operation, an input voltage is applied to at least one of the inverting side capacitor and the non-inverting side capacitor, a predetermined charge is set in the remaining capacitor, and at least a pair of inverting sides is set during a holding operation. Control for connecting the capacitor and the non-inverting capacitor to the non-inverting output terminal and the inverting output terminal of the operational amplifier, respectively, and controlling the input voltage to be applied to at least one of the remaining inverting and non-inverting capacitors. With circuit,
The total capacitance value of the inverting capacitor to which the input voltage is applied during the sampling operation is set to be substantially different from the total capacitance value of the non-inverting capacitor (third condition),
When N is a positive value, the capacitance values of the at least one pair of inverting and non-inverting capacitors respectively connected to the non-inverting output terminal and the inverting output terminal of the operational amplifier during the hold operation are (at the time of the sampling operation) Total capacitance value of inversion side capacitor to which input voltage is applied-Total capacitance value of non-inversion side capacitor to which input voltage is applied during sampling operation-Total capacitance value of inversion side capacitor to which input voltage is applied during hold operation + Hold A sample-and-hold circuit characterized by being set to be substantially equal to (the total capacitance value of the non-inversion side capacitor to which an input voltage is applied during operation) × (N / 2) (fourth condition).   The total capacitance value of the inverting capacitor to which the input voltage is applied during the hold operation and the total capacitance value of the non-inverting capacitor are set to be substantially equal (second condition). Sample hold circuit.   The total capacitance value of the capacitor to which the input voltage is applied during the sampling operation and the total capacitance value of the capacitor to which the input voltage is applied during the hold operation are set to be substantially equal (first condition). Item 3. The sample hold circuit according to Item 2. A band-limited input voltage sample and hold circuit,
An operational amplifier that differentially outputs the held voltage;
A plurality of inverting capacitors connected to the inverting input terminal of the operational amplifier;
A plurality of non-inverting capacitors connected to the non-inverting input terminal of the operational amplifier and having the same capacitance value as each of the inverting capacitors that form a pair;
At the time of an input voltage sampling operation, an input voltage is applied to at least one of the inverting side capacitor and the non-inverting side capacitor, a predetermined charge is set in the remaining capacitor, and at least a pair of inverting sides is set during a holding operation. Control for connecting the capacitor and the non-inverting capacitor to the non-inverting output terminal and the inverting output terminal of the operational amplifier, respectively, and controlling the input voltage to be applied to at least one of the remaining inverting and non-inverting capacitors. With circuit,
The total capacitance value of the capacitor to which the input voltage is applied during the sampling operation is set to be substantially equal to the total capacitance value of the capacitor to which the input voltage is applied during the hold operation (first condition),
The sum of the total capacitance value of the inverting capacitor to which the input voltage is applied during the sampling operation and the total capacitance value of the non-inverting capacitor to which the input voltage is applied during the hold operation, and the non-input to which the input voltage is applied during the sampling operation The sum value of the total capacitance value of the inverting side capacitor and the total capacitance value of the inverting side capacitor to which the input voltage is applied during the hold operation is set to be substantially different (fifth condition),
When N is a positive value, the capacitance values of the at least one pair of inverting and non-inverting capacitors respectively connected to the non-inverting output terminal and the inverting output terminal of the operational amplifier during the hold operation are (at the time of the sampling operation) Total capacitance value of inversion side capacitor to which input voltage is applied-Total capacitance value of non-inversion side capacitor to which input voltage is applied during sampling operation-Total capacitance value of inversion side capacitor to which input voltage is applied during hold operation + Hold A sample-and-hold circuit characterized by being set to be substantially equal to (the total capacitance value of the non-inversion side capacitor to which an input voltage is applied during operation) × (N / 2) (fourth condition). A band-limited input voltage sample and hold circuit,
An operational amplifier that differentially outputs the held voltage;
A plurality of inverting capacitors connected to the inverting input terminal of the operational amplifier;
A plurality of non-inverting capacitors connected to the non-inverting input terminal of the operational amplifier and having the same capacitance value as each of the inverting capacitors that form a pair;
At the time of an input voltage sampling operation, an input voltage is applied to at least one of the inverting side capacitor and the non-inverting side capacitor, a predetermined charge is set in the remaining capacitor, and at least a pair of inverting sides is set during a holding operation. Control for connecting the capacitor and the non-inverting capacitor to the non-inverting output terminal and the inverting output terminal of the operational amplifier, respectively, and controlling the input voltage to be applied to at least one of the remaining inverting and non-inverting capacitors. With circuit,
The total capacitance value of the capacitor to which the input voltage is applied during the sampling operation is set to be substantially equal to the total capacitance value of the capacitor to which the input voltage is applied during the hold operation (first condition),
The total capacitance value of the inverting side capacitor to which the input voltage is applied during the sampling operation and the total capacitance value of the inverting side capacitor to which the input voltage is applied during the holding operation are set to be substantially different (fifth A condition)
The total capacitance value of the non-inversion side capacitor to which the input voltage is applied during the sampling operation is set to be substantially different from the total capacitance value of the non-inversion side capacitor to which the input voltage is applied during the hold operation (Condition 5B) ,
When N is a positive value, the capacitance values of the at least one pair of inverting and non-inverting capacitors respectively connected to the non-inverting output terminal and the inverting output terminal of the operational amplifier during the hold operation are (at the time of the sampling operation) Total capacitance value of inversion side capacitor to which input voltage is applied-Total capacitance value of non-inversion side capacitor to which input voltage is applied during sampling operation-Total capacitance value of inversion side capacitor to which input voltage is applied during hold operation + Hold A sample-and-hold circuit characterized by being set to be substantially equal to (the total capacitance value of the non-inversion side capacitor to which an input voltage is applied during operation) × (N / 2) (fourth condition). When the input voltage is a differential input voltage composed of an inverting input voltage and a non-inverting input voltage,
The third condition is satisfied for each of the inverting input voltage and the non-inverting input voltage,
The value obtained by subtracting the total capacitance value of the non-inverting side capacitor to which the non-inverting input voltage is applied from the total capacitance value of the inverting side capacitor to which the non-inverting input voltage is applied during the sampling operation, and the non-inverting mode to which the inverting input voltage is applied. A value obtained by subtracting the total capacitance value of the inverting side capacitor to which the inverting input voltage is applied from the total capacitance value of the side capacitor is set to be substantially equal (sixth condition),
The capacitance values of the at least one pair of inverting and non-inverting capacitors connected to the non-inverting output terminal and the inverting output terminal of the operational amplifier at the time of the hold operation are (the inversion to which the non-inverting input voltage is applied during the sampling operation). The total capacitance value of the non-inverting input voltage to which the non-inverting input voltage is applied during the sampling operation-The total capacitance value of the inverting capacitor to which the non-inverting input voltage is applied during the holding operation + 2. The sample according to claim 1, wherein the sample is set so as to be substantially equal to (total capacitance value of non-inversion side capacitor to which inverting input voltage is applied) × (N / 2) (seventh condition). Hold circuit. When the input voltage is a differential input voltage composed of an inverting input voltage and a non-inverting input voltage,
The third condition is satisfied for each of the inverting input voltage and the non-inverting input voltage,
The value obtained by subtracting the total capacitance value of the non-inverting side capacitor to which the non-inverting input voltage is applied from the total capacitance value of the inverting side capacitor to which the non-inverting input voltage is applied during the sampling operation, and the non-inverting mode to which the inverting input voltage is applied. A value obtained by subtracting the total capacitance value of the inverting side capacitor to which the inverting input voltage is applied from the total capacitance value of the side capacitor is set to be substantially equal (sixth condition),
The capacitance value of the at least one pair of inverting and non-inverting capacitors connected to the non-inverting output terminal and the inverting output terminal of the operational amplifier at the time of the hold operation is − (inversion to which the inverting input voltage is applied during the sampling operation). -Capacitor side capacitance-total capacitance value of non-inversion side capacitor to which inverted input voltage is applied during sampling operation-total capacitance value of inverted side capacitor to which inverted input voltage is applied during hold operation + inverted input voltage during hold operation 2. The sample-and-hold circuit according to claim 1, wherein the sample-and-hold circuit is set so as to be substantially equal to (total capacitance value of non-inversion side capacitors to which N is applied) × (N / 2) (seventh condition).   For each of the inverting input voltage and the non-inverting input voltage, the total capacitance value of the inverting side capacitor to which the input voltage is applied during the hold operation and the total capacitance value of the non-inverting side capacitor are set to be substantially equal (first 8. The sample-and-hold circuit according to claim 6 or 7, characterized by two conditions).   For each of the inverting input voltage and the non-inverting input voltage, the total capacitance value of the capacitor to which the input voltage is applied during the sampling operation is set to be substantially equal to the total capacitance value of the capacitor to which the input voltage is applied during the hold operation. 9. The sample hold circuit according to claim 8, wherein the sample hold circuit is a first condition.   10. The inverting input terminal and non-inverting input terminal of the operational amplifier are biased to a predetermined voltage by operating the operational amplifier as a voltage follower during an input voltage sampling operation. The sample-and-hold circuit described.   The capacitance value of the at least one pair of inversion-side capacitors and non-inversion-side capacitors respectively connected to the non-inversion output terminal and the inversion output terminal of the operational amplifier during a hold operation can be changed. Item 11. The sample and hold circuit according to any one of Items 1 to 10.   12. The sample-and-hold circuit according to claim 1, wherein the sample-and-hold circuit has an input voltage applied to at least one of the inverting side capacitor and the non-inverting side capacitor during the sampling operation. A multiplying D / A converter characterized by applying and controlling a DAC voltage set in accordance with an input digital value to at least one other capacitor. 13. A sub A / D converter for A / D converting an input voltage into an input digital value corresponding to the magnitude thereof, and a multiplying D / A converter according to claim 12, wherein the input voltage is multiplied by 1 / N. A unit conversion circuit that outputs a residual voltage by doubling a difference voltage between the obtained value and the D / A conversion value of the input digital value;
An A / D conversion code for an A / D conversion target voltage is generated by performing an operation of inputting a residual voltage output from the unit conversion circuit to the unit conversion circuit and obtaining a new residual voltage as many times as necessary. A / D converter characterized by the above.   14. The A / D converter according to claim 13, wherein a plurality of the unit conversion circuits are provided and connected in series.   14. The A / D converter according to claim 13, further comprising a configuration in which a residual voltage output from the unit conversion circuit is sequentially circulated as an input voltage of the unit conversion circuit.   Only when the A / D conversion target voltage is input to the unit conversion circuit to obtain the first residual voltage, the unit conversion circuit can calculate the value obtained by multiplying the input voltage by 1 / N and the D / D of the input digital value. When the difference voltage from the A conversion value is doubled to output a residual voltage and the residual voltage is input to the unit conversion circuit to obtain a new residual voltage, the unit conversion circuit 16. The A / D converter according to claim 13, wherein a difference voltage between the input digital value and a D / A conversion value is doubled to output a residual voltage.

Images