JP4345152B2 - Start-up circuit and voltage supply circuit using the same - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention is built in a voltage supply circuit, for example, a bandgap reference voltage circuit, and operates using the bandgap reference voltage circuit to start the reference voltage circuit reliably, and is configured using the starter circuit. The present invention relates to a voltage supply circuit.
[0002]
[Prior art]
Conventionally, it operates normally if no signal is given to the feedback loop of the operational amplifier at the start of the circuit, such as a band gap reference voltage circuit using feedback of an operational amplifier circuit (operation amplifier, hereinafter simply referred to as an operational amplifier for convenience). In a circuit that does not start the circuit, there is a need for an activation circuit that has a simple circuit configuration and can reliably activate the circuit.
[0003]
FIG. 14 is a circuit diagram showing an example of a voltage supply circuit including a conventional startup circuit.
As shown in the figure, the voltage supply circuit of this example is constituted by a starter circuit 10 and a bandgap reference voltage circuit 20. The startup circuit 10 includes an inverter INV101, a NAND gate NA101, and a delay circuit D101. Since the pMOS transistors T104 and T105 and the inverter INV102 also contribute to the operation of the bandgap reference voltage circuit 20, a circuit constituted by these circuit elements can be regarded as a part of the startup circuit.
[0004]
The activation circuit 10 receives the standby signal STB and generates signals S1 and S2 for reliably operating the bandgap reference voltage circuit 20 in accordance with the standby signal STB.
The band gap reference voltage circuit 20 includes an operational amplifier circuit (op-amp) OPA1, pMOS transistors T101, T102, T103, and diode-connected npn transistors B101, B102, B103.
The transistor T101, the resistance element R101, and the diode-connected transistor B101 have a power supply voltage V_CCTransistor B102, which is connected in series between the supply line and a reference potential, for example, a ground potential GND supply line, and is diode-connected to transistor T102, is connected to power supply voltage V_CCTransistor T103, resistance element R102, and diode-connected transistor B103 connected in series between the supply line of power supply and ground potential GND are connected to power supply voltage V_CCAre connected in series between the supply line and the ground potential GND. The gates of the transistors T101, T102, and T103 are all connected to the output terminal of the operational amplifier OPA1, and currents I1, I2, and I3 are output according to the output signal of the operational amplifier OPA1, respectively.
[0005]
The non-inverting input terminal (+) of the operational amplifier OPA1 is connected to a node n1 that is a connection midpoint between the transistor T101 and the resistor element R101, and its inverting input terminal (−) is a connection midpoint between the transistor T102 and the transistor B102. Is connected to a node n2. The output signal of the operational amplifier OPA1 is applied to the gates of the transistors T101, T102, and T103, respectively. Therefore, the operational amplifier OPA1 forms a feedback loop, and the currents I1, I2, and I3 of the transistors T101, T102, and T103 are controlled by controlling the feedback loop so that the voltages at the nodes n1 and n2 are equal during normal operation. Is done.
[0006]
In the standby (stopped) state, the output terminal of the operational amplifier OPA1, that is, the node n3 is in a high impedance state. At this time, since the standby signal STB is at the high level, the output terminal of the inverter INV102 is held at the low level, and the transistor T105 is turned on._CCIs held at the level. Accordingly, the transistors T101, T102, and T103 are turned off and no direct current flows, so that the voltages at the nodes n1 and n2 are indefinite. At the start of operation, as the standby signal STB is switched from the high level to the low level, the output terminal of the inverter INV102 is switched from the low level to the high level, so that the transistor T105 is turned off and the operational amplifier OPA1 is input to the input nodes n1 and n2. The voltage at the node n3 is controlled according to the voltage of the currents I1, I2 and I3 of the transistors T101, T102 and T103.
[0007]
However, if there is no start circuit, the voltage V at node n1_n1Is the voltage V of the node n2._n2If higher, ie V_n1> V_n2In this case, since the signal voltage input to the non-inverting input terminal (+) is higher than the signal voltage applied to the inverting input terminal (−), the operational amplifier OPA1 continues to output a high level signal, and the transistor T101, T102, and T103 remain off. In such a state, the band gap reference voltage circuit 20 cannot operate normally.
[0008]
As described above, the standby signal STB is held at a high level when the voltage supply circuit is stopped, and is switched from a high level to a low level when the voltage supply circuit starts operation. In response to this, the delay time Δt of the delay circuit D101 is detected from the falling edge of the standby signal STB by the illustrated startup circuit 10._dDuring this period, the low level signal S1 is output. At other times, the signal S1 is held at the high level.
[0009]
Since the transistor T104 is turned on while the signal S1 is at the low level, the current flowing through the transistor T104 is input to the node n2. The emitter area of the diode-connected bipolar transistor B101 is larger than the emitter area of the transistor B102. For this reason, when the same current is supplied to these transistors, or when the current is supplied only to the transistor B102, the voltage V of the node n2 in the initial stage of operation._n2Is always the voltage V of the node n1_n1Get higher. Therefore, in the operational amplifier OPA1, the input signal voltage at the inverting input terminal (−) is greater than the input signal voltage at the non-inverting input terminal (+), and the output signal is held at a low level. In response, transistors T101, T102 and T103 are turned on, and currents I1, I2 and I3 are output.
[0010]
The signal S1 applied to the gate of the transistor T104 is the delay time Δt of the delay circuit D101._dIs held at the low level for the time set by, and then switched to the high level again. Since the transistor T104 is turned on only while the signal S1 is at a low level and then turned off, the bandgap reference voltage circuit 20 is controlled by the feedback loop formed by the operational amplifier OPA1, and the output terminal T_OUTTo supply voltage V_CCAnd stable voltage V without temperature dependence_OUTIs output.
[0011]
[Problems to be solved by the invention]
In the conventional voltage supply circuit described above, the node at the time when the transistor T105 is stopped is controlled by the start-up circuit 10 after the circuit is started, and the transistor T105 is turned off and the transistor T104 is turned on for a certain period of time and then turned off. Regardless of the voltage of n1 and n2, it can start normally. Here, if the transistor T104 is kept on, the feedback loop composed of the operational amplifier OPA1 cannot operate normally, and the operational amplifier OPA1 cannot control the transistors T101, T012, and T103. Therefore, the transistor T104 is turned on by the delay time of the delay circuit D101. A control signal S1 for controlling time is generated.
[0012]
However, the switching of the level of the signal S1 is not performed after confirming the operating state of the bandgap reference voltage circuit 20, but is set empirically, so that it is always set to an optimum value. is not. If this switching time is too long, the rise time of the voltage supply circuit is extended more than necessary, and the rise characteristics deteriorate, and if it is too short, the voltage V of the node n2_n2There is a possibility that the starting circuit stops before the voltage becomes sufficiently high, and the band gap reference voltage circuit 20 does not start normally.
Therefore, this starting circuit requires a careful attention at the time of design, and is disadvantageous in that it is easily affected by variations in manufacturing and circuit operating conditions.
[0013]
The present invention has been made in view of such circumstances, and its purpose is to have a simple circuit configuration, easy design, resistance to manufacturing variations, no dependency on temperature and power supply voltage, and minimum power consumption. An object of the present invention is to provide a start-up circuit that can be suppressed to the limit and a voltage supply circuit using the same.
[0014]
[Means for Solving the Problems]
  In order to achieve the above object, a start circuit according to the present invention is a start circuit that supplies a start current to a predetermined functional circuit and starts the function circuit. The start circuit receives the start signal and supplies the start current to the functional circuit. And a starting current supply means for receiving a voltage of a predetermined operation node of the functional circuit as a second input signal.Depending on the level of the first and second input signalsA bistable logic circuit controlled in the first and second states, and a logic gate that outputs a signal corresponding to a logical operation result of the first signal and the output signal of the bistable logic circuit, Supplying start current to the start current supplying means when the output signal of the logic gate is at the first levelLetAnd an activation control means for causing the activation current supply means to stop supplying the activation current at the second level after the current supply.
[0015]
  In addition, the voltage supply circuit of the present invention includes a start-up current supply unit that outputs a start-up current in response to a start-up signal, a voltage generation circuit that starts up in response to the start-up current and outputs a stable voltage during normal operation, The activation signal is received as a first input signal, and the voltage at a predetermined operation node of the voltage generation circuit is received as a second input signal.Depending on the level of the first and second input signalsA bistable logic circuit controlled in the first and second states, and a logic gate that outputs a signal corresponding to a logical operation result of the first signal and the output signal of the bistable logic circuit, Supplying start current to the start current supplying means when the output signal of the logic gate is at the first levelLetAnd an activation control means for causing the activation current supply means to stop supplying the activation current at the second level after the current supply.
[0016]
  Specifically, the voltage supply circuit of the present invention includes a first current supply transistor connected between the power supply voltage supply line and the first node, and the first node and the reference potential line. A first resistor connected in series, a first diode in the forward direction toward the reference potential line, and a second current connected between the power supply voltage supply line and the second node A supply transistor, a second diode connected between the second node and the reference potential line and directed in a forward direction toward the reference potential line; and the power supply voltage supply line and the third node A third current supply transistor connected in between, a second resistance element connected in series between the third node and the reference potential line, and a forward direction toward the reference potential line A third diode and a first input terminal And a second input terminal is connected to the second node, and a voltage signal corresponding to a difference between signals input to the first and second input terminals is applied to the first, second, and second nodes. An amplifier circuit to be applied to the control terminal of the third current supply transistor, start-up current supply means for supplying a start-up current to the second node in response to a start-up signal at start-up, and an output voltage of the amplifier circuit being a predetermined reference Start control means for stopping the supply of the start current when the value is reached.The activation control means is,The activation signal is received as a first input signal, the output signal of the amplifier circuit is received as a second input signal, and the first and second states are controlled according to the levels of the first and second input signals. Bistable logic circuit,A logic gate that outputs a signal corresponding to a logical operation result of the activation signal and the output signal of the bistable logic circuit; and when the output signal of the logic gate is at the first level, the activation current supply means The start-up current is supplied, and the start-up current supply means stops the supply of the start-up current at the second level after the supply of the current..
[0017]
In the present invention, it is preferable that the activation control means receives the activation signal as a first input signal and the output signal of the amplifier circuit as a second input signal. A bistable logic circuit controlled to a first state and a second state according to an input signal, and a logic gate for outputting a signal corresponding to a logical operation result of the start signal and an output signal of the bistable logic circuit, Have The bistable logic circuit includes first and second transistors connected in series between a power supply voltage supply line and a reference potential line, and the gate of the first transistor is connected to the amplifier circuit. An output voltage is applied, and the activation signal is applied to the gate of the second transistor.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
First embodiment
FIG. 1 is a circuit diagram showing a first embodiment of a starting circuit according to the present invention.
As shown in the figure, the activation circuit 10a of the present embodiment includes pMOS transistors PT1, PT2, PT3, an nMOS transistor NT1, inverters INV1, INV2, and a NAND gate NA1.
[0022]
Transistors PT1 and NT1 have a power supply voltage V_CCAre connected in series between the supply line and the ground potential GND. The gate of the transistor PT1 is connected to the signal terminal SN1, and the gate of the transistor NT1 is connected to the input terminal IN1. A connection point between the drains of the transistors PT1 and NT1 is connected to the node ND1. The input terminal of the inverter INV1 is connected to the input terminal IN1, and the input terminal of the inverter INV2 is connected to the node ND1. Both input terminals of the NAND gate NA1 are connected to the output terminals of the inverters INV1 and INV2, respectively.
The gate of the transistor PT2 is connected to the output terminal of the NAND gate NA1, and its source is the power supply voltage V_CCThe drain is connected to the output terminal OUT1.
The gate of the transistor PT3 is connected to the output terminal of the inverter INV1, and the source thereof is the power supply voltage V_CCThe drain is connected to the signal terminal SN1.
[0023]
The start-up circuit 10a configured in this way is applied with a standby signal STB that is set to a high level when stopped and a low level after the operation is applied to the input terminal IN1, and a current is temporarily supplied to start up (voltage is applied). Output terminal OUT1 is connected to the necessary operation node, and the power supply voltage V_CCAfter the start of operation, the power supply voltage V_CCThe signal terminal SN1 is connected to an operation node that needs to be lowered to a voltage sufficient to turn on the pMOS transistor.
[0024]
Hereinafter, the operation of the activation circuit of the present embodiment will be described with reference to FIG.
The standby signal STB is input to the input terminal IN1. The standby signal STB is held at a high level while the circuit is stopped (standby state), and is switched to a low level when the circuit starts to operate.
[0025]
In the standby state, the output terminal of the inverter INV1 is at a low level. Further, the transistor NT1 is turned on, and the node ND1 is held at a low level, for example, the level of the ground potential GND. Since the output terminal of the NAND gate NA1 is held at a high level according to the output signals of the inverters INV1 and INV2, the transistor PT2 is turned off.
On the other hand, since the gate of the transistor PT3 is at the low level, the transistor PT3 is turned on and the signal terminal SN1 is at the high level, for example, the power supply voltage V_CCOr it is held at a level close to it.
[0026]
After the voltage supply circuit starts operation, the standby signal STB is switched from the high level to the low level. In response to this, the transistor NT1 is turned off from on. The output terminal of the inverter INV1 is switched from the low level to the high level, and accordingly, the transistor PT3 is turned off. However, the signal terminal SN1 is held at the high level unless a new signal is input from the signal terminal SN1. The
For this reason, since both the transistors PT1 and NT1 are turned off, the node ND1 is in a high impedance state, and its voltage does not change and is held at a low level.
[0027]
At this time, since both input terminals of the NAND gate NA1 are both at the high level, the output terminals are held at the low level. In response to this, the transistor PT2 is turned on, and the starting current I is applied to the output terminal OUT1._STIs supplied.
The current I supplied from the output terminal OUT1_STAccordingly, for example, the band gap reference voltage circuit starts to operate, and the voltage of the signal terminal SN1 starts to decrease. When the voltage at the terminal decreases to a value sufficient to turn on the pMOS transistor PT1, the transistor PT1 is turned on, and the node ND1 changes from low level to high level, for example, the power supply voltage V_CCOr raised to that close level.
[0028]
When the voltage of the node ND1 exceeds the logic threshold value of the inverter INV2, the output terminal of the inverter INV2 is switched from high level to low level, and accordingly, the output terminal of the NAND gate NA1 is switched from low level to high level. . For this reason, the transistor PT2 is turned off, and the supply of current to the output terminal OUT1 is stopped. Starting current I_STAfter the supply is stopped, the band gap reference voltage circuit starts to operate normally.
[0029]
As described above, the startup circuit 10a of the present embodiment operates when the voltage supply circuit is started. For example, the startup current I required for the bandgap reference voltage circuit is_STSupply. Since the operation is stopped after the operation of the bandgap reference voltage circuit is confirmed, the voltage supply circuit can be reliably started. Also, the starting current I to the band gap_STIs automatically stopped according to the operating state of the band gap, so that the starting current I_STThe supply timing can be set as appropriate, and the power consumption at startup can be suppressed to the minimum necessary. The circuit configuration is simple, the application range is wide, and the design is easy. Furthermore, it has the characteristic of being resistant to process variations.
[0030]
Second embodiment
FIG. 2 is a circuit diagram showing a second embodiment of the starting circuit according to the present invention.
Compared to the first embodiment of the starter circuit shown in FIG. 1, the starter circuit 10b of this embodiment is provided with an inverter INV3 and an nMOS transistor NT2 instead of the pMOS transistor PT2 on the output side of the NAND gate NA1. It is different. Since the other parts are almost the same as those of the first embodiment shown in FIG. 1, in FIG. 2, the same components as those in the circuit are denoted by the same reference numerals as those in FIG.
[0031]
As shown in FIG. 2, the input terminal of the inverter INV3 is connected to the output terminal of the NAND gate NA1, and the output terminal is connected to the gate of the transistor NT2. The source of the transistor NT2 is grounded, and the drain is connected to the output terminal OUT2.
[0032]
In the start-up circuit of this embodiment, since a pull-in current flows to the output terminal OUT2 at the start-up, the output terminal OUT2 is connected to an operation node where it is necessary to temporarily pull in the current (lower the voltage) after the operation starts.
[0033]
Hereinafter, the operation of the activation circuit 10b of the present embodiment will be briefly described with reference to FIG.
In the standby state, the standby signal STB input to the input terminal IN1 is held at a high level. In response to this, the output terminal of the inverter INV1 is held at a low level, the transistor PT3 is turned on, and the signal terminal SN1 is held at a high level. The transistor NT1 is turned on, the node ND1 is held at a low level, and the output terminal of the inverter INV2 is at a high level. At this time, since the output terminal of the NAND gate NA1 is at the high level, the output terminal of the inverter INV3 is at the low level, and the transistor NT2 is turned off.
[0034]
After the circuit starts operation, the standby signal STB is switched from the high level to the low level. Accordingly, the output terminal of the inverter INV1 is changed to the high level and the transistor PT3 is turned off. However, unless a new signal is input to the signal terminal SN1, the voltage does not change and is maintained at the high level.
On the other hand, the transistor NT1 is turned off, the node ND1 is in a high impedance state, the voltage is held at a low level, and the output terminal of the inverter INV2 is also kept at a high level.
[0035]
Therefore, both the input terminals of the NAND gate NA1 are at a high level, the output terminal thereof is at a low level, and the output terminal of the inverter INV3 is at a high level, so that the transistor NT2 is turned on, and a current drawn into the output terminal OUT2 Flowing.
[0036]
For example, the bandgap reference voltage circuit starts to operate according to the current drawn from the output terminal OUT2. Accordingly, when the voltage of the signal terminal SN1 decreases and the voltage decreases to a voltage sufficient to turn on the pMOS transistor PT1, the transistor PT1 is turned on and the node ND1 is raised from the low level to the high level. For this reason, the output signal levels of the inverter INV2, the NAND gate NA1 and the inverter INV3 are sequentially switched. As a result, the output terminal of the inverter INV3 becomes a low level, and the transistor NT2 is turned off.
[0037]
After the transistor NT2 is turned off, no current is drawn into the output terminal OUT2, and the bandgap reference voltage circuit enters a normal operation state. For example, the output voltage is stabilized by a feedback loop composed of an operational amplifier or the like. Supply a constant voltage.
[0038]
Third embodiment
FIG. 3 is a circuit diagram showing a third embodiment of the activation circuit according to the present invention.
As shown in the figure, the activation circuit 10c of the present embodiment includes pMOS transistors PT1 and PT2, nMOS transistors NT1 and NT3, an inverter INV4, and a NAND gate NA1.
[0039]
Transistors PT1 and NT1 have a power supply voltage V_CCAre connected in series between the supply line and the ground potential GND. The gate of the transistor PT1 is connected to the input terminal of the inverter INV4, and the gate of the transistor NT1 is connected to the signal terminal SN2. A connection point between the drains of the transistors PT1 and NT1 is connected to the node ND1. Note that the input terminal of the inverter INV1 is connected to the input terminal IN1. A standby signal STB is applied to the input terminal IN1.
[0040]
The two input terminals of the NAND gate NA1 are connected to the node ND1 and the output terminal of the inverter INV4, respectively.
The gate of the transistor PT2 is connected to the output terminal of the NAND gate NA1, and the source is the power supply voltage V._CCThe drain is connected to the output terminal OUT1.
The gate of the transistor NT3 is connected to the input terminal IN1, the drain is connected to the signal terminal SN2, and the source is grounded.
[0041]
In the starting circuit 10c of the present embodiment, a standby signal STB that is set to a high level when stopped and to a low level after the operation is applied is applied to the input terminal IN1. The output terminal OUT1 is connected to an operation node that needs to temporarily flow current for starting, and is fixed to the ground potential GND when the operation is stopped, and is a voltage sufficient to turn on the nMOS transistor from the ground potential GND after the operation is started. The signal terminal SN2 is connected to the operation node that needs to be raised to.
[0042]
Hereinafter, the operation of the activation circuit of the present embodiment will be described with reference to FIG.
In the standby state, since the high-level standby signal STB is input, the output terminal of the inverter INV4 is held at the low level, and the transistor PT1 is turned on. At this time, since the transistor NT3 is turned on, the signal terminal SN2 is held at a low level, for example, the ground potential GND level, and the transistor NT1 is turned off. Therefore, the node ND1 is almost at the power supply voltage V_CCIs held at the level.
At this time, since the output terminal of the NAND gate NA1 is held at a high level, the transistor PT2 is turned off.
[0043]
After the operation of the voltage supply circuit starts, the standby signal STB is switched from the high level to the low level. In response to this, the output terminal of the inverter INV4 is switched from the low level to the high level, and the transistor PT1 is turned off. On the other hand, the transistor NT3 is turned off, the signal terminal SN2 is held at a low level, and the transistor NT1 is also kept off. For this reason, the node ND1 is in a high impedance state, and the voltage is also held at a high level.
[0044]
At this time, both the input terminals of the NAND gate NA1 are at the high level, the output terminal thereof is changed to the low level, and the transistor PT2 is turned on. Accordingly, the starting current I is applied to the output terminal OUT1._STIs supplied.
The current I supplied from the output terminal OUT1_STAccordingly, for example, the band gap reference voltage circuit starts to operate, and the voltage of the signal terminal SN2 starts to rise from the low level. When the voltage at the terminal SN2 rises to the threshold voltage of the nMOS transistor NT1, the transistor NT1 is turned on, and the node ND1 is switched from the high level to the low level. Accordingly, the output terminal of the NAND gate NA1 is switched from the low level to the high level, the transistor PT2 is turned off, and the start-up current I_STSupply stops. Starting current I_STAfter the supply is stopped, the band gap reference voltage circuit starts to operate normally.
[0045]
As described above, the startup circuit 10c of the present embodiment operates when the voltage supply circuit is started. For example, the startup current I required for the bandgap reference voltage circuit is_STSupply. Since the operation is stopped after the operation of the bandgap reference voltage circuit is confirmed, the voltage supply circuit can be reliably started. Also, the starting current I to the band gap_STIs automatically stopped according to the operating state of the band gap, so that the starting current I_STThe supply timing can be set as appropriate, and the power consumption at startup can be suppressed to the minimum necessary. The circuit configuration is simple, the application range is wide, and the design is easy. Furthermore, it has the characteristic of being resistant to process variations.
[0046]
Fourth embodiment
FIG. 4 is a circuit diagram showing a fourth embodiment of the activation circuit according to the present invention.
Compared with the start-up circuit of the third embodiment shown in FIG. 3, in the start-up circuit 10d of the present embodiment, an inverter INV3 and an nMOS transistor NT2 are provided on the output side of the NAND gate NA1 instead of the pMOS transistor PT2. It is different in point. Since the other parts are almost the same as those of the third embodiment shown in FIG. 3, in FIG. 4, the same components as those of the activation circuit are denoted by the same reference numerals as those in FIG.
[0047]
As shown in FIG. 4, the input terminal of the inverter INV3 is connected to the output terminal of the NAND gate NA1, and the output terminal is connected to the gate of the transistor NT2. The source of the transistor NT2 is grounded, and the drain is connected to the output terminal OUT2.
[0048]
In the start-up circuit of this embodiment, since a pull-in current flows to the output terminal OUT2 at the start-up, the output terminal OUT2 is connected to an operation node where it is necessary to temporarily pull in the current (lower the voltage) after the operation starts.
[0049]
Hereinafter, the operation of the activation circuit 10d of the present embodiment will be briefly described with reference to FIG.
In the standby state, the standby signal STB input to the input terminal IN1 is held at a high level. In response to this, the output terminal of the inverter INV4 is held at the low level, the pMOS transistor PT1 is turned on, and the node ND1 is held at the high level. At this time, since the output terminal of the NAND gate NA1 is at the high level, the output terminal of the inverter INV3 is at the low level, and the transistor NT2 is turned off.
[0050]
After the operation of the voltage supply circuit starts, the standby signal STB is switched from the high level to the low level. In response to this, the output terminal of the inverter INV4 is switched from the low level to the high level, and the transistor PT1 is turned off. On the other hand, the transistor NT3 is turned off, the signal terminal SN2 is held at a low level, and the transistor NT1 is also kept off. For this reason, the node ND1 is in a high impedance state, and the voltage is also held at a high level.
[0051]
At this time, the output terminal of the NAND gate NA1 is switched to the low level, and the transistor NT2 is turned on in response to this, and is pulled into the output terminal OUT2._STFlows.
Pull-in current I of output terminal OUT2_STAccordingly, for example, the band gap reference voltage circuit starts to operate, and the voltage of the signal terminal SN2 starts to rise from the low level. When the voltage at the terminal SN2 rises to the threshold voltage of the nMOS transistor NT1, the transistor NT1 is turned on, and the node ND1 is switched from the high level to the low level. As a result, the transistor NT2 is turned off, and the pull-in current I_STNo longer flows. Thereafter, the bandgap reference voltage circuit starts normal operation, and supplies a constant voltage having a desired level without depending on the power supply voltage and temperature.
[0052]
Fifth embodiment
FIG. 5 is a circuit diagram showing a fifth embodiment of the activation circuit according to the present invention.
As shown in the figure, the activation circuit 10e of this embodiment is different from the first embodiment shown in FIG. 1 in that the delay circuit DLY1 is connected between the node ND1 and the input terminal of the inverter INV2. Apart from that, it has almost the same configuration. In FIG. 5, the same parts of the start-up circuit are denoted by the same reference numerals as in FIG. 1.
[0053]
Hereinafter, the configuration and operation of the startup circuit 10e of the present embodiment will be described focusing on differences from the startup circuit of the first embodiment.
As shown in FIG. 5, the input terminal of the delay circuit DLY1 is connected to the node ND1, and its output terminal is connected to the input terminal of the inverter INV2. Note that the delay circuit DLY1 is configured by, for example, an even number of inverters connected in series, or an RC circuit including a resistance element and a capacitor.
[0054]
FIG. 6 shows two configuration examples of the delay circuit DLY1. As shown in FIG. 4A, the delay circuit DLY1-1 is configured by an even number of inverters connected in series. In this case, the delay time Δt of the delay circuit DLY1-1._dIs determined by the sum of the delay times of the inverters.
The delay circuit DLY1-2 illustrated in FIG. 6B includes a resistance element R and a capacitor C. As illustrated, the delay circuit DLY1-2 has substantially the same configuration as the integration circuit. By setting the resistance value of the resistance element R and the capacitance value of the capacitor C, the delay time of the delay circuit can be controlled.
[0055]
Hereinafter, the operation of the activation circuit 10e of the present embodiment will be described. As described above, the present embodiment is obtained by adding the delay circuit DLY1 to the first embodiment, and basically operates in the same manner as the first embodiment. However, hereinafter, only the operation related to the delay circuit is performed. Will be explained.
[0056]
First, in the standby state, the standby signal STB is at a high level, the transistor NT1 is turned on, and the node ND1 is held at a low level. At this time, the output terminal of the NAND gate NA1 is at a high level, and the transistor PT2 is turned off.
[0057]
After the voltage supply circuit starts operation, the standby signal STB is switched from the high level to the low level. In response to this, the transistor NT1 is turned off from on. While the node ND1 is held at a low level, its output signal is also at a low level. In response to the level change of the standby signal STB, the output terminal of the inverter INV1 is switched from the low level to the high level. At this time, since both input terminals of the NAND gate NA1 are both at the high level, the output terminals are held at the low level. In response to this, the transistor PT2 is turned on, and the starting current I is applied to the output terminal OUT1._STIs supplied.
The current I supplied from the output terminal OUT1_STAccordingly, for example, the band gap reference voltage circuit starts to operate, and the voltage of the signal terminal SN1 starts to drop. When the voltage at the terminal decreases to a value sufficient to turn on the pMOS transistor PT1, the transistor PT1 is turned on, the node ND1 is charged by the current flowing through the transistor PT1, and its high level rises.
[0058]
Delay time Δt of delay circuit DLY1_dAfter elapses, the output terminal of the delay circuit DLY1 also switches from the low level to the high level. In response to this, the output signals of the inverter INV2 and the NAND gate NA1 are sequentially switched. When the output signal of the NAND gate NA1 switches to a high level, the transistor PT2 is turned off and the starting current I_STSupply stops. Starting current I_STAfter the supply stops, the bandgap reference voltage circuit starts to operate normally and supplies a desired constant voltage to the outside.
[0059]
That is, the starting circuit 10e of the present embodiment, for example, applies a starting current I to the bandgap reference voltage circuit according to the falling edge of the standby signal STB._STAnd the supply of the starting current is controlled according to the level change of the signal terminal SN1. In the start-up circuit 10a of the first embodiment shown in FIG. 1, when the voltage level of the signal terminal SN1 drops and the transistor PT1 is turned on, the transistor PT2 is turned off accordingly, and the start-up current I_STWas stopped. However, in the activation circuit 10e of the present embodiment, the delay time Δt of the delay circuit DLY1 after the voltage of the signal terminal SN1 drops and the transistor PT1 is turned on._dAfter a lapse of time, the transistor PT2 is turned off and the starting current I_STStop supplying.
[0060]
In the band gap reference voltage circuit constituting the voltage supply circuit, a certain period of time elapses after the voltage at the signal terminal SN1 drops and reaches the level at which the pMOS transistor is turned on, depending on the operating conditions, manufacturing variations, etc. After that, the circuit reaches a normal operating state. For this reason, as soon as the voltage of the signal terminal SN1 drops and reaches a predetermined value, the starting current I_STWhen the supply of power is stopped, the bandgap reference voltage circuit may not be started normally. By using the starting circuit 10e of the present embodiment, the starting current I after the voltage of the signal terminal SN1 reaches a predetermined value._STIs the delay time Δt of the delay circuit DLY1._dSince the voltage can be appropriately controlled by adjusting the voltage, the voltage supply circuit can be reliably started.
[0061]
In addition, the logic part in the starting circuit of each embodiment mentioned above, ie, the part comprised by the inverter and logic gates, for example, NAND gate, can be replaced with another logic circuit whose logic is equivalent or whose function is equivalent. . Even when equivalent circuits having the same logic or function are used, it goes without saying that the start circuit has a similar function.
[0062]
Embodiment of voltage supply circuit using starter circuit
FIG. 7 is a circuit diagram showing an embodiment of a voltage supply circuit configured using the start-up circuit according to the present invention.
As shown in the figure, the voltage supply circuit of this example is configured by the start-up circuit 10a and the band gap reference voltage circuit 20 shown in the first embodiment. The output terminal OUT1 in the activation circuit 10a is connected to the node n2 of the bandgap reference voltage circuit 20, and the signal terminal SN1 is a node n3, that is, a connection point between the output terminal of the operational amplifier OPA1 and the gates of the transistors T101, T102, and T103. It is connected to the.
[0063]
A standby signal STB that switches to a high level in the standby state and switches to a low level after the voltage supply circuit starts operating is input to the input terminal IN1 of the activation circuit 10a.
In response to the fall of the standby signal STB, the starting circuit 10a receives the starting current I from the output terminal OUT1._STIs supplied to the node n2 of the bandgap reference voltage circuit 20, and the operating state of the bandgap reference voltage circuit 20 is confirmed based on the level of the node n3._STThe supply timing is controlled. Specifically, after the bandgap reference voltage circuit 20 is activated and the voltage at the node n3 decreases and reaches a level sufficient to turn on the transistor PT1, the activation circuit 10a turns off the transistor PT2. Starting current I_STStop supplying. For this reason, the starting current I_STIs stopped, the bandgap reference voltage circuit 20 performs a normal operation, and based on the control of the feedback circuit formed by the operational amplifier OPA1, the power supply voltage and the constant voltage V having no temperature dependence_OUTSupply.
[0064]
First embodiment of band gap reference voltage circuit
FIG. 8 is a circuit diagram showing a first embodiment of the bandgap reference voltage circuit 20.
As illustrated, the bandgap reference voltage circuit 20 includes an operational amplifier circuit OPA1, pMOS transistors T101, T102, and T103, resistance elements R101 and R102, and diode-connected npn transistors B101, B102, and B103.
[0065]
The transistor T101, the resistance element R101, and the diode-connected transistor B101 have a power supply voltage V_CCThe transistor B102 connected in series between the supply line and the ground potential GND and diode-connected to the transistor T102 is connected to the power supply voltage V_CCTransistor T103, resistance element R102, and diode-connected transistor B103 connected in series between the supply line of power supply and ground potential GND are connected to power supply voltage V_CCAre connected in series between the supply line and the ground potential GND.
The gates of the transistors T101, T102, and T103 are all connected to the output terminal of the operational amplifier OPA1, and output currents I1, I2, and I3, respectively, according to the output signal of the operational amplifier OPA1.
[0066]
The non-inverting input terminal (+) of the operational amplifier OPA1 is connected to a node n1 that is a connection midpoint between the transistor T101 and the resistor element R101, and its inverting input terminal (−) is a connection midpoint between the transistor T102 and the transistor B102. Is connected to a node n2. The output terminal of the bandgap reference voltage circuit 20 is formed by the midpoint of connection between the transistor T103 and the resistor element R102. During normal operation, the power supply voltage and the constant voltage V having no temperature dependence are output from the output terminal._OUTIs output.
The output signal of the operational amplifier OPA1 is applied to the gates of the transistors T101, T102, and T103, respectively. For this reason, the operational amplifier OPA1 forms a feedback loop, and the control of the feedback loop causes the voltages V of the nodes n1 and n2 during normal operation._n1And V_n2Are controlled so that the currents I1, I2, and I3 of the transistors T101, T102, and T103 are equal to each other.
[0067]
Since the transistors T101, T102, and T103 have the same characteristics such as channel width, the currents I1, I2, and I3 flowing through these transistors are equal during normal operation by controlling the feedback loop formed by the operational amplifier OPA1. Become.
The emitter size of the transistor B101 is 10 times the emitter size of the transistor B102. Note that the emitter sizes of the transistors B102 and B103 are equal.
[0068]
Hereinafter, the operating principle of the bandgap reference voltage circuit 20 will be described in detail using mathematical expressions.
Bipolar transistor base-emitter voltage V_BEIs calculated by the following equation.
[0069]
[Expression 1]
V_BE= V_Tln (I_C/ I_S(1)
[0070]
Where V_T= KT / q, k is the Boltzmann constant, T is the absolute temperature, and q is the charge of the electrons. I_CIs the collector current of the transistor, I_SIs a constant current value proportional to the emitter size of the transistor.
[0071]
In the band gap reference voltage circuit 20, the voltage V of the nodes n1 and n2 during normal operation._n1, V_n2Is V_n1= V_n2Therefore, the following equation is obtained accordingly.
[0072]
[Expression 2]
I₁R₁+ V_BE1= V_BE2            ... (2)
[0073]
Where V_BE1And V_BE2Are the base-emitter voltages of transistors B101 and B102, respectively.₁Is the resistance value of the resistance element R1. Substituting equation (1) into equation (2) yields:
[0074]
[Equation 3]
I₁R₁+ V_Tln (I₁/ I_S1)
= V_Tln (I₂/ I_S2(3)
[0075]
In formula (3), I₁, I₂Are current values of currents I1 and I2 flowing through transistors T101 and T102, respectively. As described above, the emitter size of the transistor B101 is 10 times the emitter size of the transistors B102 and B103. That is, I_S1= 10I_S2It is. Substituting this into equation (3) gives the current I₁Is required.
[0076]
[Expression 4]
I₁= V_T(Ln10) / R₁        (4)
[0077]
Further, the current value of the current I3 flowing through the transistor T103 is expressed as I_ThreeThen I₁= I₂= I_ThreeHolds. Based on this, the output voltage V of the band gap reference voltage circuit 20_OUTIs obtained by the following equation.
[0078]
[Equation 5]
V_OUT= V_BE3+ R₂V_T(Ln10) / R₁
... (5)
[0079]
In equation (5), V_BE3Is the base-emitter voltage of transistor B103, R₂Is the resistance value of the resistance element R102.
[0080]
In equation (5), the transistor base-emitter voltage V_BE3Has a negative temperature characteristic, for example, d (V_BE3) / DT = −2 mV / K. Therefore, by setting the temperature characteristic of the second term on the right side of Equation (5) to 2 mV / K, the output voltage V_OUTThe temperature dependence of can be completely eliminated. V_T= KT / q, so the output voltage V_OUTThe condition for eliminating the temperature dependence of is obtained by the following equation.
[0081]
[Formula 6]
ln10 (R₂/ R₁) (k / q) = 2mV / K
... (6)
[0082]
That is, the resistance element R of the resistance elements R101 and R102₁And R₂When satisfying the relationship shown in equation (6), the output voltage V_OUTDoes not depend on temperature change, and always has a constant voltage value. When the condition shown in Expression (6) is satisfied, when the temperature T is 300 K (27 degrees Celsius), the second term on the right side of Expression (5) is (R₂V_T(Ln10) / R₁) = 0.6V. Further, the base-emitter voltage V of the transistor B103_BE3Is 0.65 V, the output voltage V of the bandgap reference voltage circuit 20 according to the equation (5)._OUTBecomes 1.25V. That is, the resistance value R of the resistance elements R101 and R102 so as to satisfy the expression (6)₁, R₂, The band gap reference voltage circuit 20 shown in FIG. 8 makes the constant voltage V completely independent of the power supply voltage and the temperature._OUTCan be earned.
[0083]
FIG. 9 is a timing chart showing an operation at the time of starting the voltage supply circuit shown in FIG. Hereinafter, the operation of the voltage supply circuit of this example will be described with reference to FIGS. 9 and 7.
[0084]
As shown in FIG. 5A, when the circuit operation is stopped (standby), the standby signal STB is at a high level, for example, the power supply voltage V_CCAfter the circuit operation starts, the standby signal STB is held at a low level, for example, the ground potential GND.
[0085]
As shown in FIG. 5B, the node ND2, that is, the output terminal of the inverter INV1, is switched from the low level to the high level with a slight delay from the falling edge of the standby signal STB. Further, as shown in FIG. 5E, the output signal of the NAND gate NA1 is switched to the low level from the fall of the standby signal STB, and in response to this, the activation circuit 10a supplies the activation current to the bandgap reference voltage circuit 20. I_STBegin to supply. In response to this, the voltage V of the node n2 as shown in FIG._n2Begins to rise. FIG. 4G shows the voltage V at nodes n1 and n2._n1, V_n2The output voltage of the operational amplifier OPA1, that is, the voltage at the node n3 is shown. As shown, the voltage V at node n2_n2As the voltage increases, the voltage at the node n3 decreases. When the voltage at the node n3 decreases and reaches a voltage sufficient to turn on the pMOS transistor PT1 in the starter circuit 10a, the transistor PT1 is turned on, and in response to this, as shown in FIG. ND1 is charged and its voltage rises.
[0086]
As shown in FIG. 9D, when the voltage at the node ND1 exceeds the logic threshold voltage of the inverter INV2, the output of the inverter INV2 is inverted. Accordingly, as shown in FIG. 5E, the output of the NAND gate NA1 is also inverted and becomes high level, so that the transistor PT2 is turned off and the starting current I_STSupply stops. Thereafter, the bandgap reference voltage circuit 20 is controlled by a feedback loop composed of the operational amplifier OPA1, and the output voltage of the operational amplifier OPA1 is held constant, and the voltages V of the nodes n1 and n2 are accordingly changed._n1, V_n2Is kept almost constant and the constant voltage V from the bandgap reference voltage circuit 20 is independent of the power supply voltage and temperature._OUTIs supplied.
[0087]
In the band gap reference voltage circuit 20, the voltage V of the node n2 is_n2Is the voltage V of the node n1_n1If it is higher, the start-up circuit 10a hardly operates and the bandgap reference voltage circuit 20 can start a normal operation state.
[0088]
As described above, according to the voltage supply circuit of the present embodiment, the voltage supply circuit is configured using the activation circuit 10a and the band gap reference voltage circuit 20, and the band gap reference voltage circuit is generated by the activation circuit 10a when the circuit is activated. 20 node n2 has a starting current I_ST, The bandgap reference voltage circuit 20 is reliably started up, and after the bandgap reference voltage circuit 20 starts operating, the output signal voltage of the operational amplifier OPA1 starts to drop, and the output signal voltage reaches the starter circuit 10a. When a voltage sufficient to turn on the pMOS transistor PT1 is reached, the starting current I_STThe band gap reference voltage circuit 20 operates under the control of the feedback loop formed by the operational amplifier OPA1 and is a constant voltage V having no power supply voltage dependency and temperature dependency._OUTSupply.
[0089]
Second embodiment of band gap reference voltage circuit
FIG. 10 is a circuit diagram showing a second embodiment of the band gap reference voltage circuit.
As shown in the figure, the bandgap reference voltage circuit 20a of this embodiment includes an operational amplifier circuit OPA1, pMOS transistors T101 and T102, resistance elements R101 and R100, and diode-connected npn transistors B101 and B102.
[0090]
The transistor T101, the resistance element R101, and the diode-connected transistor B101 have a power supply voltage V_CCThe transistor B102, which is connected in series between the supply line and the node n4 and diode-connected to the transistor T102, is connected to the power supply voltage V_CCAre connected in series between the supply line and the node n4.
The gates of the transistors T101 and T102 are connected to the output terminal of the operational amplifier OPA1, and currents I1 and I2 are output according to the output signal of the operational amplifier OPA1, respectively.
[0091]
The non-inverting input terminal (+) of the operational amplifier OPA1 is connected to a node n1 that is a connection midpoint between the transistor T101 and the resistor element R101, and its inverting input terminal (−) is a connection midpoint between the transistor T102 and the transistor B102. Is connected to a node n2. Further, the output terminal of the band gap reference voltage circuit 20a is formed at the node n2, and the power supply voltage and the constant voltage V having no temperature dependence are output from the output terminal during normal operation._OUTIs output.
[0092]
The output signal of the operational amplifier OPA1 is applied to the gates of the transistors T101 and T102, respectively. For this reason, a feedback loop is formed by the operational amplifier OPA1, and the voltage V of the nodes n1 and n2 during normal operation is controlled by the control of the feedback loop._n1And V_n2Are controlled so that the output currents I1 and I2 of the transistors T101 and T102 are equal.
If the channel widths of the transistors T101 and T102 are set equal, the output currents I1 and I2 of these transistors are also equal.
The emitter size of the transistor B101 is 10 times the emitter size of the transistor B102.
[0093]
Compared to the bandgap reference voltage circuit 20 shown in FIG. 8, the bandgap reference voltage circuit 20a of this embodiment is omitted from the transistor T103, the resistor element R102, and the transistor B103, and is based on the connection point n2 between the transistors T102 and B102. Voltage V_OUTIs output. Further, the connection point between the emitters of the transistors B101 and B102 is grounded via the resistance element R100. Hereinafter, the operation of the bandgap reference voltage circuit 20a of the present embodiment will be described in comparison with FIG.
[0094]
In the band gap reference voltage circuit 20 of the first embodiment shown in FIG. 8, the voltages of the nodes n1 and n2 are respectively input to the operational amplifier circuit OPA1, and the output signal of the operational amplifier circuit OPA1 is the gates of the transistors T101, T102 and T103. Apply to. By this feedback control, the voltages V of the nodes n1 and n2_n1And V_n2Are controlled almost equally. For example, the voltage V of the nodes n1 and n2_n1And V_n2Is controlled to about 0.7V and the output voltage V_OUTIs held at about 1.25V. Therefore, in the transistors T101, T102, and T103 in which the same control voltage is applied to the gates, the source-drain voltage V of the transistors T101 and T102_dsAre equal to each other, but only the source-drain voltage of the transistor T103 is different.
[0095]
There is a slight difference ΔI in the current flowing through the transistors T101 (T102) and T103 due to the difference between the source-drain voltages. Power supply voltage V_CC, The source-drain voltages of the transistors T101, T102, and T103 change, so the current difference ΔI also changes and the output voltage V_OUTHas a slight power supply voltage dependency.
[0096]
Hereinafter, the output voltage V_OUTThe power supply voltage dependency will be described in more detail. MOS transistor current I_dsAnd source-drain voltage V_dsThe relationship shown in the following equation is established between
[0097]
[Expression 7]
I_ds= K (V_gs-V_th)²(1 + λV_ds)
... (7)
[0098]
In equation (7), V_gsIs the voltage between the gate and source of the MOS transistor, V_thIs a threshold voltage, k is a constant determined by the size of the transistor, and λ is I_dsV_dsIt is a proportionality constant that represents the dependence. In formula (7), I_dsV_dsAlthough the dependence on is approximated by a linear expression, strictly speaking, this approximate expression includes a second-order or higher-order term.
[0099]
In the ideal case where the currents of the transistors T101 and T103 are equal, the output voltage V_OUTCan be expressed as:
[0100]
[Equation 8]
V_OUT= V_BE3+ I_ThreeR₂
= V_BE3+ I₁R₂            (8)
[0101]
In equation (8), V_BE3Is the base-emitter voltage of transistor B103, I₁And I_ThreeAre the current values of currents I1 and I3, R₂Is the resistance element R₁₀₂Represents the resistance value. Actually, the current I_ThreeAnd I₁Since there is a difference ΔI, the output voltage V_OUTIs represented by the following equation.
[0102]
[Equation 9]
V_OUT= V_BE3+ I_ThreeR₂
= V_BE3+ (I₁+ ΔI) R₂
... (9)
[0103]
Since the difference current ΔI is dependent on the power supply voltage, the output voltage V_OUTAlso has power supply voltage dependency.
Further, in the band gap reference voltage circuit 20 shown in FIG. 8, the output currents I1 and I2 of the transistors T101 and T102 flow to the ground potential GND as they are, so that the current consumption increases.
[0104]
In the bandgap reference voltage circuit 20a of the second embodiment shown in FIG. 10, the voltages V at the nodes n1 and n2 are controlled by the operational amplifier circuit OPA1._n1And V_n2Are kept equal, so (V_n1-V_E= V_n2-V_E) Holds. Where V_EIs the voltage at node n4. As a result, the following equation is established.
[0105]
[Expression 10]
I₁R₁+ V_BE1= V_BE2            (10)
[0106]
Where I₁Is the current value of current I1, R₁Is the resistance value of the resistance element R101, V_BE1And V_BE2Represents the base-emitter voltages of the transistors B101 and B102, respectively. That is, the following formula is established.
[0107]
## EQU11 ##
V_BE1= V_Tln (I_C1/ I_S1(11)
[0108]
[Expression 12]
V_BE2= V_Tln (I_C2/ I_S2(12)
[0109]
Substituting Equations (11) and (12) into Equation (10),_c1= I₁, I_C2= I₂And the emitter size of the transistor B101 is 10 times that of the transistor B102, that is, I_S1= 10I_S2Using the condition, the following equation is obtained.
[0110]
[Formula 13]
I₁= V_T(Ln10) / R₁        ... (13)
[0111]
Here, the resistance value of the resistance element R100 is set to R_TenAnd Current I3 flowing through resistance element R100 is the sum of currents I1 and I2. That is, the current value of the current I3 is changed to I_ThreeThen I_Three= (I₁+ I₂) = 2I₁Is obtained. For this reason, the output voltage V_OUTIs obtained by the following equation.
[0112]
[Expression 14]
V_OUT= V_BE2+ I_ThreeR_Ten
= V_BE2+ 2V_T(Ln10) R_Ten/ R₁
... (14)
[0113]
Transistor base-emitter voltage V_BE2Has a negative temperature characteristic, for example, d (V_BE2) / DT = −2 mV / K. Therefore, by setting the temperature characteristic of the second term on the right side of Equation (14) to 2 mV / K, the output voltage V_OUTThe temperature dependence of can be completely eliminated. V_T= KT / q, so the output voltage V_OUTThe condition for eliminating the temperature dependence of is obtained by the following equation.
[0114]
[Expression 15]
2ln10 (R_Ten/ R₁) (k / q) = 2mV / K
... (15)
[0115]
When the resistance elements R100 and R101 satisfy the condition shown in the equation (15), the output voltage V_OUTDoes not depend on temperature change and always has a constant voltage value. In addition, when satisfy | filling Formula (15), when the temperature T is 300K (27 degreeC), the 2nd term | claim of the right side of Formula (14) is (2V_T(Ln10) R_Ten/ R₁) = 0.6V. Further, the base-emitter voltage V of the transistor B103_BE3Is 0.65V, the output voltage V of the bandgap reference voltage circuit 20 according to the equation (14)._OUTBecomes 1.25V.
[0116]
As described above, in the bandgap reference voltage circuit 20a of this embodiment, the constant output voltage V is not dependent on the temperature change._OUTIs obtained. Further, when operating normally, the drain potentials of the transistors T101 and T102 are controlled to be equal by feedback control of the operational amplifier circuit OPA1. That is, the drain-source voltage V of the transistors T101 and T102._dsAre controlled equally, the currents I1 and I2 flowing through these transistors are always set equal. For this reason, the output voltage V_OUTCan be suppressed.
[0117]
Third embodiment of band gap reference voltage circuit
FIG. 11 is a circuit diagram showing a third embodiment of the bandgap reference voltage circuit. As shown in the figure, the bandgap reference voltage circuit 20b of this embodiment includes transistor groups 22 and 24 including a plurality of pMOS transistors, an operational amplifier circuit OPA1, resistance elements R101 and R100, and diode-connected npn transistors B101 and B102. It is comprised by.
[0118]
As shown in the figure, the bandgap reference voltage circuit 20b of this embodiment has a plurality of MOS transistors connected in parallel instead of the MOS transistors T101 and T102, as compared with the bandgap reference voltage circuit 20a shown in FIG. Transistor groups 22 and 24 comprising transistors are provided. The transistor group 22 includes, for example, m (m is a natural number) pMOS transistors. These transistors have a power supply voltage V_CCAre connected in parallel between the supply line and the node n1. Almost the same, the transistor group 24 is composed of, for example, n (n is a natural number) pMOS transistors. These transistors have a power supply voltage V_CCAre connected in parallel between the supply line and the node n2.
[0119]
The gates of the transistors constituting the transistor groups 22 and 24 are connected to the output terminal of the operational amplifier circuit OPA1, that is, the node n3.
The other parts of the band gap reference voltage circuit 20b are substantially the same as those of the band gap reference voltage circuit 20a shown in FIG. For example, the non-inverting input terminal and the inverting input terminal of the operational amplifier circuit OPA1 are connected to the nodes n1 and n2, respectively. A resistor B101 and a diode-connected transistor B101 are connected in series between the node n1 and the node n4, and a diode-connected transistor B102 is connected between the node n2 and the node n4. Further, the node n4 is grounded via the resistance element R100.
[0120]
The sizes of the transistors constituting the transistor groups 22 and 24, for example, the channel widths are all set similarly. The emitter sizes of the transistors B101 and B102 are also set in the same manner.
[0121]
In the band gap reference voltage circuit 20b configured as described above, the output current of each transistor group can be controlled by appropriately setting the number of transistors in the transistor groups 22 and 24. For example, here, the number of transistors in the transistor group 22 is one, and the number of transistors in the transistor group 24 is ten. That is, assuming that m = 1 and n = 10, the current values I of the output currents I1 and I2 of the transistor groups 22 and 24₁And I₂Is 10I₁= I₂The relationship holds. Based on this, the current value I₁And I₂Is obtained as follows.
[0122]
The voltage V of the nodes n1 and n2 is controlled by the operational amplifier circuit OPA1._n1And V_n2Are held equally. That is, (V_n1-V_E= V_n2-V_E) Holds. For this reason, the above-described equations (10) to (12) are also established in the band gap reference voltage circuit 20b of the present embodiment. However, in this embodiment, since the emitter sizes of the transistors B101 and B102 are equal, I_S1= I_S2. On the other hand, I_c1= I₁, I_C2= I₂So I_C2= 10I_c1It becomes. Based on these conditions, the current I₁And I₂Are obtained by the following equations.
[0123]
[Expression 16]
I₁= V_T(Ln10) / R₁        ... (16)
[0124]
[Expression 17]
I₂= 10V_T(Ln10) / R₁    ... (17)
[0125]
That is, I₂= 10I₁It is. For this reason, the output voltage V_OUTIs obtained by the following equation.
[0126]
[Formula 18]
V_OUT= V_BE2+ I_ThreeR_Ten
= V_BE2+111₁R_Ten
= V_BE2+ 11V_T(Ln10) R_Ten/ R₁
... (18)
[0127]
In equation (18), V_BE2Has a negative temperature characteristic, for example, a temperature characteristic of -2 mV / K. On the other hand, V_THas a positive temperature characteristic, the resistance value R of the resistance elements R100 and R101_Ten, R₁By appropriately setting the output voltage V_OUTThe temperature dependence of can be negated. Further, as can be seen from equation (18), the output voltage V_OUTDoes not depend on the power supply voltage.
[0128]
As described above, the bandgap reference voltage circuit 20b according to the present embodiment enables a stable voltage V having no temperature dependency and no power supply voltage dependency._OUTCan be provided. Furthermore, the ratio of the current values of the currents I1 and I2 can be arbitrarily set by appropriately setting the number of transistors in the transistor groups 22 and 24, respectively. For this reason, for example, by setting the number n of transistors in the transistor group 24 to be large, the output current I2 of the transistor group 24 can be largely controlled. As shown in FIG. 11, the output current I supplied to the load circuit is increased by increasing the current I2._OUTFor example, when driving a capacitive load as shown in FIG._LThe charging current to the battery is large, and the rising characteristics of the load can be improved. Furthermore, as shown in the equation (18), the output voltage V_OUTSince the coefficient 11 is attached to the second term on the right side of the_TenCan be set small, and the layout area can be reduced.
[0129]
As described above, in the bandgap reference voltage circuit 20b of the present embodiment, by appropriately setting the number of transistors in the transistor groups 22 and 24 that are configured by a large number of transistors all having the same characteristics such as channel size, Output currents I1 and I2 from each transistor group can be controlled. Here, it goes without saying that the same effect can be achieved by appropriately setting the channel sizes of the respective transistors constituting the transistor group.
[0130]
Further, by setting the channel sizes of the transistors T101 and T102 of the band gap reference voltage circuit 20a of the second embodiment shown in FIG. 10, substantially the same effect as that of this embodiment using the transistor groups 22 and 24 can be obtained. . Further, in the above description, the emitter sizes of the diode-connected transistors B101 and B102 are assumed to be equal. However, the emitter sizes of these transistors are set to be different from each other. It can also be set to k times the emitter size. In this case, the output voltage V shown in Equation (18)_OUTLn (10) of the second term on the right side of ln becomes ln (10k). In this way, by appropriately setting the emitter sizes of the transistors B101 and B102, the output voltage V shown in Expression (18) is obtained._OUTThe coefficient of the second term on the right side of the resistance element R100 can be changed._TenIn some cases, the layout area can be reduced.
[0131]
Fourth embodiment of band gap reference voltage circuit
FIG. 12 is a circuit diagram showing a fourth embodiment of the band gap reference voltage circuit. As shown in the figure, the bandgap reference voltage circuit 20c of the present embodiment includes transistor groups 22 and 24 composed of a plurality of pMOS transistors, an operational amplifier circuit OPA1, resistance elements R101 and R100, and diode-connected npn transistors B101 and B102. It is comprised by.
[0132]
The band gap reference voltage circuit 20c of the present embodiment is almost the same as the band gap reference voltage circuit 20b of the third embodiment except that the resistor element R101 and the diode-connected transistor B101 are replaced with each other. . That is, in the bandgap reference voltage circuit 20b of the third embodiment, one terminal of the resistance element R101 is connected to the node n1, and the other terminal is connected to the collector and base of the transistor B101. On the other hand, in the band gap reference voltage circuit 20c of the present embodiment, the connection point between the base and collector of the transistor B101 is connected to the node n1, and the resistance element R101 is connected between the emitter of the transistor B101 and the node n4. Has been.
[0133]
The band gap reference voltage circuit 20c of the present embodiment is almost the same as that of the third embodiment except that the connection relationship described above is different from the band gap reference voltage circuit 20b of the third embodiment. Here, the number of transistors in the transistor groups 22 and 24 is m and n, respectively, and the output voltage V_OUTFind a more general formula for.
[0134]
It is assumed that the transistors constituting the transistor groups 22 and 24 have the same size, and the transistors B101 and B102 have the same size. That is, the current value I of the output currents I1 and I2 of the transistor groups 22 and 24.₁And I₂The following relationship is established.
[0135]
[Equation 19]
I₁/ M = I₂/ N
nI₁= MI₂                      ... (19)
[0136]
That is, I₂= (N / m) I₁. In transistors B101 and B102, I_c1= I₁, I_C2= I₂And I_S1= I_S2Therefore, according to the equations (10) to (12), the current I₁And I₂Are obtained by the following equations.
[0137]
[Expression 20]
I₁= V_T(Ln (n / m)) / R₁  ... (20)
[0138]
[Expression 21]
I₂= (N / m) V_T(Ln (n / m)) / R₁
... (21)
[0139]
Since the current I3 flowing through the resistance element R100 is an addition current of the currents I1 and I2, I_Three= I₁+ I₂= (M + n) I₁/ M. As a result, the output voltage V_OUTIs given by:
[0140]
[Expression 22]
V_OUT= V_BE2+ I_ThreeR_Ten
= V_BE2+ (M + n) V_T(Ln (n / m)) R_Ten/ (R₁m)
... (22)
[0141]
For example, in the band gap reference voltage circuit 20b of the third embodiment described above, when m = 1 and n = 10, the output voltage V_OUTIs V_OUT= V_BE2+ 11V_Tln (10) R_Ten/ R₁It is.
[0142]
Resistance value R of resistance elements R100 and R101_TenAnd R₁By appropriately setting the output voltage V_OUTThe temperature dependence of can be negated. Further, as can be seen from the equation (22), the output voltage V_OUTDoes not depend on the power supply voltage. Further, in the expression (22), the output voltage V_OUTSince the coefficient (m + n) / m is attached to the second term on the right side of, the resistance value R of the resistance element R100 can be determined by appropriately setting the number of transistors m and n._TenCan be set small, and the layout area can be reduced.
[0143]
In the above description, it is assumed that the emitter sizes of the diode-connected transistors B101 and B102 are equal. However, the emitter size ratio of the transistors B101 and B102 can be appropriately set. For example, when the emitter size of the transistor B101 is set to k times the emitter size of the transistor B102, ln (n / m) becomes ln (nk / m) in the second term on the right side of Expression (22). As a result, R_Ten/ R₁The coefficient attached to changes. That is, by appropriately setting the emitter size ratio of the transistors B101 and B102, the resistance value R of the resistance element R100_TenCan be reduced and the layout area can be reduced.
[0144]
Fifth embodiment of the band gap reference voltage circuit
FIG. 13 is a circuit diagram showing a fifth embodiment of the band gap reference voltage circuit 20.
As shown in the figure, the bandgap reference voltage circuit 20d of this embodiment is connected to transistor groups 22, 24, and 26 each consisting of a plurality of pMOS transistors, an operational amplifier circuit OPA1, resistance elements R101, R102, and R100, and a diode connection. The npn transistors B101, B102, and B103 are included.
[0145]
As shown in FIG. 11, in the bandgap reference voltage circuit 20d of the present embodiment, the portion constituted by the transistor groups 22 and 24, the operational amplifier circuit OPA1, the transistors B101 and B102, and the resistance elements R101 and R100 is shown in FIG. The band gap reference voltage circuit 20b of the third embodiment has almost the same configuration. That is, this embodiment can be regarded as a transistor group 26, a transistor B103, and a resistance element R102 added to the band gap reference voltage circuit 20b of the third embodiment.
[0146]
The transistor group 26 includes a plurality of, for example, j (j is a natural number) pMOS transistors. These transistors have a power supply voltage V_CCAre connected in parallel between the supply line and the node n5, and each gate is connected to the output terminal of the operational amplifier circuit OPA1, that is, the node n3. A diode-connected transistor B103 and a resistance element R102 are connected in series between the node n5 and the ground potential GND. Note that there is no particular limitation on the connection order of the transistor B103 and the resistor element R102.
[0147]
Here, it is assumed that the channel sizes of the transistors constituting the transistor groups 22, 24, and 26 are the same, and the emitter sizes of the diode-connected transistors B101, B102, and B103 are also equal. Assuming that the number of transistors in the transistor groups 22 and 24 is m and n, respectively, equations (20) and (21) are established, as in the band gap reference voltage circuit 20c of the fourth embodiment described above.
[0148]
Further, in this embodiment, the current value of the output current I4 of the transistor group 26 is expressed as I_FourAnd the resistance value of the resistance element R102 is R₂And As described above, since the number of transistors constituting the transistor group 26 is j, I_Four/ I₁= J / m holds. Based on this condition, the output voltage V_OUTIs given by:
[0149]
[Expression 23]
V_OUT= V_BE3+ I_FourR₂
= V_BE3+ JV_T(Ln (n / m)) R₂/ (R₁m)
... (23)
[0150]
In formula (23), V_BE3Has a negative temperature characteristic, for example, a temperature characteristic of -2 mV / K. On the other hand, V_THas a positive temperature characteristic, the resistance value R of the resistance elements R102 and R101₂, R₁By appropriately setting the output voltage V_OUTThe temperature dependence of can be negated. Further, as can be seen from equation (23), the output voltage V_OUTDoes not depend on the power supply voltage.
[0151]
As described above, the bandgap reference voltage circuit 20d of the present embodiment has no temperature dependency and no power supply voltage dependency, and a stable voltage V_OUTCan be provided. Output voltage V_OUTIs provided independently of the voltage-controlled feedback loop, so that no load is applied to the feedback loop. For this reason, the stable output voltage V is not affected by the characteristics of the load circuit._OUTCan supply.
[0152]
In each of the embodiments described above, the voltage supply circuit constituted by the start circuit of the present invention and the band gap reference voltage circuit has been described as an example. However, the start circuit of the present invention is not limited to the band gap reference voltage circuit. Needless to say, the present invention can be applied to other functional circuits. For example, the start-up circuit of the present invention can be applied to a case where a start-up current is supplied to a voltage controlled oscillation circuit (VCO) or the like at the time of start-up in the PLL circuit to start up the VCO.
[0153]
【The invention's effect】
As described above, according to the starter circuit of the present invention and the voltage supply circuit configured using the starter circuit, the circuit configuration is simple, the design is easy, the application range is wide, and it is resistant to variations in the manufacturing process. A voltage supply circuit having no dependency and no power supply voltage dependency can be realized.
In addition, the starting circuit of the present invention generates a constant voltage, for example, confirms the operating state of the bandgap reference voltage circuit, and controls the supply timing of the starting current accordingly. Depending on the operating conditions, it is possible to supply only the startup current required to start the circuit, the circuit startup time can be set appropriately, and the power consumption of the startup circuit can be minimized. is there.
Furthermore, in the band gap reference voltage circuit constituting the voltage supply circuit of the present invention, a stable voltage having no temperature dependency and no power supply voltage dependency can be supplied, low voltage operation can be realized, and low power consumption can be realized. . Also, by appropriately setting the number of transistors in the transistor group constituting the band gap reference voltage circuit and the emitter size of the diode-connected bipolar transistor, the resistance value of the resistance element can be freely changed, and the layout area can be reduced. In addition, the output current value can be arbitrarily set, and the output rising characteristic can be improved. In addition, by providing the voltage output circuit independently from the feedback control loop, it is possible to avoid the influence of the load characteristics on the feedback loop and to improve the stability of the operation of the voltage supply circuit without being affected by fluctuations in the load. There is.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a first embodiment of a start-up circuit according to the present invention.
FIG. 2 is a circuit diagram showing a second embodiment of a start-up circuit according to the present invention.
FIG. 3 is a circuit diagram showing a third embodiment of a start-up circuit according to the present invention.
FIG. 4 is a circuit diagram showing a fourth embodiment of a start-up circuit according to the present invention.
FIG. 5 is a circuit diagram showing a fifth embodiment of a start-up circuit according to the present invention.
FIG. 6 is a circuit diagram illustrating a configuration example of a delay circuit.
FIG. 7 is a circuit diagram of a voltage supply circuit configured by a starter circuit and a bandgap reference voltage circuit.
FIG. 8 is a circuit diagram showing a first embodiment of a bandgap reference voltage circuit;
9 is a timing chart of the voltage supply circuit shown in FIG.
FIG. 10 is a circuit diagram showing a second embodiment of the bandgap reference voltage circuit;
FIG. 11 is a circuit diagram showing a third embodiment of the bandgap reference voltage circuit;
FIG. 12 is a circuit diagram showing a fourth embodiment of the bandgap reference voltage circuit;
FIG. 13 is a circuit diagram showing a fifth embodiment of the bandgap reference voltage circuit;
FIG. 14 is a circuit diagram showing an example of a conventional voltage supply circuit.
[Explanation of symbols]
10, 10a, 10b, 10c, 10d, 10e ... start-up circuit, 20, 20a, 20b, 20c, 20d ... band gap reference voltage circuit, 22, 24, 26 ... transistor group, PT1, PT2, PT3, T101, T102, T103... PMOS transistor, NT1, NT2, NT3... NMOS transistor, B101, B102, B103... Npn transistor, NA1... NAND gate, INV1, INV2, INV3, INV4. , R102... Resistance element, V_CC... power supply voltage, GND ... ground potential.

Claims (19)

A startup circuit that supplies a startup current to a predetermined functional circuit to start the functional circuit,
A starting current supplying means for receiving the starting signal and supplying the starting current to the functional circuit;
The activation signal is used as a first input signal, the voltage of a predetermined operation node of the functional circuit is received as a second input signal, and the first and second input signals according to the levels of the first and second input signals . A bistable logic circuit controlled to a state of the logic circuit, and a logic gate that outputs a signal corresponding to a logical operation result of the first signal and the output signal of the bistable logic circuit, has but to supply the starting current to the starting current supply means when the first level, and a start control means for stopping the supply of the starting current to the starting current supply means when the second level after the current supply Start-up circuit. The bistable logic circuit includes first and second transistors connected in series between a supply terminal for a predetermined voltage and a reference potential line,
A voltage of the operation node of the functional circuit is applied to a gate of the first transistor;
The start circuit according to claim 1, wherein the start signal is applied to a gate of the second transistor. 2. The start-up according to claim 1, wherein the start-up current supply means includes a switching circuit connected between a power supply voltage supply line and a start-up current input terminal in the functional circuit and turned on / off according to an output signal of the logic gate. circuit. The start-up circuit according to claim 3, wherein the switching circuit is configured by a transistor having an output signal of the logic gate applied to a control terminal. The starter circuit according to claim 1, further comprising a delay circuit that inputs a delay signal obtained by delaying an output signal of the bistable logic circuit by a predetermined time to the logic gate. The startup circuit according to claim 5, wherein the delay circuit includes an even number of inverters connected in series. The delay circuit includes a resistance element connected between an input terminal and an output terminal;
The starter circuit according to claim 5, further comprising a capacitor connected between the output terminal and a reference potential line. The functional circuit includes a first current supply transistor connected between the power supply voltage supply line and the first node;
A first resistance element connected in series between the first node and a reference potential line; and a first diode forwardly directed toward the reference potential line;
A second current supply transistor connected between the power supply voltage supply line and a second node;
A second diode connected between the second node and the reference potential line and directed in the forward direction toward the reference potential line;
A third current supply transistor connected between the power supply voltage supply line and a third node;
A second resistance element connected in series between the third node and the reference potential line; and a third diode forwardly directed toward the reference potential line;
The first input terminal is connected to the first node, the second input terminal is connected to the second node, and a voltage corresponding to a difference between signals input to the first and second input terminals An amplifier circuit for applying a signal to the control terminals of the first, second and third current supply transistors;
The startup current from the startup circuit is supplied to the second node at startup,
The starter circuit according to claim 1, wherein the output voltage of the amplifier circuit is input to the starter control means as a voltage of the operation node. The starting circuit according to claim 8, wherein the current supply transistor is configured by a field effect transistor. The functional circuit includes a first current supply transistor connected between the power supply voltage supply line and the first node;
A first resistance element connected in series between the first node and the third node, and a first diode forwardly directed toward the third node;
A second current supply transistor connected between the power supply voltage supply line and a second node;
A second diode connected between the second node and the third node and directed forward toward the third node;
A second resistance element connected between the third node and a reference potential line;
The first input terminal is connected to the first node, the second input terminal is connected to the second node, and a voltage corresponding to a difference between signals input to the first and second input terminals An amplifier circuit for applying a signal to the control terminals of the first and second current supply transistors;
The startup current from the startup circuit is supplied to the second node at startup,
The starter circuit according to claim 1, wherein the output voltage of the amplifier circuit is input to the starter control means as a voltage of the operation node. The functional circuit includes a first transistor group including m (m is a natural number) current supply transistors connected in parallel between a power supply voltage supply line and a first node;
A first resistance element connected in series between the first node and the third node, and a first diode forwardly directed toward the third node;
A second transistor group consisting of n (n is a natural number) current supply transistors connected in parallel between the power supply voltage supply line and the second node;
A second diode connected between the second node and the third node and directed forward toward the third node;
A second resistance element connected between the third node and a reference potential line;
The first input terminal is connected to the first node, the second input terminal is connected to the second node, and a voltage corresponding to a difference between signals input to the first and second input terminals An amplifier circuit for applying a signal to the control terminal of each transistor of the first and second transistor groups;
The startup current from the startup circuit is supplied to the second node at startup,
The starter circuit according to claim 1, wherein the output voltage of the amplifier circuit is input to the starter control means as a voltage of the operation node. The functional circuit includes a first transistor group including m (m is a natural number) current supply transistors connected in parallel between a power supply voltage supply line and a first node;
A first resistance element connected in series between the first node and the third node, and a first diode forwardly directed toward the third node;
A second transistor group consisting of n (n is a natural number) current supply transistors connected in parallel between the power supply voltage supply line and the second node;
A second diode connected between the second node and the third node and directed forward toward the third node;
A second resistance element connected between the third node and a reference potential line;
A third transistor group consisting of j (j is a natural number) current supply transistors connected in parallel between the power supply voltage supply line and the fourth node;
A third resistance element connected in series between the fourth node and the reference potential line; and a third diode forwardly directed toward the reference potential line;
The first input terminal is connected to the first node, the second input terminal is connected to the second node, and a voltage corresponding to a difference between signals input to the first and second input terminals An amplifier circuit for applying a signal to the control terminal of each transistor of the first, second and third transistor groups;
The startup current from the startup circuit is supplied to the second node at startup,
The starter circuit according to claim 1, wherein the output voltage of the amplifier circuit is input to the starter control means as a voltage of the operation node. A starting current supply means for receiving a starting signal and outputting a starting current;
A voltage generating circuit that starts upon receiving the above starting current and outputs a stable voltage during normal operation;
The activation signal is received as a first input signal, the voltage at a predetermined operation node of the voltage generation circuit is received as a second input signal, and the first and second input signals are received according to the levels of the first and second input signals . A bistable logic circuit controlled to a state of 2, and a logic gate that outputs a signal corresponding to a logical operation result of the first signal and the output signal of the bistable logic circuit, and the output of the logic gate A startup control means for causing the startup current supply means to supply a startup current when the signal is at a first level, and for causing the startup current supply means to stop supplying the startup current when the signal is at a second level after the current supply; Having a voltage supply circuit. A first current supply transistor connected between the power supply voltage supply line and the first node;
A first resistance element connected in series between the first node and a reference potential line; and a first diode forwardly directed toward the reference potential line;
A second current supply transistor connected between the power supply voltage supply line and a second node;
A second diode connected between the second node and the reference potential line and directed in the forward direction toward the reference potential line;
A third current supply transistor connected between the power supply voltage supply line and a third node;
A second resistance element connected in series between the third node and the reference potential line; and a third diode forwardly directed toward the reference potential line;
The first input terminal is connected to the first node, the second input terminal is connected to the second node, and a voltage corresponding to a difference between signals input to the first and second input terminals An amplifier circuit for applying a signal to the control terminals of the first, second and third current supply transistors;
Start-up current supply means for supplying a start-up current to the second node in response to a start-up signal at start-up;
When the output voltage of the amplifier circuit reaches a predetermined reference value, it possesses a start control means for stopping the supply of the starting current,
The activation control means includes
The activation signal is received as a first input signal, the output signal of the amplifier circuit is received as a second input signal, and the first and second states are controlled according to the levels of the first and second input signals. A bistable logic circuit ,
A logic gate for outputting a signal corresponding to a logical operation result of the start signal and the output signal of the bistable logic circuit;
When the output signal of the logic gate is at the first level, the startup current supply means is supplied with the startup current, and when the output signal is at the second level after the current supply, the startup current supply means is supplied with the startup current. A voltage supply circuit that stops supply. The bistable logic circuit includes first and second transistors connected in series between a power supply voltage supply line and a reference potential line,
The output voltage of the amplifier circuit is applied to the gate of the first transistor;
The voltage supply circuit according to claim 14, wherein the activation signal is applied to a gate of the second transistor. The voltage supply according to claim 14, wherein the starting current supply means includes a switching circuit connected between a supply terminal of a predetermined voltage and the second node, and turned on / off in accordance with an output signal of the logic gate. circuit. The voltage supply circuit according to claim 16 , wherein the switching circuit is configured by a transistor having an output signal of the logic gate applied to a control terminal. The voltage supply circuit according to claim 14, wherein the current supply transistor includes a field effect transistor. The voltage supply circuit according to claim 14, further comprising a delay circuit that inputs a delay signal obtained by delaying an output signal of the bistable logic circuit by a predetermined time to the logic gate.

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