JP2008015779A - Constant current source circuit and power source circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make it possible to have excellent tolerance to a change in a power source voltage and reduce start-up time. <P>SOLUTION: A constant current source circuit comprises a constant current generation circuit 12 for generating a constant current Iconst according to a current that flows through a control node n<SB>1</SB>, a capacitor C<SB>1</SB>that is connected between a power source VDD and the control node n<SB>1</SB>and stabilizes the constant current Iconst against a change in a power source voltage, a capacitor charging circuit 13 that charges the capacitor C<SB>1</SB>by forcibly applying a current to it, and a control circuit 14 for operating the capacitor charging circuit 13 in the period from the power-on until a predetermined condition is met. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a constant current source circuit capable of stably outputting an output current against fluctuations in a power supply voltage, and a power supply circuit including the constant current source circuit.

As a constant current source circuit, as shown in FIG. 6, a constant current generating circuit 12 that generates a constant current Iconst, a startup circuit 11 that starts the constant current generating circuit 12 when power is turned on, and a constant current source circuit with respect to fluctuations in power supply voltage. There is known a constant current source circuit including a capacitor C ₁ for stabilizing the current Iconst.

The constant current generating circuit 12 generates a constant current Iconst according to the current flowing through the control node n ₁ . The startup circuit 11 activates the constant current generation circuit 12 by passing a current through the control node n ₁ when the power is turned on. Capacitor C ₁ is connected between power supply VDD and control node n ₁ .

In the state where the capacitor C ₁ is charged, even if the power supply voltage fluctuates, the capacitor C ₁ functions to keep the potential of the control node n ₁ constant, so even if the power supply voltage fluctuates, the constant current Iconst Can be supplied stably.
JP 2006-50437 A

However, when the power supply voltage is turned on, it takes a certain time to charge the capacitor C _1. Until the capacitor C ₁ is charged, the potential of the control node n ₁ is not stable, so that the startup time until the constant current Iconst is generated increases.

  In view of the above problems, an object of the present invention is to provide a constant current source circuit and a power supply circuit that have good resistance to fluctuations in the power supply voltage and can shorten the startup time.

  In order to achieve the above object, a first feature of the present invention is that a constant current generating circuit that generates a constant current according to a current flowing through the control node is connected between the power supply and the control node, and the power supply voltage A capacitor that stabilizes the constant current against fluctuations of the capacitor, a capacitor charging circuit that charges the capacitor by forcibly passing a current through the capacitor, and a capacitor charging circuit during a period from when the power is turned on until a predetermined condition is satisfied The gist of the present invention is that it is a constant current source circuit including a control circuit for operating the circuit.

  According to this feature, a capacitor that stabilizes a constant current against fluctuations in the power supply voltage, a capacitor charging circuit that charges the capacitor by forcibly passing a current through the capacitor, and a predetermined condition is established from the rise of the power supply voltage In this period, the control circuit for operating the capacitor charging circuit is provided, so that the capacitor can be charged rapidly when the power is turned on. Therefore, it is possible to provide a constant current source circuit that has good resistance to fluctuations in the power supply voltage and can shorten the startup time. In addition, after a predetermined condition is established from the rise of the power supply voltage, the operation of forcibly passing a current through the capacitor is stopped, so that an increase in current consumption can be avoided.

  The second feature is that, in the constant current source circuit according to the first feature, the control circuit operates the capacitor charging circuit in a period until the power supply voltage exceeds the reference voltage.

  According to this feature, the control circuit operates the capacitor charging circuit during the period until the power supply voltage exceeds the reference voltage, and the current is forced to flow through the capacitor only during the period until the power supply voltage exceeds the reference voltage. Thus, an increase in current consumption can be avoided.

  According to a third feature, in the constant current source circuit according to the first or second feature, the start-up circuit further includes a start-up circuit that starts the constant-current generating circuit by causing a current to flow through the control node when the power supply voltage rises. Includes a first resistor having one end grounded, a start-up transistor having a collector connected to the power source, a base connected to the control node, and an emitter connected to the other end of the first resistor. A second resistor having one end connected to the control node, a charging transistor having a drain connected to the other end of the second resistor, a gate connected to the control circuit, and a source grounded. The gist is that the value is larger than the resistance value of the second resistor.

  According to this feature, since the resistance value of the first resistor for flowing current to the control node is larger than the resistance value of the second resistor for forcing current to flow to the capacitor, the current flowing to the control node is small. The amount of current forcibly flowing through the capacitor can be made large while maintaining the amount, so that the consumption current can be reduced and the capacitor can be charged rapidly.

  The fourth feature is summarized as a power supply circuit including the constant current source circuit according to any one of the first to third features.

  According to this feature, the constant current source circuit has good resistance to fluctuations in the power supply voltage and can shorten the start-up time, so it has good resistance to fluctuations in the power supply voltage and is stable. Thus, it is possible to provide a power supply circuit that can shorten the time required until the output voltage is generated.

  According to the present invention, it is possible to provide a constant current source circuit and a power supply circuit that have good resistance to fluctuations in the power supply voltage and can shorten the startup time.

  Next, an embodiment of the present invention will be described with reference to the drawings. In the description of the drawings in the following embodiments, the same or similar parts are denoted by the same or similar reference numerals.

(Constant current source circuit)
As shown in FIG. 1, the constant current source circuit 1 according to the present embodiment includes a capacitor C ₁ , a startup circuit 11, a constant current generation circuit 12, a capacitor charging circuit 13, and a control circuit 14. The constant current generation circuit 12 generates a constant current Iconst according to the current flowing through the control node n ₁ . The capacitor C ₁ is connected between the power supply VDD and the control node n ₁ and stabilizes the constant current Iconst against fluctuations in the power supply voltage. The capacitor charging circuit 13 charges the capacitor C ₁ by forcing a current to flow through the capacitor C ₁ . The control circuit 14 operates the capacitor charging circuit 13 during a period until the power supply voltage exceeds the reference voltage Vref. The startup circuit 11 starts up the constant current generation circuit 12 by passing a current through the control node n ₁ when the power supply voltage rises.

Thus, the constant current source circuit 1 has a configuration capable of rapidly charging the capacitor C ₁ when the power is turned on. Even if the power supply voltage fluctuates due to the electric charge charged in the capacitor C ₁ , the constant current Iconst is maintained. For example, as shown in FIG. 2 (a), to increase the power supply voltage at time t1, when reduced at time t2, if not provided with the capacitor C _1, as shown in FIG. 2 (b), the power supply The constant current Iconst changes due to voltage fluctuation. On the other hand, when the capacitor C ₁ is provided, as shown in FIG. 2B, the amount of change in the constant current Iconst is small due to fluctuations in the power supply voltage.

The start-up circuit 11 includes a resistor R ₁ and an npn-type bipolar transistor (hereinafter “npn transistor”) Q ₁ . One end of the resistor R ₁ is connected to the ground. The npn transistor Q ₁ has a collector connected to the power supply VDD, a base connected to the control node n ₁ , and an emitter connected to the other end of the resistor R ₁ .

The constant current generating circuit 12 includes resistors R ₅ , R ₆ , R ₇ , pnp bipolar transistors (hereinafter “pnp transistors”) Q ₂ , Q ₃ , Q ₆ , and npn transistors Q ₄ , Q ₅ . Prepare. Note that a plurality of resistors R ₆ , pnp transistors Q ₃ , npn transistors Q ₅ , and resistors R ₇ are provided. However, for convenience of explanation, it is assumed that the number of each is one.

One end of each of the resistors R ₅ and R ₆ is connected to the power supply VDD. One end of the resistor R ₇ is connected to ground. The npn transistors Q ₄ and Q ₅ constitute a current mirror circuit. That is, the bases of npn transistors Q ₄ and Q ₅ are connected in common, and the base of npn transistor Q ₄ is connected to its own collector. The emitter of npn transistor Q ₄ is grounded, and the emitter of npn transistor Q ₅ is connected to the other end of resistor R ₇ . As a result, the collector current of npn transistor Q ₅ is determined according to the mirror ratio from the collector current of npn transistor Q ₄ .

The pnp transistor Q ₂ has an emitter connected to the other end of the resistor R ₅ , a base connected to the control node n ₁ , and a collector connected to the collector and base of the npn transistor Q ₄ . The pnp transistor Q ₃ has an emitter connected to the other end of the resistor R ₆ , a base connected to the control node n ₁ , and an npn transistor Q ₅ and a collector connected in common. The collector of the pnp transistor Q ₃ is connected to its own base.

Further, the output stage pnp transistor Q ₆ has an emitter connected to the power supply VDD and a base connected to the control node n ₁ . The collector current of the pnp transistor Q ₆ is used as a constant current Iconst.

The capacitor charging circuit 13 includes a resistor R ₂ and an n-channel MOS transistor (hereinafter “nMOS transistor”) Tr ₁ . One end of the resistor R ₂ is connected to the control node n ₁ . In the nMOS transistor Tr ₁ , the drain is connected to the other end of the resistor R ₂ , the gate is connected to the control circuit 14, and the source and back gate are grounded.

Here, the resistance value of the resistor R ₁ of the start-up circuit 11 is larger than the resistance value of the resistor R ₂ of the capacitor charging circuit 13. The resistance value of the resistor R ₁ for supplying a current to the control node n ₁ is, is greater than the resistance value of the resistor R ₂ for supplying a forced current to the capacitor C _1, current applied to the control node n ₁ is small The amount of current forcibly flowing through the capacitor is set to a large value.

The control circuit 14 includes resistors R ₃ and R ₄ and a comparator 141. The resistors R ₃ and R ₄ are connected in series between the power supply VDD and the ground. The comparator 141 has a non-inverting input (−) connected to a connection point between the resistors R ₃ and R ₄ , and a reference voltage Vref is applied to the inverting input (+). The output of the comparator 141 is connected to the gate of the nMOS transistor Tr ₁ of the capacitor charging circuit 13.

The comparator 141 compares the reference voltage Vref with the voltage obtained by dividing the power supply voltage by the resistors R ₃ and R ₄ . The comparator 141 outputs a high level signal when the reference voltage is larger than the voltage obtained by dividing the voltage, and outputs a low level signal when the voltage obtained by dividing the voltage is larger than the reference voltage Vref. To do.

Therefore, the nMOS transistor Tr ₁ is kept on until the power supply voltage becomes a constant value, and when the power supply voltage becomes a constant value, the nMOS transistor Tr ₁ is turned off. During the period in which the nMOS transistor Tr ₁ is kept on, a current flows from the power supply VDD to the ground via the capacitor C ₁ , the resistor R ₂ , and the nMOS transistor Tr ₁ , and the capacitor C ₁ is rapidly charged. The

  The operation of the constant current source circuit 1 will be described below.

First, when the power supply voltage is turned on, a current path from the power supply VDD to the ground via the resistor R ₅ , the pnp transistor Q ₂ , the npn transistor Q ₁ , the resistor R ₁ , and the power supply VDD to the resistors R ₆ , pnp Current flows through the transistor Q ₃ , the npn transistor Q ₁ , and the current path that reaches the ground via the resistor R ₁ .

Further, since the nMOS transistor Tr ₁ is in the ON state, a current flows from the power supply VDD to the ground via the capacitor C ₁ , the resistor R ₂ , and the nMOS transistor Tr ₁ , and the capacitor C ₁ is rapidly charged. When the power supply voltage becomes a constant value, the nMOS transistor Tr ₁ is turned off.

In the constant current generation circuit 12, a current flows from the power supply VDD toward the ground through the resistor R ₅ , the pnp transistor Q ₂ , and the npn transistor Q ₄ . Therefore, a current corresponding to the mirror ratio flows from the power supply VDD to the ground via the resistor R ₆ , the pnp transistor Q ₃ , the npn transistor Q ₅ , and the resistor R ₇ . Therefore, since the current flowing through the control node n ₁ (base current of the pnp transistor Q ₆ ) is kept constant, the constant current Iconst is kept constant.

(Power circuit)
The constant current source circuit 1 described above is provided, for example, inside a power supply circuit as shown in FIG. The power supply circuit shown in FIG. 3 includes a reference voltage generation circuit (BGR; Band Gap Reference) 15, a reference voltage detection circuit 201, and an LDO (Low Dropout) regulator circuit in addition to the constant current source circuit 1 shown in FIG. 23, an output detection circuit 202, and a start control circuit 203, and an output transistor Tr _4. A p-channel type power MOS transistor is used as the output transistor Tr ₄ . The control circuit 14 shown in FIG. 1 is incorporated in the reference voltage generation circuit 15. That is, the output signal of the comparator 141 shown in FIG. 1 corresponds to the activation signal STR shown in FIG.

The activation control circuit 203 forcibly turns on the output transistor Tr ₄ when an enable signal EN is input from the outside. When the output transistor Tr ₄ is turned on, the output voltage Vout is supplied to the load 25 via the output terminal 24. The output voltage Vout is supplied to the constant current source circuit 1 as a power supply voltage for the constant current source circuit 1.

  The output detection circuit 202 detects the output voltage Vout and supplies the detection result to the LDO regulator circuit 23 as the detection voltage Vdet.

The reference voltage generation circuit 15 generates the reference voltage Vref according to the constant current Iconst from the constant current source circuit 1. LDO regulator circuit 23 outputs a voltage V _LDO corresponding to the difference between the reference voltage Vref and the detection voltage Vdet.

The reference voltage detection circuit 201 detects the reference voltage Vref generated by the reference voltage generation circuit 15. Further, the reference voltage detection circuit 201 stops the operation of the activation control circuit 203 when detecting the reference voltage Vref. When the operation of the start control circuit 203 is stopped, the output transistor Tr ₄ is controlled by the output voltage V _LDO of the LDO regulator circuit 23.

  Next, the configuration of the reference voltage detection circuit 201, the output detection circuit 202, and the activation control circuit 203 will be described in detail.

The reference voltage detection circuit 201 includes resistors R ₈ and R ₉ , a comparator 21, and an inverter 22. The resistors R ₈ and R ₉ are connected in series between the power supply VDD and the ground. The comparator 21 has a non-inverting input (+) connected to the connection point between the resistors R ₈ and R ₉ and a reference voltage Vref applied to the inverting input (−). The output of the comparator 21 is connected to the input of the inverter 22. The comparator 21 is activated by the activation signal STR generated by the reference voltage generation circuit 15.

The output detection circuit 202 includes resistors R ₁₀ and R ₁₁ . The resistors R ₁₀ and R ₁₁ are connected in series between the output terminal 24 and the ground. The connection point between the resistors R ₁₀ and R ₁₁ is connected to the inverting input (−) of the LDO regulator circuit 23.

The activation control circuit 203 includes nMOS transistors Tr ₂ and Tr ₃ . The nMOS transistor Tr ₂ has a drain connected to the gate of the output transistor Tr ₄ and the output of the LDO regulator circuit 23, and a gate connected to the output of the inverter 22. In the nMOS transistor Tr ₃ , the drain is connected to the source of the nMOS transistor Tr ₂ , the enable signal EN is input to the gate, and the source is grounded.

  The operation of the power supply circuit shown in FIG. 3 will be described below.

First, when an enable signal EN is input from the outside, the nMOS transistor Tr ₃ is turned on. At this time, the comparator 21 outputs a low level signal, and the inverter 22 outputs a high level signal. Therefore, since both the nMOS transistors Tr ₂ and Tr ₃ are in the on state and the gate of the output transistor Tr ₄ is at the low level, the output transistor Tr ₄ is turned on.

When the output transistor Tr ₄ is turned on, the output voltage Vout is supplied from the power supply VDD to the load 25 via the output terminal 24. The output voltage Vout is supplied to the constant current source circuit 1 as a power supply voltage.

  When the power supply voltage is supplied to the constant current source circuit 1, the constant current source circuit 1 generates the constant current Iconst as described above. The constant current source circuit 1 is activated in a shorter time than the conventional constant current source circuit by the operation of the capacitor charging circuit 13, as shown in FIG.

  When the constant current Iconst is generated, the reference voltage generation circuit 15 stops the operation of the capacitor charging circuit 13 and starts the comparator 21 using the start signal STR. The reference voltage generation circuit 15 generates a reference voltage Vref based on the constant current Iconst. The reference voltage Vref is applied to the inverting input (−) of the comparator 21 and the non-inverting input (+) of the LDO regulator circuit 23.

When the reference voltage Vref becomes larger than the voltage obtained by dividing the power supply voltage by the resistors R ₈ and R ₉ , the output signal of the comparator 21 is switched from the low level to the high level. When the output signal of the comparator 21 is switched from the low level to the high level, the output signal of the inverter 22 becomes the low level, and the nMOS transistor Tr ₂ is turned off. Further, the LDO regulator circuit 23 is activated.

As shown in FIG. 5, the LDO regulator circuit 23 outputs a voltage V _LDO corresponding to the difference between the reference voltage Vref and the detection voltage Vdet so as to keep the output voltage Vout constant.

(Function and effect)
According to the present embodiment, the capacitor C ₁ that stabilizes a constant current against fluctuations in the power supply voltage, the capacitor charging circuit 13 that charges the capacitor C ₁ by forcibly passing a current through the capacitor C ₁ , and the power supply voltage There only during the period to over the reference voltage Vref, since a control circuit 14 for controlling the capacitor charging circuit 13 to flow to force the current to the capacitor C _1, rapidly charging the capacitor C ₁ at power-on Can do. For this reason, it is possible to provide the constant current source circuit 1 that has good resistance to fluctuations in the power supply voltage and can shorten the startup time.

Further, in this embodiment, the resistance value of the resistor R ₁ for flowing current to the control node n ₁ is larger than the resistance value of the resistor R ₂ for forcing current to flow to the capacitor C _1. While the current flowing through n ₁ can be made small, the current forcibly flowing through capacitor C ₁ can be made large, so that an increase in current consumption can be suppressed and capacitor C ₁ can be charged quickly. .

  Furthermore, in the power supply circuit according to the present embodiment, the constant current source circuit 1 has good resistance to fluctuations in the power supply voltage and can shorten the startup time. It is possible to provide a power supply circuit that has high tolerance and can reduce the time required to generate a stable output voltage.

(Other embodiments)
As mentioned above, although this invention was described by embodiment, it should not be understood that the description and drawing which form a part of this indication limit this invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

In the above-described embodiment, an example has been described in which the control circuit 14 operates the capacitor charging circuit 13 during a period until the power supply voltage exceeds the reference voltage Vref. However, the control circuit 14 may include a timer or the like, measure a certain period from the time of power-on, and operate the capacitor charging circuit 13 until the certain time elapses.

Further, although an example in which a bipolar transistor is used as the transistor used in the startup circuit 11 and the constant current generating circuit 12 has been described, a field effect transistor such as a MOS transistor may be used instead of the bipolar transistor. Absent.

  Furthermore, each of the constant current source circuit 1 shown in FIG. 1 and the power supply circuit shown in FIG. 3 can be monolithically integrated on the same semiconductor chip and configured as a semiconductor integrated circuit.

  Thus, it should be understood that the present invention includes various embodiments and the like not described herein. Therefore, the present invention is limited only by the invention specifying matters in the scope of claims reasonable from this disclosure.

It is a circuit diagram which shows the structural example of the constant current source circuit which concerns on embodiment of this invention. It is a wave form diagram for demonstrating the operation | movement at the time of the power supply fluctuation | variation in the constant current source circuit which concerns on embodiment of this invention. It is a circuit diagram which shows the structural example of the power supply circuit which concerns on embodiment of this invention. It is a wave form diagram for demonstrating operation | movement of the constant current source circuit which concerns on embodiment of this invention. It is a wave form diagram for demonstrating operation | movement of the power supply circuit which concerns on embodiment of this invention. It is a block diagram which shows the structure of the constant current source circuit which concerns on the background art of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Constant current source circuit 11 ... Start-up circuit 12 ... Constant current generation circuit 13 ... Capacitor charging circuit 14 ... Control circuit 15 ... Reference voltage generation circuit 21 ... Comparator 22 ... Inverter 23 ... LDO regulator circuit 24 ... Output terminal 25 ... Load 141 ... comparator 201 ... reference voltage detection circuit 202 ... output-detection circuit 203 ... starting control circuit C ₁ ... capacitors _{Q 1, Q 4, Q 5} ... npn transistors _{Q 2, Q 3, Q 6} ... pnp transistor R ₁ to R ₁₁ ... Resistor n ₁ ... Control node Tr _{1 to} Tr ₃ ... nMOS transistor Tr ₄ ... Output transistor

Claims (4)

A constant current generating circuit for generating a constant current according to the current flowing through the control node;
A capacitor connected between a power supply and the control node and stabilizing the constant current against fluctuations in power supply voltage;
A capacitor charging circuit for charging the capacitor by forcing a current to flow through the capacitor;
And a control circuit for operating the capacitor charging circuit during a period from when the power is turned on to when a predetermined condition is satisfied.   The constant current source circuit according to claim 1, wherein the control circuit operates the capacitor charging circuit during a period until the power supply voltage exceeds a reference voltage. A startup circuit for starting up the constant current generation circuit by causing a current to flow through the control node when the power supply voltage rises;
The startup circuit is
A first resistor having one end grounded;
A start-up transistor having a collector connected to the power source, a base connected to the control node, and an emitter connected to the other end of the first resistor;
The capacitor charging circuit is:
A second resistor having one end connected to the control node;
A charging transistor having a drain connected to the other end of the second resistor, a gate connected to the control circuit, and a source grounded;
The constant current source circuit according to claim 1, wherein a resistance value of the first resistor is larger than a resistance value of the second resistor.   A power supply circuit comprising the constant current source circuit according to claim 1.

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