JP4084984B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a manufacturing technique of a semiconductor device, and more particularly to a technique effective when applied to a manufacturing method of a semiconductor device with high output and high heat generation such as a single power transistor or a power integrated circuit device.
[0002]
[Prior art]
In general, a high output and high heat generation semiconductor device such as a power transistor or a power integrated circuit device is a switching regulator, a laptop computer, or a laptop computer that is frequently used as a stabilized power source for electronic circuits such as home appliances, OA devices, and portable electronic devices. It is used for the charging circuit of a mobile phone, the backlight control of a liquid crystal panel, etc., and its use is rapidly expanding in recent years.
[0003]
As such a high output and high heat generation semiconductor device, there is a field effect transistor (MOSFET: Metal Oxide Semiconductor Field Effect Transistor) called a power MOS transistor (see, for example, Patent Document 1).
[0004]
This power MOS transistor is connected to, for example, a plurality of inner leads electrically connected to the surface electrode of the semiconductor pellet, a resin encapsulant formed by resin-sealing the semiconductor pellet and the inner lead, and the inner lead. A plurality of outer leads projecting side by side from the same side surface of the resin sealing body, and a surface opposite to the main surface of the semiconductor pellet, and projecting to the side surface opposite to the side surface from which the outer lead of the resin sealing body projects A header having a header protrusion, and a surface of the header opposite to the surface to be joined to the semiconductor pellet is exposed from the resin sealing body.
[0005]
[Patent Document 1]
International Patent Publication WO 00/49656 Pamphlet
[0006]
[Problems to be solved by the invention]
The power MOS transistor is mounted on the surface of the printed wiring board because the header can be reflow soldered to a foot pattern formed on the printed wiring board. As a result, the external resistance can be reduced, and the heat generated from the semiconductor pellet is released to the printed wiring board by heat conduction, so that the heat dissipation performance can be greatly improved.
[0007]
However, as a result of examination by the present inventor, it has been clarified that when the power MOS transistor is surface-mounted on a printed wiring board, there is a problem that the power MOS transistor is lifted due to poor solder wetting.
[0008]
That is, the foot pattern for the header of the printed wiring board is, for example, after depositing a copper (Cu) material on the substrate by means of a sputtering method or the like using a mask die-cut into a rectangle that matches the shape of the header, It is formed by depositing nickel (Ni) or gold (Au) on the surface by plating. The header is joined to the foot pattern using solder paste containing flux. However, if the header area is relatively large, the flux in the solder paste is trapped in the solder paste without escaping to the outside. The power MOS transistor is lifted by the flux trapped in the solder paste.
[0009]
In addition, a rectangular hole may be provided in a part of the header in contact with the peripheral portion of the resin sealing body to prevent the resin sealing body and the header from peeling off. Since no solder paste is attached, flux tends to accumulate in the holes, voids are formed due to the flux, and the power MOS transistor is peeled off from the printed wiring board when the power MOS transistor is assembled and mounted.
[0010]
In recent years, lead-free solder has been developed in response to the regulatory trend of lead (Pb), and mounting of power MOS transistors using this lead-free solder is also being studied. There are several candidates for alloys that constitute lead-free solder. Among them, tin (Sn) -zinc (Zn) eutectic has the melting point closest to that of tin-lead eutectic (eutectic temperature 199 ° C). Therefore, it is one of candidate alloy systems that are close to practical use because they have no problem with toxicity and are inexpensive. However, tin-zinc eutectic has a problem of low wettability, and in order to use it, it is necessary to contain a large amount of flux. For this reason, when a tin-zinc eutectic is used instead of a tin-lead eutectic for mounting a power MOS transistor, peeling of the power MOS transistor from the printed wiring board due to flux becomes a further serious problem.
[0011]
An object of the present invention is to provide a technology capable of improving the mountability of a power MOS transistor by removing excess flux in a solder paste.
[0012]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0013]
[Means for Solving the Problems]
Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.
[0014]
The present invention provides a step of preparing a semiconductor pellet having a field effect transistor formed on the main surface, a step of preparing a plurality of inner leads and a plurality of outer leads electrically connected to the inner leads, and a header The step of electrically connecting the inner lead and the surface electrode of the semiconductor pellet, the step of joining the header and the surface opposite to the main surface of the semiconductor pellet, and the semiconductor pellet, inner lead group and header. A process of forming a resin sealing body by partially sealing with resin, exposing a surface of the header opposite to the bonding surface with the semiconductor pellet, and projecting the header protruding portion in a direction opposite to the protruding direction of the outer lead. And soldering the header and the outer lead to the foot pattern formed on the wiring board, respectively, and the header is soldered In which slits are provided on the foot pattern.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.
[0016]
A method for manufacturing a power MOS transistor according to an embodiment of the present invention will be described with reference to FIGS.
[0017]
In this power MOS transistor manufacturing method, the semiconductor pellet 1 shown in FIG. 1, the multiple lead frame 2 shown in FIG. 2, and the header 3 shown in FIG. prepare.
[0018]
The semiconductor pellet 1 shown in FIG. 1 is manufactured by appropriately forming a field effect transistor in a wafer state in a so-called pre-process of a power MOS transistor manufacturing process, and then dividing (dicing) into a small rectangular thin plate shape. It is.
[0019]
The semiconductor pellet 1 includes a substrate 4, and a gate 5 is formed on the substrate 4 with polysilicon and an underlying silicon oxide film 6. A source 7 as a semiconductor diffusion layer is formed inside the substrate 4 corresponding to the outside of the gate 5 in the substrate 4, and a drain 8 is formed below the substrate 4.
[0020]
In addition, an insulating film 9 made of a CVD (Chemical Vapor Deposition) oxide film or the like is formed on the substrate 4 so as to cover the gate 5 and the source 7, and the insulating film 9 is opposed to the gate 5. The gate contact hole 10 is opened so as to penetrate the gate 5. A plurality of source contact holes 11 are formed in a region of the insulating film 9 facing the source 7 so as to penetrate the source 7 on one side of the gate contact hole 10.
[0021]
Further, a gate electrode pad 12 is formed inside the gate contact hole 10, and a source electrode pad 13 is formed inside each source contact hole 11. These electrode pads 12 and 13 are formed by depositing an aluminum-based material (aluminum or an alloy thereof) on the insulating film 9 by means such as sputtering, and then patterning it by photolithography.
[0022]
That is, since the aluminum-based material deposited on the insulating film 9 is filled in the contact holes 10 and 11, respectively, the electrode pads 12 and 13 formed by the filling portions are the gate 5 and the source 7 respectively. Are electrically connected to each other. On the other hand, a drain electrode pad 14 is formed on the lower surface of the substrate 4 by applying an aluminum-based material.
[0023]
On the gate electrode pad 12 and the plurality of source electrode pads 13, a protective film 15 made of an insulating material such as phosphosilicate glass or polyimide resin is applied. Gate bumps 16 and source bumps 17 project from the main surface 1a of the semiconductor pellet 1 at positions facing the electrode pads 12 and the source electrode pads 13, respectively.
[0024]
These bumps 16 and 17 are formed by a stud bump bonding method using a gold wire. In other words, a bump formed by a wire nail head type wire bonding apparatus or a nail head ultrasonic type wire bonding apparatus crimping a ball at the tip of the wire on the pad and then tearing the wire at the connection portion between the ball and the wire It is.
[0025]
The multiple lead frame 2 shown in FIG. 2 is stamped or etched using a thin plate made of a material having good conductivity such as iron (Fe) -nickel alloy, phosphor bronze, or a copper alloy of the same material as the header 3. It is integrally formed by means such as processing. The multiple lead frame 2 will be described in the case of a matrix frame 18 in which a single semiconductor device region is a group of 2 rows × 2 columns arranged in a matrix. That is, the matrix frame 18 is a group of four power MOS transistors. However, the number of matrices in one group in the matrix frame 18 is not limited to 2 rows × 2 columns, and may be other numbers.
[0026]
The matrix frame 18 includes a pair of outer frames 19 in which positioning holes 19a are formed. The outer frames 19 at both ends are arranged in parallel at a predetermined interval and extend in series. Further, a pair of section frames 20 are arranged in parallel with each other between the outer frames 19 at both ends between the adjacent matrix frames 18. Four unit lead frames 21 are formed in a substantially rectangular frame (frame) formed by the outer frame and the section frame.
[0027]
In the single lead frame 21, a dam member 22 is installed between the outer frames 19 on both sides so as to go straight to the outer frame 19. An inner lead 23 for the gate is integrally projected at a right angle to the dam member 22 at one end of the inner end of the dam member 22, and the inner lead 23 for the gate is a rectangular flat plate-shaped gate. The connection piece 23a is integrally formed.
[0028]
Further, a plurality of source inner leads 24 (three in FIG. 2) are distributed to the remaining part of the inner end side of the dam member 22 and protruded at equal pitches in the length direction. The inner lead 24 for the source is integrally formed with a rectangular plate-shaped source connecting piece 24a.
[0029]
Although not shown in the drawing, the surface of one main surface of the gate connection piece 23a and the source connection piece 24a is plated with tin, gold or the like by the bumps 16 and 17 protruding from the semiconductor pellet 1. It is applied so that the mechanical and electrical connection action is carried out properly.
[0030]
A gate outer lead 25 projects from the inner lead 23 for the gate at a position facing the inner lead 23 for the gate on the outer side edge of the dam member 22.
[0031]
In addition, outer lead 26 for each source projects from each inner lead 24 for each source at a position facing the inner lead 24 for each source on the outer side edge of the dam member 22. ing. And between the adjacent outer leads and the outer frames 19 on both sides, dams 22a are formed for blocking the flow of the resin when molding a resin sealing body to be described later.
[0032]
In the matrix frame 18, since four power MOS transistors are grouped into one group, it is necessary to change the direction of the semiconductor pellet 1 on both sides of the partition window 18a. The arrangement is such that
[0033]
The header 3 shown in FIG. 3 is formed in a substantially rectangular flat plate shape that is slightly larger than the semiconductor pellet 1. In this embodiment, in order to manufacture four power MOS transistors as one group, a header frame in which four headers 3 corresponding to four power MOS transistors are integrally provided in a 2-row × 2-column arrangement. 27, when joining each header 3 to the semiconductor pellet 1, the four integrated headers 3 are joined together to each of the four semiconductor pellets 1 (shown in part B in FIG. 3). The header 3 is a header 3 used for one power MOS transistor).
[0034]
Further, one header frame 27 is provided with four round holes 3a for positioning with a guide of a header attaching device (not shown) when attaching the header, and two of the round holes 3a communicate with the slit 3b. ing. In addition, a rectangular hole 3c for preventing the resin sealing body and the header 3 from peeling off is formed in a part of the header 3 that contacts the peripheral edge of the resin sealing body during molding.
[0035]
The semiconductor pellet 1, the matrix frame 18 and the header plate 27 configured as described above are assembled to form an assembly.
[0036]
First, pellet bonding for bonding the semiconductor pellet 1 and the matrix frame 18 is performed by flip chip.
[0037]
Here, as shown in FIG. 4, the back surface 1 b of the four semiconductor pellets 1 is directed upward, and the four semiconductor pellets 1 are connected to the gate connection piece 23 a and the source connection in the respective semiconductor device regions of the matrix frame 18. It arrange | positions on the piece 24a and pellet bonding is performed by thermocompression bonding.
[0038]
That is, the gate connection piece 23a for supporting the inner lead 23 and the gate electrode pad 12 (see FIG. 1) of the semiconductor pellet 1 are thermocompression-bonded to the gate bump 16 attached to the gate electrode pad 12. It joins by the gate connection part 16a formed. Thus, the gate electrode pad 12 and the inner lead 23 are electrically connected via the gate connection portion 16a and the gate connection portion piece 23a.
[0039]
Similarly, the source connecting portion piece 24a that supports the inner lead 24 and the source electrode pad 13 (see FIG. 1) of the semiconductor pellet 1 are thermocompression bonded to the source bump 17 attached to the source electrode pad 13. It joins by the source connection part 17a formed. Thus, the source electrode pad 13 and the inner lead 24 are electrically connected through the source connection portion 17a and the source connection portion piece 24a. The gate bump 16 and the source bump 17 may be attached to the inner leads 23 and 24, respectively.
[0040]
Further, the positional relationship between the main surface 1a of the semiconductor pellet 1 after flip-chip mounting, the gate connection piece 23a, and the source connection piece 24a is the same as that shown in FIG.
[0041]
That is, in the power MOS transistor of the present embodiment, the source connection portion 24a that supports the three inner lead 24 for the source is disposed on the main surface 1a of the semiconductor pellet 1 so as to be opposed thereto, and A base end portion 24 b of each inner lead 24 is disposed on an inner region of the main surface 1 a of the semiconductor pellet 1.
[0042]
Further, a gate connection piece 23 a that supports one inner lead 23 for the gate is also arranged on the main surface 1 a of the semiconductor pellet 1 so as to be insulated from the source connection piece 24 a and arranged side by side. The base end portion 23 b is also disposed on the inner region of the main surface 1 a of the semiconductor pellet 1.
[0043]
Next, header attachment which is attachment of the header frame 27 to the semiconductor pellet 1 is performed.
[0044]
Here, as shown in FIG. 5, first, a silver (Ag) paste 28 as a header bonding material is applied to the back surface 1 b of each semiconductor pellet 1.
[0045]
Subsequently, as shown in FIG. 6, each header 3 of the header frame 27 is placed on each back surface 1 b of the four semiconductor pellets 1.
[0046]
Further, the semiconductor pellet 1 is pressurized and scrubbed or the like, thereby joining each header 3 and the back surface 1b of each semiconductor pellet 1 through the silver paste 28, respectively.
[0047]
Next, the assembly of the semiconductor pellet 1 with the header and the inner lead group is resin-sealed (molded) using a transfer molding apparatus.
[0048]
As shown in FIG. 7, the transfer molding device 29 used includes a mold composed of a pair of an upper die 30 and a lower die 31 that are clamped together by a cylinder device (not shown). A plurality of sets (only one set is shown in the figure) such that the upper mold cavity recess 33a and the lower mold cavity recess 33b cooperate with each other to form the cavity 33. ) It is buried.
[0049]
A pot 34 is provided on the mating surface 32 of the upper mold 30, and a plunger 35 that is advanced and retracted by a cylinder device (not shown) feeds a molding resin, that is, a resin 36 as a molding material. Has been inserted to get. On the mating surface 32 of the lower mold 31, a cull 37 is disposed at a position facing the pot 34 and is buried. One end of a gate 38 for injecting the resin 36 into the cavity 33 is connected to the cull 37, and the other end of the gate 38 is connected to the lower mold cavity recess 33b.
[0050]
Further, a through gate 39 is connected to the opposite side of the lower mold cavity recess 33b facing the gate 38, and the through gate 39 is connected to the facing piece of the adjacent lower mold cavity recess 33b. The through gate 39 is configured to circulate the resin 36 filled in the upstream cavity 33 and fill the downstream cavity 33.
[0051]
When molding the resin sealing body by the transfer molding device 29 configured as described above, first, an assembly of the semiconductor pellet 1 with the header 3 and the inner lead group in the cavity 33 of the upper mold 30 and the lower mold 31. Place.
[0052]
Subsequently, the upper mold 30 and the lower mold 31 are clamped and the lower surface of the header 3 is brought into close contact with the bottom surface of the upper mold cavity recess 33a, and then the resin 36 is moved from the pot 34 by the plunger 35 to the gate 38 and the through gate. The cavities 33 are sequentially supplied through 39 and filled. After filling, the resin 36 is thermally cured to form a resin sealing body, and then the upper mold 30 and the lower mold 31 are opened. Further, the resin sealing body is released by an ejector pin (not shown).
[0053]
At this time, as shown in FIG. 8, by injecting the resin with the lower surface (exposed surface 3 d) of the header 3 being in close contact with the bottom surface of the cavity of the upper mold 30, The surface opposite to the bonding surface 3 e, that is, the exposed surface 3 d is exposed from the resin sealing body 40. Further, the resin projecting body 40 is formed by projecting the header projecting portion 3 f in the direction opposite to the projecting direction of the outer leads 25 and 26.
[0054]
In addition, alignment is performed so that the peripheral edge of the resin sealing body 40 and a part of the rectangular hole 3c provided in a part of the header 3 connected to the header protruding part 3f overlap each other, and the resin sealing is performed. .
[0055]
Thereafter, as shown in FIG. 9, cutting and molding are performed in which the plurality of outer leads 25 and 26 are cut from the matrix frame 18 and bent. At the same time, the integrated header frame 27 is cut at each of the four round holes 3a and separated into four headers 3 through the slits 3b.
[0056]
In this cutting / molding step, the outer leads 25 and 26 are bent into a gull wing shape.
[0057]
FIG. 10 shows an example of an external view of a power MOS transistor manufactured and configured as described above.
[0058]
The power MOS transistor Tr has three source outer leads 26 and one gate outer lead 25 bent into a gull-wing shape from one of two opposing side surfaces of the sealing resin body 40. A flat and substantially rectangular header protruding portion 3f protrudes from the other side surface that protrudes and faces this side surface. Further, an exposed surface 3 d exposed from the resin sealing body 40 is formed on the lower surface of the header 3, that is, the surface of the header 3 opposite to the surface in contact with the semiconductor pellet 1.
[0059]
Next, the power MOS transistor Tr is surface-mounted on the printed wiring board.
[0060]
FIG. 11 is a partial plan view showing an example of a printed wiring board on which one power MOS transistor Tr is mounted.
[0061]
On the surface of the main body 42 of the printed wiring board 41 on which the power MOS transistor Tr is mounted, one gate foot pattern 43 made of a conductor layer, three source foot patterns 44 and one drain having a slightly larger area than the header 3 A foot pattern 45 is formed.
[0062]
The gate foot pattern 43 and the source foot pattern 44 to which the ends of the outer leads 25 and 26 are respectively joined are rectangular patterns, but the drain foot pattern 45 to which the header 3 is joined has a notch slit 45a. The rectangular pattern is formed so that a part of the cutout slit 45 a overlaps a part of the hole 3 c provided in the header 3 when the power MOS transistor Tr is surface-mounted on the printed wiring board 41.
[0063]
The main body 42 of the printed wiring board 41 is formed by, for example, alternately stacking thin copper sheet layers and epoxy fiber glass insulating layers and pressing them. Further, each of the foot patterns 43, 44, 45 is a printed wiring board made of a copper material by means of a sputtering method or the like using a mask die-cut according to the end portions of the outer leads 25, 26 and the shape and dimensions of the header 3. After depositing on 41, nickel or gold is formed on the surface by plating.
[0064]
FIG. 12 shows an example of a mounting state of the power MOS transistor Tr.
[0065]
The outer lead 25 for the gate of the power MOS transistor Tr is formed on the gate foot pattern 43 formed on the main body 42 of the printed wiring board 41, the outer lead 26 for each source is formed on the respective foot pattern 44 for source, and the drain electrode pad 14. The header 3 to which (see FIG. 1) is connected is aligned with the drain foot pattern 45 and soldered by an infrared hot air reflow method of about 235 ° C., for example.
[0066]
At this time, the flux in the solder paste 46 is released to the outside from the notch slits 45 a provided in the drain foot pattern 45. Further, by overlapping a part of the hole 3c provided in the header 3 and a part of the notch slit 45a provided in the drain foot pattern 45, the flux in the solder paste 46 that easily collects in the hole 3c is released to the outside. Let As a result, void formation due to the flux in the solder paste 46 can be prevented, and the power MOS transistor Tr can be prevented from being peeled off from the printed wiring board 29.
[0067]
As described above, according to the present embodiment, the power MOS transistor Tr in which the surface (exposed surface 3 d) opposite to the surface in contact with the semiconductor pellet 1 of the header 3 is exposed from the resin sealing body 40 is applied to the printed wiring board 41. When reflow soldering is performed, a notch slit 45a is provided in the drain foot pattern 45 formed on the printed wiring board 41 to which the header 3 is bonded, thereby facilitating release of the flux contained in the solder paste 46 to the outside. Therefore, the formation of voids due to the flux can be prevented, and the peeling of the power MOS transistor Tr from the printed wiring board 41 can be prevented.
[0068]
In particular, in the header 3 in which the hole 3c is formed in order to prevent the resin sealing body 40 and the header 3 from being peeled off, the flux tends to accumulate in the hole 3c during reflow soldering, but a part of the notch slit 45a is formed. By overlapping with a part of the hole 3 c provided in the header 3, it is possible to easily release the flux that tends to accumulate in the hole 3 c to the outside.
[0069]
As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments of the invention. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.
[0070]
For example, in the above-described embodiment, the case where the shape of the notch slit is a rectangle and the notch slit is provided at one place in the drain foot pattern of the printed wiring board, but the shape may be other than a rectangle, Two or more notch slits may be provided.
[0071]
In the above-described embodiment, three source outer leads and one gate outer lead bent in a gull wing shape protrude from one side surface, and a flat plate shape projects from the other side surface facing this side surface. In the case of the power MOS transistor in which the substantially rectangular header protruding portion protrudes and the exposed surface exposed from the resin sealing body is formed on the surface opposite to the surface in contact with the semiconductor pellet of the header, The present invention can be applied to any power MOS transistor in which the surface opposite to the surface in contact with is exposed from the resin sealing body.
[0072]
For example, a header is integrally formed on a lead frame, a semiconductor pellet is fixed on the header, and a surface electrode of the semiconductor pellet and another inner lead are electrically connected by a bonding wire. The present invention can also be applied to a power MOS transistor in which a part of a pellet, an inner lead group, and a header are sealed with a resin sealing body.
[0073]
Further, in the above-described embodiment, the case of the power MOS transistor in which the rectangular hole for preventing the resin sealing body and the header from peeling off is described in a part of the header has been described, but the hole is not formed in the header. It can also be applied to power MOS transistors.
[0074]
【The invention's effect】
Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.
[0075]
Excess flux in the solder paste is released to the outside by notching the printed circuit board foot pattern on the printed circuit board that solders the header exposed from the resin encapsulant on the surface opposite to the surface to be bonded to the semiconductor pellet. Therefore, the mountability of the power MOS transistor can be improved.
[Brief description of the drawings]
1A and 1B are diagrams showing an example of a structure of a semiconductor pellet used in a method for manufacturing a power MOS transistor according to an embodiment of the present invention, where FIG. 1A is a plan view, and FIG. 1B is a plan view of FIG. It is an expanded sectional view which follows an AA line.
FIG. 2 is a partial plan view showing an example of a structure of a matrix frame used in a method for manufacturing a power MOS transistor according to an embodiment of the present invention.
FIG. 3 is a plan view showing an example of the structure of a header frame used in the method for manufacturing a power MOS transistor according to an embodiment of the present invention.
4A and 4B are diagrams showing an example of a structure at the time of flip-chip mounting in a manufacturing process of a power MOS transistor according to an embodiment of the present invention, where FIG. 4A is a partial plan view, and FIG. Sectional drawing which follows CC line, (c) is the partial bottom view which looked at the D section of (a) from the lead side.
FIGS. 5A and 5B are diagrams showing an example of a structure when silver paste is applied in a manufacturing process of a power MOS transistor according to an embodiment of the present invention, where FIG. 5A is a partial plan view, and FIG. It is sectional drawing which follows the EE line.
6A and 6B are diagrams showing an example of a structure when a header is attached in a manufacturing process of a power MOS transistor according to an embodiment of the present invention, where FIG. 6A is a partial plan view, and FIG. It is sectional drawing which follows the -F line.
FIG. 7 is a view showing an example of a structure at the time of molding in the manufacturing process of the power MOS transistor according to the embodiment of the present invention, and (a) shows the state in the molding die through the molding die. The partial top view to show, (b) is the fragmentary sectional view which follows the GG line of (a) when the mold is clamped, (c) is H of (a) when the mold is clamped It is a fragmentary sectional view which follows the -H line.
8 is an enlarged partial cross-sectional view taken along the line II of FIG. 7A when the molding die is clamped.
FIGS. 9A and 9B are diagrams showing an example of a structure at the time of cutting and molding in a manufacturing process of a power MOS transistor according to an embodiment of the present invention, where FIG. 9A is a partial plan view, and FIG. It is sectional drawing which follows a JJ line.
10A and 10B are diagrams showing an example of the structure of a power MOS transistor according to an embodiment of the present invention, where FIG. 10A is a plan view, FIG. 10B is a front view, and FIG. 10C is a bottom view.
FIG. 11 is a partial plan view showing an example of a printed wiring board on which a power MOS transistor according to an embodiment of the present invention is mounted.
12A and 12B are diagrams showing an example of a mounted state of a power MOS transistor according to an embodiment of the present invention, where FIG. 12A is a partial plan view, and FIG. 12B is a cross section taken along line KK in FIG. FIG.
[Explanation of symbols]
1 Semiconductor pellet
1a Main surface
1b Back side
2 Multiple lead frames
3 Header
3a round hole
3b slit
3c hole
3d exposed surface
3e Joint surface
3f Header protrusion
4 Substrate
5 Gate
6 Silicon oxide film
7 Source
8 Drain
9 Insulating film
10 Contact hole for gate
11 Contact hole for source
12 Gate electrode pad
13 Electrode pad for source
14 Electrode pad for drain
15 Protective film
16 Bump for gate
16a Gate connection
17 Bump for source
17a Connection for source
18 Matrix frame
18a partition window
19 Outer frame
19a Positioning hole
20 section frame
21 Unit lead frame
22 Dam material
22a Dam
23 Innerlead
23a Connection piece for gate
23b Base end
24 Innerlead
24a Connection piece for source
24b Base end
25 Outerlead
26 Outer Lead
27 Header frame
28 Silver paste
29 Transfer molding equipment
30 Upper mold
31 Lower mold
32 mating surface
33 cavity
33a Upper cavity cavity recess
33b Lower cavity cavity
34 pots
35 Plunger
36 Resin
37 Cal
38 gate
39 Through Gate
40 Resin encapsulant
41 Printed circuit board
42 body
43 Foot pattern for gate
44 Foot Pattern for Source
45 Drain foot pattern
45a Notch slit
46 Solder paste
Tr power MOS transistor

Claims (4)

(A) preparing a semiconductor pellet having a power amplification field effect transistor formed on the main surface;
(B) preparing a plurality of inner leads and a plurality of outer leads respectively connected to the inner leads;
(C) preparing a header provided with a through hole in a part overlapping the peripheral edge of the resin sealing body;
(D) connecting the inner lead and the surface electrode of the semiconductor pellet;
(E) joining the header and the surface opposite to the main surface of the semiconductor pellet;
(F) Resin-sealing the semiconductor pellet, the inner lead group, and a part of the header to expose a surface of the header opposite to the joint surface with the semiconductor pellet, opposite to the protruding direction of the outer lead. A step of projecting a header projecting portion in the direction of, and forming the resin sealing body by overlapping the peripheral portion of the through hole provided in the header; and
(G) soldering the header and the outer lead to a foot pattern formed on a wiring board,
A slit is provided in the foot pattern to which the header is soldered, and a part of the through hole provided in the header and a part of the slit provided in the foot pattern overlap. A method for manufacturing a semiconductor device. (A) preparing a semiconductor pellet having a power amplification field effect transistor formed on the main surface;
(B) preparing a plurality of inner leads and a plurality of outer leads respectively connected to the inner leads;
(C) preparing a header in which a rectangular through hole is provided in a part overlapping the peripheral edge of the resin sealing body;
(D) connecting the inner lead and the surface electrode of the semiconductor pellet;
(E) joining the header and the surface opposite to the main surface of the semiconductor pellet;
(F) Resin-sealing the semiconductor pellet, the inner lead group, and a part of the header to expose a surface of the header opposite to the joint surface with the semiconductor pellet, opposite to the protruding direction of the outer lead. A step of projecting a header projecting portion in the direction of and forming the resin sealing body by overlapping the peripheral portion of the through hole provided in the header; and
(G) soldering the header and the outer lead to a foot pattern formed on a wiring board,
A rectangular slit is provided in the foot pattern to which the header is soldered, and a part of the through hole provided in the header and a part of the slit provided in the foot pattern overlap. A method of manufacturing a semiconductor device. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the solder is lead-free solder. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the solder is a tin-zinc eutectic.

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