JP3950871B2 - Image processing method and apparatus - Google Patents

Description

  The present invention relates to an image processing method and an apparatus thereof, and inputs multi-value image data in which one pixel is represented by an n value, and the n-value multi-value image data according to a desired number of gradations and pixel depth. The present invention relates to an image processing method and apparatus for binarizing or m (n> m> 2).

  In a facsimile or the like that can read and transmit an original image by a scanner, when the image data is read by the scanner, the read image data is transmitted or is simply copied. The image data was always read at a predetermined resolution and the image data was binarized. Similarly, in the case of error diffusion processing, which is a pseudo-halftone process generally used in facsimile machines, 64 bits of 6 bits, for example, are fixedly employed in both copying and transmission. It was.

  In recent years, recording apparatuses capable of recording with high resolution have been provided at low cost in LBP (laser beam printers) and the like, and multi-value recording such as four values can be easily performed. ing. For example, when recording image data with a resolution of 400 dpi in the main scanning direction on a recording apparatus having a resolution of 1200 dpi (dots / inch) in the main scanning direction, a small value of 1200 dpi according to the density value of the input image data. By making the number of dots (three in this case) correspond to the density value of the input image, recording with four values can be realized. Of course, when performing binary recording at 400 dpi, all three small dots of 1200 dpi correspond to black if black, and all three small dots of 1200 dpi correspond to white if white.

  In recent years, copying machines and facsimile machines have become more and more complex, and high-quality printing with 256 gradations or more is required for facsimile machines when copying. For this reason, when the original image is read by the scanner of the facsimile apparatus, when the read image data is transmitted, for example, binary image data of 64 gradations is generated by binarization processing and a copy is taken. Therefore, in order to make the best use of the recording characteristics (resolution, gradation, etc.) of the printer unit, for example, it is desired to generate image data of 256 gradations by m-value processing. In such image processing, binary error diffusion processing is widely used as binarized image processing, and binary error diffusion processing is expanded as m-value conversion processing so that an output value is converted to m-value. The m-value error diffusion processing is widely adopted, and these functions are implemented separately according to the purpose of each device.

  However, in the above-described facsimile apparatus or the like, a binarization processing circuit that performs binarization processing in order to use the read image for communication and a multivalue processing circuit that performs multi-value processing for copying the read image are provided. If they are configured with separate circuits, there is a drawback that the facsimile apparatus becomes very expensive.

The present invention has been made in consideration of the above prior art, a feature of the present invention, the m-valued pixel data when the dot development, in the pixel of m-valued pixel data, the even-numbered pixels Provided is an image processing method and apparatus capable of improving the quality of an image recorded using dots by arranging dots so that the on dots and the on dots of odd-numbered pixels are continuous and symmetrical. Is to do

In addition, a feature of the present invention is to improve the quality of an image recorded using the dots by changing the arrangement direction of the dots according to the density gradient of the adjacent pixels of the pixel of interest of the m-valued pixel data. It is an object of the present invention to provide an image processing method and an apparatus for the same.

In order to achieve the above object, an image processing apparatus of the present invention has the following arrangement. That is,
Image input means for inputting multivalued image data in which one pixel is represented by an n value;
Filter means for performing spatial filter processing on the multivalued image data input by the image input means;
Processing means for converting each pixel data of the image data into m (2 <m <n) values for the image data filtered by the filter means;
Dot arrangement means for converting the pixel data converted to m-value by the processing means into (m−1) dot arrangement having a resolution higher than the resolution of the pixel data;
The dot arrangement means is m-valued so that even-numbered pixel on-dots and odd-numbered pixel on-dots of the pixel data m-valued by the processing means are continuously and symmetrically arranged. The halftone representation pixel data is converted into the dot array.

In order to achieve the above object, the image processing method of the present invention includes the following steps. That is,
An image input step of inputting multivalued image data in which one pixel is represented by an n value;
A filtering step of performing spatial filtering on the multi-valued image data input in the image input step;
A processing step of converting each pixel data of the image data into m (2 <m <n) values for the image data filtered in the filtering step;
A dot arrangement step of converting the pixel data converted to m-value in the processing step into (m−1) dot arrangements having a resolution higher than the resolution of the pixel data,
In the dot arrangement step, the m-value is converted so that the even-numbered pixel on-dots and the odd-numbered pixel on-dots are continuously and symmetrically arranged in the pixel data m-valued in the processing step. The halftone representation pixel data is converted into the dot array.

According to the present invention, when m-valued pixel data is expanded into dots , even-numbered pixel on-dots and odd-numbered pixel on-dots are continuous in m-valued pixel data pixels . By arranging the dots so as to be symmetric, the quality of an image recorded using the dots can be improved.

According to the present invention, the quality of an image recorded using the dots is improved by changing the dot arrangement direction according to the density gradient of the adjacent pixels of the pixel of interest of the m-valued pixel data. There is an effect that can be.

  Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

  FIG. 1 is a functional block diagram showing the overall functions of the image processing apparatus according to the present embodiment.

  A scanner unit 100 reads an original image with a CCD (solid-state imaging device) or the like, converts the read analog image signal into a digital signal, for example, with an 8-bit A / D converter, and one pixel has 8 bits (256). (Gradation) image data. In addition, the scanner unit 100 performs correction processing of a CCD (solid-state imaging device) and an optical system such as shading correction simultaneously with the image reading. Reference numeral 200 denotes a spatial filter processing unit, which inputs image data in which one pixel output from the scanner unit 100 is represented by 8 bits, and performs a two-dimensional spatial filter operation on the image data, thereby resolving the resolution of the image data. Compensation is performed. Here, if scaling is required, scaling by linear interpolation calculation (not shown) can be performed between the scanner unit 100 and the spatial filter processing unit 200. A luminance density conversion unit 300 converts image data (luminance data) whose resolution has been compensated by the spatial filter processing unit 200 into density data using, for example, a look-up table. Note that the look-up table of the luminance density conversion unit 300 includes an image processing apparatus according to the present embodiment in accordance with image processing modes such as dark / light images and binarization / quaternarization described later. Table data is downloaded from the control unit 110 (FIG. 2). The lookup table uses data that is corrected based on the LOG conversion curve and further taking into account the recording characteristics of the printer 700.

  Reference numeral 400 denotes a binary / quaternarization processing unit which receives density data output from the luminance / density conversion unit 300, performs binarization or quaternization processing, and outputs the result. Reference numeral 500 denotes an image memory composed of DRAM, SRAM, or the like. Image data read by the scanner unit 100 and generated by binarization or quaternarization processing is composed of 2 bits or 1 bit, or Image data input via a communication line (not shown) is stored as an image file. A binary / quaternary developing unit 600 inputs 400 dpi binary image data or 400 dpi quaternary image data to a printer 700 having a recording resolution of 1200 dpi in the main scanning direction. An optimum arrangement of small dots of 1200 dpi is applied and output to the printer 700. The printer 600 is, for example, an LBP printer with a resolution of 1200 dpi, and prints the image data on a recording medium (such as recording paper) using the binary data (0 or 1) developed by the binary / quaternary developing unit 600. is doing.

  In the present embodiment, the multilevel error diffusion process is described as a quaternary process. However, the present invention is not limited to this, and is generally limited according to the resolution of the printer 700 and the like. Needless to say, m-value conversion can be performed.

  FIG. 2 is a block diagram showing the basic configuration of the image processing apparatus according to the present embodiment. The parts common to those shown in FIG.

  Reference numeral 110 denotes a control unit that controls the entire apparatus described above. The CPU 120 such as a microcomputer is used as a work area when the CPU 120 executes processing. The RAM 121 temporarily stores various data, and the CPU 120 control program and data are stored. Program memory 122 and the like. The look-up table (LUT) 123 stores a table used for the above-described luminance density conversion. Reference numeral 124 stores a Laplacian filter constant used in the spatial filter processing unit 200. A display unit 111 displays a document image read by the scanner 100 and an image subjected to various processes. Reference numerals 201 and 202 denote line buffers used in spatial filter processing, which will be described later. In this embodiment, one address is configured by commonly using RAM addresses that can store 16-bit data. A latch circuit group 203 latches output values of line buffers 201 and 202, which will be described later.

  The spatial filter processing unit 200 in FIG. 1 is achieved by the control unit 110, the line buffers 201 and 202, the latch group 203, and the like, and the processing of the luminance density conversion unit 300 is realized by the CPU 120 of the control unit 110 and the like. Further, in the present embodiment, the quaternary / binarization processing unit 400 and the binary / quaternary development unit 600 are configured by hardware, but may be realized by a program executed by the CPU 120.

[Embodiment 1]
Hereafter, it demonstrates in detail focusing on the characteristic of each process part of Embodiment 1 of this invention.

<Spatial filter processing unit 200>
Usually, in order to perform spatial filter processing on image data, as many line buffers as there are reference lines or (reference lines minus 1) are required. Conventionally, such a line buffer is composed of an external SRAM or the like, and many SRAMs having a bit width of 8 bits are prepared. For this reason, when the input data is 8 bits, there is no particular problem in terms of apparatus cost even if the reference line buffer is composed of all 8-bit memories. However, due to recent advances in IC technology, it has become possible to easily incorporate an SRAM used as an external reference buffer. However, if such a line buffer is built in, the memory capacity is directly reflected as a manufacturing cost, so that it is necessary to reduce the memory capacity. For this reason, in this embodiment, the effective number of the reference buffer is reduced to such an extent that the influence of the operation is small, thereby achieving both the performance maintenance of the device and the reduction of the device cost.

  FIG. 3A is a diagram showing an example of a matrix of Laplacian filters for resolution compensation that is used relatively frequently, and FIG. 3B is a diagram for explaining a line buffer used for the matrix calculation. is there.

  In order to perform arithmetic processing for spatial filter processing with reference to image data (pixel data) for three lines, two 8-bit line buffers are required to simultaneously refer to pixels in the sub-scanning direction. . In the present embodiment, the number of bits of line 1 that is relatively less affected by operations is reduced from 8 bits to 6 bits, so that the balance between device performance and device cost is maintained. As a result, when B4 image data is stored at 400 dpi, the memory capacity can be reduced by 8192 bits.

  FIG. 4 is a block diagram showing the configuration of the line buffer and latch group of the spatial filter processing unit 200.

  The line buffers 201 and 202 are line buffers for delaying pixel data in the sub-scanning direction and simultaneously referring to pixel data for three lines. The latch group 203 delays pixel data in the main scanning direction. Data for spatial filtering is extracted from these latch groups.

  In this embodiment, one pixel of image data is represented by 8 bits, the line buffers 201 and 202 are configured by one RAM (16 bits / 1 address), and the lower (0 to 7) bits (8 bits) of the RAM. ) Is assigned to the line buffer 202 for delaying one line, and the upper (8-13) bits (6 bits) are assigned to the line buffer 201 for delaying the second line.

  Further, the input pixel data (8 bits) is directly latched in the latch circuit group 203a corresponding to the line 3 of the latch group 203, and the output data (8 bits) of the line buffer 202 is latched in the latch circuit group 203b corresponding to the line 2. The output data (6 bits) of the line buffer 201 is further latched in the latch circuit group 203c.

  FIG. 5 is a timing chart showing memory access in the spatial filter processing unit 200 of the present embodiment.

  Image data (DATIN) input in synchronization with the rising edge of the clock (DCLK) is stored in the designated addresses (A1 to An) of the line buffers 201 and 202 in synchronization with the rising edge of the clock (DCLK). The access in FIG. 5 is a diagram showing the access timing to the data stored in this line buffer, RD indicates the read timing, and WR indicates the write timing. For example, at the read (RD) timing 210 in FIG. 5, data (ID1) obtained by shifting the data “D1” stored at the address “A1” of the line buffer (RAM) by 2 bits is read (indicated by RDDAT). At the next write timing (WR) 211, the data (ID1) read out after being shifted by 2 bits and the original data (D1) are combined and stored in the same address (A1). Thereby, the original pixel data (D1) is arranged in the lower bits (0 to 7) of the address (A1), and the data (ID1) shifted by 2 bits is the upper bits of the address (A1). (8-13). In this way, the read address and the write address are made the same, and the RAM (line buffer) is updated by read modified write. By repeating such an operation, the pixel data delayed by one line in the lower bit (0-7) position (corresponding to the line buffer 202) of the RAM becomes the upper bit (8-13) position ( The pixel data delayed by two lines is stored in the line buffer 201).

  The image data delayed by the line read from the line buffers 201 and 202 and the input image data (DATIN) are sequentially taken into the latch group 203 in synchronization with the rising edge of the clock (DCLK). In the latch group 203, the data read from the line buffers 201 and 202 and the input image data are sequentially shifted in synchronization with the rising edge of the clock (DCLK). As a result, two-dimensional (3 × 3) image data is extracted.

  Here, among the data latched by the latch group 203, the data indicated by X, A, B, C, and D in FIG. 4 are the X, A, B, and C of the spatial filter in FIG. , D corresponding to each position. In the actual spatial filter operation, the values corresponding to A and B are only the upper 6 bits of the memory, so that they are bit-shifted and “00” is inserted into the lower 2 bits, and the operation is performed as 8-bit data. Processing is done.

filter = X << 2 − ((A << 2) + (B << 2) + C + D);
The above expression expresses the operation of the spatial filter of this embodiment in C language. Since X has a filter coefficient of “4”, it is shifted left by 2 bits (× 4), and A and B are shifted left by 2 bits in order to handle 6-bit data in the same way as other 8-bit data. In an actual apparatus, for example, when such an operation is realized by hardware, such a bit shift is realized by shifting the bit position in the wiring from the latch circuit group 203 to the adder. The spatial filter value obtained here is further added to the X data, and one pixel is output as 8-bit image data after resolution compensation. Further, when such an operation is realized by software, it can be easily realized by executing and adding a register shift instruction.

<Luminance Density Converter 300>
The luminance density conversion unit 300 receives luminance data of which one pixel has been subjected to resolution compensation by the spatial filter processing unit 200, converts the luminance data into density data with reference to a lookup table, and outputs the density data. As described above, normally, the luminance density conversion table is obtained by adding the correction of the recording characteristics of the printer 700 to the LOG conversion.

  In the present embodiment, the density data is converted so that the data width required by the quaternary / binarization processing unit 400 in the subsequent stage corresponds to the respective modes of the binarization process and the quaternary process. Conversion is performed.

  First, in the present embodiment, when binary error diffusion processing is performed, data processing is performed assuming that all white data is “0” and all black data is “63” (6 bits).

  FIG. 6A is a diagram showing a characteristic example of luminance-density conversion for binary error diffusion processing.

  In the case of binary error diffusion, image data of 8 bits, that is, “0” to “255” is input, converted to density data of 6 bits, that is, “63” to “0”, and output. Further, in the case of performing quaternary error diffusion processing, data processing is performed with all white data set to “0” and all black data set to “255”.

  FIG. 6B is a diagram illustrating a characteristic example of luminance-density conversion for four-value error diffusion processing. Here, image data of 8 bits, that is, “0” to “255” is input, converted to density data of 8 bits, that is, “255” to “0”, and output.

  Furthermore, depending on the performance of the printer 700, when an output pattern having a specific density is recorded, the recorded image quality may be deteriorated (the image becomes rough). For example, when image data of 256 gradations in which one pixel is represented by 8 bits is used and printed by performing quaternary error diffusion processing, the image of the density data output pattern with a density of around “31” tends to be rough. It is in. This is considered to be because, in the image data of density “31”, the output data becomes a checkered state of “0” and “1” due to the error diffusion characteristic, and the recording characteristics of the printer 700 cannot follow this checkered data. It is done. Therefore, in such a case, a luminance-density conversion table is created by skipping image data having a density (here, density “31”) that makes the recorded image rough.

  FIG. 6C is a diagram showing a characteristic example of the luminance-density conversion table created by skipping the density “31” in this way.

<Binary and Quaternization Processing Unit 400>
First, an algorithm of a quaternary error diffusion process as the m-value conversion process will be described. The difference between binary error diffusion and quaternary error diffusion is that an error is calculated from three threshold values and four output densities. Similarly to the binary error diffusion, the error diffusion in the four values is the output pixel density (here, DENT3 = 255, DENT2 = 170, DENT1 = 85, DENT0 = 0) and the correction density X′ij (pixel density Xij). As a new error, the difference from the sum of the error diffusion amount) is diffused as shown in FIG. 7 while weighting corresponding pixels to the diffusion matrix of error distribution. In the processing relating to the error distribution to the adjacent pixels, the correction density X′ij is the same for both binary error diffusion and quaternary error diffusion.
X'ij = Xij + SUM (Ekl × αkl) / SUM (αkl)
Here, α represents a weighting coefficient for error distribution, and Ekl represents an error generated before the processing pixel.

  Next, the signal level of the correction density X′ij is determined by three threshold values using the following equations (1) to (4), and the recording output signal level (OUTPUT) and the error amount (E) are determined. .

  Here, the threshold values are TH1 = (DENT1 + DENT0) / 2, TH2 = (DENT2 + DENT1) / 2, and TH3 = (DENT3 + DENT2) / 2.

If X'ij> TH3, output pixel density OUTPUT = 3 and error E = X'ij-DENT3 (1)
If TH3> = X'ij> TH2, output pixel density OUTPUT = 2 and error E = X'ij-DENT2 (2)
If TH2> = X'ij> TH1, output pixel density OUTPUT = 1 and error E = X'ij-DENT1 (3)
If TH1> = X'ij, output pixel density OUTPUT = 0 and error E = X'ij-DENT0 (4)
The new error E = X′ij− (DENT 3, DENT 2, DENT 1, DENT 0) generated here is again diffused and arranged in the near pixel elements with the weights as shown in FIG. By repeating this, 8-bit input image data (0 to 255) is converted into any one of four values (0 to 3) and output.

  In the case of binary error diffusion processing, assuming that the density for the error calculation of the above four-value error diffusion is BDENT1 = 63, BDENT0 = 0, and the threshold is BTH1 = (BDENT1 + BDENT0) / 2, the following equation (5) ), (6), the error (E) determined in accordance with the output pixel density (OUTPUT) is diffused with the weighting shown in FIG. 7 as a new error as described above. .

If X'ij> BTH1, output pixel density OUTPUT = 1 and error E = X'ij-BDENT1 (5)
If BTH1> = X'ij, output pixel density OUTPUT = 0 and error E = X'ij-BDENT0 (6)
In this embodiment, paying attention to the fact that the error distribution calculation is common in binary error diffusion and quaternary error diffusion processing, the error distribution calculation processing block and the error buffer access block are shared, It is possible to realize quaternary error diffusion and binary error diffusion at the same time while preventing the apparatus from becoming large. More specifically, the error distribution arithmetic circuit is composed of effective bits for quaternary error diffusion having a large effective bit number, and the effective bit number is clamped to the effective bit number for binary error diffusion when stored in the error buffer. This reduces the size of the error buffer memory. In the present embodiment, the error buffer is 6 bits, and the error amount calculated when the error buffer is stored in this error buffer is clamped to “−32” to “+31”.

  FIG. 8 is a block diagram showing an example of an error diffusion circuit for commonly processing binary error diffusion and quaternary error diffusion processing in the present embodiment.

  Reference numerals 401 to 403 denote latch circuits, which hold error data that is weighted and distributed and diffused, and the data is updated in synchronization with the pixel clock. Reference numerals 404 to 407 denote adders that add data output from an error distributor 411 (to be described later) in which errors generated during processing of each pixel are distributed. 408 is a clamp processing circuit. When the output data of the adder 405 is “−32” or less, it is clamped to “−32”, and when it is “+31” or more, it is clamped to “31”. ("-32" to "31") and output to the image memory 500. Reference numeral 409 denotes a comparator which compares the error density value corrected by the error data output from the adder 407 with a threshold value according to each processing mode of binary or quaternary error diffusion, and outputs an output value and error calculation. A signal 415 for selecting a calculation formula is output. An error calculator 410 receives the signal 415 from the comparator 409 and the addition result from the adder 407, and calculates and outputs a new error amount of the pixel of interest determined thereby. An error distributor 411 weights the new error amount output from the error calculator 410 with a weighting coefficient corresponding to FIG. 7 and distributes the error amount to the adders 404, 405, and 406.

  The data flow in the quaternary / binarization processing unit 400 will be described by taking quaternary error diffusion processing as an example. In the case of binary error diffusion, the same processing flow as that of the quaternary error diffusion processing described below is performed, except that the threshold and the calculation formula for calculating a new error are changed.

  First, the input image data 414 is added to the output of the latch 403 (diffused error data) in the adder 407 and output to the comparator 409 and the error calculator 410. In the comparator 409, as shown in the above formulas (1) to (4), the correction pixel data, which is the output data of the adder 407, is compared with the threshold values TH1 to TH3 to determine a quaternary output value. At the same time, a selection signal 415 for selecting a new error amount calculation formula is output to the error calculator 410. The error calculator 410 includes a subtracting circuit (not shown) corresponding to the above equations (1) to (4). Which of the results of the above equations (1) to (4) is used is determined from the comparator 409. A selection is made according to the selection signal 415, and a new error is output.

  Note that a new error amount may be calculated by switching a subtracter provided in the error calculator 410 with a value to be subtracted by a selection signal 415 from the comparator 409.

  The new error amount output from the error calculator 410 is weighted corresponding to that in FIG. 7 by the error distributor 411, and the result is output to each adder 404, 406, 409 and latch 401. The error weighted with “W 3” is latched in the latch 401, and is added by the adder 404 with the error weighted with “W 2” generated by calculating the error of the next pixel. The output of the adder 404 is latched in the latch 402 and further added by the adder 405 with a weighted error of “W 1” generated by the error calculation of the next pixel. The output of the adder 405 is an error amount diffused to the next line of the processing line. The clamp circuit 408 clamps and outputs the signed 6-bit data from “−32” to “31”. The output of the clamp processing circuit 408 is temporarily stored in the error buffer in order to delay the data for one line, and is read when the next line is processed.

  The adder 406 adds the read value from the error buffer delayed by one line and the weighted error amount of “W 4” and latches the addition result in the latch 403. The latch 403 outputs the sum of the diffused errors as a correction amount. Thereafter, returning to the adder 407 and sequentially adding with the input image data 414, the binarized image data is output from the comparator 409.

  As described above, the input image data 414 is binarized in the binary error diffusion mode and is binarized in the quaternary error diffusion mode, and is output as binary data or quaternary data. At this time, the number of effective bits of each latch and each adder is configured according to the number of effective bits of the quaternary error diffusion process.

<Binary / Quaternary Expansion Unit 600>
The binary / quaternary developing unit 600 outputs image data with a resolution of 400 dpi in main scanning to a printer 700 capable of binary recording with a resolution of 1200 dpi. Therefore, 1200 dpi “0” (white) and “ It is converted into 1 ″ (black) image data.

  When the input data is quaternary image data, the quaternary value is made to correspond to the number of three small dots of 1200 dpi. First, when the four-value is “0”, all the small dots of 1200 dpi output “0”. Next, in the case of quaternary “1”, one of three small dots of 1200 dpi is output as “1” and the remaining two are output as “0”. Similarly, in the case of quaternary “2”, two of the 1200 dpi three small dots are output as “1” and the remaining one as “0”, and the quaternary data is “3”. In this case, all three small dots of 1200 dpi are output as “1”.

  If the input image data is binary 400 dpi image data, three 1200 dpi small dots are grouped together. If the input binary data is “0”, all three small dots are set to “0”. When the binary input data is “1”, all three small dots are output as “1”, and binary 400 dpi image data is developed. The data composed of “0” and “1” expanded in this way is printed by the printer 700.

  In this embodiment, a case will be described in which binary and quaternary image data are expanded as input image data at 400 dpi main scanning. As described above, when image data with a resolution of 400 dpi in the main scanning is output to the printer 700 capable of binary recording with a resolution of 1200 dpi in the main scanning direction, the input quaternary image data is a small dot 3 of 1200 dpi. Corresponding to the number of pieces, it is possible to record four-value 400 dpi image data. If the input data is binary 400 dpi image data, it is possible to record 400 dpi image data as binary data by combining three small dots of 1200 dpi to “0” or “1”. It becomes.

  First, the arrangement rules for small dots in the present embodiment will be described.

  FIG. 9A shows a case in which image data of 255 gradations is converted into four values by four-value error diffusion processing, and the four-valued image data is regularly arranged with small dots from the left according to the image density. It is a graph which shows the relationship between density data and recording density.

  Normally, a printer 700 such as LBP turns on / off irradiation with a semiconductor laser depending on whether input image data is “1” or “0”, and the point where the laser beam is turned on is black. To be recorded. At this time, since the dot diameter of the laser beam is circular and the dot diameter expresses all black, a dot size is selected such that the dots overlap each other little by little. For this reason, on / off data having a high frequency such that black and white are alternated is recorded as an image composed of dots that are black and tend to be crushed. For this reason, as shown in FIG. 9A, the recording density with respect to the density of the image data is extremely non-linear.

  In consideration of the characteristics of the printer 700 as described above, in this embodiment, when arranging small dots, as shown below, an arrangement pattern 0 (pattern 0) is selected for even pixels. Black dots “1” are arranged from the right side, and in the case of odd pixels, arrangement pattern 1 (pattern 1) is selected and black dots “1” are arranged from the left side. By developing in small dots in this way, the frequency component of the output data can be suppressed, and a pattern in which black and white alternate can be eliminated. At the same time, since the black dots are arranged so as to be continuous as much as possible, the collapse of the image due to the protrusion of the dot system is suppressed.

Even pixels odd pixels
(Placement pattern 0) (Placement pattern 1)
Pixel density 0 000 000
1 001 100
2 011 110
3 111 111
FIG. 9B shows the image density in the case where 255-level image data is converted into four values by four-value error diffusion, and the four-value data is further developed into small dots using the symmetric pattern. It is a graph which shows the relationship between data and recording density.

  FIG. 9B differs from FIG. 9A in that the relationship between the recording density and the density of the image data is much more linear than in FIG. 9A. Therefore, when dots are developed using the arrangement pattern and recorded, an image with more excellent gradation characteristics can be recorded.

  However, when such an arrangement pattern is used, there is no problem with halftone expression. However, in a character / line image, the sharpness of the recorded image may be deteriorated at the edge depending on whether the pixel at the edge corresponds to an even number or an odd number. There is.

  FIG. 10A is a diagram illustrating an example in which a pseudo line is generated at the edge portion because the low density portion of the edge is an odd pixel in the main scanning direction.

  In the present embodiment, the following exception processing is performed in order to prevent such a problem at the edge portion. That is, in this embodiment, when inputting m-valued image data, the pixel density of interest takes an intermediate value between “1” to “(m−1)”, and the pixels on both sides are expressed by the equation (7). , (8) is satisfied. If it is satisfied, the fixed pattern is selected regardless of the even number or the odd number. That is, the edge of the image is detected by comparing the pixel of interest with the density of the left and right pixels. In the case of the edge portion, the reproducibility at the edge portion is improved by arranging small dots according to the inclination direction of the pixel density. Here, DATn-1 indicates pixel data on the right side of DATn, and DATn + 1 indicates pixel data on the left side of DATn.

DATn−1 <DATn <DATn + 1 → arrangement pattern 0 (7)
DATn-1>DATn> DATn + 1 → placement pattern 1 (8)
FIG. 10B is a diagram showing an output example when exception processing is further introduced into the even-numbered and odd-numbered symmetrical pattern development in the present embodiment.

  According to this, it can be seen that an excellent result is obtained without generating a pseudo line in the edge portion of the image.

  Next, a specific configuration example of the binary / quaternary expansion unit 600 according to the present embodiment will be described in detail with reference to FIG.

  FIG. 11 is a block diagram showing a configuration of a circuit that determines the arrangement of small dots in the binary / quaternary developing unit 600.

  In order to synchronize the image output with the horizontal synchronization signal of the printer 700, the image data input here is temporarily buffered in a line buffer (not shown) and then from the line buffer while synchronizing with the horizontal synchronization signal. This is the read image data. A decoder 601 includes a target pixel value (DATn), pixel values before and after the target pixel in the main scanning direction (DATn-1, DTAn + 1), and an output value 610 of a 1-bit toggle counter that counts input pixel values. Entered. Whether the pixel is an even-numbered pixel or an odd-numbered pixel is determined based on the output value 610 of the toggle counter.

  The decoding logic in the decoder 601 is output to the selector 602 as a selection signal SEL for determining whether to select the arrangement pattern 0 or the arrangement pattern 1 in accordance with a logical expression described in the following C language. The selector 602 selects a small dot pattern according to the density value of the pixel of interest DATn and the value of the selection signal SEL, and outputs it to the parallel / serial conversion circuit (P / S) 603. The parallel / serial conversion circuit 603 converts the input 3-bit data into serial data of a desired speed requested by the printer 700 and outputs the data to the printer 700 as, for example, on / off data of laser light.

if (DATn = 1 || DATn = 2) {
if ((DATn-1 <DATn) && (DATn <DATn + 1)) {
SEL = pattern0;
} else if ((DATn-1> DATn) &&(DATn> DATn + 1)) {
SEL = pattern1;
} else {
if (TOGC = 1) {
SEL = pattern1;
} else {
SEL = pattern0;
}
{
} else {
if (TOGC = 1) {
SEL = pattern1;
} else {
SEL = pattern0;
}
}
As described above, according to the present embodiment, the spatial filter processing unit 200 can reduce the number of bits of the line buffer for extracting reference data in the sub-scanning direction, and further binarization and quaternary processing. The output range of luminance-density conversion is switched according to the conversion, and the error data stored in the error buffer by error diffusion is clamped to the number of significant digits of the error buffer at the time of binarization in the quaternary processing Thus, the blocks to be processed can be made common, and the image data can be generated by making the best use of the recording capability of the printer.

  Further, as described above, according to the present embodiment, when m-valued image data is developed into dots and output to the printer 700, pixels are even-numbered pixels and odd-numbered pixels in m-value input image data. By arranging the small dots in a pattern that is symmetric in the case of the second pixel, the gradation recording characteristics of the printer device can be greatly improved. Further, it is determined whether or not the pixel of interest has an intermediate value in the m-value input image data. If the pixel of interest has an intermediate value, the adjacent pixel is referenced with reference to adjacent pixels located on the left and right of the pixel of interest. By determining the arrangement of small dots based on the comparison result between the target pixel and the target pixel, it is possible to provide image recording with improved reproducibility of the edge portion included in the image.

[Other embodiments]
Next, an algorithm of a quaternarization method that is another embodiment of the present invention will be described. In the case of binarization, since binarization is performed by a known binary error diffusion method, the description thereof is omitted here. In this embodiment, in the density region where the followability is poor in the printer 700, processing is performed to switch the pixel density of the output image data and the error calculation method so as to suppress the occurrence of isolated black dots.

  The quaternarization process according to another embodiment of the present invention is based on quaternary error diffusion. As described above, the problem with the low-cost printer 700 is the image data in the vicinity of the threshold TH1 = (DENT1: 85 + DENT0: 0) / 2 => 42. Therefore, in this other embodiment, first, comparison means for identifying whether or not the input image data has a density that causes image unevenness is provided. Further, when the pixel density of the input image data is within a specific density range based on the comparison result of the comparison means, as shown in the following equations (9) and (10), an error diffused in the input image data is calculated. A threshold value DENT1 = 85 for comparing the added correction density is set. When the correction density is larger than this threshold, the value of the output pixel is set to “2”, and the error calculated for this pixel is obtained by subtracting DENT2 = 170 from the correction density. If the correction density is less than or equal to the threshold value, the output pixel value is set to “0”, and the error calculated for this pixel is calculated by subtracting DENT0 = 0 from the correction value.

  As a result, the conventional quaternary output pattern in the specific density region where image unevenness occurs is changed from the conventional density “1” and density “0” patterns to the density “2” and density “0” patterns. As a result, when the four-valued data is developed and output in this density region, an isolated pixel of 1200 dpi is not generated, thereby generating a dot pattern within the range of the followability of the printer 700, and generating a floor pattern. Tonal characteristics are improved.

  When the input image data is outside the specific density range, the same four-value error diffusion process as that in the past may be performed. The threshold value, output value, and generated error at that time are expressed by equations (11) to (14).

When the density of the input pixel is DTH1 <Xij <DTH2
If X'ij> DENT1, output pixel density OUTPUT = 2 and error E = X'ij-DENT2 (9)
If DENT> = X'ij, output pixel density OUTPUT = 0 and error E = X'ij-DENT0 (10)
When the density of the input pixel is DTH1 ≧ Xij ≦ Xij
If X'ij> TH3, output pixel density OUTPUT = 3 and error E = X'ij-DENT3 (11)
If TH3> = X'ij> TH2, output pixel density OUTPUT = 2 and error E = X'ij-DENT2 (12)
If TH2> = X'ij> TH1, output pixel density OUTPUT = 1 and error E = X'ij-DENT1 (13)
If TH1> = X'ij, output pixel density OUTPUT = 0 and error E = X'ij-DENT0 (14)
FIG. 12B shows an example in which a patch pattern of density data of 0 to 255 is recorded using the quaternary error diffusion process and the quaternary expansion process of the present embodiment, and the density is measured using a densitometer. FIG. As is apparent from FIGS. 12A and 12B, the gradation characteristics are improved in the vicinity of the density “42”.

  A description will be given with reference to FIG. 13 showing a circuit example of quaternary error diffusion processing according to another embodiment. In FIG. 13, the same parts as those in FIG. 8 are denoted by the same reference numerals, and the description thereof is omitted.

  The latch circuits 401 to 403 hold weighted and distributed error data, and the data is updated in synchronization with the pixel clock. Adders 404 to 407 add data output from the error distributor 411 and distributed with errors generated during processing of each pixel. The comparator 416 detects whether or not the pixel density of the input image data 414 is a specific density region (in this case, from −40 to 44). The comparator 409 compares the input pixel density value corrected by the diffused error data for the input pixel output from the adder 407 with a threshold value, and selects the output value in the error calculator 410 and the calculation formula for error calculation. The signal 415 is output. An error calculator 410 receives the signal 415 from the comparator 409 and the addition result from the adder 407, and calculates and outputs a new error amount of the pixel of interest determined thereby. The error distributor 411 weights the new error amount output from the error calculator 410 with a weighting coefficient corresponding to FIG. 7 and distributes the error amount to the adders 404, 405, and 406.

  A data flow in the quaternary / binarization processing unit 400 will be described.

  First, the input image data 414 is added to the output of the latch 403 (diffused error data) in the adder 407 and output to the comparator 409 and the error calculator 410. Further, the comparator 416 detects whether the density of the input pixel is in a specific density region. In the comparator 409, based on the comparison result of the comparator 416, as shown in the above formulas (9), (10) or (11) to (14), the correction pixel data as the output data of the latch 403 and the threshold values TH1 to TH1. A quaternary output value is determined by comparison with TH3 or DENT1, and at the same time, a selection signal 415 for selecting a new error amount calculation formula is output to the error calculator 410. In this error calculator 410, the above equations (11) to (14) [equation (9) uses equation (12) and equation (10) uses the same subtraction equation as equation (13)]. There is a subtracting circuit shown in the figure, which of the above formulas (11) to (14) is used is selected according to the selection signals 415 and 417 from the comparator 416 and the comparator 409, and a new error is output. .

  Note that a new error amount may be calculated by switching the value to be subtracted by the selection signals 415 and 417 from the comparators 409 and 416 with respect to the subtracter provided in the error calculator 410.

  The new error amount output from the error calculator 410 is weighted corresponding to that in FIG. 7 by the error distributor 411, and the result is output to each adder 404, 406, 409 and latch 401. The error weighted with “W 3” is latched in the latch 401, and is added by the adder 404 with the error weighted with “W 2” generated by calculating the error of the next pixel. The output of the adder 404 is latched in the latch 402 and further added by the adder 405 with a weighted error of “W 1” generated by the error calculation of the next pixel. The output of the adder 405 is temporarily stored in the error buffer to delay the data for one line, and is read when the next line is processed.

  The adder 406 adds the read value from the error buffer delayed by one line and the weighted error amount of “W 4” and latches the addition result in the latch 403. The latch 403 outputs the sum of the diffused errors as a correction amount. Thereafter, returning to the adder 407 and sequentially adding with the input image data 414, the binarized image data is output from the comparator 409.

  The configuration of the subsequent binary / quaternary developing unit 600 is as described above with reference to FIG.

  As described above, by switching the output pattern of m-value error diffusion in the specific density area of the input image data, even if the m-valued data is dot-developed for output to the printer 700, the low density In addition, generation of a dot pattern having a high frequency component is suppressed, and printing with excellent gradation characteristics can be performed without causing image roughness even in a co-cost printer.

  FIGS. 14 to 18 show flowcharts when the above-described functions are realized by software. A control program for executing these processes is stored in the program memory 122 and executed under the control of the CPU 120.

  FIG. 14 is a flowchart showing the spatial filter processing in the present embodiment.

  First, in step S1, the input image data (8 bits) is sequentially stored in the line buffers 201 and 202 in synchronization with the clock (DCLK). As described above, the line buffer 201 shifts right by 2 bits and stores it as 6-bit data. After the image data for two lines is stored in the line buffers 201 and 202 in this way, the pixel data of 3 lines × 3 pixels is latched in the latch group 203 in synchronization with the input of the image data of the next line, and the filter matrix and Multiply (step S2). The value obtained in this way is added to the pixel of interest, and pixel data subjected to filter calculation is output (step S3). The filter calculation formula at this time is represented by filter = X << 2-((A << 2) + (B << 2) + C + D).

  FIG. 15 is a flowchart showing luminance-density conversion processing.

  This luminance-density conversion process is determined depending on whether binary or quaternary processing is performed in the subsequent quaternary / binarization processing. That is, if it is determined in step S11 that binary processing is to be performed, the process proceeds to step S12, where processing is performed to convert all white of 8-bit data to “0” and all black to “63” density data. If it is determined in step S11 that quaternary processing is to be performed, the process proceeds to step S13, where processing is performed to convert all white of 8-bit data to “0” and all black to “255” density data. In step S14, if there is a density (density value “31” in the above example) that causes image roughness in the printer 700, conversion to the density value is not performed. Such luminance-density conversion is preferably performed using a lookup table.

  FIG. 16 is a flowchart showing binary / quaternarization processing. This processing is performed using binary or quaternary error diffusion processing.

  First, in step S21, the correction density X′ij of the pixel of interest Xij is obtained. When the error of the previous line is stored in the error buffer, the correction density is determined using the value stored in the error buffer. In step S22, it is determined whether binary or quaternary error diffusion is to be performed. If quaternary error diffusion is to be performed, the process proceeds to step S23, where the above equations (1) to (4) are used. As shown, an output level (OUTPUT) and an error (E) are obtained from three threshold values. When binary error diffusion is performed, the process proceeds to step S24, where an output pixel value (OUTPUT) and an error (E) are determined based on the threshold value (BTH1) as shown in the equations (5) and (6).

  When the error is thus determined, the process proceeds to step S25, where the weighted addition shown in FIG. 7 is executed, and the error (E) obtained thereby is clamped to 6-bit data (step S26). In step S27, the obtained error (E) is stored in the error buffer and delayed by one line, and the delayed error is referred to in the error diffusion process of the pixel on the next line.

  FIG. 17 is a flowchart showing processing for developing binary / quaternary data into binary data (expressed by small dots).

  In FIG. 17, the density gradient of the image is obtained, and the arrangement of small dots is determined according to the density gradient. That is, in step S31, m-value image data is input, and it is determined whether the density gradient of the pixels located on the left and right (main scanning direction) of the arrival pixel of the image data is rising to the right or falling to the right (step S32). ), The above-mentioned pattern 0 (dots are developed from the right side) is selected if it rises to the right (step S33), and the above-mentioned pattern 1 (dots are developed from the left side) is selected if it goes down to the right (step S33). Step S34).

  In addition, when there is no density gradient, the arrangement of small dots is determined depending on whether the target pixel is an odd-numbered pixel or an even-numbered pixel. That is, in step S32, m-value image data is input, and it is checked whether the destination pixel of the image data has a density gradient. If there is no density gradient, whether the pixel of interest is an odd-numbered pixel or an even-numbered pixel. (Step S35). If it is an odd-numbered pixel, pattern 1 (dots are developed from the left side) is selected (step S36), and if it is an even-numbered pixel, pattern 0 (dots are developed from the right side) is selected (step S37). ).

  FIG. 18 is a flowchart showing binary / quaternarization processing according to another embodiment of the present invention.

  First, in step S51, it is determined whether or not the input image data corresponds to a specific density range having a density that causes image unevenness in the printer 700. If it is determined that the density is out of the specific density range, the process proceeds to step S22 in FIG. 16 to execute the above-described processing.

  If determined to be within the specific density range, the process proceeds to step S52, where a corrected density value obtained by adding the diffused error to the input image data is obtained, and the corrected density value is compared with a threshold value for comparison. . If the corrected density value is larger, the process proceeds to step S53 where the output pixel density (OUTPUT) is set to “2” and the error at that time is obtained. If the corrected density value is smaller, the process proceeds to step S54 where the output pixel density (OUTPUT) is set to “0” and the error at that time is obtained. When the process of step S53 or step S54 is completed in this way, the process proceeds to step S25 of FIG. 16, and the above-described process is executed.

  Note that the present invention can be applied to a system composed of a plurality of devices (for example, a copier, a facsimile machine, etc.) even if it is applied to a system composed of a plurality of devices (for example, a host computer, interface device, reader, printer, etc.). You may apply.

  Another object of the present invention is to supply a storage medium storing software program codes for implementing the functions of the above-described embodiments to a system or apparatus, and the computer (or CPU or MPU) of the system or apparatus stores the storage medium. This can also be achieved by reading and executing the program code stored in.

  In this case, the program code itself read from the storage medium realizes the functions of the above-described embodiments, and the storage medium storing the program code constitutes the present invention.

  As a storage medium for supplying the program code, for example, a floppy disk, a hard disk, an optical disk, a magneto-optical disk, a CD-ROM, a CD-R, a magnetic tape, a nonvolatile memory card, a ROM, or the like can be used.

  Further, by executing the program code read by the computer, not only the functions of the above-described embodiments are realized, but also an OS (operating system) operating on the computer based on the instruction of the program code. A case where part or all of the actual processing is performed and the functions of the above-described embodiments are realized by the processing is also included.

  Further, after the program code read from the storage medium is written into a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer, the function expansion is performed based on the instruction of the program code. This includes a case where the CPU or the like provided in the board or the function expansion unit performs part or all of the actual processing, and the functions of the above-described embodiments are realized by the processing.

  As described above, according to the present embodiment, the number of bits of the line buffer for extracting the reference data in the sub-scanning direction in the spatial filter processing unit is reduced, and further the luminance density according to binarization and quaternization. By switching the output range of conversion, and in the quaternarization process, the error data stored in the error buffer by error diffusion is clamped to the number of significant digits of error diffusion at the time of binarization, so that the common block Therefore, it is possible to generate image data that makes the most of the capacity of the recording system at the time of copying.

It is a functional block diagram which shows the function structure of the image processing apparatus in embodiment of this invention. It is a block diagram which shows the structure of the image processing apparatus in embodiment of this invention. It is a figure which shows the example (A) of the coefficient of the spatial filter in this Embodiment, and a response | compatibility (B) with each line buffer. It is a block diagram which shows the structure of the spatial filter process part in this Embodiment. It is a timing chart for demonstrating the timing of the memory access in the spatial filter process part of this Embodiment. It is a figure which shows the brightness | luminance-density conversion characteristic (A) of the binary error diffusion process part in this Embodiment, and the brightness | luminance-density conversion characteristics (B) (C) of a quaternary error diffusion process part. It is a figure which shows the weighting of the error distribution of the binary and quaternary error diffusion process in this Embodiment. It is a block diagram which shows the structure of the binary and quaternary error diffusion process part in this Embodiment. It is a figure which shows the example of a recording characteristic of 4 value data in this Embodiment. FIG. 4A is a diagram for explaining generation of pseudo lines at an edge portion of image data, and FIG. 6B is a diagram showing an example in which generation of pseudo lines is suppressed according to the present embodiment. It is a block diagram which shows the structure of the binary and quaternary expansion part in this Embodiment. It is a figure which shows the correspondence (A) with the recording density of the density | concentration of the data of the conventional 4-value development, and the correspondence (B) with the recording density of the density of the data of the 4-value development in this embodiment. It is a block diagram which shows the structure of the binary and quaternary error diffusion process part in other embodiment of this invention. It is a flowchart which shows the spatial filter process in the image processing apparatus of this Embodiment. It is a flowchart which shows the luminance-density conversion process in the image processing apparatus of this Embodiment. 4 is a flowchart showing binary / quaternarization processing in the image processing apparatus according to the present embodiment. It is a flowchart which shows the binary and quaternary expansion process in the image processing apparatus of this Embodiment. It is a flowchart which shows the binary and quaternarization process in the image processing apparatus of the other embodiment of this embodiment.

Explanation of symbols

100 Scanner 120 CPU
121 RAM
122 Program memory 123 Look-up table (LUT)
124 Laplacian filter value 200 Spatial filter 201, 202 Line buffer 203 Latch group 300 Luminance-density conversion unit 400 Four-value / binarization processing unit 401, 402, 403 Latch 404, 405, 406, 407 Adder 408 Clamp circuit 409 , 416 Comparator 410 Error calculator 411 Error distributor 500 Image memory 600 Binary / quaternary developing unit 700 Printer

Claims (8)

Image input means for inputting multivalued image data in which one pixel is represented by an n value;
Filter means for performing spatial filter processing on the multivalued image data input by the image input means;
Processing means for converting each pixel data of the image data into m (2 <m <n) values for the image data filtered by the filter means;
Dot arrangement means for converting the pixel data converted to m-value by the processing means into (m−1) dot arrangement having a resolution higher than the resolution of the pixel data;
The dot arrangement means is m-valued so that even-numbered pixel on-dots and odd-numbered pixel on-dots of the pixel data m-valued by the processing means are continuously and symmetrically arranged. An image processing apparatus for converting pixel data of halftone expression into the dot array. The image processing apparatus according to claim 1, wherein the value of m is 4, and the dot arrangement unit converts the m-valued pixel data into an array of three dots. Before Symbol dot arrangement means such that said ON dots according to the concentration gradient of the neighboring pixels of the target pixel of the pixel data is arranged, the pixel data of the m-valued edge portion (m-1) number of The image processing apparatus according to claim 1, wherein the image processing apparatus is converted into a dot array. The value of m is 4, and the dot arrangement means converts the m-valued pixel data into an array of three dots, and when the density gradient is rising to the right, the dots are arranged from the right side. The image processing apparatus according to claim 3, wherein when the density gradient is lowering to the right, the dots are arranged from the left side. An image input step of inputting multivalued image data in which one pixel is represented by an n value;
A filtering step of performing spatial filtering on the multi-valued image data input in the image input step;
A processing step of converting each pixel data of the image data into m (2 <m <n) values for the image data filtered in the filtering step;
A dot arrangement step of converting the pixel data converted to m-value in the processing step into (m−1) dot arrangements having a resolution higher than the resolution of the pixel data,
In the dot arrangement step, the m-value is converted so that the even-numbered pixel on-dots and the odd-numbered pixel on-dots are continuously and symmetrically arranged in the pixel data m-valued in the processing step. An image processing method comprising: converting halftone representation pixel data into the dot arrangement. 6. The image processing method according to claim 5, wherein the value of m is 4, and in the dot arrangement step, the m-valued pixel data is converted into an array of three dots. Prior Symbol dot arrangement step, wherein as according to the concentration gradient of the neighboring pixels of the target pixel of the pixel data on dots are arranged, the pixel data of the m-valued edge portion (m-1) number of The image processing method according to claim 5, wherein the image processing method is converted into a dot array. The value of m is 4, and in the dot arrangement step, m-valued pixel data is converted into three dot arrangements, and when the density gradient rises to the right, the dots are arranged from the right side. The image processing method according to claim 7, wherein when the density gradient is descending to the right, the dots are arranged from the left side.

Images