JP3811176B2 - Liquid crystal display - Google Patents

Description

  The present invention relates to a liquid crystal display device, and more particularly to an active matrix liquid crystal display device using thin film transistors and the like.

  An active matrix type liquid crystal display device is provided with a nonlinear element (switching element) corresponding to each of a plurality of pixel electrodes arranged in a matrix. Since the liquid crystal in each pixel is theoretically driven at all times (duty ratio 1.0), the active method has a better contrast than the so-called simple matrix method, which employs the time-division driving method. Now it is becoming an indispensable technology. A typical switching element is a thin film transistor (TFT).

A liquid crystal display unit (liquid crystal display panel) is a lower part in which a thin film transistor, a transparent pixel electrode, a protective film for a thin film transistor, and a lower alignment film for setting the orientation of liquid crystal molecules are sequentially provided on a lower transparent glass substrate with the liquid crystal layer as a reference. The substrate and the upper substrate on which the black matrix, the color filter, the color filter protective film, the common transparent pixel electrode, and the upper alignment film are sequentially provided on the upper transparent glass substrate are overlapped so that the alignment films face each other. Both substrates are bonded together with a sealing material disposed around the edge of the substrate and the liquid crystal is sealed between the substrates. A backlight is disposed on the lower substrate side.
Note that an active matrix type liquid crystal display device using a thin film transistor is known, for example, in Patent Document 1 and Non-Patent Document 1 below.

JP-A 63-309921 "12.5 inch active matrix color liquid crystal display with redundant configuration", Nikkei Electronics, pp. 193-210, December 15, 1986, published by Nikkei McGraw-Hill

The conventional liquid crystal display device has a separate storage case for the backlight and a reflector made of a metal plate such as aluminum for reflecting the light from the backlight toward the liquid crystal display, and has a large number of parts. There is a problem that the structure is complicated and the manufacturing cost is high.
One object of the present invention is to provide a liquid crystal display device that can reduce the number of components, another object is to simplify the structure, and still another object is to reduce the manufacturing cost.

In order to solve the above-mentioned problems, a liquid crystal display device of the present invention includes a liquid crystal display panel, a shield case made of a metal plate that covers the periphery of the liquid crystal display panel, and a direct backlight having a plurality of fluorescent tubes. A backlight support that supports the backlight, and a lower case that is fixed to the shield case, has a backlight light reflecting surface, and houses the backlight. The light support has a plurality of recesses formed outward from the end of the backlight light reflecting surface, and each of the ends of the plurality of fluorescent tubes is formed of silicon in each of the plurality of recesses. is fitted through the rubber, the respective ends of the fluorescent tube of the plurality of, in each of the plurality of recesses are connected to the lead wire, the lead wire, Serial is led from the lead line lead hole provided in each of the plurality of recesses, the backlight support is characterized in that it is fixed to the lower case.
Further, the liquid crystal display device of the present invention supports a liquid crystal display panel, a shield case made of a metal plate covering the periphery of the liquid crystal display panel, a direct type backlight having a plurality of fluorescent tubes, and the backlight. And a backlight support having an inner surface combined from a plurality of planes, and a lower case fixed to the shield case, having a backlight light reflecting surface, and housing the backlight. The backlight support has a plurality of recesses formed outward from the end of the backlight light reflecting surface, and each of the ends of the plurality of fluorescent tubes is the plurality of the plurality of recesses. of which is fitted through the silicon rubber respective recesses, each of the end portions of the fluorescent tubes of the plurality of, in each of the plurality of recesses, it is connected to a lead wire , The lead wire, the plurality of is led from the lead line lead hole provided in the respective recesses, the backlight support in a state where an end portion of said plurality of fluorescent tubes have been fitted into the front Stories It is fixed to the lower case.
Further, the liquid crystal display device of the present invention supports a liquid crystal display panel, a shield case made of a metal plate covering the periphery of the liquid crystal display panel, a direct type backlight having a plurality of fluorescent tubes, and the backlight. A backlight support, a lower case that is fixed to the shield case, has a backlight light reflecting surface, and stores the backlight, and an inverter connected to the lead wires connected to the plurality of fluorescent tubes A liquid crystal display device having a circuit board, wherein the backlight support has a plurality of concave portions formed outward from an end portion of the backlight light reflecting surface, and the plurality of fluorescent tubes. each of the ends is fitted through the silicon rubber to each of the plurality of recesses, wherein each end of the plurality of fluorescent tubes, each of the plurality of recesses In the middle, the is connected to the lead wire, the lead wire, the plurality of is led from the lead line lead hole provided in the respective recesses, the backlight support is fixed to the lower case The inverter circuit board is also fixed through a fixing hole in the lower case.
Further, the liquid crystal display device of the present invention supports a liquid crystal display panel, a shield case made of a metal plate covering the periphery of the liquid crystal display panel, a direct type backlight having a plurality of fluorescent tubes, and the backlight. A backlight support, a lower case that is fixed to the shield case, has a backlight light reflecting surface, and stores the backlight, and an inverter connected to the lead wires connected to the plurality of fluorescent tubes A liquid crystal display device comprising: a circuit board; a drive IC chip connected to the liquid crystal display panel; and a drive circuit board having a power supply circuit that supplies a plurality of divided voltages to the drive IC chip. , the backlight support has a plurality of recesses formed toward outside the end portion of the backlight light reflecting surface, the ends of the fluorescent tube of the plurality of Respectively are fitted through the silicon rubber to each of the plurality of recesses, each of the end portions of the fluorescent tubes of the plurality of, in each of the plurality of recesses, are connected to the lead wire The lead wire is drawn out from a lead wire lead hole provided in each of the plurality of recesses, the backlight support is fixed to the lower case, and the inverter circuit board is also It is fixed through a fixing hole in the lower case, and the inverter circuit board and the drive circuit board do not overlap in the vertical direction.

  According to the present invention, the number of parts can be reduced, the structure can be simplified, and the manufacturing cost can be reduced. Therefore, the vibration shock resistance and thermal shock resistance of the liquid crystal display module can be improved, and the reliability can be improved.

The present invention, other objects of the present invention, and other features of the present invention will be apparent from the following description with reference to the drawings.
<Active matrix liquid crystal display device>
An embodiment in which the present invention is applied to an active matrix color liquid crystal display device will be described below. In the drawings described below, components having the same function are denoted by the same reference numerals, and repeated description thereof is omitted.

<Outline of the matrix part>
FIG. 1 is a plan view showing one pixel of an active matrix color liquid crystal display device to which the present invention is applied and its periphery, FIG. 2 is a cross-sectional view taken along line 2-2 in FIG. 1, and FIG. It is sectional drawing in 3-3 cutting line. FIG. 4 is a plan view when a plurality of the pixels shown in FIG. 1 are arranged.

  As shown in FIG. 1, each pixel includes two adjacent scanning signal lines (gate signal lines or horizontal signal lines) GL and two adjacent video signal lines (drain signal lines or vertical signal lines) DL. They are arranged in the intersection area (in the area surrounded by four signal lines). Each pixel includes a thin film transistor TFT, a transparent pixel electrode ITO1, and a storage capacitor element Cadd. The scanning signal lines GL extend in the column direction, and a plurality of scanning signal lines GL are arranged in the row direction. The video signal lines DL extend in the row direction, and a plurality of video signal lines DL are arranged in the column direction.

  As shown in FIG. 2, a thin film transistor TFT and a transparent pixel electrode ITO1 are formed on the lower transparent glass substrate SUB1 side based on the liquid crystal LC, and a color filter FIL and a light blocking black matrix pattern BM are formed on the upper transparent glass substrate SUB2 side. Is formed. The lower transparent glass substrate SUB1 has a thickness of about 1.1 mm, for example. In addition, silicon oxide films SIO formed by dipping or the like are provided on both surfaces of the transparent glass substrates SUB1 and SUB2. For this reason, even if there are sharp scratches on the surfaces of the transparent glass substrates SUB1 and SUB2, the sharp scratches can be covered with the silicon oxide film SIO. The film quality can be kept homogeneous.

  A light shielding film BM, a color filter FIL, a protective film PSV2, a common transparent pixel electrode ITO2 (COM), and an upper alignment film ORI2 are sequentially stacked on the inner surface (liquid crystal LC side) of the upper transparent glass substrate SUB2. Yes.

<Outline of the matrix area>
16 is a plan view of the main part around the matrix (AR) of the display panel PNL including the upper and lower glass substrates SUB1 and SUB2, FIG. 17 is a plan view of the peripheral part further exaggerated, and FIG. 18 is the panel of FIGS. It is a figure which shows the expansion plane of seal | sticker part SL vicinity corresponding to an upper left corner | angular part. FIG. 19 is a diagram showing a cross section taken along the section line 19a-19a in FIG. 18 on the left side and a cross section in the vicinity of the external connection terminal DTM to which the video signal driving circuit is to be connected on the right side, with the cross section of FIG. is there. Similarly, FIG. 20 is a diagram showing a cross section near the external connection terminal GTM to which the scanning circuit is to be connected on the left side, and a cross section near the seal portion where there is no external connection terminal on the right side.

  In the manufacture of this panel, if small size divided from simultaneously processing a plurality fraction of the device in one glass substrate for improving throughput, standardized any breed for shared manufacturing facilities if large size After processing the glass substrate of the size, the glass substrate is reduced to a size suitable for each type, and in any case, the glass is cut after going through a single process. FIGS. 16 to 18 show the latter example. Both FIGS. 16 and 17 show the state after cutting the upper and lower substrates SUB1 and SUB2, FIG. 18 shows the state before cutting, and LN shows the state before cutting both substrates. Numerals CT1 and CT2 indicate positions where the substrates SUB1 and SUB2 should be cut, respectively. In any case, in the completed state, the size of the upper substrate SUB2 is set so that the external connection terminal groups Tg and Td (subscript omitted) exist (the upper and lower sides and the left side in the drawing) are exposed so that the lower substrate SUB1 is exposed. Is restricted to the inside. The terminal groups Tg, Td are respectively a scanning circuit connection terminal GTM and a video signal circuit connection terminal DTM, which will be described later, and a tape carrier package TCP (FIGS. 20 and 21) on which an integrated circuit chip CHI is mounted. Multiple units are named collectively. The lead-out wiring from the matrix portion of each group to the external connection terminal portion is inclined as it approaches both ends. This is to match the terminals DTM and GTM of the display panel PNL to the arrangement pitch of the package TCP and the connection terminal pitch in each package TCP.

  A seal pattern SL is formed between the transparent glass substrates SUB1 and SUB2 so as to seal the liquid crystal LC along the edge except for the liquid crystal sealing inlet INJ. The sealing material is made of, for example, an epoxy resin. The common transparent pixel electrode ITO2 on the upper transparent glass substrate SUB2 side is connected to the lead-out wiring INT formed on the lower transparent glass substrate SUB1 side by silver paste material AGP at four corners of the panel in this embodiment in at least one place. ing. The lead-out wiring INT is formed in the same manufacturing process as a gate terminal GTM and a drain terminal DTM described later.

  The alignment films ORI1 and ORI2, the transparent pixel electrode ITO1, and the common transparent pixel electrode ITO2 are formed on the inner side of the seal pattern SL. The polarizing plates POL1 and POL2 are formed on the outer surfaces of the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2, respectively. The liquid crystal LC is sealed in a region partitioned by a seal pattern SL between the lower alignment film ORI1 and the upper alignment film ORI2 that set the direction of liquid crystal molecules. The lower alignment film ORI1 is formed on the protective film PSV1 on the lower transparent glass substrate SUB1 side.

  In this liquid crystal display device, various layers are separately stacked on the lower transparent glass substrate SUB1 side and the upper transparent glass substrate SUB2 side, and a seal pattern SL is formed on the substrate SUB2 side, so that the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2 are formed. And the liquid crystal LC is injected from the opening INJ of the sealing material SL, the injection port INJ is sealed with an epoxy resin or the like, and the upper and lower substrates are cut.

<< Thin Film Transistor TFT >>
The thin film transistor TFT operates such that when a positive bias is applied to the gate electrode GT, the channel resistance between the source and the drain decreases, and when the bias is set to zero, the channel resistance increases.

  The thin film transistor TFT of each pixel is divided into two (plural) in the pixel, and is composed of thin film transistors (divided thin film transistors) TFT1 and TFT2. Each of the thin film transistors TFT1 and TFT2 has substantially the same size (channel length and channel width are the same). Each of the divided thin film transistors TFT1 and TFT2 includes an i-type semiconductor made of a gate electrode GT, a gate insulating film GI, i-type (intrinsic, intrinsic, conductivity type-determining impurity is not doped) amorphous silicon (Si). It has a layer AS, a pair of source electrodes SD1, and a drain electrode SD2. It should be understood that the source and drain are originally determined by the bias polarity between them, and the polarity is inverted during operation in the circuit of this liquid crystal display device, so that the source and drain are interchanged during operation. However, in the following description, for convenience, one is fixed as a source and the other is fixed as a drain.

<< Gate electrode GT >>
As shown in FIG. 5 (a plan view depicting only the second conductive film g2 and the i-type semiconductor layer AS in FIG. 1), the gate electrode GT is perpendicular to the scanning signal line GL (upward in FIGS. 1 and 5). It is comprised by the shape which protrudes in (it is branched by the T-shape). The gate electrode GT protrudes beyond the active regions of the thin film transistors TFT1 and TFT2. The gate electrodes GT of the thin film transistors TFT1 and TFT2 are integrally formed (as a common gate electrode) and are formed continuously with the scanning signal line GL. In this example, the gate electrode GT is formed of a single-layer second conductive film g2. For example, an aluminum (Al) film formed by sputtering is used as the second conductive film g2 and is formed with a film thickness of about 1000 to 5500 mm. An Al anodic oxide film AOF is provided on the gate electrode GT.

  As shown in FIGS. 1, 2, and 5, the gate electrode GT is formed larger than the i-type semiconductor layer AS (as viewed from below). Therefore, when a backlight BL such as a fluorescent lamp is attached below the lower transparent glass substrate SUB1, the opaque Al gate electrode GT is shaded and the i-type semiconductor layer AS is not exposed to the backlight. In addition, the conductive phenomenon due to light irradiation, that is, the off-characteristic deterioration of the thin film transistor TFT is less likely to occur. Note that the original size of the gate electrode GT is the minimum required to cross between the source electrode SD1 and the drain electrode SD2 (including the alignment margin between the gate electrode GT, the source electrode SD1, and the drain electrode SD2). ) Has a width and the depth length that determines the channel width W is a ratio of the distance (channel length) L between the source electrode SD1 and the drain electrode SD2, that is, a factor W / L that determines the mutual conductance gm. It depends on what you do. The size of the gate electrode GT in this liquid crystal display device is of course made larger than the original size described above.

<< Scanning signal line GL >>
The scanning signal line GL is composed of the second conductive film g2. The second conductive film g2 of the scanning signal line GL is formed in the same manufacturing process as the second conductive film g2 of the gate electrode GT and is integrally formed. An Al anodic oxide film AOF is also provided on the scanning signal line GL.

<Insulating film GI>
The insulating film GI is used as a gate insulating film of each of the thin film transistors TFT1 and TFT2. The insulating film GI is formed above the gate electrode GT and the scanning signal line GL. For example, a silicon nitride film formed by plasma CVD is used as the insulating film GI and is formed with a film thickness of 1200 to 2700 mm (in this liquid crystal display device, a film thickness of about 2000 mm). As shown in FIG. 18, the gate insulating film GI is formed so as to surround the entire matrix portion AR, and the peripheral portion is removed so as to expose the external connection terminals DTM and GTM.

<< i-type semiconductor layer AS >>
As shown in FIG. 5, the i-type semiconductor layer AS is used as a channel formation region of each of the thin film transistors TFT1 and TFT2 divided into a plurality. The i-type semiconductor layer AS is formed of an amorphous silicon film or a polycrystalline silicon film, and has a thickness of 200 to 2200 mm (in this liquid crystal display device, a thickness of about 2000 mm).

This i-type semiconductor layer AS is formed by using the same plasma CVD apparatus in succession to the formation of the insulating film GI used as a gate insulating film made of Si ₃ N ₄ by changing the components of the supply gas. It is formed without being exposed to the outside. Similarly, the N ⁺ type semiconductor layer d0 (FIG. 2) doped with 2.5% of phosphorus (P) for ohmic contact is continuously 200 to 500 mm thick (in this liquid crystal display device, about 300 mm thick). Thickness). Thereafter, the lower transparent glass substrate SUB1 is taken out from the CVD apparatus, and the N ⁺ type semiconductor layer d0 and the i type semiconductor layer AS are formed into independent islands as shown in FIGS. 1, 2 and 5 by photographic processing technology. Is patterned.

  As shown in FIGS. 1 and 5, the i-type semiconductor layer AS is also provided between both intersections (crossover portions) between the scanning signal lines GL and the video signal lines DL. This crossing portion i-type semiconductor layer AS reduces a short circuit between the scanning signal line GL and the video signal line DL at the crossing portion.

<< Transparent pixel electrode ITO1 >>
The transparent pixel electrode ITO1 constitutes one of the pixel electrodes of the liquid crystal display unit.
The transparent pixel electrode ITO1 is connected to both the source electrode SD1 of the thin film transistor TFT1 and the source electrode SD1 of the thin film transistor TFT2. For this reason, even if a defect occurs in one of the thin film transistors TFT1 and TFT2, if the defect causes a side effect, an appropriate portion is cut by a laser beam or the like, and if not, the other thin film transistor operates normally. You can just leave it. It is rare that two thin film transistors TFT1 and TFT2 have defects at the same time, and the probability of point defects and line defects can be extremely reduced by such a redundancy method. The transparent pixel electrode ITO1 is composed of a first conductive film d1, and the first conductive film d1 is made of a transparent conductive film (Indium-Tin-Oxide ITO) formed by sputtering, and has a film thickness of 1000 to 2000 mm. It is formed with a thickness (in this liquid crystal display device, a film thickness of about 1400 mm).

<< Source electrode SD1, drain electrode SD2 >>
The source electrode SD1 and the drain electrode SD2 of each of the thin film transistors TFT1 and TFT2 divided into a plurality are shown in FIGS. 1, 2, and 6 (a plan view depicting only the first to third conductive films d1 to d3 in FIG. As shown in FIG. 2, the i-type semiconductor layer AS is provided separately from each other.

Each of the source electrode SD1 and the drain electrode SD2 is configured by sequentially stacking a second conductive film d2 and a third conductive film d3 from the lower layer side in contact with the N ⁺ type semiconductor layer d0. The second conductive film d2 and the third conductive film d3 of the source electrode SD1 are formed in the same manufacturing process as the second conductive film d2 and the third conductive film d3 of the drain electrode SD2.

The second conductive film d2 is formed of a chromium (Cr) film formed by sputtering and has a thickness of 500 to 1000 mm (in this liquid crystal display device, a thickness of about 600 mm). The Cr film is formed in a range that does not exceed a thickness of about 2000 mm because stress increases as the film thickness increases. The Cr film has good contact with the N ⁺ type semiconductor layer d0. The Cr film constitutes a so-called barrier layer that prevents Al of a third conductive film d3 described later from diffusing into the N ⁺ type semiconductor layer d0. As the second conductive film d2, a refractory metal (Mo, Ti, Ta, W) film or a refractory metal silicide (MoSi ₂ , TiSi ₂ , TaSi ₂ , WSi ₂ ) film may be used in addition to the Cr film.

  The third conductive film d3 is formed to a thickness of 3000 to 5000 mm (in this liquid crystal display device, a thickness of about 4000 mm) by sputtering of Al. The Al film is less stressed than the Cr film, can be formed thick, and is configured to reduce the resistance values of the source electrode SD1, the drain electrode SD2, and the video signal line DL. In addition to the pure Al film, an Al film containing silicon or copper (Cu) as an additive may be used as the third conductive film d3.

After patterning the second conductive film d2 and the third conductive film d3 with the same mask pattern, the N ⁺ type semiconductor layer d0 is removed using the same mask or using the second conductive film d2 and the third conductive film d3 as a mask. Is done. That is, the N ⁺ -type semiconductor layer d0 remaining on the i-type semiconductor layer AS is removed by self-alignment except for the second conductive film d2 and the third conductive film d3. At this time, since the N ⁺ type semiconductor layer d0 is etched so that the entire thickness thereof is removed, the surface portion of the i type semiconductor layer AS is also slightly etched, but the degree can be controlled by the etching time. Good.

The source electrode SD1 is connected to the transparent pixel electrode ITO1. The source electrode SD1 is obtained by adding the steps of the i-type semiconductor layer AS (the thickness of the second conductive film g2, the thickness of the anodic oxide film AOF, the thickness of the i-type semiconductor layer AS, and the thickness of the N ⁺ -type semiconductor layer d0). It is configured along a step corresponding to the film thickness. Specifically, the source electrode SD1 includes a second conductive film d2 formed along the step of the i-type semiconductor layer AS, and a third conductive film d3 formed on the second conductive film d2. ing. The third conductive film d3 of the source electrode SD1 cannot be formed thick because the Cr film of the second conductive film d2 increases due to increased stress, and the step shape of the i-type semiconductor layer AS cannot be overcome. Is configured for. In other words, step coverage is improved by forming the third conductive film d3 thick. Since the third conductive film d3 can be formed thick, it greatly contributes to the reduction of the resistance value of the source electrode SD1 (the same applies to the drain electrode SD2 and the video signal line DL).

<< Protective film PSV1 >>
A protective film PSV1 is provided on the thin film transistor TFT and the transparent pixel electrode ITO1. The protective film PSV1 is formed mainly to protect the thin film transistor TFT from moisture and the like, and a film having high transparency and good moisture resistance is used. The protective film PSV1 is formed of, for example, a silicon oxide film or a silicon nitride film formed by a plasma CVD apparatus, and is formed with a film thickness of about 1 μm.

  As shown in FIG. 18, the protective film PSV1 is formed so as to surround the entire matrix part AR, the peripheral part is removed so as to expose the external connection terminals DTM and GTM, and the common electrode COM on the upper substrate side SUB2 is placed below. The portion connected to the external connection terminal connection lead line INT of the side substrate SUB1 by the silver paste AGP is also removed. Regarding the thickness relationship between the protective film PSV1 and the gate insulating film GI, the former is increased in consideration of the protective effect, and the latter is decreased in the mutual conductance gm of the transistor. Accordingly, as shown in FIG. 18, the protective film PSV1 having a high protective effect is formed larger than the gate insulating film GI so as to protect the peripheral portion over as wide a range as possible.

<< Light shielding film BM >>
A light shielding film BM is provided on the upper transparent glass substrate SUB2 side so that external light (light from above in FIG. 2) does not enter the i-type semiconductor layer AS used as a channel formation region. The pattern is as shown by hatching in FIG. FIG. 7 is a plan view illustrating only the first conductive film d1, the color filter FIL, and the light shielding film BM made of the ITO film in FIG. The light shielding film BM is formed of, for example, an aluminum film or a chromium film having a high light shielding property. In this liquid crystal display device, the chromium film is formed to a thickness of about 1300 mm by sputtering.

  Accordingly, the i-type semiconductor layer AS of the thin film transistors TFT1 and TFT2 is sandwiched by the upper and lower light shielding films BM and the large gate electrode GT, and the portion is not exposed to external natural light or backlight light. As shown by the hatched portion in FIG. 7, the light shielding film BM is formed around the pixels, that is, the light shielding film BM is formed in a lattice shape (black matrix), and an effective display area of one pixel is partitioned by this lattice. . Therefore, the outline of each pixel is clear by the light shielding film BM, and the contrast is improved. That is, the light shielding film BM has two functions of light shielding for the i-type semiconductor layer AS and a black matrix.

  In addition, since the portion (lower right portion in FIG. 1) facing the edge portion on the base side in the rubbing direction of the transparent pixel electrode ITO1 is shielded by the light shielding film BM, the domain can be seen even if the domain is generated in the above portion. Therefore, the display characteristics are not deteriorated.

  In addition, a backlight can be attached to the upper transparent glass substrate SUB2 side, and the lower transparent glass substrate SUB1 can be used as an observation side (external exposure side).

  As shown in FIG. 17, the light shielding film BM is also formed in a frame-like pattern as shown in FIG. 17, and the pattern is formed continuously with the pattern of the matrix portion shown in FIG. . As shown in FIGS. 17 to 20, the light shielding film BM in the peripheral portion is extended to the outside of the seal portion SL to prevent leakage light such as reflected light caused by a mounting machine such as a personal computer from entering the matrix portion. . On the other hand, the light-shielding film BM is retained about 0.3 to 1.0 mm from the edge of the substrate SUB2, and is formed so as to avoid the cutting region of the substrate SUB2.

<Color filter FIL>
The color filter FIL is configured by coloring a dye on a dyeing substrate formed of a resin material such as an acrylic resin. The color filters FIL are formed in stripes at positions facing the pixels (FIG. 8) and dyed separately (FIG. 8 shows only the first conductive film d1, the light shielding film BM, and the color filter FIL in FIG. 4). The B, R, and G color filters FIL are cross hatched at 45 ° and 135 °, respectively. As shown in FIGS. 7 and 9, the color filter FIL is formed in a large size so as to cover all of the transparent pixel electrode ITO1, and the light shielding film BM overlaps the edge portions of the color filter FIL and the transparent pixel electrode ITO1. It is formed inside the peripheral edge.

  The color filter FIL can be formed as follows. First, a dyeing base material is formed on the surface of the upper transparent glass substrate SUB2, and the dyeing base material other than the red filter forming region is removed by a photolithography technique. Thereafter, the dyeing substrate is dyed with a red dye, and a fixing process is performed to form a red filter R. Next, a green filter G and a blue filter B are sequentially formed by performing the same process.

<< Protective film PSV2 >>
The protective film PSV2 is provided to prevent the dyes obtained by dyeing the color filter FIL into different colors from leaking into the liquid crystal LC. The protective film PSV2 is formed of a transparent resin material such as an acrylic resin or an epoxy resin.

<< Common transparent pixel electrode ITO2 >>
The common transparent pixel electrode ITO2 faces the transparent pixel electrode ITO1 provided for each pixel on the lower transparent glass substrate SUB1 side, and the optical state of the liquid crystal LC is between each pixel electrode ITO1 and the common transparent pixel electrode ITO2. Changes in response to potential difference (electric field). A common voltage Vcom is applied to the common transparent pixel electrode ITO2. In this embodiment, the common voltage Vcom is set to an intermediate potential between the low level driving voltage Vdmin and the high level driving voltage Vdmax applied to the video signal line DL. If it is desired to reduce the power supply voltage to about half, an AC voltage may be applied. Refer to FIGS. 17 and 18 for the planar shape of the common transparent pixel electrode ITO2.

<Gate terminal section>
9A and 9B are diagrams showing a connection structure from the scanning signal line GL of the display matrix to the external connection terminal GTM. FIG. 9A is a plan view, and FIG. 9B is a cross section taken along the line BB in FIG. ing. This figure corresponds to the vicinity of the lower part of FIG. 18, and the diagonal wiring portion is represented by a straight line for convenience.

AO is a mask pattern for photographic processing, in other words, a selective anodic oxidation photoresist pattern. Therefore, the photoresist is removed after anodic oxidation, and the pattern AO shown in the figure does not remain as a finished product. However, since the oxide film AOF is selectively formed on the gate wiring GL as shown in the cross-sectional view, the locus thereof is changed. Remains. In the plan view, on the basis of the boundary line AO of the photoresist, the left side is a region covered with resist and not anodized, and the right side is a region exposed from the resist and anodized. The anodized AL layer g2 is formed with the oxide Al ₂ O ₃ film AOF on the surface, and the volume of the conductive part below is reduced. Of course, the anodic oxidation is performed by setting an appropriate time and voltage so that the conductive portion remains. The mask pattern AO does not intersect with the scanning line GL on a single straight line, but bends in a crank shape and intersects.

  In the figure, the AL layer g2 is hatched for easy understanding, but the region that is not anodized is patterned in a comb shape. This is because whisker is generated on the surface when the width of the Al layer is wide, so that the width of each one is narrowed, and a configuration in which a plurality of them are bundled in parallel prevents disconnection of whiskers. The aim is to minimize the sacrifice of the probability and conductivity. Therefore, in this example, the portion corresponding to the root of the comb is also shifted along the mask AO.

  The gate terminal GTM has a good adhesion to the silicon oxide SIO layer and has a higher electric resistance than Al, etc., and a transparent conductive layer having the same level (same layer and simultaneous formation) as the pixel electrode ITO1. d1. Note that the conductive layers d2 and d3 formed on the gate insulating film GI and on the side surfaces thereof have regions so that the conductive layers g2 and g1 are not etched together due to pinholes during etching of the conductive layers d3 and d2. It remains as a result of covering with photoresist. Further, the ITO layer d1 extending over the gate insulating film GI and extending in the right direction is one in which the same measures are further taken.

  In the plan view, the gate insulating film GI is formed on the right side of the boundary line, and the protective film PSV1 is formed on the right side of the boundary line. The terminal portion GTM located at the left end is exposed from them and is electrically connected to the external circuit. Contact is made. In the figure, only one pair of the gate line GL and the gate terminal is shown, but actually, a plurality of such pairs are arranged vertically as shown in FIG. 18, and the terminal group Tg (FIGS. 17 and 18) is formed. In the manufacturing process, the left end of the gate terminal extends beyond the substrate cutting region CT1 and is short-circuited by the wiring SHg. Such a short-circuit line SHg in the manufacturing process is useful for feeding power during anodization and preventing electrostatic breakdown during rubbing of the alignment film ORI1.

<< Drain terminal DTM >>
10A and 10B are diagrams showing the connection from the video signal line DL to the external connection terminal DTM. FIG. 10A is a plan view, and FIG. 10B is a cross section taken along the line BB in FIG. FIG. 18 corresponds to the vicinity of the upper right of FIG. 18 and the direction of the drawing is changed for convenience, but the right end direction corresponds to the upper end (or lower end) of the substrate SUB1.

  TSTd is an inspection terminal, to which no external circuit is connected, but is wider than the wiring portion so that a probe needle or the like can be contacted. Similarly, the drain terminal DTM is also wider than the wiring portion so that it can be connected to an external circuit. A plurality of inspection terminals TSTd and external connection drain terminals DTM are alternately arranged in a staggered manner in the vertical direction, and the inspection terminals TSTd terminate without reaching the end of the substrate SUB1 as shown in the figure, but the drain terminals DTM As shown in FIG. 18, the terminal group Td (subscript omitted) is formed and further extended beyond the cutting line CT1 of the substrate SUB1, and all of them are short-circuited by the wiring SHd to prevent electrostatic breakdown during the manufacturing process. . A drain connection terminal is connected to the opposite side across the matrix of video signal lines DL where the inspection terminals TSTd exist, and conversely, an inspection terminal is located across the matrix of video signal lines DL where the drain connection terminals DTM exist. Is connected.

  The drain connection terminal DTM is formed of two layers of the Cr layer g1 and the ITO layer d1 for the same reason as the gate terminal GTM described above, and is connected to the video signal line DL at a portion where the gate insulating film GI is removed. The semiconductor layer AS formed on the end portion of the gate insulating film GI is for etching the edge of the gate insulating film GI in a tapered shape. Needless to say, the protective film PSV1 is removed on the terminal DTM for connection to an external circuit. AO is the anodic oxidation mask described above, and its boundary line is formed so as to largely surround the entire matrix. In the figure, the left side of the boundary line is covered with the mask, but the layer g2 is not covered in this figure. This pattern is not directly related because it does not exist.

  The lead-out wiring from the matrix portion to the drain terminal portion DTM has the same level as that of the video signal line DL immediately above the layers d1 and g1 at the same level as the drain terminal portion DTM, as shown in FIG. 19C. Although the layers d2 and d3 are laminated to the middle of the seal pattern SL, this minimizes the probability of disconnection and protects the Al layer d3 that is easy to contact with the protective film PSV1 and the seal pattern SL as much as possible. Is the aim.

<< Structure of Retention Capacitor Cadd >>
The transparent pixel electrode ITO1 is formed so as to overlap the adjacent scanning signal line GL at the end opposite to the end connected to the thin film transistor TFT. As is apparent from FIGS. 1 and 3, this superposition is performed by a storage capacitor element (capacitance element) in which the transparent pixel electrode ITO1 is one electrode PL2 and the adjacent scanning signal line GL is the other electrode PL1. Configure Cadd. The dielectric film of the storage capacitor element Cadd is composed of an insulating film GI used as a gate insulating film of the thin film transistor TFT and an anodic oxide film AOF.

  As is apparent from FIG. 5, the storage capacitor element Cadd is formed in a portion where the width of the second conductive film g2 of the scanning signal line GL is increased. Note that the portion of the second conductive film g2 that intersects with the video signal line DL is thinned to reduce the probability of a short circuit with the video signal line DL.

  Even if the transparent pixel electrode ITO1 is disconnected at the step portion of the electrode PL1 of the storage capacitor element Cadd, the defect is caused by the island region constituted by the second conductive film d2 and the third conductive film d3 formed so as to cross the step. Is compensated.

<< Equivalent circuit for the entire display device >>
FIG. 11 shows a connection diagram of an equivalent circuit of the display matrix portion and its peripheral circuits. Although this figure is a circuit diagram, it is drawn corresponding to the actual geometric arrangement. AR is a matrix array in which a plurality of pixels are arranged two-dimensionally.

  In the figure, X means a video signal line DL, and subscripts G, B, and R are added corresponding to green, blue, and red pixels, respectively. Y means the scanning signal line GL, and subscripts 1, 2, 3,..., End are added according to the order of scanning timing.

  The video signal lines X (subscript omitted) are alternately connected to the upper (or odd) video signal driving circuit He and the lower (or even) video signal driving circuit Ho.

  The scanning signal line Y (subscript omitted) is connected to the vertical scanning circuit V.

  SUP uses CRT (cathode ray tube) information from a power supply circuit or host (high-order processing unit) to obtain a plurality of stabilized voltage sources divided from one voltage source, and information for TFT liquid crystal display devices. This is a circuit including a circuit to be replaced.

<< Equivalent Circuit of Retention Capacitance Element Cadd and Its Operation >>
FIG. 12 shows an equivalent circuit of the pixel shown in FIG. In FIG. 12, Cgs is a parasitic capacitance formed between the gate electrode GT and the source electrode SD1 of the thin film transistor TFT. The dielectric films having the parasitic capacitance Cgs are the insulating film GI and the anodic oxide film AOF. Cpix is a liquid crystal capacitance formed between the transparent pixel electrode ITO1 (PIX) and the common transparent pixel electrode ITO2 (COM). The dielectric films of the liquid crystal capacitor Cpix are the liquid crystal LC, the protective film PSV1, and the alignment films ORI1 and ORI2. Vlc is a midpoint potential.

  The storage capacitor element Cadd serves to reduce the influence of the gate potential change ΔVg on the midpoint potential (pixel electrode potential) Vlc when the thin film transistor TFT is switched. This situation is expressed by the following equation.

ΔVlc = {Cgs / (Cgs + Cadd + Cpix)} × ΔVg
Here, ΔVlc represents a change in midpoint potential due to ΔVg. This change ΔVlc causes a direct current component applied to the liquid crystal LC, but the value can be reduced as the storage capacitor Cadd is increased. In addition, the storage capacitor element Cadd also has an action of extending the discharge time, and accumulates video information after the thin film transistor TFT is turned off. Reduction of the direct current component applied to the liquid crystal LC can improve the life of the liquid crystal LC and reduce the so-called burn-in in which the previous image remains when the liquid crystal display screen is switched.

  As described above, since the gate electrode GT is enlarged so as to completely cover the i-type semiconductor layer AS, the overlap area with the source electrode SD1 and the drain electrode SD2 is increased, and thus the parasitic capacitance Cgs is increased. The potential Vlc has the adverse effect of being easily affected by the gate (scanning) signal Vg. However, this disadvantage can be eliminated by providing the storage capacitor element Cadd.

  The storage capacitance of the storage capacitor element Cadd is 4 to 8 times the liquid crystal capacitance Cpix (4 · Cpix <Cadd <8 · Cpix) and 8 to 32 times (8 to 32 times the parasitic capacitance Cgs due to pixel writing characteristics. Set to a value of about Cgs <Cadd <32 · Cgs).

<< Connection Method of Retention Capacitor Cadd Electrode Line >>
As shown in FIG. 11, the first scanning signal line GL (Y ₀ ) used only as the storage capacitor electrode line is set to the same potential as the common transparent pixel electrode ITO2 (Vcom). In the example of FIG. 18, the scanning signal line in the first stage is short-circuited to the common electrode COM through the terminal GT0, the lead-out line INT, the terminal DT0, and the external wiring. Alternatively, the first-stage storage capacitor electrode line Y ₀ is connected to the last-stage scanning signal line Yend, connected to a DC potential point (AC grounding point) other than Vcom, or one extra scanning pulse Y ₀ from the vertical scanning circuit V. You may connect to receive.

<Connection structure with external circuit>
FIG. 21 is a diagram showing a cross-sectional structure of a tape carrier package TCP in which an integrated circuit chip CHI constituting a scanning signal driving circuit V and video signal driving circuits He and Ho is mounted on a flexible wiring board (commonly called TAB, Tape Automated Bonding). FIG. 22 is a cross-sectional view of an essential part showing a state in which the liquid crystal display panel is connected to the video signal circuit terminal DTM in this example.

  In the figure, TTB is an input terminal / wiring part of the integrated circuit CHI, and TTM is an output terminal / wiring part of the integrated circuit CHI, which is made of, for example, Cu, and each inner tip (commonly called inner lead) Bonding pads PAD of the integrated circuit CHI are connected by a so-called face-down bonding method. The outer tips (commonly referred to as outer leads) of the terminals TTB and TTM correspond to the input and output of the semiconductor integrated circuit chip CHI, respectively, and the CRT / TFT conversion circuit / power supply circuit SUP is connected to the anisotropic conductive film ACF by soldering or the like. Is connected to the liquid crystal display panel PNL. The package TCP is connected to the panel so that the tip thereof covers the protective film PSV1 exposing the connection terminal DTM on the panel PNL side. Therefore, the external connection terminal DTM (GTM) is at least either of the protective film PSV1 or the package TCP. On the other hand, since it is covered, it is strong against electric contact.

  BF1 is a base film made of polyimide or the like, and SRS is a solder resist film for masking so that the solder does not stick to an extra portion during soldering. The gap between the upper and lower glass substrates outside the seal pattern SL is protected by an epoxy resin EPX after cleaning, and a silicone resin SIL is further filled between the package TCP and the upper substrate SUB2 to multiplex the protection.

"Production method"
Next, a manufacturing method on the substrate SUB1 side of the liquid crystal display device described above will be described with reference to FIGS. In the figure, the central character is an abbreviation of the process name, the left side shows the pixel portion shown in FIG. 2, and the right side shows the processing flow as seen in the cross-sectional shape near the gate terminal shown in FIG. Steps A to I, except for step D, are classified according to each photographic process, and any cross-sectional view of each process shows a stage where the processing after the photographic process is finished and the photoresist is removed. In this description, photographic processing refers to a series of operations from application of a photoresist to selective exposure using a mask and development thereof, and repeated description is avoided. This will be described in accordance with the divided steps.

Process A, FIG. 13
After silicon oxide films SIO are provided on both surfaces of the lower transparent glass substrate SUB1 made of 7059 glass (trade name) by dipping, baking is performed at 500 ° C. for 60 minutes. A first conductive film g1 made of chromium having a thickness of 1100 mm is provided on the lower transparent glass substrate SUB1 by sputtering, and after the photographic processing, the first conductive film g1 is selectively etched with a second cerium ammonium nitrate solution as an etchant. . Thereby, the gate terminal GTM, the drain terminal DTM, the anodized bus line SHg for connecting the gate terminal GTM, the bus line SHd for short-circuiting the drain terminal DTM, and the anodized pad connected to the anodized bus line SHg (not shown) Form.

Process B, FIG. 13
A second conductive film g2 made of Al—Pd, Al—Si, Al—Si—Ti, Al—Si—Cu, or the like having a thickness of 2800 mm is provided by sputtering. After the photographic processing, the second conductive film g2 is selectively etched with a mixed acid solution of phosphoric acid, nitric acid, and glacial acetic acid.

Process C, FIG.
After photographic processing (after the formation of the anodic oxidation mask AO described above), a solution prepared by diluting 3% tartaric acid to pH 6.25 ± 0.05 with ammonia was diluted 1: 9 with an ethylene glycol solution into an anodic oxidation solution. The substrate SUB1 is immersed and adjusted so that the formation current density is 0.5 mA / cm ² (constant current formation). Next, anodic oxidation is performed until the formation voltage of 125 V necessary for obtaining a predetermined Al ₂ O ₃ film thickness is reached. Thereafter, it is desirable to maintain this state for several tens of minutes (constant voltage formation). This is important for obtaining a uniform Al ₂ O ₃ film. As a result, the conductive film g2 is anodized, and an anodic oxide film AOF having a thickness of 1800 mm is formed on the scanning signal line GL, the gate electrode GT, and the electrode PL1.
Ammonia gas, silane gas, and nitrogen gas are introduced into the plasma CVD apparatus to provide a silicon nitride film having a thickness of 2000 mm, and silane gas and hydrogen gas are introduced into the plasma CVD apparatus to form an i-type amorphous film having a thickness of 2000 mm. After providing the Si film, hydrogen gas and phosphine gas are introduced into the plasma CVD apparatus to form an N ⁺ type amorphous Si film having a thickness of 300 mm.

Process E, FIG. 14
After the photographic processing, the island of the i-type semiconductor layer AS is etched by selectively etching the N ⁺ -type amorphous Si film and the i-type amorphous Si film using SF ₆ and CCl ₄ as dry etching gases. Form.

Process F, FIG. 14
After the photo processing, the Si nitride film is selectively etched using SF ₆ as a dry etching gas.

Process G, FIG. 15
A first conductive film d1 made of an ITO film having a thickness of 1400 mm is provided by sputtering. After the photographic processing, the first conductive film d1 is selectively etched with a mixed acid solution of hydrochloric acid and nitric acid as an etching solution, thereby forming the gate terminal GTM, the uppermost layer of the drain terminal DTM, and the transparent pixel electrode ITO1.

Process H, FIG. 15
A second conductive film d2 made of Cr with a thickness of 600 Å is provided by sputtering, and a third conductive film made of Al-Pd, Al-Si, Al-Si-Ti, Al-Si-Cu, etc. with a thickness of 4000 さ ら に. d3 is provided by sputtering. After the photographic processing, the third conductive film d3 is etched with the same liquid as in the process B, and the second conductive film d2 is etched with the same liquid as in the process A to form the video signal line DL, the source electrode SD1, and the drain electrode SD2. To do. Next, by introducing CCl ₄ and SF ₆ into a dry etching apparatus and etching the N ⁺ type amorphous Si film, the N ⁺ type semiconductor layer d0 between the source and the drain is selectively removed.

Step I, FIG.
Ammonia gas, silane gas, and nitrogen gas are introduced into the plasma CVD apparatus to provide a 1 μm-thick Si nitride film. After the photographic processing, the protective film PSV1 is formed by selectively etching the Si nitride film by a photolithography technique using SF ₆ as a dry etching gas.

<Overall configuration of liquid crystal display module>
FIG. 23 is an exploded perspective view of the liquid crystal display module MDL, and the specific configuration of each component is shown in FIGS.

  SHD is a shield case (= metal frame) made of a metal plate, LCW is a liquid crystal display window, PNL is a liquid crystal display panel, SPB is a light diffusion plate, MFR is an intermediate frame, BL is a backlight, BLS is a backlight support, LCA Is a lower case, and the modules MDL are assembled by stacking the members in the vertical arrangement as shown in the figure.

The module MDL has three types of holding members: a lower case LCA, an intermediate frame MFR, and a shield case SHD. Each of these three members has a substantially box shape and is stacked in a heavy box type in the order described above, and is configured to hold the other two members on which the respective components are mounted by a shield case SHD. The display panel PNL and the light diffusing plate SPB can be once placed on the intermediate frame MFR, and the backlight support BLS that supports the four backlights (cold cathode fluorescent tubes) BL is once placed on the lower case LCA. be able to. Accordingly, the two parts of the lower case LCA and the intermediate frame MFR can be stacked and manufactured without being turned over while mounting the necessary parts, so that the manufacture can be easily performed and the assemblability can be improved. There is an advantage that a good and reliable device can be provided. This is one major feature of this module.
Hereinafter, each member will be described in detail.

《Shield case SHD》
FIG. 24 is a diagram showing the top surface, front side surface, rear side surface, right side surface, and left side surface of the shield case SHD, and FIG. 25 is a perspective view of the shield case SHD as viewed obliquely from above.

  The shield case (metal frame) SHD is manufactured by punching or bending a single metal plate by a press working technique. LCW indicates an opening exposing the display panel PNL to the field of view, and is hereinafter referred to as a display window.

  Reference numeral CL denotes intermediate frame MFR fixing claws (19 in total), and FK denotes lower case LCA fixing hooks (9 in total), which are integrally provided on the shield case SHD. When assembled, the fixing claws CL in the state shown in the drawing are bent inward and inserted into square fixing claw holes CLH (see the side views in FIG. 27) provided in the intermediate frame MFR. Thereby, the shield case SHD holds the intermediate frame MFR for holding and storing the display panel PNL and the like, and both are firmly fixed. The fixing hooks FK are fitted into fixing protrusions FKP (see each side view of FIG. 34) provided on the lower case LCA. As a result, the shield case SHD holds the lower case LCA that holds and stores the backlight BL, the backlight support BLS, and the like, and both are firmly fixed. The intermediate frame MFR and the lower case LCA are fitted at the periphery, and the shield case SHD is covered and fitted to the intermediate frame MFR, and the three members are united. In addition, thin and long rectangular rubber spacers (rubber cushions, not shown) are provided around the four edges that do not affect the display on the upper and lower surfaces of the display panel PNL. The upper surface side rubber spacer is interposed between the display panel PNL and the shield case SHD, and the lower surface side rubber spacer is interposed between the display panel PNL, the intermediate frame MFR, and the light diffusion plate SPB. By utilizing the elasticity of these rubber spacers, the shield case SHD is pushed toward the inside of the apparatus, whereby the fixing hook FK is engaged with the fixing protrusion FKP, both fixing members function as stoppers, and the fixing claws CL Is bent, inserted into the claw hole CLH, the intermediate frame MFR and the lower case LCA are fixed by the shield case SHD, the entire module is firmly held together, and no other fixing member is required. Therefore, assembly is easy and manufacturing cost can be reduced. Further, the mechanical strength is large, the vibration shock resistance can be improved, and the reliability of the apparatus can be improved. Also, because the fixing claw CL and the fixing hook FK are easy to remove (just extend the bending of the fixing claw CL and remove the fixing hook FK), the three members can be easily disassembled and assembled, making repair easy. The backlight BL can be easily replaced (the fixing hook FK of the lower case LCA, which has a high removal rate due to backlight replacement or the like, is easier to remove than the fixing claw CL). In addition, in this module, the lower case LCA and the intermediate frame MFR are attached by the fixing member as described above, and four through holes LHL each provided with a screw hole of the lower case LCA provided (see FIGS. 34 to 36). ), A screw hole MVH (see FIG. 28) of the intermediate frame MFR, and a screw.

  COH is a common through hole. In addition to the shield case SHD, two common through holes COH are common to the drive circuit board PCB1 of the display panel PNL, the drive circuit board PCB2 of the intermediate frame MFR, the intermediate frame MFR, and the lower case LCA (in the same plane position). In the through holes provided, each component and each component is mounted by inserting each common through hole COH in the order from the lower case LCA to the pin that is fixed and standing at the time of manufacture. This is for setting the relative position with high accuracy. Further, when the module MDL is mounted on an application product such as a personal computer, the common through hole COH can be used as a positioning reference.

  FG is six frame grounds formed integrally with the metal shield case SHD, and has a “U” -shaped opening opened in the shield case SHD, in other words, an elongated protrusion extending into the square opening. Consists of. Each of the elongated protrusions is bent in the direction toward the inside of the device, and is connected to the frame ground pad FGP (FIG. 26) to which the ground line of the drive circuit board PCB1 of the display panel PNL is connected by soldering. Yes.

<< Display Panel PNL and Drive Circuit Board PCB1 >>
FIG. 26 is a top view showing a state where a drive circuit is mounted on the display panel PNL shown in FIG.
CHI is a driving IC chip for driving the display panel PNL (the lower three are driving IC chips on the vertical scanning circuit side, and the left and right six are driving IC chips on the video signal driving circuit side). As described with reference to FIGS. 21 and 22, TCP is a tape carrier package in which the driving IC chip CHI is mounted by the tape automated bonding method (TAB), and PCB1 is a PCB (printer) in which TCP, a capacitor CDS, etc. are mounted. Drive circuit board, which is divided into three. FGP is a frame ground pad. FC is a flat cable that electrically connects the lower drive circuit board PCB1 and the left drive circuit board PCB1, and the lower drive circuit board PCB1 and the right drive circuit board PCB1. As shown in the figure, a flat cable FC is used in which a plurality of lead wires (phosphor bronze material Sn plated) are sandwiched and supported by a striped polyethylene layer and a polyvinyl alcohol layer.

<< Drive circuit board PCB1 >>
As shown in FIG. 26, the drive circuit board PCB1 is divided into three parts, arranged in a “U” shape around the display panel PNL, and electrically and mechanically connected by two flat cables FC. ing. Since the drive circuit board PCB1 is divided, the stress (stress) generated in the major axis direction of the drive circuit board PCB1 due to the difference in thermal expansion coefficient between the display panel PNL and the drive circuit board PCB1 is absorbed by the flat cable FC. Further, peeling of the output lead (TTM in FIGS. 21 and 22) of the tape carrier package TCP tape having a weak connection strength and the external connection terminal DTM (GTM) of the display panel can be prevented, and the reliability of the module against heat can be improved. Such a substrate dividing method further has a simple shape on a rectangle as compared with a single “U” -shaped substrate, so that a large number of substrates PCB1 can be obtained from a single substrate material. There is an effect that the utilization rate of the printed circuit board material is increased and the cost of parts and materials can be reduced (in the case of this embodiment, it is reduced to about 50%). In addition, if flexible FPC (flexible printed circuit) is used for the drive circuit board PCB1 instead of PCB, since the FPC is bent, the effect of preventing lead peeling can be further enhanced. In addition, an integrated “U” -shaped PCB that is not divided can be used, in which case man-hours are reduced, manufacturing process management is simplified by reducing the number of parts, and reliability is improved by eliminating the connection cable between PCBs. There is an effect.

  As shown in FIG. 26, a total of six frame ground pads FGP connected to each ground line of each drive circuit board PCB1 divided into three are provided for each board. In the case where the drive circuit board PCB1 is divided into a plurality of parts, an electrical problem does not occur if at least one of the drive circuit boards is connected to the frame ground in terms of DC. If the number is low, the potential for generating unnecessary radiated radio waves that cause EMI (electromagnetic interference) is high due to the reflection of electrical signals due to differences in the characteristic impedance of each drive circuit board and the potential of the ground line. Become. In particular, the module MDL using a thin film transistor uses a high-speed clock, so that it is difficult to take measures against EMI. In order to prevent this, at least one drive circuit board PCB1 divided into a plurality of parts, in this embodiment two ground lines (AC ground potential) is connected to a common frame (that is, a shield) having a sufficiently low impedance. Case SHD). As a result, the ground line in the high-frequency region is strengthened. Therefore, in comparison with the case where only one place is connected to the shield case SHD as a whole, in the case of the six places of this embodiment, the improvement of the electric field intensity of the radiation is 5 dB or more. It was.

  The frame ground FG of the shield case SHD is formed of a long and thin metal protrusion, and can be easily connected to the frame ground pad FGP of the display panel PNL by bending, and a special wire (lead wire) for connection is unnecessary. Further, since the shield case SHD and the drive circuit board PCB1 can be mechanically connected via the frame ground FG, the mechanical strength of the drive circuit board PCB1 can be improved.

《Intermediate frame MFR》
27 is a top view, front side view, rear side view, right side view, left side view, FIG. 28 is a bottom view of the intermediate frame MFR, and FIG. 29 is a top view of the intermediate frame MFR. FIG.

  The intermediate frame MFR is a holding member for the liquid crystal display LCD, the light diffusion plate SPB, and the L-shaped drive circuit board PCB2 that are integrally formed with the drive circuit board PCB1.

  BLW is a backlight light intake window for taking the light of the backlight BL into the liquid crystal display unit LCD, and a light diffusion plate SPB is placed and held therein. SPBS is a holding part of the light diffusion plate SPB. RDW is a heat radiating hole, and CW is a notch for a connector connected to the outside. MVH has four screw holes, and the lower case LCA and the intermediate frame MFR are fixed by screws (not shown) through the screw holes MVH and through holes LHL (see FIGS. 34 to 36) of the lower case LCA. The CLH is a fixing claw hole into which the fixing claw CL of the shield case SHD is inserted (see each side view of FIG. 27 and FIG. 29). 2HL is a fixing hole for the drive circuit board PCB2 (see FIG. 30), and a stopper such as a nylon rivet is inserted therein. The L-shaped drive circuit board PCB2 is disposed in the L-shaped regions on the right and lower edges of the top view of the intermediate frame MFR in FIG. The intermediate frame MFR is formed of the same white synthetic resin as the backlight support BLS and the lower case LCA. Further, since the intermediate frame MFR is made of synthetic resin, it is advantageous in terms of insulation between the drive circuit board PCB1 and the drive circuit board PCB2.

<< Light diffusion plate SPB >>
The light diffusing plate SPB (see FIG. 23) is on the holding portion SPBS (see FIGS. 27 and 29, which is lower than the upper surface of the intermediate frame MFR) provided at the four peripheral edges of the backlight light intake window BLW of the intermediate frame MFR. Held in. When the light diffusing plate SPB is placed on the holding portion SPBS, the upper surface of the light diffusing plate SPB and the upper surface of the intermediate frame MFR are flush with each other. On the light diffusion plate SPB, a liquid crystal display LCD integrated with the drive circuit board PCB1 is placed. Between the liquid crystal display LCD and the light diffusing plate SPB, four rubber spacers are arranged around the four edges of the lower surface of the liquid crystal display LCD (not shown; see the description of << Shield Case SHD >>) Is interposed between the liquid crystal display portion LCD and the light diffusion plate SPB by these rubber spacers. That is, the light diffusing plate SPB is placed on the intermediate frame MFR (frame body), the upper surface of the light diffusing plate SPB is covered with the liquid crystal display portion LCD, and the gap between the liquid crystal display portion LCD and the light diffusing plate SPB. Is completely sealed by a rubber spacer (the light diffusion plate SPB and the liquid crystal display portion LCD are integrated and fixed independently from the backlight portion using the intermediate frame MFR). Therefore, it is possible to suppress the problem that the display quality deteriorates due to foreign matter entering between the liquid crystal display part LCD and the light diffusion plate SPB, or foreign matter adhering to the display area other than the display area moving to the display area. it can. Since the light diffusion plate SPB is thicker than the light diffusion sheet, the presence of foreign matter on the lower surface side of the light diffusion plate SPB is inconspicuous. Further, since the foreign matter existing on the lower surface side of the light diffusing plate SPB is far from the liquid crystal display portion LCD, it is difficult to focus and the image is diffused, so that there is almost no problem. Furthermore, since the light diffusion plate SPB and the liquid crystal display LCD are sequentially held by the intermediate frame MFR, the assemblability is good.

<< Drive circuit board PCB2 >>
FIG. 30 is a bottom view of the drive circuit board PCB2. As shown in FIG. 30, the drive circuit board PCB2 of the liquid crystal display portion LCD held and accommodated in the intermediate frame MFR has an L shape and is mounted with electronic components such as an IC, a capacitor, and a resistor. The drive circuit board PCB2 is provided with a power supply circuit for obtaining a plurality of stabilized voltage sources divided from one voltage source and information for a CRT (cathode ray tube) from a host (high-order processing unit). A circuit including a circuit for converting into information for a TFT liquid crystal display device is mounted. CJ is a connector connecting portion to which a connector (not shown) connected to the outside is connected. The drive circuit board PCB2 and the drive circuit board PCB1 are electrically connected by a flat cable FC (details will be described later) as shown in FIG. Further, the drive circuit board PCB2 and the inverter circuit board IPCB are connected by a backlight connector and a backlight cable (not shown) connected to the backlight connection part BC2 of the drive circuit board PCB2 and the backlight connection part BCI of the inverter circuit board IPCB. Electrical connection is made via a connector hole CHL (see FIGS. 27 to 29) provided in the intermediate frame MFR.

<< Electrical connection between drive circuit board PCB1 and drive circuit board PCB2 >>
FIG. 31 is a top view showing a connection state between the driving circuit board PCB1 (the upper surface is visible) of the liquid crystal display LCD and the driving circuit board PCB2 (the lower surface is visible) of the intermediate frame MFR.

  The liquid crystal display part LCD and the drive circuit board PCB2 are electrically connected by a foldable flat cable FC. An operation check can be performed in this state. The drive circuit board PCB2 is placed on the lower surface side of the liquid crystal display LCD by folding the flat cable FC 180 °, fitted in a predetermined recess of the intermediate frame MFR, and fixed with a fastener such as a nylon rivet. Then, the driving circuit board PCB1 integrated with the liquid crystal display LCD is placed and held thereon.

<< Backlight support BLS >>
FIG. 32 is a top view, rear side view, right side view, left side view of the backlight support BLS, and FIG. 33 is a perspective view of the backlight support BLS viewed from the top side.

  The backlight support BLS supports four backlights (cold cathode fluorescent tubes) BL (see FIGS. 37 and 23). SPC is a hole (space), and the backlight support BLS forms a frame.

  The backlight support BLS supports the four backlights BL via white silicon rubber SG (see FIGS. 37 and 39). Reference numeral SS denotes a backlight support portion which supports both ends of each backlight BL via silicon rubber SG. Note that the silicon rubber SG also serves to prevent foreign matter from entering the lighting area of the backlight BL. RH is a lead wire hole through which a lead wire LD (see FIG. 37) connected to both ends of the backlight BL passes.

  SHL is four through holes provided in the backlight support BLS, and coincides with the screw holes LVH of the lower case LCA, and is fixed to the lower case LCA by screws (not shown).

  SRM is a backlight light reflecting portion of a backlight BL (two backlights BL out of four backlights BL) formed on both right and left inner surfaces of the backlight support BLS in FIG. Similar to the upper surface of the backlight light reflection mountain RM (see FIGS. 34 and 36) of the case LCA, it is composed of a combination of a plurality of planes for efficiently reflecting the light of the backlight BL toward the liquid crystal display LCD. (Refer to the description of << lower case >>). The backlight support BLS is made by molding the same white synthetic resin as the intermediate frame MFR and the lower case LCA.

<Lower case LCA>
34 is a top view of the lower case LCA (reflection side), rear side view, right side view, left side view, FIG. 35 is a bottom view of the lower case LCA, and FIG. 36 is a top view of the lower case LCA. FIG. 38 is a cross-sectional view of the lower case LCA (cross-sectional view taken along the line 38-38 in FIG. 34).

  The lower case LCA is a holding member (backlight storage case) for the backlight BL, the backlight support BLS, and the inverter circuit board IPCB for the backlight BL lighting, and also serves as a backlight light reflector of the backlight BL. It is made by integrally molding in one mold with a white synthetic resin that reflects the light of the backlight BL most efficiently. On the upper surface of the lower case LCA, three backlight light reflection mountains RM formed integrally with the lower case LCA are formed to constitute the backlight light reflection surface of the backlight BL. The three backlight light reflection mountains RM are composed of a combination of a plurality of planes for efficiently reflecting the light of the backlight BL toward the liquid crystal display portion LCD. That is, as shown in the cross-sectional view of FIG. 38, the cross-sectional shape of the backlight light reflection mountain RM is constituted by an approximate straight line of a curve obtained by calculation so as to reflect the light of the backlight BL most efficiently. Yes. The height of the backlight light reflection mountain RM is higher than the upper surface of the backlight BL in order to increase the reflected light rate (see FIG. 39). Thus, since the storage case of the backlight BL and the backlight light reflecting plate of the backlight BL are configured as an integral member, the number of parts can be reduced, the structure can be simplified, and the manufacturing cost can be reduced. Therefore, the vibration shock resistance and thermal shock resistance of the apparatus can be improved, and the reliability can be improved. Further, since the lower case LCA is made of a synthetic resin, it is advantageous for insulation of the inverter circuit board IPCB.

  Note that LVH has four screw holes, and the backlight support BLS is attached to the lower case by screws (not shown) through the screw holes LVH and through holes SHL (see FIGS. 32 and 33) of the backlight support BLS. Fixed to LCA. LHL is four through holes, and the intermediate frame MFR and the lower case LCA are fixed by screws (not shown) through the through holes LHL and screw holes MVH (see FIG. 28) of the intermediate frame MFR. IHL is a fixing hole for an inverter circuit board IPCB into which a fastener such as a nylon rivet is inserted, CW is a notch for a connector to be connected to the outside, and FKP is a fixing for fitting a fixing hook FK for a shield case SHD It is a protrusion (see each side view of FIG. 34, FIG. 36).

<< Backlight BL >>
FIG. 37 is a top view, rear side view, right side view, left side view, and FIG. 39 showing a state where the backlight support BLS, the backlight BL, and the inverter circuit board IPCB are mounted on the lower case LCA. It is sectional drawing in the 39-39 cutting line.

  The backlight BL is a direct type backlight disposed directly below the liquid crystal display unit LCD. The backlight BL is composed of four cold cathode fluorescent tubes and is supported by the backlight support BLS. The backlight support BLS is attached to the lower case LCA using screws (not shown) and the through holes of the backlight support BLS. By fixing through the screw holes LVH of the SHL and the lower case LCA, the lower case LCA, which is a backlight storage case, is held.

  The ECL is the sealing side of the cold cathode tube (refers to the side on which the phosphor is applied to the inner surface of the tube, the gas is evacuated, or the gas is sealed). As shown in FIG. 37, the sealing side ECLs of the four backlights BL arranged side by side are arranged alternately left and right (upper and lower in FIG. 37) (staggered arrangement). Thereby, the left-right inclination of the color temperature of the display screen resulting from the phosphor coating in the fluorescent tube (the color temperature on the sealing side is higher) can be made inconspicuous, and the display quality can be improved.

<< Inverter circuit board IPCB >>
The inverter circuit IPCB is a circuit board for lighting of the four backlights BL, and is placed on the lower case LCA as shown in FIG. 37, and the fixing hole IHL (FIGS. 34 to 36) of the lower case LCA. And a fastener such as a nylon rivet (not shown). On the inverter circuit IPCB, two transformers TF1 and TF2 and electronic components such as capacitors, coils and resistors are mounted. Note that the inverter circuit board IPCB serving as a heat source is arranged on the upper side of the apparatus (shown on the left side of the top view in FIG. 37), and therefore has good heat dissipation. The inverter circuit board IPCB is disposed on the upper side of the device, and the L-shaped drive circuit board PCB2 is on the lower side and the left side of the device (L-shaped regions on the right and lower edges of the top view of the intermediate frame MFR in FIG. 27). The inverter circuit board IPCB and the drive circuit board PCB2, which are heat sources, are arranged so as not to overlap each other in terms of heat dissipation and the thickness of the entire module.

<< Backlight BL, Backlight Support BLS, Inverter Circuit Board IPCB >>
After the four backlights BL with lead wires LD (see FIG. 37) are fitted into the backlight support BLS, the backlight support BLS and the inverter circuit board IPCB are attached to the lower case LCA. Before storing and fixing, the lead wire LD of each backlight BL is soldered to the inverter circuit board IPCB. Thereby, one unit is comprised by the backlight BL, the backlight support body BLS, and the inverter circuit board IPCB (refer FIG. 23, FIG. 37). In this state, it is possible to perform a lighting test of the backlight BL. Conventionally, after the backlight and the inverter circuit board were fixed to the backlight storage case, the backlight lead wires were soldered to the inverter circuit board, so the space for soldering was very narrow, Although workability was poor, in this module, before fixing the backlight BL and the inverter circuit board IPCB to the lower case LCA, the backlight BL was read with the backlight BL supported by the backlight support BLS. Since the line LD can be soldered to the inverter circuit board IPCB, workability is good. In addition, it is easy to replace parts when defective parts occur. When the lighting test is completed, as shown in FIG. 37, the inverter circuit board IPCB is fixed through the fixing hole IHL of the lower case LCA using a fastener such as a nylon rivet, and the backlight support BLS is illustrated. It fixes to lower case LCA with four through-holes SHL and screw holes LVH (refer FIG. 36, FIG. 34) with the screw which does not carry out.

  Conventionally, six cold cathode tubes and two inverter circuit boards are used, and each of the two cold cathode tubes is turned on with three cold cathode tubes per inverter circuit board (having two transformers each). The inverter circuit boards are arranged on the upper and lower sides of the backlight in the backlight storage case (left and right in the top view of the lower case LCA in FIG. 37), so that the overall size of the backlight portion increases. Since the two inverter circuit boards that are heat sources are arranged on both the upper and lower sides, there is a problem in terms of heat dissipation. However, in this apparatus, since there is only one inverter circuit board IPCB, the overall size of the backlight unit can be reduced and heat dissipation is also good. Further, in this device, the inverter circuit board IPCB is arranged on the upper side of the device (shown on the left side of the top view in FIG. 37), so that the heat dissipation is good.

1 is a plan view of a main part showing one pixel of a liquid crystal display unit of an active matrix color liquid crystal display device to which the present invention is applied and its periphery; It is sectional drawing which shows 1 pixel and its periphery in the 2-2 cutting line of FIG. FIG. 3 is a cross-sectional view of an additional capacitor Cadd along the section line 3-3 in FIG. 1. It is a principal part top view of the liquid crystal display part which has arranged several pixels shown in FIG. FIG. 2 is a plan view illustrating only a pixel layer g <b> 2 and AS illustrated in FIG. 1. FIG. 2 is a plan view illustrating only pixel layers d1, d2, and d3 illustrated in FIG. 1. FIG. 2 is a plan view illustrating only a pixel electrode layer, a light shielding film, and a color filter layer of the pixel illustrated in FIG. 1. FIG. 7 is a plan view of a main part illustrating only a pixel electrode layer, a light shielding film, and a color filter layer of the pixel array shown in FIG. 6. It is the figure of the plane and cross section which show the connection part vicinity of the gate terminal GTM and the gate wiring GL. It is the figure of the plane and cross section which show the connection part vicinity of the drain terminal DTM and video signal line DL. It is an equivalent circuit diagram showing a liquid crystal display unit of an active matrix type color liquid crystal display device. FIG. 2 is an equivalent circuit diagram of the pixel shown in FIG. 1. It is a flowchart of sectional drawing of the pixel part and gate terminal part which show the manufacturing process of process AC of the board | substrate SUB1 side. It is a flowchart of sectional drawing of the pixel part and gate terminal part which show the manufacturing process of process DF by the side of the board | substrate SUB1. It is a flowchart of sectional drawing of the pixel part and gate terminal part which show the manufacturing process of process GI by the side of the board | substrate SUB1. 4 is a plan view for explaining a configuration of a matrix peripheral portion of the display panel. FIG. FIG. 17 is a panel plan view illustrating the peripheral portion of FIG. 16 slightly exaggerated and more specifically. It is an enlarged plan view of the corner | angular part of the display panel containing the electrical connection part of an upper and lower board | substrate. FIG. 4 is a cross-sectional view showing the vicinity of the panel angle and the vicinity of the video signal terminal portion on both sides with the pixel portion of the matrix at the center. It is sectional drawing which shows the panel edge part which does not have a scanning signal terminal on the left side, and an external connection terminal on the right side. It is a figure which shows the cross-section of tape carrier package TCP in which the integrated circuit chip CHI which comprises a drive circuit was mounted in the flexible wiring board. It is principal part sectional drawing which shows the state which connected the tape carrier package TCP to the terminal DTM for video signal circuits of liquid crystal display panel PNL. It is a disassembled perspective view of a liquid crystal display module. It is a top view, a front side view, a rear side view, a right side view, and a left side view of a shield case of a liquid crystal display module. It is the perspective view seen from the upper surface side of the shield case. It is a top view which shows the state which mounted the peripheral drive circuit on the liquid crystal display panel. It is a top view, a front side view, a rear side view, a right side view, and a left side view of the intermediate frame. It is a bottom view of an intermediate frame. It is the perspective view seen from the upper surface side of the intermediate frame. It is a bottom view of the drive circuit board mounted on the intermediate frame. It is a top view which shows the connection state of the drive circuit board (upper surface is visible) of a liquid crystal display part, and the drive circuit board (lower surface is visible) of an intermediate | middle frame. It is a top view of a backlight support body, a rear side view, a right side view, and a left side view. It is the perspective view seen from the upper surface side of a backlight support body. It is a top view (reflection side), rear side view, right side view, and left side view of the lower case. It is a bottom view of a lower case. It is the perspective view seen from the upper surface side of the lower case. FIG. 4 is a top view, a rear side view, a right side view, and a left side view showing a state where a backlight support, a backlight, and an inverter circuit board are mounted on the lower case. FIG. 35 is a cross-sectional view of the lower case (a cross-sectional view taken along line 38-38 in FIG. 34). FIG. 38 is a cross-sectional view taken along the line 39-39 in FIG. 37.

Explanation of symbols

SUB ... Transparent glass substrate, GL ... Scanning signal line, DL ... Video signal line GI ... Insulating film, GT ... Gate electrode, AS ... i-type semiconductor layer SD ... Source electrode or drain electrode, PSV ... Protective film, BM ... Light shielding film LC ... liquid crystal, TFT ... thin film transistor, ITO ... transparent pixel electrode g, d ... conductive film, Cadd ... holding capacitor element, AOF ... anodized film AO ... anodized mask, GTM ... gate terminal, DTM ... drain terminal SHD ... shield case , PNL ... liquid crystal display panel, SPB ... light diffusion plate,
MFR ... intermediate frame, BL ... backlight, BLS ... backlight support,
LCA: lower case, RM: backlight light reflection mountain.

Claims (4)

A liquid crystal display panel;
A shield case made of a metal plate covering the periphery of the liquid crystal display panel;
A direct backlight having a plurality of fluorescent tubes;
A backlight support for supporting the backlight;
A liquid crystal display device fixed to the shield case, having a backlight light reflecting surface, and having a lower case for housing the backlight;
The backlight support has a plurality of recesses formed outward from the end of the backlight light reflecting surface, and each of the end portions of the plurality of fluorescent tubes is each of the plurality of recesses. Is fitted with silicone rubber ,
Each of the end portions of the plurality of fluorescent tubes is connected to a lead wire in each of the plurality of concave portions,
The lead wire is drawn out from a lead wire lead hole provided in each of the plurality of recesses,
The liquid crystal display device, wherein the backlight support is fixed to the lower case. A liquid crystal display panel;
A shield case made of a metal plate covering the periphery of the liquid crystal display panel;
A direct backlight having a plurality of fluorescent tubes;
A backlight support that supports the backlight and has an inner surface combined from a plurality of planes;
A liquid crystal display device fixed to the shield case, having a backlight light reflecting surface, and having a lower case for housing the backlight;
The backlight support has a plurality of recesses formed outward from the end of the backlight light reflecting surface, and each of the end portions of the plurality of fluorescent tubes is each of the plurality of recesses. Is fitted with silicone rubber ,
Each of the end portions of the plurality of fluorescent tubes is connected to a lead wire in each of the plurality of concave portions,
The lead wire is drawn out from a lead wire lead hole provided in each of the plurality of recesses,
The liquid crystal display device backlight support, characterized in that said a plurality of states in which the end portion of the fluorescent tube has been fitted into and fixed to the front Symbol lower case. A liquid crystal display panel;
A shield case made of a metal plate covering the periphery of the liquid crystal display panel;
A direct backlight having a plurality of fluorescent tubes;
A backlight support for supporting the backlight;
A lower case that is fixed to the shield case, has a backlight light reflecting surface, and stores the backlight;
A liquid crystal display device having an inverter circuit board to which lead wires connected to the plurality of fluorescent tubes are connected,
The backlight support has a plurality of recesses formed outward from the end of the backlight light reflecting surface, and each of the end portions of the plurality of fluorescent tubes is each of the plurality of recesses. Is fitted with silicone rubber ,
Each of the ends of the plurality of fluorescent tubes is connected to the lead wire in each of the plurality of recesses,
The lead wire is drawn out from a lead wire lead hole provided in each of the plurality of recesses,
The backlight support is fixed to the lower case;
The liquid crystal display device, wherein the inverter circuit board is also fixed through a fixing hole in the lower case. A liquid crystal display panel;
A shield case made of a metal plate covering the periphery of the liquid crystal display panel;
A direct backlight having a plurality of fluorescent tubes;
A backlight support for supporting the backlight;
A lower case that is fixed to the shield case, has a backlight light reflecting surface, and stores the backlight;
An inverter circuit board to which lead wires connected to the plurality of fluorescent tubes are connected;
A driving IC chip connected to the liquid crystal display panel;
A liquid crystal display device having a drive circuit substrate having a power supply circuit for supplying a plurality of divided voltages to the drive IC chip,
The backlight support has a plurality of recesses formed outward from the end of the backlight light reflecting surface, and each of the end portions of the plurality of fluorescent tubes is each of the plurality of recesses. Is fitted with silicone rubber ,
Each of the ends of the plurality of fluorescent tubes is connected to the lead wire in each of the plurality of recesses,
The lead wire is drawn out from a lead wire lead hole provided in each of the plurality of recesses,
The backlight support is fixed to the lower case;
The inverter circuit board is also fixed through a fixing hole in the lower case,
The liquid crystal display device, wherein the inverter circuit board and the drive circuit board do not overlap in a vertical direction.

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