JP3718251B2 - Data processing device - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a data processor and a microcomputer that are operated in synchronization with a clock signal, and also to a data processing system equipped with the data processor, in particular, the frequency of the operating clock signal, and the frequency of the operating clock signal and the voltage of the operating power supply The present invention relates to a technique for switching both of them to achieve low power consumption, for example, a technique effective when applied to a microcomputer.
[0002]
[Prior art]
Japanese Patent Application Laid-Open No. 3-68007 discloses a technique that contributes to low power consumption by switching the frequency of an operation clock signal as required in a microcomputer that operates in synchronization with a clock signal. ing. Japanese Patent Application Laid-Open No. 5-108193 describes a microcomputer in which the power supply voltage and clock signal frequency supplied from the outside are changed according to the set value of the built-in register to reduce power consumption.
[0003]
[Problems to be solved by the invention]
However, as semiconductor integrated circuits such as microcomputers become more sophisticated, when the circuit module is coupled to a hierarchical internal bus according to the operating frequency or operating speed of the circuit module, the switching of the internal clock signal frequency is hierarchical. This must be done in consideration of the nature of the circuit module. For example, when the internal operating frequency is changed by rewriting the register value, for the circuit module such as a bus controller that controls the interface with the external bus, the operating clock signal frequency is set in consideration of the relationship with the external bus. It has been clarified by the inventor that it must be controlled.
[0004]
Also, when the operating voltage is made variable and the power consumption is reduced along with the operating frequency of the circuit module that constitutes the microcomputer, etc., whether or not the specific circuit module is operated with low power consumption depends on whether the circuit module is a peripheral circuit or a central circuit. The present inventor has found that it cannot be determined uniformly only by the difference in general functions such as whether it is a processing device. For example, in a central processing unit, priority is given to low power consumption for tasks that do not require high-speed data processing, and for tasks that require high-speed processing, even if power consumption increases, data processing speed is maximized. In order to do so, it is necessary to have a degree of freedom in which the operating frequency and operating voltage of the circuit module can be switched in task units. That is, the power supply voltage and the data processing efficiency of the circuit module can be set relatively freely according to the data processing performance of the circuit module and the weight of the data processing, so that the power consumption and the data processing efficiency can be optimized. . Low power consumption is prioritized for tasks or circuit modules that do not require relatively high-speed data processing, and an increase in power consumption is allowed for tasks or circuits that require relatively high processing speed. This realizes low power consumption while improving the data processing efficiency as a whole.
[0005]
When the operating power supply voltage and the operating frequency can be set relatively freely as described above, the circuit module is prevented from malfunctioning when the setting is changed, and the malfunction occurs depending on the combination mode. The inventor has found that proactively addressing this is necessary to increase system reliability. For example, when the operation power supply voltage of the circuit is lowered, the drive capability of the circuit is lowered and the signal delay is increased. Accordingly, the frequency change is allowed so as not to malfunction, and the operation frequency of the circuit is increased. In some cases, the power supply voltage must be allowed to change so as not to malfunction.
[0006]
An object of the present invention is to provide a degree of freedom in which the operating frequency and operating voltage of a circuit module can be switched even in units of tasks, and at this time, malfunctions of the circuit that may occur when the operating frequency and operating voltage of the circuit module are switched. Another object of the present invention is to provide a data processing apparatus that can prevent the above. It is another object of the present invention to make it possible to realize the malfunction prevention relatively easily.
[0007]
Another object of the present invention is to provide a data processing apparatus capable of arbitrarily setting the clock signal frequency of the built-in circuit module in consideration of the interface with the external bus when the internal bus is hierarchized.
[0008]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0009]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0010]
[1] According to the invention for controlling both the operating frequency and the operating voltage of the circuit module, the data processing device includes a clock generation circuit (120, 320) capable of selectively outputting clock signals having different frequencies, and the above circuit. Power supply circuits (110, 310) capable of selectively outputting different voltages as module operating voltages are provided to specify the frequency of the clock signal to be supplied to one or a plurality of circuit modules and the voltage of the operating voltage. Control information is rewritably stored in the storage means (114, 124, 307), and the selection of the clock signal frequency and the selection of the operating voltage in the clock generation circuit and the power supply circuit are controlled based on the stored control information. To. At this time, when an instruction to reduce the clock signal frequency and reduce the operating voltage in absolute value is detected, a state in which the operating voltage is reduced in absolute value prior to the change of the current operating frequency is prevented, Also, when an instruction to increase the frequency of the clock signal and increase the operating voltage in absolute value is detected, the state in which the clock signal with the increased frequency is output prior to the increase of the operating voltage in absolute value is prevented. Thus, the first control means (131, 3341) for controlling the switching of the output state of the clock generation circuit and the power supply circuit is employed to prevent malfunction of the circuit module at the time of switching the frequency and operating voltage or immediately after the switching. To do.
[0011]
In order to easily realize the control mode by the first control means, an output gate (1206, 3261) that stops the output of the clock signal for a certain period based on an instruction from the first control means when switching the output of the frequency. , 3262, 3263) can be provided in the clock generation circuit.
[0012]
Furthermore, although it is possible to prohibit pre-setting, control from before and after the rewriting of the storage means is performed in order to prevent the possibility of malfunction due to undesired switching between the frequency and the power supply voltage. Based on the information, by detecting an instruction to increase the frequency of the clock signal without increasing the operating voltage in absolute value, or an instruction to decrease the operating voltage in absolute value without reducing the clock signal frequency, Further, second control means (132, 3342) for suppressing changes in the output state of the clock generation circuit and the power supply circuit based on the instruction are further employed.
[0013]
In order to individually switch and control the clock frequency and the power supply voltage for a plurality of circuit modules, the storage means stores a plurality of storage areas (3071, 3072) in which control information for each predetermined circuit module is rewritable. The clock generation circuit is provided with a selection circuit (3251, 3252, 3253) for individually selecting a clock signal to be supplied to the corresponding circuit module in accordance with control information of each of the plurality of storage areas in the storage means. In addition, the power supply circuit includes selection circuits (3141, 3142, 3143) can be easily accommodated.
[0014]
In the data processing apparatus, the circuit module is one circuit module that is a central processing unit and another circuit module whose operation is controlled by the central processing unit, and is formed on a single semiconductor substrate as a whole. It can be configured as a single chip microcomputer. The circuit module, the storage means, the first control means, and the second control means are a one-chip semiconductor integrated circuit, and the clock generation circuit and the power supply circuit are provided outside the semiconductor integrated circuit to provide a data processing apparatus. Can be configured. The circuit module is a circuit module that is a central processing unit and another circuit module whose operation is controlled by the central processing unit. The circuit module that is the central processing unit, and the other circuit module A part of the circuit modules, the storage unit, the first control unit, and the second control unit are one-chip semiconductor integrated circuits, and the remaining circuit modules in the other circuit modules, the clock generation circuit, and A power supply circuit is provided outside the semiconductor integrated circuit, and can be configured as a multichip microcomputer.
[0015]
[2] According to the invention relating to the operation frequency switching for the data processing device in which the internal bus is hierarchized, the data processing device includes the first internal bus (60) to which the central processing unit (61) is coupled, A second internal bus (70) that is interfaced with an external bus via an output circuit (73) and is coupled to a bus controller (72) that performs interface control with the external bus, and a third internal bus that is coupled with a predetermined peripheral circuit. Internal bus (80), a first clock signal (91) for the circuit module coupled to the first internal bus, and a second clock signal for the circuit module coupled to the second internal bus (92) and a clock pulse generator (9) for outputting a third clock signal (93) for the circuit module coupled to the third internal bus, and coupled to the first internal bus And a clock control circuit (65) for varying the frequency of at least one of the first and third clock signals according to control information set in the central processing unit. It is made up.
[0016]
When an external device (for example, a synchronous dynamic random access memory) connected to an external bus and operated according to a bus cycle controlled by the bus controller is operated in synchronization with a clock signal, the external device In consideration of supplying the clock signal for synchronous operation to the data processing device, the data processing device is provided with an output terminal (CKIO) of the external clock signal, and at this time, the clock control circuit sets the frequency of the second clock signal to the above-described frequency. Match the frequency of the external clock signal.
[0017]
If the frequency of the second clock signal for the second internal bus to which the bus controller is coupled is not set to a frequency corresponding to the operating speed of the external device coupled to the external bus, the internal or external bus cycle or bus operation In consideration of the inability to synchronize, it is desirable for high-speed data processing that the circuit module of the first internal bus to which the central processing unit is coupled can operate at high speed as necessary. Therefore, when a cache memory device is built in the data processing device, it is preferable to use the cache memory device as an interface between the first internal bus and the second internal bus in order to improve data processing efficiency. .
[0018]
In a more detailed mode, the data processing apparatus includes a first internal bus (60) to which a central processing unit (61) is coupled, and an external bus via an input / output circuit (73) and interface control with the external bus. A second internal bus (70) to which a bus controller (72) for performing the operation is coupled, a third internal bus (80) to which a predetermined peripheral circuit is coupled, and a circuit module coupled to the first internal bus A first clock signal (91) for a second clock signal (92) for a circuit module coupled to a second internal bus, and a circuit module coupled to a third internal bus A clock pulse generator (9) for outputting a third clock signal (93) and a clock control circuit (65) for controlling the first to third clock signal frequencies individually. It is Group-chip microcomputer of. The clock pulse generator includes first frequency changing means (910, 911, 912, 913, 914) coupled to first connection terminals (XTAL, EXTAL) that can be coupled to an external clock source, and an external clock. Second frequency changing means (921) coupled to a second connection terminal (CKIO) that can be coupled to the source, and selecting means for selecting one of the outputs of the first and second frequency changing means (930, 931) and third frequency changing means (940, 941, 942, 943) for receiving the clock signal selected by the selecting means and changing the first to third clock signal frequencies individually. And a clock signal path (951) for outputting the clock signal output from the first frequency changing means as an external clock signal. At this time, the clock control circuit (65) is coupled to the external clock mode terminals (MD0 to MD2), specially specifies the frequency change rate for the first and third clock signals by the third frequency changing means, and A clock control register (650) in which control information for designating a frequency change rate by the frequency change means of 2 is set by the central processing unit is provided, and the frequency change by the first frequency change means according to the state of the external clock mode terminal The rate is determined so that the clock signal can be transmitted from the first connection terminal to the input of the third frequency changing means, and the second clock signal frequency matches the clock signal frequency output from the first frequency changing means. To control the third frequency changing means in the first state, or from the second connection terminal to the input of the third frequency changing means. The second state for controlling the transmission of the clock signal is selected, and the frequency change rate by the second frequency changing means and the first and third frequency changing means by the third frequency changing means according to the control information set in the clock control register. The frequency change rate corresponding to the third clock signal is variably controlled, and in the second state designated by the clock mode terminal, the second clock signal is controlled according to the control information set in the clock control register. The frequency change rate for the second clock signal by the third frequency changing means is controlled so that the frequency of the second clock signal matches the frequency of the clock signal supplied from the second connection terminal.
[0019]
In order to further expand the frequency changeable range of the first and second clock signals, the output of the first frequency change means is used as the input of the second frequency change means in the first state designated by the clock mode terminal. Connection means (920) for connection may be provided. At this time, when an external device (for example, a synchronous dynamic random access memory) is operated in synchronization with a clock signal as described above, a clock signal for synchronous operation is supplied to the external device. In consideration, the clock signal path may be coupled to the second connection terminal.
[0020]
When the first connection terminal is used both as the connection terminal of the vibrator and the input terminal of the external clock signal, the first frequency changing means is connected to the first connection terminal as an oscillator that is oscillated by externally attaching an oscillator. 910) and a clock signal directly supplied from the first connection terminal are selected, and a frequency dividing circuit (913) and a phase-locked loop circuit (912) for receiving the selected clock signal are provided. Any one of the outputs can be constituted by a selection means (914) for outputting the basic clock signal. When the third frequency changing means is constituted by a frequency divider, the frequency changeable range can be increased if the second frequency changing means is constituted by a phase-locked loop circuit as a multiplying means.
[0021]
[Action]
[1] According to the above means for controlling both the operating frequency and the operating voltage of the circuit module, the control information indicating the switching mode of the clock signal frequency and the operating voltage can be rewritten by the central processing unit or the like. Since it is set in the storage means, the control information is rewritten as necessary according to the data processing performance of the circuit module and the weight of the data processing, thereby allowing free switching with respect to the operating voltage and operating frequency of the circuit module. This gives priority to low power consumption for tasks or circuit modules that do not require relatively high-speed data processing, and reduces power consumption for tasks or circuit modules that require relatively high-speed processing. An increase is allowed, thereby realizing low power consumption while improving the overall data processing efficiency. Making it possible to individually switch the clock frequency and the operating voltage for each predetermined circuit module makes it possible to more finely implement control for reducing power consumption while improving the overall data processing efficiency.
[0022]
When reducing both the frequency of the clock signal and the operating voltage, if the operating voltage is reduced first, the drive capability of the circuit in the operating state is lowered until the clock signal frequency is reduced, which is undesirable. There is a risk of malfunction due to a short signal delay. In this case, the first control means controls the switching procedure of the frequency and the operating voltage so as to prevent the state where the operating voltage is reduced prior to the change of the current operating frequency. In addition, when increasing the clock signal frequency and operating voltage, if the clock signal frequency is increased first, the drive capability of the circuit in the operating state is increased until the operating voltage is increased. There is a risk of malfunctioning without being able to follow up. In this case, the first control means described above controls the switching procedure of the frequency and the operating voltage so as to prevent the state in which the clock signal having the increased frequency is output prior to the increase of the operating voltage. In this way, the first control means prevents malfunction in terms of the switching procedure of the clock signal frequency and the operating voltage.
[0023]
When switching the clock frequency and power supply voltage, increasing the frequency of the clock signal without increasing the power supply voltage in absolute value means that even if the operation of the circuit is accelerated, the drive capability of the circuit is not improved and the high-speed operation This results in a relatively large signal propagation delay that is inadequate for. Further, reducing the power supply voltage in absolute value without reducing the clock signal frequency means that the circuit still operates at high speed despite the fact that the drive capability of the circuit is reduced and the signal propagation delay is increased. Become. In response to such an instruction, the second control means described above suppresses switching between the clock frequency and the power supply voltage, thereby preventing a malfunction due to an undesired switching mode between the frequency and the power supply voltage.
[0024]
[2] According to the above-described means for switching the operating frequency for the data processing device in which the internal bus is hierarchized, in the data processing device in which the first to third internal buses are hierarchized, the second clock signal is Excluded from clock signals with variable frequency. In the means of the above specific aspect, when the frequencies of the first and third clock signals are dynamically changed according to the control information, the clock control circuit is controlled to keep the frequency of the second clock signal constant. To do. This is because the frequency of the second clock signal for the second internal bus to which the bus controller is coupled is not the frequency corresponding to the operation speed of the external device coupled to the external bus. Alternatively, the condition that the bus operation cannot be synchronized is satisfied. Enabling the variable control of the first clock signal frequency dynamically with control information means that the circuit module of the first internal bus to which the central processing unit is coupled can operate at high speed as necessary. In order to satisfy the point that it is desirable for data processing, and conversely, when executing a task that does not require high-speed operation, the clock signal frequency is lowered to realize low power consumption. The fact that the frequency of the third clock signal can be dynamically variably controlled by the control information means that the function and operation state of the circuit module coupled with the third internal bus is a peripheral circuit module. Accordingly, the operation speed can be controlled independently of other circuit modules, and the reduction in power consumption is promoted.
[0025]
The external clock signal output from the output terminal (CKIO) matches the frequency of the second clock signal. An external device that operates in synchronization with the clock signal is controlled by a bus controller (operation that receives the second clock signal), and is output from the external terminal (CKIO) as a clock signal for synchronization operation of such an external device. Signal available.
[0026]
【Example】
[1] First, a plurality of embodiments relating to the invention for controlling both the operating frequency and operating voltage of a circuit module will be described with reference to FIGS.
[0027]
FIG. 1 is a block diagram of a single chip microcomputer according to the first embodiment of the present invention. The single-chip microcomputer 1 of this embodiment includes a central processing unit (also referred to as CPU) 100, a multiplier circuit (also referred to as MULT) 101, a division (DIVU) 102, and direct memory access as circuit modules that are operated in synchronization with a clock signal. A controller (also referred to as DMAC) 103, a timer (also referred to as TMR1) 104, and a timer (also referred to as TMR2) 105 are typically provided, and further include a RAM, a ROM, an external bus interface circuit, and the like (not shown). It is possible to connect via a predetermined internal bus. Although not particularly limited, both the multiplication circuit 101 and the division 102 are positioned as coprocessors that decode commands issued by the central processing unit 100 and perform data processing. The ROM (not shown) holds an operation program for the central processing unit 100 and the like. A RAM (not shown) is used as a work area of the central processing unit 100 or a temporary storage area for data.
[0028]
The operation power supply of the circuit modules 100 to 105 representatively shown in FIG. 1 is supplied from the power supply circuit 110. The power supply circuit 110 receives a power supply voltage such as 5V from the power supply pin 111 and a ground voltage such as 0V from the ground pin 112, and can selectively output different internal voltages 113 as the operation power supply of the circuit modules 100 to 105. To be. According to this embodiment, the internal voltage 113 is the power supply voltage or a voltage obtained by stepping down the power supply voltage with reference to the ground potential. The ground potential is commonly supplied to each circuit module.
[0029]
The operation clock signals of the circuit modules 100 to 105 representatively shown in FIG. The clock generation circuit 120 receives an external clock signal from an external clock input pin 121 or an oscillation output generated via a vibrator (not shown), and can selectively output a clock signal having a different frequency as the internal clock signal 122. .
[0030]
FIG. 2 shows a detailed example of the clock generation circuit 120. A clock generation circuit 120 shown in FIG. 1 includes a PLL circuit 1201 that receives an external clock signal and multiplies the output of the clock signal, and a frequency dividing circuit 1202 coupled in two stages to the output of the PLL circuit 1201 in series. 1203. For example, the frequency dividing circuits 1202 and 1203 set the input frequency to ¼ and output them. The outputs of the PLL circuit 1201 and the frequency dividing circuits 1022 and 1023 are selected via a selector 1205, and the selected clock signal is sent to the clock of each circuit module 100 to 105 via an output gate 1206 such as a clocked inverter. Supplied to the input terminal. In the figure, one set of selector and output gate is representatively shown. However, when the frequency of the internal clock signal is set for each predetermined circuit module, the selector 1205 and the output gate 1206 are set for each predetermined circuit module. Should be understood to be provided. The same applies to the internal voltage 113 selected by the power supply circuit 110.
[0031]
The voltage setting register 114 and the frequency setting register 124 shown in FIG. 1 store rewritable control information for designating the frequency of the internal voltage 113 and the internal clock signal 123 to be supplied to the circuit modules 100 to 105. It is a storage means. The voltage setting register 114 and the frequency setting register 124 are arranged, for example, in a predetermined address space of the central processing unit 100, and control information is obtained when the central processing unit 100 executes an instruction such as an LDC (load control register) instruction. Is set. Therefore, the voltage setting register 114 and the frequency setting register 124 can be rewritten as desired depending on the operation program of the microcomputer 1. For example, it can be set for each task according to the processing weight. That is, it is only necessary to include the registers 114 and 124 in the target of saving, initial setting, restoration, etc. of the stack pointer and status register of the CPU 100 when starting the task.
[0032]
FIG. 3 shows a detailed example of the voltage setting register 114 and the frequency setting register 124. Although the voltage setting register 114 is not particularly limited, it is composed of 8 bits. For example, the internal voltage 113 supplied to the CPU 100, MULT 101, DIVU 102, and DMAC 103 is determined by a 2-bit value. In each 2 bits, “00” means the maximum voltage level (Vmax), “01” means (Vmax) × 1/2, “10” means (Vmax) × 1/4, “11” means the ground potential. To do. Although the frequency setting register 124 is not particularly limited, it is composed of 8 bits. For example, the internal clock signal frequency supplied to the CPU 100, MULT 101, DIVU 103, and DMAC 103 is determined by a 2-bit value. In each 2 bits, “00” is the maximum frequency (Fmax), “01” is (Fmax) × 1/4, “10” is (Fmax) × 1/16, “11” is the internal clock supply stop. means. At the time of power-on reset, both registers 114 and 124 are initialized to all 0 bits. In the configuration of the registers 114 and 124 as shown in FIG. 3, the operating power supply and internal clock signal frequency to be supplied to other circuit modules can be fixed to predetermined values. In order to increase the number of modules subject to variable control of the operating voltage and clock signal frequency, the number of bits of the voltage setting register 114 and the frequency setting register 124 is increased, and the voltage and clock in the power supply circuit 110 and the clock generation circuit 120 are increased accordingly. What is necessary is just to increase the logic scale for signal frequency selection.
[0033]
In FIG. 1, reference numeral 130 denotes a frequency selection of the internal clock signal 122 and a level selection of the internal voltage 113 in the clock generation circuit 120 and the power supply circuit 110 based on the control information stored in the voltage setting register 114 and the frequency setting register 124. It is a control circuit to control. The control information stored in the voltage setting register 112 and the frequency setting register 124 is given to the power supply circuit 100 and the clock generation circuit 120 via the control circuit 130, so that the power supply circuit 100 and the clock generation circuit 120 are in accordance with the control information. The frequency of the internal clock signal 122 and the internal voltage 113 are selected and supplied to the corresponding circuit module.
[0034]
The control circuit 130 includes first control means 131 and second control means 132 in order to prevent malfunction of the circuit module when switching between the operating voltage and the clock signal frequency.
[0035]
The first control means 131 is responsible for control for preventing malfunction of the internal circuit module in terms of the switching procedure of the frequency of the internal clock signal 122 and the internal voltage 113. That is, in a case where both the frequency of the internal clock signal 122 and the internal voltage 113 are decreased, if the internal voltage 113 is decreased first, the circuit kept in an operating state until the frequency of the internal clock signal 122 is decreased. There is a possibility that the drive capability of the circuit in the module is lowered and malfunction occurs due to an undesired signal delay. When the frequency of the internal clock signal 122 and the internal voltage 113 are increased, if the frequency of the internal clock signal 122 is first increased, the circuit module that has been in an operating state until the internal voltage 113 is increased. The driving ability of the internal circuit may not follow the improvement of the operation speed and may cause a malfunction. Therefore, in order to deal with these, the first control unit 131 uses the frequency of the clock signal 122 and the internal voltage 113 as a procedure for changing the frequency of the internal clock signal 122 and the internal voltage 113 in the clock generation circuit 120 and the power supply circuit 110. When the instruction to decrease the operating voltage 113 is detected, the state in which the operating voltage 113 is reduced prior to the change of the current operating frequency is prevented, and when the instruction to increase the frequency of the internal clock signal 122 and the internal voltage 113 is detected. Prior to the increase of the voltage 113, the clock signal 122 having an increased frequency is prevented from being supplied to the circuit module.
[0036]
For example, when the switching mode of the operating voltage and the frequency is determined and both the frequency of the internal clock signal 122 and the internal voltage 113 are decreased, the changed value of the frequency setting register 124 is supplied to the clock generation circuit 120 first. When the operating voltage is changed after changing the frequency to increase both the frequency of the internal clock signal 122 and the internal voltage 113, the value of the changed voltage setting register 114 is supplied to the power supply circuit 100 first. Then, the procedure of changing the frequency after raising the operating voltage can be adopted for the first control means 131. Alternatively, the procedure of stopping the supply of the clock signal 122 to the circuit module via the output gate 1206 at the time of switching between the operating voltage and the frequency, and restarting the supply of the clock signal 122 after a certain period of time during which the circuit operation is stabilized is provided. It can be adopted as one control means 131. In FIG. 1, the first control means 131 is illustrated as hardware independent of the central processing unit 100, but its function can be realized by the central processing unit 100 and its operation program.
[0037]
The second control means 132 performs control for preventing malfunction due to an undesired switching mode between the frequency of the internal clock signal 122 and the internal voltage 113. That is, if the frequency of the clock signal 122 is increased without increasing the internal voltage 113 in switching between the frequency of the internal clock signal 122 and the internal voltage 113, the driving capability of the circuit is not improved even if the operation of the circuit is increased. In other words, a relatively large signal propagation delay that is unsuitable for the high-speed operation occurs. Further, if the internal voltage 113 is decreased without decreasing the frequency of the clock signal 122, the circuit still operates at a high speed although the driving capability of the circuit is reduced and the signal propagation delay is increased. Therefore, the second control means 132 is based on the control information before and after the rewriting of the storage means composed of the voltage setting register 114 and the frequency setting register 124 in order to prevent the malfunction by switching in these modes. And detecting an instruction to increase the frequency of the internal clock signal 122 without increasing the internal voltage 113, or an instruction to decrease the internal voltage 113 without decreasing the frequency of the internal clock signal 122. The change of the output state of the clock generation circuit 120 and the power supply circuit 110 is suppressed.
[0038]
For example, when the second control means detects a rewrite instruction to the voltage setting register 114 and the frequency setting register 124, the second control means holds the values of the registers 114 and 124 immediately before the rewriting, and the registers 114 rewritten with the held values. , 124 is compared with each other to determine whether the undesired state has been instructed. When it is detected that the instruction is undesired, the control circuit 130 is made to suppress the frequency and voltage selection state update by the changed values of the registers 114 and 124, and further the error state is sent to the central processing unit 100. Notification is made to prompt the user to set the registers 114 and 124 again. As a result, malfunction due to an undesired switching mode between the frequency and the power supply voltage can be prevented.
[0039]
Although the second control unit 132 is illustrated in FIG. 1 as being configured by hardware independent of the central processing unit 100, its function can be realized by the central processing unit 100 and its operation program. it can. That is, in the change processing routine of the voltage setting register 114 and the frequency setting register 124, the central processing unit 100 first reads the values of the registers 114 and 124, compares the read values with the values to be changed, and compares the undesired values. It is determined whether it is in the instruction state, and if it is in an undesired instruction state, the change processing routine is terminated and a predetermined exception processing routine is performed.
[0040]
FIG. 4 shows an example of an operation voltage and frequency switching control procedure by the control circuit 130. When lowering the operating voltage and frequency, the CPU 100 rewrites the frequency setting register 124 with a value that lowers the frequency of the required circuit module (step S10), and a value that lowers the operating voltage of the required circuit module. Thus, the voltage setting register 114 is rewritten by the CPU 100 (step S11). The control circuit 130 and the logic circuit 140 check the setting state for the rewritten value (step S12). If the result of the check is an instruction to increase the frequency of the internal clock signal 122 without increasing the internal voltage 113, or an instruction to decrease the internal voltage 113 without decreasing the frequency of the internal clock signal 122, This is notified to the central processing unit 100 and the processing is terminated. In the other switching mode, in the idling state where the output of the internal clock signal 122 is stopped by the output gate 1206 (step S13), the internal voltage 113 and the internal clock are set according to the set values of the frequency setting register 124 and the voltage setting register 114. The frequency of the signal 122 is switched. This idling state is continued for a predetermined time until the states of the power supply circuit 110 and the clock generation circuit 120 are stabilized, and thereafter, the output gate 1206 restarts the output of the internal clock signal, thereby enabling operation at a new voltage and frequency. (Step S14).
[0041]
When increasing the operating voltage and frequency, the CPU 100 rewrites the voltage setting register 114 with a value that increases the internal operating voltage of the required circuit module (step S20), so as to increase the operating frequency of the required circuit module. With this value, the CPU 100 rewrites the frequency setting register 124 (step S21). The control circuit and the logic circuit check the set state for the rewritten value (step S22). If the result of the check is an instruction to increase the frequency of the internal clock signal 122 without increasing the internal voltage 113, or an instruction to decrease the internal voltage 113 without decreasing the frequency of the internal clock signal 122, This is notified to the central processing unit 100 and the processing is terminated. In the other switching mode, in the idling state where the output of the internal clock signal 122 is stopped by the output gate 1206 (step S23), the internal voltage 113 and the internal clock are set according to the set values of the frequency setting register 124 and the voltage setting register 114. The frequency of the signal 122 is switched. This idling state is continued for a predetermined time until the states of the power supply circuit 110 and the clock generation circuit 120 are stabilized, and thereafter, the output gate 1206 restarts the output of the internal clock signal, thereby enabling operation at a new voltage and frequency. (Step S24). The other switching modes are similarly controlled.
[0042]
The procedure of switching between the internal clock signal frequency and the internal voltage in the idling state in which the output of the internal clock signal 122 is stopped in the procedure of FIG. The state in which the power supply voltage is decreased prior to the change of the power supply voltage is prevented, and the state in which the clock signal having the increased frequency is supplied to the circuit module prior to the increase in the power supply voltage is prevented. In particular, this can be realized by a simple method of stopping the supply of the internal clock signal at the time of switching. The idling period can be controlled by the timer 105. The timer 105 is supplied with a clock signal through a path different from other circuit modules, and the timer 105 can maintain counting or timing operation even if the supply of the clock signal to the other circuit modules is stopped. It has become. As a control procedure by the first control means, when lowering the voltage and frequency, first, the switching operation for lowering the frequency is completed and then the operation for lowering the internal voltage is performed, and the voltage and frequency are raised. In some cases, it is possible to perform control so as to perform an operation of increasing the frequency after completing the switching for raising the internal voltage first. However, in that case, the control of the switching procedure must be individualized or classified for each switching mode.
[0043]
The first embodiment has the following operational effects. (1) Since the control information for instructing the mode of switching between the clock frequency and the operating voltage is set in the frequency setting register 124 and the voltage setting register 114 so as to be rewritable by the central processing unit, the circuit module built in the single chip microcomputer 1 By rewriting the control information as necessary according to the performance of the circuit and the weight of data processing, free switching with respect to the operating voltage and operating frequency of the circuit module can be realized. Therefore, prioritize low power consumption for tasks or circuit modules that do not require relatively high-speed data processing, and increase power consumption for tasks or circuit modules that require relatively high-speed processing. In this way, low power consumption can be realized while improving the overall data processing efficiency. By making it possible to individually switch the clock frequency and the power supply voltage for each predetermined circuit module, it is possible to further finely implement the control for reducing the power consumption while improving the overall data processing efficiency.
[0044]
(2) Increasing the frequency of the clock signal without increasing the operating voltage in switching between the clock frequency and the operating voltage is not suitable for the high-speed operation without improving the circuit driving capability even if the operation of the circuit is increased. A relatively large signal propagation delay. Further, reducing the power supply voltage without lowering the clock signal frequency results in the circuit still operating at high speed despite the fact that the drive capability of the circuit is reduced and the signal propagation delay is increased. The second control means 132 described above suppresses switching of the clock frequency and the power supply voltage in response to such an instruction, thereby preventing a malfunction due to an undesired switching mode of the frequency and the operating voltage.
[0045]
(3) When reducing both the frequency of the clock signal and the operating voltage, if the operating voltage is reduced first, the drive capability of the circuit in the operating state is reduced until the clock signal frequency is reduced. There is a risk of malfunction due to undesired signal delay. In this case, the first control means 131 controls the switching procedure of the frequency and the operating voltage so as to prevent the state where the operating voltage is reduced prior to the change of the current operating frequency. Also, when increasing the clock signal frequency and operating voltage, if the clock signal frequency is increased first, the drive capability of the circuit in the operating state is increased until the operating voltage is increased. There is a risk of malfunctioning without being able to follow up. Also in this case, the first control unit 131 controls the switching procedure of the frequency and the operating voltage so as to prevent the state where the clock signal whose frequency is increased prior to the increase of the operating voltage is supplied. Therefore, it is possible to prevent the possibility that the circuit module malfunctions in terms of the switching procedure of the clock signal frequency and the operating voltage.
[0046]
FIG. 5 shows a second embodiment of the data processing apparatus according to the present invention. Circuit blocks having the same functions as those shown in FIG. 1 are given the same reference numerals, and detailed descriptions thereof are omitted. In the second embodiment shown in FIG. 5, the power supply circuit 110 and the clock generation circuit 120 are arranged outside the chip with respect to the embodiment shown in FIG. 1, and the power supply voltage selection signal 150 and the frequency selection signal 151 are provided. A power supply of a voltage received by the microcomputer and instructed thereby is supplied to the power supply pin 111, and a clock signal having a frequency designated thereby is supplied to the clock input pin 121. As in the embodiment of FIG. 1, when the internal voltage and the operating frequency can be set for each predetermined circuit module, a plurality of power supply pins 111 and clock input pins 121 are required. Further, although not specifically shown, in the embodiment of FIG. 1, a part of the voltage setting register 114 and the frequency setting register 124 are allocated for selecting the operation of the external power supply circuit and the external clock generation circuit, and the values set thereby are set. A corresponding control signal can be output to the outside of the chip, and in the embodiment of FIG. 1, the frequency of the power supply voltage supplied to the power supply pin 111 and the frequency of the external clock signal supplied to the clock input pin 121 can be switched. it can.
[0047]
FIG. 6 is a block diagram of a single chip microcomputer which is a third embodiment of the data processing apparatus according to the present invention. The single-chip microcomputer 3 of this embodiment includes a central processing unit (also referred to as CPU) 300, a multiplication circuit (also referred to as MULT) 301, a division (DIVU) 302, a memory 303, as circuit modules that are operated in synchronization with a clock signal. And a timer 304 as a representative, and further, an external bus interface circuit (not shown) and the like, which are connectable via a predetermined internal bus 305. Although not particularly limited, both the multiplication circuit 301 and the division circuit 302 are positioned as coprocessors that decode commands issued from the central processing unit 300 and perform data processing. The memory 303 constitutes a ROM holding an operation program of the central processing unit 100, a RAM serving as a work area of the central processing unit 100 or a temporary storage area for data.
[0048]
In FIG. 6, reference numeral 306 denotes a voltage / frequency control unit that generates an operation power supply and an operation clock signal for the circuit modules 300 to 304 shown as representatives and outputs the operation clock signal to each unit. Reference numeral 311 denotes a power supply pin to which a power supply voltage Vin such as 3.3V is supplied, 312 denotes a ground pin receiving a ground potential such as 0V, and 321 denotes a clock input pin to which an external clock signal CLKin is supplied. 340 is an internal clock signal output from the voltage / frequency control unit 306 and supplied to the circuit modules 300 to 303, 341 is an internal clock signal supplied exclusively to the timer 304, and 342 is supplied to each part of the microcomputer. This is an operating voltage as a power supply voltage.
[0049]
First, the voltage / frequency control unit 306 will be schematically described. The voltage / frequency control unit 306 has a mode register 307 for designating the clock signal frequency and the operating voltage of the circuit module for each circuit module, and is set by the central processing unit 300 to be rewritable to the mode register 307. In accordance with the control information, the operating voltage and operating clock frequency of the circuit module are changed and supplied to each unit. Control information is written to the mode register 307 from the central processing unit 300 via the internal bus 305, and when control information having an inappropriate content is set in the mode register 307, this is notified to the central processing unit 300. When the switching mode between the operating voltage and the operating frequency is likely to malfunction, the switching is prohibited. When switching is permitted, the supply of the clock signal for a certain period of time managed by the timer 304 is stopped, so that malfunction does not occur due to unstable operation of the circuit accompanying switching. The contents of the mode register 307 can be switched for each task, and the power consumption and data processing performance can be controlled in units of tasks.
[0050]
FIG. 7 shows a detailed example of the voltage / frequency control unit 306. The voltage / frequency control unit 306 includes a power supply circuit 310, a clock generation circuit 320, and a control circuit 330. The power supply circuit 310 receives the power supply voltage Vin from the power supply pin 311 and receives a ground voltage such as 0 V from the ground pin 312 and can selectively output different internal voltages 342 as the operation power supply of the circuit modules 300 to 304. . According to this embodiment, the internal voltage 342 is set to the power supply voltage (Vin = 3.3V) or a voltage obtained by stepping down the power supply voltage (2.5V) with reference to the ground potential. The ground potential is commonly supplied to each circuit module. The stepped down voltage is formed by a DC / DC converter 313. Both operating voltages are supplied to the inputs of representatively shown selectors 3141 to 3143 provided for each of the modules 300 to 304, and the outputs of the respective selectors 3141 to 3143 are coupled to the power supply terminals of the corresponding circuit modules. Representatively shown selectors 3141 to 3143 select and output an input voltage individually according to control information stored in a voltage setting field (to be described later) of mode register 307. Although not particularly limited to other circuits such as a voltage / frequency control circuit, 3.3 V is supplied as an operation power supply.
[0051]
As shown in FIG. 8, the DC / DC converter 313 includes a switching element 3131, a reference potential generation circuit 3132 that forms a reference potential Vref of 2.5 V from the input voltage Vin, an operational amplifier 3133, a Schottky diode 3134, a coil 3135, The step-down switching regulator includes a smoothing capacitor 3136, and generates a voltage Vout stepped down to 2.5V by a negative feedback operation by the operational amplifier 3133. The coil 3135 is external to the chip, and the Schottky diode 3134 may be internal or external to the chip.
[0052]
The clock generation circuit 320 receives an external clock signal from an external clock input pin 321 or an oscillation output generated via a vibrator (not shown), and can selectively output a clock signal having a different frequency as the internal clock signal 340. Is done. That is, the clock generation circuit 120 includes a PLL circuit 322 that receives an external clock signal, multiplies the frequency, and outputs the PLL circuit 322, and frequency dividing circuits 323 and 324 coupled in series to the output of the PLL circuit 322. Prepare. The frequency dividing circuits 323 and 324 output the input frequency, for example, by 1/4. The outputs of the PLL circuit 322 and the frequency dividing circuits 323 and 324 are supplied to the inputs of representative selectors 3251 to 3253 provided in the circuit modules 300 to 303, and the outputs of the selectors 3251 to 3253 are output. Are coupled to the clock input terminals of the corresponding circuit modules via output gates 3261 to 3263 such as clocked inverters. Representative selectors 3251 to 3253 select and output inputs according to control information stored in a frequency setting field (described later) of mode register 307. Note that the supply of the clock signal 341 dedicated to the timer 304 is not stopped.
[0053]
FIG. 9 shows a detailed example of the mode register 307. The mode register 307 includes a voltage setting field 3071 and a frequency setting field 3072. The voltage setting field 3071 is assigned bit by bit to each of the circuit modules 300 to 303 that are representatively shown, and the logical value “1” means 2.5V and “0” means 3V. The internal voltage to be supplied is specified. The frequency setting field 3072 is assigned by 2 bits to each of the circuit modules 300 to 303 shown representatively. “00” is 100 MHz, “01” is 25 MHz, “10” is 6.25 MHz, and “11” is a clock. This means stop, and the clock signal frequency to be supplied to the corresponding circuit module is designated accordingly. According to the configuration of FIG. 7, the control information in the voltage setting field 3071 is latched in the latch circuit 331 at a predetermined timing, and the latched control information is supplied to the selection terminals of the selectors 3141 to 1143 for the corresponding circuit module. The The control information in the frequency setting field 3072 is latched in the latch circuit 332 at a predetermined timing, and the latched control information is decoded by the decoder 333 every 2 bits, and the decoded selection signal for each corresponding circuit module is decoded. It is supplied to the selection terminals of the selectors 3251-3253. As a result, the operating voltage specified in the voltage setting field 3071 and the clock signal having the frequency specified in the frequency setting field 3072 are supplied to each of the circuit modules 300 to 303 separately.
[0054]
The mode register 307 is arranged, for example, in a predetermined address space of the central processing unit 300, and control information is set by the central processing unit 300 executing an instruction such as an LDC (load control register) instruction. . Therefore, the mode register 307 can be rewritten as desired depending on the operation program of the microcomputer 3. For example, it can be set for each task according to the processing weight. That is, it is only necessary to include the mode register in the target of saving, initial setting, restoration, etc. of the stack pointer and status register of the CPU 300 when starting the task. At the time of power-on reset, both registers 114 and 124 are initialized to all 0 bits.
[0055]
The control circuit 330 includes the latch circuits 331 and 332 and the decoder 333, and has a sequence control unit 334 that controls the latch timing of the latch circuits 331 and 332 and the operation of the output gates 3261 to 3263, and the mode register 307. The switching of the operating voltage and frequency based on the control information stored in is controlled. The sequence control unit 334 includes a first control unit 3341 and a second control unit 3342 in order to prevent malfunction of the circuit module when switching the operating voltage and the clock signal frequency.
[0056]
The first control means 3341 manages the control for preventing malfunction of the internal circuit module in terms of the switching procedure between the frequency of the internal clock signal 340 and the internal voltage 342. That is, in a case where both the frequency of the internal clock signal 340 and the internal voltage 342 are decreased, if the internal voltage 342 is decreased first, the circuit kept in an operating state until the frequency of the internal clock signal 340 is decreased. There is a possibility that the drive capability of the circuit in the module is lowered and malfunction occurs due to an undesired signal delay. When the frequency of the internal clock signal 340 and the internal voltage 342 are increased, if the frequency of the internal clock signal 340 is first increased, the circuit module that has been in an operating state until the internal voltage 342 is increased. The driving ability of the internal circuit may not follow the improvement of the operation speed and may cause a malfunction. Therefore, in order to deal with these, the first control unit 3341 uses the frequency of the clock signal 340 and the internal voltage 342 as a procedure for changing the frequency of the internal clock signal 340 and the internal voltage 342 in the clock generation circuit 320 and the power supply circuit 310. When an instruction to decrease the operating voltage 342 is detected before the current operating frequency is changed, a state in which the operating voltage 342 is reduced is prevented, and when an instruction to increase the frequency of the internal clock signal 340 and the internal voltage 342 is detected. The state where the clock signal 340 having an increased frequency is supplied prior to the increase of the voltage 342 is prevented.
[0057]
The second control means 3342 manages control for preventing malfunction due to an undesired switching mode between the frequency of the internal clock signal 340 and the internal voltage 342. That is, if the frequency of the clock signal 340 is increased without increasing the internal voltage 342 in switching between the frequency of the internal clock signal 340 and the internal voltage 342, the driving capability of the circuit is not improved even if the operation of the circuit is increased. In other words, a relatively large signal propagation delay that is unsuitable for the high-speed operation occurs. Further, if the internal voltage 342 is decreased without decreasing the frequency of the clock signal 340, the circuit still operates at a high speed although the driving capability of the circuit is reduced and the signal propagation delay is increased. Therefore, the second control means 3342 can be switched in these manners so as not to cause a malfunction, based on the control information before and after rewriting the mode register 307 without increasing the internal voltage 342. By detecting an instruction to increase the frequency of the internal clock signal 340 or an instruction to decrease the internal voltage 342 without decreasing the frequency of the internal clock signal 340, the outputs of the clock generation circuit 320 and the power supply circuit 310 based on the instruction are detected. Prohibit state change.
[0058]
FIG. 10 shows an example of the control mode by the first and second control means 3341 and 3342. That is, the mode of error in which switching between the frequency and the operating voltage is prohibited by the second control means 3342 is that the frequency is increased without changing the operating voltage (a), and the operating voltage is decreased without changing the frequency. (D) and (f) when the operating voltage is decreased by increasing the frequency. The operation voltage and frequency switching procedure should be defined by the first control means 3341 when the frequency and the operating voltage are both increased (e), when the frequency and the operating voltage are both decreased (h), And (g) when the frequency is decreased and the operating voltage is increased. In the case of the mode (e), the circuit module must not be operated with the clock signal whose operating frequency is increased before the operating voltage is increased. In the cases (g) and (h), the operating voltage must not be changed before the current operating frequency is changed.
[0059]
For example, the first control means 3341 determines the switching mode between the operating voltage and the frequency, and in the case of (g) and (h) in FIG. 10, the value of the frequency setting field 3072 is first latched in the latch circuit 332. Thus, the frequency is changed, and then the value of the voltage setting field is latched by the latch circuit 331 to change the operating voltage. In the case of the mode (e), the value of the voltage setting field is latched by the latch circuit 331 to change the operating voltage, and then the value of the frequency setting field 3072 is latched by the latch circuit 332 to change the frequency. Regarding other aspects, the latch timing of the latch circuits 332 and 331 is not defined at all. The first control means 3341 stops the supply of the clock signal 340 to the circuit module through the output gates 3261 to 3263 when the operating voltage and frequency are switched, and a certain period of time during which the circuit operation is stabilized elapses. You may employ | adopt the procedure which restarts supply of the clock signal 340 later. In FIG. 6, the first control means 3341 is illustrated as hardware independent of the central processing unit 300, but its function can be realized by the central processing unit 300 and its operation program.
[0060]
For example, when the second control unit 3342 detects a rewrite instruction to the mode register 307, the second control unit 3342 holds the value of the register 307 immediately before the rewrite, and stores the previous value held and the value of the rewritten mode register 307. In comparison, it is determined whether the error modes (a), (d), and (f) are instructed. When the error mode is detected, the frequency and voltage selection state change due to the changed value of the mode register 307 is suppressed. That is, the latch operation by the latch circuits 331 and 332 is prohibited. Furthermore, the central processing unit 100 is notified that the error mode has been instructed, and the setting of the mode register 307 is prompted again. As a result, malfunction due to an undesired switching mode between the frequency and the power supply voltage can be prevented.
[0061]
The second control means 3342 is illustrated in FIG. 6 as being configured by hardware independent of the central processing unit 300, but its function can be realized by the central processing unit 300 and its operation program. it can. That is, in the change processing routine of the mode register 307, the central processing unit 300 first reads the value of the register 307, compares the read value with the value to be changed, and determines whether or not the above-described error mode is present. If so, the change processing routine is terminated and a predetermined exception processing routine is performed.
[0062]
FIG. 11 shows an example of an operation voltage and frequency switching control procedure by the sequence control unit 334. First, control information is written in the mode register 307 by the central processing unit 300 (step S30). The sequence control unit 334 checks the setting state based on the control information before and after rewriting (step S31). As a result of the check, when it is detected that the setting state is any of the modes (a), (d), and (f) in FIG. 10, an error is notified to the central processing unit 300 and the process is terminated (step S32). ). When the mode of switching is other than that, the output gates 3261 to 3263 are controlled to the high output impedance state to stop the output of the clock signal 340 (step S34), and the timer count operation by the timer 304 is started (step S34). ). In this state, since the operation clock signal is not supplied to the circuit module that enables switching between the clock signal frequency and the operation voltage, each operation is stopped. At this time, the sequence control unit 334 performs the latch operation of the latch circuits 331 and 332, whereby the selection state of the clock signal by the selectors 3251 to 3253 is changed according to the latched control information and the selectors 3141 to 3143 are used. The selection state of the operating voltage is changed, and the operating voltage and the frequency are switched (step S35). Next, it is detected that the timer count by the timer 304 has been counted up (step S36), and the supply of the clock signal 340 is resumed. The time until the timer count by the timer 304 is counted up is a time required until the states of the power supply circuit 310 and the clock generation circuit 320 are stabilized and the switched voltage is stabilized in the corresponding circuit module. The This allows operation at new operating voltages and frequencies.
[0063]
The procedure of switching the internal clock signal frequency and the internal voltage in a state where the output of the internal clock signal 340 is stopped in this control procedure and then restarting the supply of the internal clock signal after a lapse of a certain time is prior to the change of the current operating frequency. Thus, a procedure for preventing a state where the power supply voltage is reduced and preventing a state where a clock signal having an increased frequency is supplied to the circuit module prior to the increase of the power supply voltage is realized. In particular, this can be realized by a simple method of stopping the supply of the internal clock signal at the time of switching. The timer 304 is supplied with a dedicated clock signal 341 different from other circuit modules, and the timer 304 can maintain the timer count operation even if the supply of the clock signal to the other circuit modules is stopped. It is like that.
[0064]
FIG. 12 shows another example of the operation voltage and frequency switching control procedure by the sequence control unit 334. In the procedure shown in the figure, after step S31, step S40 for determining whether the switching corresponds to the modes (g) and (h) in FIG. 10 is interposed. In this mode, the internal clock signal is stopped. (Step S41) and the timer count is started (Step S42), the frequency is changed first (Step S43), and after the timer count ends (Step S44), the supply of the clock signal is resumed (Step S45). The operating voltage is changed (step S46).
[0065]
The third embodiment has the following operational effects. (1) Since the control information for instructing the mode of switching between the clock frequency and the operating voltage is set in the mode register 307 so as to be rewritable by the central processing unit, the performance of the circuit module built in the single chip microcomputer 3 and data processing By rewriting the control information as needed according to the weight, free switching with respect to the operating voltage and operating frequency of the circuit module can be realized. Therefore, prioritize low power consumption for tasks or circuit modules that do not require relatively high-speed data processing, and increase power consumption for tasks or circuit modules that require relatively high-speed processing. In this way, low power consumption can be realized while improving the overall data processing efficiency. Furthermore, by making it possible to individually switch the clock frequency and the power supply voltage for each predetermined circuit module, the control for reducing the power consumption while improving the overall data processing efficiency can be realized more finely.
[0066]
(2) The second control means 3342 can prevent malfunction due to an undesired switching mode of the frequency and the operating voltage as in the first embodiment.
[0067]
(3) The first control means 3341 can prevent the circuit module from malfunctioning in terms of the switching procedure of the clock signal frequency and the operating voltage as in the first embodiment.
[0068]
FIG. 13 shows a fourth embodiment of the data processing apparatus according to the present invention. Circuit blocks having the same functions as those shown in FIG. 1 are given the same reference numerals, and detailed descriptions thereof are omitted. In the fourth embodiment shown in FIG. 13, the power supply circuit 310 and the clock generation circuit 320 are arranged outside the single-chip microcomputer 4 with respect to the embodiment shown in FIG. The selection signal 401 is received from the microcomputer 4, and the power supply of the voltage designated thereby is supplied to the plurality of power supply pins 402, and the clock signal of the frequency designated thereby is supplied to the plurality of clock input pins 403. Although not specifically shown, in the embodiment of FIG. 6, the mode register 307 is provided with a control information designation field for selecting the operation of the external power supply circuit and the external clock generation circuit, and a control signal corresponding to the set value is provided. It is possible to output to the outside of the chip so that the power supply voltage supplied to the power supply pin 311 and the frequency of the external clock signal supplied to the clock input pin 321 can be switched in the embodiment of FIG.
[0069]
FIG. 14 shows a fifth embodiment of the data processing apparatus according to the present invention. The figure shows a multi-chip microcomputer formed on a circuit board, which is a central processing unit 500, a display controller 501, a memory 502, a coprocessor 503, and an input / output circuit 504, each of which is formed as a semiconductor integrated circuit. Etc. are configured by sharing an external bus. In this system, the central processing unit 500, the display controller 501, the memory 502, and the coprocessor 503 can be individually switched between the clock signal and the operating power supply voltage. For this purpose, the clock generation circuit 320 and the power supply circuit 310 are provided, and the mode register 307 and the control unit 330 are built in the central processing unit 500. In this embodiment, a storage area for individually setting the operating frequency and operating voltage of the central processing unit 500, display controller 501, memory 502, and coprocessor 503 is allocated to the mode register.
[0070]
[2] Next, an embodiment of the invention relating to switching of the operating frequency for a data processing apparatus having a hierarchical internal bus will be described with reference to FIGS.
[0071]
FIG. 15 shows a microcomputer 6 according to another embodiment of the present invention. The microcomputer 6 shown in the figure is formed on a single semiconductor substrate such as single crystal silicon by, for example, a known semiconductor integrated circuit manufacturing technique. The microcomputer has a three-bus configuration including a CPU bus (first internal bus) 60, a cache bus (second internal bus) 70, and a peripheral bus (third internal bus) 80, although not particularly limited. . Each of the buses 60, 70, and 80 includes a signal line group for data, an address, and a control signal. A central processing unit (CPU) 61, a cache memory device 62, an address translation buffer (TLB) 63, a clock control circuit 65, and a break controller 64 are coupled to the CPU bus 60. On the other hand, the cache memory device 62 is coupled to the cache bus 70, and a peripheral bus interface 71, a bus controller 72, and an input / output circuit 73 are coupled to the cache bus 70. The input / output circuit 73 is coupled to an external bus (not shown), and the bus controller 72 performs interface control between the circuit module coupled to the external bus and the cache bus 70. The peripheral bus interface 71 performs interface control for peripheral circuit modules such as a timer 81, an interrupt controller 82, and a serial interface 83 connected to the peripheral bus 80. A bus master is not coupled to the peripheral bus 80.
[0072]
The microcomputer 6 of this embodiment divides the logical address space into units called logical pages, and supports virtual storage for performing address conversion to physical addresses in units of pages. The address conversion buffer 63 includes a memory unit and its control unit. The memory unit is an associative memory that stores a conversion pair associated with a logical page number and a physical page number as a TLB entry, and the control unit converts the logical address output from the central processing unit 61 into a physical address using the memory unit. Take control. In the case of a TLB miss, the TLB entry corresponding to the logical address is read from the external page table via the control unit.
[0073]
The central processing unit 61 uses a 32-bit address to support a logical address space of 4 gigabytes, for example. In the circuit block of the central processing unit 61, arithmetic units represented by general-purpose registers and arithmetic logic units, control registers such as program counters, instruction fetching and decoding, and instruction execution procedures are controlled and operated. Provide a control unit for controlling. The central processing unit 61 fetches an instruction from an external memory (not shown) via the input / output circuit 73, and performs data processing according to the instruction description.
[0074]
The cache memory device 62 includes, but is not limited to, an associative memory unit and a cache control unit. The memory part is indexed by using a part of the logical address, the physical part of the tag part of the entry is held, and the indexed tag part is compared with the physical address converted by the address translation buffer 63. A cache miss / hit is determined according to the comparison result. In the case of a cache miss, the data or instruction related to the cache miss is read from the external memory (not shown) by the cache control unit via the bus controller 72 and the input / output circuit 73, and the read data or instruction is cached as a new cache entry. The data is stored in the device 62 and supplied to the CPU bus 60. An interface between the CPU bus 60 and the cache bus 70 is performed by a cache control unit included in the cache memory device 62. A data input / output terminal and an address input terminal of the associative memory unit are coupled to the CPU bus 60.
[0075]
The clock pulse generator 9 outputs a CPU clock signal (first clock signal) 91, a bus clock signal (second clock signal) 92, and a peripheral clock signal (third clock signal) 93. The CPU clock signal 91 is an operation clock signal for circuit modules (CPU 61, cache memory device 62, TLB 63, break controller 64, clock control circuit 65) coupled to the CPU bus 60. The bus clock signal 92 is an operation clock signal for circuit modules (peripheral bus interface 71, bus controller 72, and input / output circuit 73) coupled to the cache bus 70. The peripheral clock signal 93 is an operation clock signal for the circuit modules (timer 81, interrupt controller 82, serial interface 83) coupled to the peripheral bus 80. The clock control circuit 65 can dynamically change the frequencies of the CPU clock signal 91 and the peripheral clock signal 93 based on control information set by the central processing unit 61 via the CPU bus 60.
[0076]
Here, the CPU clock signal 91 is a clock signal for a circuit module to be operated at high speed, such as the central processing unit 61, the cache memory device 62, and the address translation buffer 63. The peripheral clock signal 93 is a clock signal for a built-in peripheral circuit module that does not require high-speed operation. The signal frequencies of the clock signals 91 and 93 can be dynamically changed depending on the setting contents for the clock control circuit 65. Since the bus clock signal 92 is a clock signal that matches the operation speed of an external device such as a memory connected via the input / output circuit 73, the bus clock signal 92 is not a target for dynamically changing the signal frequency. When the internal state of the clock pulse generator 9 is changed to change the frequency of the clock signals 91 and 93, the clock pulse generator 9 is controlled by the clock control circuit 6 so as not to change the frequency of the bus clock signal 92. The
[0077]
FIG. 16 shows a detailed example block diagram of the clock pulse generator 9 and the clock control circuit 65. The clock pulse generator 9 can be coupled to a vibrator connection terminal XTAL and a vibrator connection or external clock signal input terminal EXTAL as a first connection terminal that can be coupled to an external clock source, to another external clock source. An external clock input or output terminal CKIO is provided as a second connection terminal.
[0078]
The crystal oscillator 910, the selector 911, the PLL circuit 912, the frequency divider 913, and the selector 914 constitute a first frequency changing unit coupled to the terminals XTAL and EXTAL, and the selector 920 and the PLL circuit 921 are coupled to the terminal CKIO. The second frequency changing means is configured. The crystal oscillator 910 is configured by, for example, an overtone type or a gate type circuit using the natural vibration of the crystal resonator connected to the terminals XTAL and EXTAL. The selector 911 selects one of the output of the crystal oscillator 910 or the clock signal directly supplied from the terminal EXTAL. The PLL circuit 912 is coupled to a PLL capacitor via a terminal CAP2, and performs synchronization and multiplication of the input clock signal. The multiplication factor is 1 or 4 times. The frequency divider 913 divides the input clock signal by 1/2. The selector 914 selects one of the output of the PLL circuit 912 and the output of the frequency divider 913 as the basic clock signal 915. The basic clock signal 915 output from the selector 914 can be output from the terminal CKIO to the outside via the clock buffer 950 when the operation is selected. 951 is a clock signal output path for this purpose. The selector 920 selects the basic clock signal 915 from the selector 914 or the clock signal input from the terminal CKIO. The PLL circuit 921 is coupled to a PLL capacitor via a terminal CAP1, and performs synchronization and multiplication of the input clock signal from the selector 920. The multiplication factor is set to 1, 2 or 4 times. The selectors 930 and 931 constitute selection means for selecting the basic clock signal 915 output from the selector 914 or the clock signal output from the PLL circuit 921. The frequency divider 940, the frequency divider 941, and the selectors 942, 943, 944 receive the clock signals selected by the selectors 930, 931, and set the frequencies of the CPU clock signal 91, the peripheral clock signal 93, and the bus clock signal 92. A third frequency changing unit that can be changed separately is configured. The frequency divider 940 divides the clock signal from the selector 930 by a division ratio of 1, 1/2, or 1/4, and one of them is selected by the selector 942 to be used as the CPU clock signal 91. The frequency divider 941 divides the clock signal from the selector 931 by a division ratio of 1, 1/2, 1/4, and one of them is selected by the selector 943 to be used as the peripheral clock signal 93. One of them is selected by the selector 944 to be a bus clock signal 92.
[0079]
The clock control circuit 65 controls the operation of the clock pulse generator 9. The control mode is roughly divided into a setting state from the outside for the mode terminals MD0, MD1, and MD2 and a setting state for the clock control register 650 by the central processing unit 61. In this embodiment, the external clock source is any one of three types: a crystal oscillator coupled to the terminals XTAL and EXTAL, an external clock signal from the terminal EXTAL, and an external clock signal from the terminal CKIO. The clock signal transmission path in the clock pulse generator must be different depending on which one is adopted, and if at least the selection states of the selectors 911 and 920 are not determined, the CPU clock signal 91 is not generated and the central processing unit 61 Since the operation cannot be performed, which one is adopted cannot be dealt with by setting control information in the clock control register 650 by the central processing unit 61. Also in this sense, the operation control of the clock pulse generator 9 by the mode terminals MD0 to MD2 is required. Furthermore, when the clock control circuit 65 generates the clock signals 91 to 93 by the basic clock signal 915 according to the state of the mode terminals MD0, MD1 and MD2 and the set value of the clock control register 650, the frequency of the bus clock signal 92 is increased. When the selection state of the selector 944 is controlled to match the frequency of the basic clock signal 915 and the clock signals 91 to 93 are generated by the clock signal supplied from the terminal CKIO, the frequency of the bus clock signal 92 is changed from the terminal CKIO. The selection state of the selector 944 is controlled to match the clock signal frequency. This is because the frequency of the bus clock signal 92 must be kept constant according to the permissible operating speed of the external device connected to the outside, so that the clock mode selection state by the mode terminals MD0 to MD2 and the clock control register 650 are changed. This is because the frequency of the bus clock signal 92 is automatically kept constant when the CPU clock signal 91 and the peripheral clock signal 93 are dynamically changed.
[0080]
FIG. 17 shows an example of the clock control register. The bit PLLEN is an enable bit of the PLL circuit 921, and PLLEN = 1 indicates enable, and PLLEN = 0 indicates disable. When the bit PLLEN = 1 is set, both the selectors 930 and 931 are controlled to select the output of the PLL circuit 921. Bits STC1 and STC0 are bits for instructing a frequency multiplication rate of the PLL circuit 921, for example, a multiplication factor of 1 (STC1 = 0, STC0 = 0), 2 times (STC1 = 0, STC0 = 1), 4 times (STC1 = 1, STC0 = 1). Bits CFC1 and CFC0 are bits for instructing the division ratio of the CPU clock signal 91, that is, selection by the selector 942, for example, division ratio 1 (CFC1 = 0, CFC0 = 0), division ratio 1/2 (CFC1 = 0) , CFC0 = 1) and a division ratio of 1/4 (CFC1 = 1, CFC0 = 1) can be selected. Bits PFC1 and PFC0 are bits for instructing the division ratio of the peripheral clock signal 93, that is, selection by the selector 943. For example, the division ratio is 1 (PFC1 = 0, PFC0 = 0), and the division ratio is 1/2 (PFC1 = 0). , PFC0 = 1) and a division ratio of 1/4 (PFC1 = 1, PFC0 = 1) can be selected. The bit MST1 is a control bit for selectively stopping the supply of the peripheral clock signal 93 to the timer 81. For example, supply is instructed when MST1 = 0, and supply stop is instructed when MST = 1. The bit MST0 is a control bit for selectively stopping the supply of the peripheral clock signal 93 to the serial interface 83. For example, supply is instructed when MST0 = 0, and supply stop is instructed when MST = 0. When the microcomputer is initialized by a power-on reset or a manual reset, all the bits of the clock control control register 650 are initialized to a logical value “0” by hardware (regardless of instruction execution by the central processing unit 61). It becomes. For the reasons described above, the frequency selection state of the bus clock signal 92 by the selector 944 is not arbitrarily performed via the clock control register 650.
[0081]
FIG. 18 shows seven clock modes set by mode terminals MD0 to MD2. No. shown in FIG. 0 and No. In the clock mode 1, a clock signal obtained by using the terminal EXTAL as a clock supply source and multiplying it by the PLL circuit 912 (clock mode No. 0 has a multiplication factor of 1 and clock mode No. 1 has a multiplication factor of 4). The selection state of the selectors 911 and 914 is controlled so as to be the basic clock signal 915. In these clock modes, the clock buffer 950 is enabled for output, the terminal CKIO is used for clock output, and the selector 920 is controlled to the selected state of the basic clock signal 915. As described above, the operation of the PLL circuit 921 is prohibited in the initial state of the clock control register 650. The selectors 930 and 931 are set to the selection state of the basic clock output from the selector 914. The clock control circuit 65 automatically controls the selector 944 so that the frequency of the bus clock signal 92 matches the frequency of the basic clock signal 915. When the microcomputer is reset, the state of the clock control register 65 is initialized to a constant value without going through the operation of the central processing unit 61. Therefore, if the clock mode by the mode terminals MD0 to MD2 is determined, the clock is reset. Signals 91 to 93 are supplied to each part of the microcomputer, and the central processing unit 61 can execute instructions. Thereafter, the central processing unit 61 rewrites the value of the clock control register 650 so that the frequencies of the CPU clock signal 91 and the peripheral clock signal 93 can be dynamically changed. For example, when the operation of the PLL circuit 921 is enabled (PLLEN = 1), the selectors 930 and 931 select the output of the PLL circuit 921, and the frequency dividing circuits 940 and 941 receive the clock signal multiplied by the PLL circuit 921. Supplied. At this time, if the multiplication rate of the PLL circuit 921 is 2, the selector 944 selects the frequency division ratio 1/2, and if the frequency multiplication factor is 4, the selector 944 selects the frequency division ratio 1/4 to select the frequency of the bus clock signal 92. To keep constant.
[0082]
No. shown in FIG. 2, no. In the clock mode 3, the clock supply source is a crystal oscillator 910, which is multiplied by a PLL circuit 912 (clock mode No. 2 has a multiplication factor of 4 times, clock mode No. 3 has a multiplication factor of 4 times and a multiplication factor of 1). The selection state of the selectors 911 and 914 is controlled so that the clock signal obtained in this way is the basic clock. The other control states are clock mode No. 0, No. This is the same as the case of 1.
[0083]
No. shown in FIG. 4, no. In the clock mode 5, the PLL circuit 912 is not operated and the selector 911, 914 selects the path passing through the frequency divider 913 to generate the basic clock. Clock mode No. 4 is an external clock signal supplied from the terminal EXTAL, the clock mode No. The clock source in 5 is a crystal oscillator 910. The other control states are clock mode No. 0, No. This is the same as the case of 1.
[0084]
No. shown in FIG. The clock mode No. 6 uses the clock signal supplied from the terminal CKIO as a clock source, selects the operation of the PLL circuit 921, and causes the selectors 930 and 931 to select the output of the PLL circuit 921. In this clock mode, the clock buffer 950 is disabled for output operation. In the operation clock mode, the operation selection of the PLL circuit 921 by the bit PLLEN of the clock control register 650 is invalidated. For example, the clock control circuit 65 has a clock mode no. When 6 is set, the bit PLLEN is forced to a logical value “1” (a circuit that forcibly pulls up the bit PLLEN is activated). Therefore, rewriting of the bit PLLEN by the central processing unit 61 is substantially disabled. In other clock modes, the operation of the PLL circuit 921 can be arbitrarily set by the bit PLLEN of the clock control register 650.
[0085]
As described above, the clock control circuit 65 determines the frequency change rate by the PLL circuit 912 and the frequency divider 913 included in the first frequency changing means according to the state of the mode terminals MD0 to MD2, and determines from the terminals XTAL and EXTAL. A first state in which the clock signal can be transmitted to the inputs of the frequency dividers 940 and 941 and the selector 944 is controlled so that the frequency of the bus clock signal 92 matches the frequency of the basic clock signal, or the PLL circuit from the terminal CKIO A second state is selected in which the clock signal is controlled to be transmitted to 921. Further, the frequency change rate by the PLL circuit 921 and the frequency selection of the CPU clock signal 91 and the peripheral clock signal 93 by the selectors 942 and 943 are variably controlled according to the control information set in the clock control register 650, and the clock terminals MD0 to MD0. In the second state designated by MD2, the division ratio of the bus clock signal 92 selected by the selector 944 by the frequency divider 941 and the multiplication factor of the PLL circuit 921 designated by the clock control register 650 are as follows. The selector 944 is selectively controlled so that the product of 1 becomes 1 (in other words, the frequency of the bus clock signal 92 matches the frequency of the input clock signal from the terminal CKIO).
[0086]
19 and 20 are timing charts showing examples of clock signal cycles and bus cycles. In FIG. 19, the frequency ratio of the clock signals is CPU clock signal 91: peripheral clock signal 93: bus clock signal 92 = 1: 1/2: 1/4, and the CPU bus 60, cache bus 70 and external bus accordingly. The bus cycle of the peripheral bus 80 has been determined. This example is an example in which the central processing unit 61 is operated at a high speed in order to prioritize the data processing speed of the central processing unit 61. The example of FIG. 20 shows a state in which the frequency of the CPU clock signal 91 is changed to ½ while the frequencies of the bus clock signal 92 and the peripheral clock signal 93 are kept constant with respect to FIG. This is a setting example when priority is given to low power consumption over the performance of the above, and the power consumption of the central processing unit 61 is reduced by half while keeping the peripheral module and external bus access speed constant. In FIG. 19 and FIG. 20, the bus cycle of the external bus is the same as the bus cycle of the cache bus 70. This is because the bus controller 72 is operated in synchronization with the bus clock signal 92, and the external bus cycle activated by the bus controller 72 is also synchronized with the bus clock signal 92.
[0087]
In FIG. 16, the clock control circuit 65 generates a clock driver control signal 651, a clock supply stop control signal 652 for the timer 81, and a clock supply stop control signal 653 for the serial interface 83. When the internal state of the clock pulse generator 9 such as the division ratio and multiplication rate is changed by rewriting the clock control register 650, the clock driver control signal 651 is changed until the clock signals 91 to 93 are stabilized. 93 is a control signal for prohibiting the operation of the circuit module by 93. Each circuit module includes a clock driver 1000 and a logic circuit 1100 as exemplarily shown in FIG. FIG. 21B shows an example of the clock driver 1000. According to this example, the clock driver 1000 receives the CPU clock signal 91, the peripheral clock signal 93, or the bus clock signal 92 from the clock pulse generator according to the type of the circuit module including the module, and receives this from the non-overlapping two-phase module. The internal clock signals CK1 and CK2 are supplied to the logic circuit 1100. A two-input NAND gate 1001 and a delay circuit (series eight-stage inverter circuit) 1002 determine a non-overlap period of rising and falling in one clock signal CK1, and a two-input NAND gate 1003 and a delay circuit (series seven-stage inverter circuit) ) 1004 and 2-input NOR gate 1005 determine the non-overlap period of the rising and falling edges of the other clock signal CK2. The clock signal 91, 92 or 93 from the clock pulse generator 9 is supplied to one input terminal of a two-input NOR gate 1006, and the other input terminal of the NOR gate 1006 has a clock driver control signal together with the other input terminal of the NOR gate 1005. When 651 is supplied and the clock driver control signal 651 is set to the logical value “1”, the outputs of both NOR gates 1005 and 1006 are fixed to the logical value “0”, whereby the clock signal CK2 is set to the logical value “0”. The clock signal CK1 is fixed to the logical value “1”. Thereby, the operation of the circuit synchronized with the internal lock signals CK1 and CK2 in the logic circuit 1100 is stopped, and the internal state can be maintained. For example, when detecting the end of the write cycle for the clock control register 650, the clock control circuit 65 changes the clock driver control signal 651 from the logical value “0” to the logical value “1” for a certain period. This period is a period from when the internal state of the clock pulse generator 9 is changed to when the clock signals 91, 92, 93 are stabilized, and is determined by the circuit characteristics. The management of the period can be performed by a timer (not shown) whose operation is not stopped by, for example, the clock driver control signal 651 or the clock supply stop control signal 652 to the timer.
[0088]
The logical value of the clock supply stop control signal 652 to the timer is determined by the bit MST1 of the clock control register 650, and the clock supply stop control signal 653 to the serial interface is also determined by the logical value of the bit MST0. Although not shown in the figure, in the clock driver in the timer and serial interface, the NOR gate shown in FIG. 21B has three inputs, and the clock supply stop control signal 652 or 653 is supplied corresponding to one of the inputs. The internal clock signals CK1 and CK2 in the circuit module can be arbitrarily stopped.
[0089]
FIG. 22 shows how the microcomputer 6 of this embodiment is connected to an external memory. In the figure, the external interface signals of the microcomputer 6 are: address signal A26-A0, data D31-D0, chip select signal CS0 # (symbol # means that the signal to which it is attached is a low enable signal) to CS4 #, read signal RD #, data enable signal DQMLL / WE0 #, DQMLU / WE1 #, DQMUL / WE2 #, DQMUU / WE3 #, read / write signal R / W #, row address strobe signal RAS # / CS #, Column address strobe signals CAS # / CE # / CASHH #, column address strobe signals CASHL #, CASLH, CASLL #, and the like. The bus controller 72 controls the change timing of various access control signals such as the address signal A26-A0, the data D31-D0 at the time of writing, and the chip select signal CS0 #, and these change in synchronization with the bus clock signal 92. Is done.
[0090]
The row address strobe signal RAS # / CS # is used as a row address strobe signal for DRAM (Dynamic Random Access Memory) and SDRAM (Synchronous DRAM) and is used as PSRAM (Pseudo Static Random Random). When used for (access memory), it is a chip enable signal for them. The column address strobe signal CAS # / CE # / CASHH # is used as a column address strobe signal for the SDRAM when used in the SDRAM, and as a column address strobe signal for selecting the most significant byte when used for the DRAM. When used in PSRAM, it is the output enable signal for it. The column address strobe signal CASHL # is the second column address address strobe signal when used in DRAM, and the column address strobe signal CASLH is the third byte column address strobe signal when used in DRAM. The column address strobe signal CASLL # is used as a column address strobe signal for the fourth byte when used in a DRAM. Data enable signal DQMLL / WE0 # instructs to select the least significant byte when used in SDRAM and to write the least significant byte when used in other memories. Data enable signal DQMLU / WE1 # instructs the selection of the third byte when used in SDRAM and the writing of the third byte when used in other memories. The data enable signal DQMUL / WE2 # instructs the second byte selection for the SDRAM when used for the SDRAM, and the second byte write when used for other memories. Data enable signal DQMUU / WE3 # instructs the most significant byte selection for it when used in SDRAM and the most significant byte write when used for other memories. Although not shown, a bus start signal, a bus right request signal, a bus use permission signal, and the like are output, and a bus release request signal, a wait signal, and the like are input. The external terminal group shown in FIG. 16 is not shown.
[0091]
In FIG. 22, each signal is connected to other memories such as DRAMs 1300 to 1303 and SRAMs 1304 to 1306 via an external bus 1200. The DRAMs 1300 to 1303 shown in FIG. 22 are assumed to perform data input / output in units of 8 bits (bytes) (× 8 DRAM). In DRAMs 1300 to 1303 and SRAMs 1304 to 1306, terminal A is an address input terminal, D is a data input / output terminal, RAS # is a row address strobe signal input terminal, CAS # is a column address strobe signal input terminal, and WE # is a write enable signal input terminal. CS # is a terminal for a chip select signal, and OE # is an input terminal for an output enable signal.
[0092]
FIG. 23 shows a connection mode in the case where DRAMs 1307 and 1308 having a parallel data input / output bit number of 16 bits are employed. In this example, terminals UCAS # of the DRAMs 1307 and 1308 are upper column address strobe signal input terminals, LCAS # is a lower column address strobe signal input terminal, and the others are the same as in FIG.
[0093]
FIG. 24 shows a connection mode in the case of adopting SDRAMs 1310 to 1313 in which the number of parallel input / output bits of data is 8 bits. Since SDRAMs 1310 to 1313 can input / output data, addresses, and control signals in synchronization with a clock as compared with DRAMs, a large-capacity memory similar to DRAMs can be realized at a high speed operation comparable to that of SRAMs. It is a memory that can realize high-speed access and large capacity at a low price. The microcomputer 6 outputs a clock enable signal CKE for interfacing with the SDRAM and outputs a clock signal CLK from the terminal CKIO. In the SDRAM, CLK is an input terminal for a clock signal CLK, CKE is a clock enable signal CKE input terminal, CS # is a chip select signal input terminal, CAS # is a column address strobe signal input terminal, RAS # is a row address strobe signal input terminal, WE # Is a write enable signal input terminal, A is an address signal input terminal, and D is a data input / output terminal. The SDRAM operation mode (row address signal fetching, column address signal fetching and writing, column address signal fetching and reading, etc.) is executed by a command in a mode register (not shown) by a memory control signal from the outside and a predetermined lower bit of the address signal. Determined by being written. The clock signal CLK is used as a master clock of the SDRAM, and other external input signals are significant in synchronization with the rising edge of the clock signal CLK, for example. The chip select signal applied to the terminal SC # instructs the start of the command input cycle by its low level. The clock enable signal CKE is a signal for instructing the validity of the next clock signal. If the signal CKE is at a high level, the rising edge of the next clock signal CLK is valid, and is invalid when the signal is at a low level. .
[0094]
FIG. 25 shows a connection mode in the case of adopting SRAMs 1314 and 1315 in which the number of parallel input / output bits of data is 16 bits (× 16). In this example, terminals DQMU of SDRAMs 1314 and 1315 are upper data enable signal input terminals, DQML is a lower data enable signal input terminal, and the others are the same as in FIG.
[0095]
26 to 30 show an example of the bus access timing of the DRAM shown in FIG. 22 or FIG. 23 by changing the frequency of the bus clock signal 92. The bus controller generates various memory access control signals such as a row address strobe signal in synchronization with the bus clock signal 92 and inputs / outputs data. In each figure, D31 to D0 are data, address lower bits are supplied to the DRAM and actually used, and address upper bits are address bits not supplied to the DRAM. BS # is a bus start signal indicating the start of a bus cycle, and is output from the bus controller 72 of the microcomputer 6. 26 to 30, Tr, Tr1, Tr2, and Tr3 are row operation states, Tc1, Tc2, and Tc3 are column operation states, and Tp is a precharge operation state. In FIG. 26, the frequency φ of the bus clock signal 92 is assumed to be smaller than 18.6 MHz, and the memory cycle of the DRAM in that case is, for example, three cycles of Tr, Tc1, Tc2, and in FIG. 27 (18.8 MHz ≦ φ ≦ The memory cycle of the DRAM is 5 cycles of Tr1, Tr2, Tc1, Tc2, and Tp. In FIG. 28 (28.5 MHz <φ ≦ 37.7 MHz), the memory cycle of the DRAM is Tr1, Tr2, Tc1, Tc2. , Tc3, Tp, and in FIG. 29 (37.7 MHz <φ <47 MHz), the memory cycle of the DRAM is Tr1, Tr2, Tc1, Tc2, Tc3, Tp, Tp, and in FIG. (47.7 MHz ≦ φ ≦ 56 MHz) The DRAM memory cycle is Tr1, There are eight cycles of Tr2, Tr3, Tc1, Tc2, Tc3, Tp, and Tp. In this way, one memory access period (the number of cycles of the bus clock signal 92) is changed depending on the frequency of the bus clock signal 92 in consideration of the speed at which an external device such as a DRAM can operate and the cycle of the bus clock signal 92. This is because one memory access period corresponding to the operable speed of an external device such as a DRAM is determined by the number of cycles of the bus clock signal 92. The number of cycles is of a nature that varies depending on how fast the external device is employed by the user of the microcomputer 6. For example, when a DRAM is operated at the maximum allowable speed with a cycle as shown in FIG. 26, the same DRAM is operated at the maximum allowable speed in another system in which the frequency of the bus clock signal 9 is higher than that. The number must be increased as shown in FIGS. In this embodiment, the basic number of bus clock signal cycles for external bus access by the bus controller 72 can be arbitrarily set. The number of cycles is not particularly limited, but is set in a register inside the bus controller by an external terminal.
[0096]
FIG. 31 and FIG. 32 show an example of read / write bus access timings for the SDRAM shown in FIG. In each figure, D31 to D0 are data, and lower address bits are a row address and a column address for selecting an SDRAM memory cell. The address A12, A11, A10, or A9 is a signal for instructing an operation mode such as a row address fetched into the SDRAM, a column address fetched, a read operation, and a column address fetched. The upper address bit means an address bit that is not supplied to the SDRAM. BS # is a bus start signal indicating the start of a bus cycle, and is output from the bus controller 72 of the microcomputer 6. The bus controller 72 performs bus control in synchronization with the bus clock signal 92 as shown in FIG. 31 and FIG. 32 when accessing the address assigned to the SDRAM. The SDRAM receives the clock signal CLK output from the terminal CKIO of the microcomputer 6 and operates in synchronization therewith. 31 to 32, Tr is a row operation state, Trw is a wait state for extending Tr, Tc1 is a column operation state, Tcw is a wait state for extending Tc1, and Td1 is a data reading state. In the read operation and the write operation, the number of states (the number of bus clock signal cycles) constituting the memory cycle is different. In the state Tr of FIG. 31, a row address is fetched, and in Tc1, a column address is fetched by a read command. Three cycles from the falling edge of the column address strobe signal CAS # (the bus clock signal, that is, the external clock signal CLK output from the terminal CKIO) The data is read after the number of cycles. In the state Tr of FIG. 32, a row address is fetched, and in Tc1, a column address is fetched by a write command, and data is written.
[0097]
According to the above-described embodiment relating to the operation frequency switching for the microcomputer 6 in which the internal bus is hierarchized, the following operational effects are obtained. (1) In the microcomputer 6 hierarchized into the CPU bus 60, the cache bus 70, and the peripheral bus 80, the bus clock signal 92 is excluded from the dynamically variable frequency clock signal. That is, the CPU clock signal 91 and the peripheral clock signal 93 can be dynamically changed in signal frequency depending on the setting contents for the clock control circuit 65, while the bus clock signal 92 is a memory connected via the input / output circuit 73. Since the clock signal should match the operation speed of the external device, the signal frequency is not dynamically changed. Even when the internal state of the clock pulse generator 9 is changed to change the frequency of the clock signals 91 and 93, the clock control circuit 6 controls the clock pulse generator 9 so as not to change the frequency of the bus clock signal 92.
[0098]
(2) By enabling the CPU clock signal 91 frequency to be dynamically variably controlled by the control information, the circuit module of the CPU bus 60 to which the central processing unit 61 is coupled is operated at a high speed as required to achieve high speed data efficiency. Conversely, when executing a task that does not require high-speed operation, the clock signal frequency can be lowered to achieve low power consumption.
[0099]
(3) By enabling the frequency of the peripheral clock signal 93 to be dynamically variably controlled by the control information, in view of the property that the circuit module coupled to the peripheral bus 80 is a peripheral circuit module, its function and operation state Accordingly, the operation speed can be controlled independently of other circuit modules to promote low power consumption.
[0100]
(4) When the clock control circuit 65 generates the clock signals 91 to 93 by the basic clock signal 915 according to the state of the mode terminals MD0, MD1 and MD2 and the set value of the clock control register 650, the frequency of the bus clock signal 92 When the selection state of the selector 944 is controlled so as to match the frequency of the basic clock signal 915 and the clock signals 91 to 93 are generated by the clock signal supplied from the terminal CKIO, the frequency of the bus clock signal 92 is set to the terminal CKIO. The selection state of the selector 944 is controlled so as to match the clock signal frequency from. As a result, the frequency of the bus clock signal 92 must be kept constant in accordance with the allowable operating speed of the external device connected to the outside. Therefore, the clock mode selection state by the mode terminals MD0 to MD2 and the clock control register 650 are changed. When the CPU clock signal 91 and the peripheral clock signal 93 are dynamically changed, the frequency of the bus clock signal 92 can be automatically kept constant.
[0101]
(5) Since the external clock signal output from the terminal CKIO matches the frequency of the bus clock signal 92, an external device such as an SDRAM operated in synchronization with the clock signal operates as a bus controller (receives the bus clock signal 92). Under the control of 72, the clock signal output from the external terminal CKIO can be used as the clock signal for the synchronous operation of such an external device. As a result, the microcomputer 6 of this embodiment can facilitate access control to a clock synchronous external device such as an SDRAM. In other words, access control can be performed by directly connecting such an external device via the external bus.
[0102]
Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.
[0103]
The present invention relates to an invention that variably controls both an operating frequency and a power supply voltage. For example, setting of control information for a storage means such as a mode register is not limited to being performed by a CPU, an external circuit is performed via a data bus, or Alternatively, an external circuit may be performed via a predetermined external terminal. The power source of the circuit may be a negative power source, and the present invention is applied in consideration of the magnitude or increase / decrease of the operating voltage in that case. The circuit module can be changed as appropriate, limited to those described in the above embodiments. Further, in the above embodiment, the change of the operating voltage may be applied to all the circuits in the circuit module to be changed, but it causes inconvenience in relation to other circuit modules or information transfer through the common bus. If there is a concern, the operating voltage of the interface circuit portion can be excluded from the change target. In particular, when the data processing apparatus is configured by multichip, the operating voltage of the interface portion of each circuit module commonly connected to the external bus can be made constant according to the information transmission specification of the bus. In addition, when the operating frequencies of the circuit modules are different from each other, information transfer can be performed by handshake control using a wait signal, a ready signal, a busy signal, or the like. In addition, if a frequency can be switched by maintaining a certain relationship, for example, 1/2 times, to a frequency that can be set for a specific circuit module, information transfer can be performed without the need for handshake control. It can be carried out. In addition, since the frequency and operating voltage can be switched for each task, if the switching is performed in consideration of the resources used in the task, the circuit modules can be operated synchronously without any special restrictions. be able to.
[0104]
With respect to the invention for controlling the operating frequency of the built-in circuit module in units of hierarchical internal buses, only the CPU clock signal may be the target for dynamically changing the operating frequency. Alternatively, only the peripheral clock signal may be used. In terms of finely controlling power consumption without sacrificing data processing performance, it is desirable that both the CPU clock signal and the peripheral clock signal be subjected to variable frequency control as described above.
[0105]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
[0106]
[1] Regarding the invention for controlling both the operating frequency and the operating voltage of the circuit module, the control information for instructing the switching mode of the clock signal frequency and the operating voltage can be rewritten by a central processing unit or the like in a register or other storage means. Therefore, by freely rewriting the control information as necessary according to the data processing performance of the circuit module and the weight of the data processing, it is possible to allow free switching with respect to the operating voltage and operating frequency of the circuit module. Therefore, prioritize low power consumption for tasks or circuit modules that do not require relatively high-speed data processing, and increase power consumption for tasks or circuit modules that require relatively high-speed processing. In this way, low power consumption can be realized while improving the overall data processing efficiency. Furthermore, enabling the clock frequency and the operating voltage to be switched individually for each predetermined circuit module can realize finer control for reducing power consumption while improving the overall data processing efficiency.
[0107]
By adopting the first control means, it is possible to prevent malfunction in terms of the switching procedure of the clock signal frequency and the operating voltage.
[0108]
By adopting the second control means, it is possible to prevent the possibility of malfunction due to an undesired switching mode between the frequency and the power supply voltage.
[0109]
[2] The invention relates to an invention for switching the operating frequency of the built-in circuit module in units of hierarchized internal buses, excluding the second clock signal such as the bus clock signal from the frequency variable signal, that is, the first and first When the frequency of the clock signal 3 is dynamically changed according to the control information, the clock control circuit controls the frequency of the second clock signal to be kept constant, thereby controlling the second internal circuit to which the bus controller is coupled. Unless the frequency of the second clock signal for the bus is set to a frequency corresponding to the operating speed of the external device coupled to the external bus, the internal and external bus cycles or bus operations cannot be synchronized. Can be satisfied.
[0110]
By enabling the first clock signal frequency to be dynamically variably controlled by the control information, the circuit module of the first internal bus to which the central processing unit is coupled is operated at a high speed as necessary to increase the data processing efficiency. On the contrary, when executing a task that does not require high-speed operation, it is possible to reduce the clock signal frequency to reduce power consumption.
[0111]
By allowing the third clock signal frequency to be dynamically variably controlled by the control information, in view of the property that the circuit module coupled to the third internal bus is a peripheral circuit module, its function and operation state are changed. Accordingly, the operation speed can be controlled independently of the other circuit modules to promote the reduction in power consumption.
[0112]
When the clock control circuit generates the first to third clock signals by the basic clock signal from the first frequency changing means according to the state of the mode terminal and the set value of the clock control register, the second clock signal When the third frequency changing means is controlled so that the frequency matches the frequency of the basic clock signal, and the first to third clock signals are generated by the clock signal supplied from the second connection terminal (CKIO). Controls the third frequency changing means so that the frequency of the second clock signal matches the frequency of the clock signal from the terminal (CKIO). As a result, the frequency of the second clock signal must be kept constant in accordance with the allowable operating speed of the external device connected to the outside. Therefore, the selection of the clock mode by the mode terminal and the first via the clock control register. In addition, when the frequency of the third clock signal is dynamically changed, the frequency of the second clock signal can be automatically kept constant.
[0113]
Since the external clock signal output from the terminal (CKIO) matches the frequency of the second clock signal, the external device operated in synchronization with the clock signal controls the bus controller (operating in response to the second clock signal). The clock signal output from the terminal (CKIO) can be used as a clock signal for the synchronous operation of such an external device.
[Brief description of the drawings]
FIG. 1 is a block diagram of a single chip microcomputer according to a first embodiment of the present invention;
FIG. 2 is a block diagram illustrating an example of a clock generation circuit of FIG.
3 is a format explanatory diagram of an example of a voltage setting register and a frequency setting register shown in FIG. 1. FIG.
FIG. 4 is a flowchart showing an example of an internal clock signal frequency and internal voltage switching control sequence.
FIG. 5 is a block diagram of a data processing apparatus according to a second embodiment of the present invention.
FIG. 6 is a block diagram of a single chip microcomputer according to a third embodiment of the present invention.
7 is a detailed example circuit diagram of the voltage / frequency control unit of FIG. 6;
FIG. 8 is a circuit diagram of an example of a DC / DC converter.
9 is a detailed example format explanatory diagram of the mode register of FIG. 6;
FIG. 10 is an explanatory diagram of an example of a control mode by the first and second control means.
11 is a flowchart illustrating an example of an operation voltage and frequency switching control procedure by the sequence control unit of FIG. 7;
12 is another flowchart of the operation voltage and frequency switching control procedure by the sequence control unit of FIG. 7;
FIG. 13 is a block diagram of a data processing apparatus according to a fourth embodiment of the present invention.
FIG. 14 is a block diagram of a data processing apparatus according to a fifth embodiment of the present invention.
FIG. 15 is a block diagram of a microcomputer according to a sixth embodiment of the present invention.
FIG. 16 is a block diagram illustrating a detailed example of a clock pulse generator and a clock control circuit.
FIG. 17 is a format diagram of an example of a clock control register.
FIG. 18 is an explanatory diagram of a clock mode set by a mode terminal.
FIG. 19 is a timing chart illustrating an example of a cycle of a CPU clock signal, a bus clock signal, and a peripheral clock signal, and a bus cycle.
FIG. 20 is a timing chart when the frequency of the CPU clock signal is changed to ½ while keeping the frequencies of the bus clock signal and the peripheral clock signal constant with respect to FIG. 19;
FIG. 21 is an explanatory diagram showing the positioning of the clock driver with respect to the circuit module in (A) and an example logic of the clock driver in (B).
FIG. 22 is a connection diagram when a DRAM (× 8) or the like is connected to the outside of the microcomputer of this embodiment.
FIG. 23 is a connection diagram when a DRAM (× 16) or the like is connected to the outside of the microcomputer of this embodiment.
FIG. 24 is a connection diagram when an SDRAM (× 8) or the like is connected to the outside of the microcomputer of this embodiment.
FIG. 25 is a connection diagram when an SDRAM (× 16) or the like is connected to the outside of the microcomputer of this embodiment.
FIG. 26 is an access timing chart to the external DRAM by the microcomputer of this embodiment when the bus clock signal frequency φ is φ <18.6 MHz.
FIG. 27 is an access timing chart to the external DRAM by the microcomputer of this embodiment when the bus clock signal frequency φ is 18.8 MHz ≦ φ ≦ 28.5 MHz.
FIG. 28 is an access timing chart to the external DRAM by the microcomputer of this embodiment when the bus clock signal frequency φ is 28.5 MHz <φ ≦ 37.7 MHz.
FIG. 29 is an access timing chart to the external DRAM by the microcomputer of this embodiment when the bus clock signal frequency φ is 37.7 MHz <φ <47 MHz.
FIG. 30 is an access timing chart for the external DRAM by the microcomputer of this embodiment when the bus clock signal frequency φ is 47.7 MHz ≦ φ ≦ 56 MHz.
FIG. 31 is a timing chart of read access to the SDRAM by the microcomputer according to this embodiment.
FIG. 32 is a timing chart of write access to the SDRAM by the microcomputer of this embodiment.
[Explanation of symbols]
1 Single-chip microcomputer
100 Central processing unit
110 Power supply circuit
113 Internal voltage
114 Voltage setting register
120 clock generation circuit
122 Internal clock signal
1206 Output gate
124 Frequency setting register
130 Control circuit
131 1st control means
132 Second control means
3 Single-chip microcomputer
300 Central processing unit
304 timer
306 Voltage / frequency controller
307 Mode register
3071 Voltage setting field
3072 Frequency setting field
310 Power supply circuit
3141-3143 selector
320 Clock generation circuit
3251-3253 selector
3261-3263 Output gate
330 Control circuit
334 Sequence control unit
3341 First control means
3342 Second control means
340 Internal clock signal
342 Internal voltage
6 Microcomputer
60 CPU bus
61 Central processing unit
62 Cache memory device
65 Clock control circuit
650 clock control register
MD0, MD1, MD2 Clock mode pins
70 cash bus
72 Bus controller
80 Peripheral bus
9 Clock pulse generator
91 CPU clock signal
92 Bus clock signal
93 Peripheral clock signal
910 crystal oscillator
912, 921 PLL circuit
911, 940, 941 frequency divider
911,914 selector
920 selector
930, 931, 942, 943, 944 selector
CKIO, XTAL, EXTAL External clock terminal

Claims (10)

A circuit module that operates in synchronization with a clock signal;
Storage means in which control information for designating the frequency of the clock signal to be supplied to the circuit module and the operating voltage to be supplied to the circuit module is rewritable;
A clock generation circuit capable of outputting a clock signal having a frequency according to the control information of the storage means to the circuit module;
A power supply circuit capable of outputting an operating voltage of a level corresponding to the control information of the storage means to the circuit module;
Based on the control information, when an instruction to reduce the clock signal frequency and reduce the operating voltage in absolute value is detected, the operating voltage is reduced in absolute value before changing the current frequency. A state in which a clock signal with an increased frequency is output prior to an increase in the absolute value of the operating voltage when an instruction to block the clock signal frequency and increase the operating voltage in absolute value is detected First control means for controlling the switching of the output state of the clock generation circuit and the power supply circuit,
When an instruction to increase the clock signal frequency and decrease the operating voltage in absolute value is detected based on the control information before and after rewriting the storage means, the output state change of the clock generation circuit and the power supply circuit based on the instruction is changed. And a second control means for prohibiting the data processing apparatus.   The clock generation circuit includes an output gate that stops the output of the clock signal for a predetermined period based on an instruction from the first control means when switching the frequency of the clock signal to be output. The data processing apparatus according to claim 1. The second control means does not further increase the clock signal frequency without increasing the operating voltage in absolute value or reduce the clock signal frequency based on the control information before and after rewriting the storage means. 3. The output state change of the clock generation circuit and the power supply circuit based on the instruction can be prohibited by detecting an instruction to decrease the operating voltage in terms of absolute value. Data processing equipment. The circuit module has a plurality, and the storage means has a plurality of storage areas for storing rewritable control information for each predetermined circuit module,
The clock generation circuit includes a selection circuit for selecting a clock signal to be individually supplied to the corresponding circuit module according to control information of each of the plurality of storage areas in the storage unit,
The power supply circuit includes a selection circuit for selecting an operating voltage to be individually supplied to a corresponding circuit module in accordance with control information of each of a plurality of storage areas in the storage unit. The data processing apparatus according to any one of claims 1 to 3. The circuit module includes one circuit module as a central processing unit and another circuit module whose operation is controlled by the central processing unit, and is formed into a single chip microcomputer formed entirely on one semiconductor substrate The data processing apparatus according to claim 1, wherein the data processing apparatus is configured as described above.   The circuit module, the storage means, the first control means, and the second control means are a one-chip semiconductor integrated circuit, and the clock generation circuit and the power supply circuit are provided outside the semiconductor integrated circuit. 5. The data processing apparatus according to claim 3, wherein the data processing apparatus is provided. A central processing unit that operates in synchronization with a clock signal;
A plurality of circuit modules operated in synchronization with a clock signal;
A clock generation circuit capable of outputting the clock signal to the central processing unit and the circuit module;
A power supply circuit capable of outputting an operating voltage to the central processing unit and the circuit module,
The central processing unit, the circuit module, the clock generation circuit, and the power supply circuit are each a semiconductor. A data processing device integrated into a body,
The central processing unit includes a storage unit in which control information for designating the frequency of the clock signal and the operating voltage is rewritable,
Based on the control information, when an instruction to reduce the clock signal frequency and reduce the operating voltage in absolute value is detected, the operating voltage is reduced in absolute value before changing the current frequency. A state in which a clock signal with an increased frequency is output prior to an increase in the absolute value of the operating voltage when an instruction to block the clock signal frequency and increase the operating voltage in absolute value is detected First control means for controlling the switching of the output state of the clock generation circuit and the power supply circuit,
Based on the control information before and after the rewriting of the storage means, by detecting an instruction to decrease the operating voltage in absolute value and increase the frequency of the clock signal, the output of the clock generation circuit and the power supply circuit based on the instruction And a second control means for prohibiting the state change. 8. A data processing apparatus according to claim 7, wherein said storage means is a register accessed by said central processing unit. A central processing unit that operates in synchronization with a clock signal;
A circuit module that operates in synchronization with the clock signal;
A control unit for transmitting control information for designating the frequency of the clock signal supplied to the circuit module and the operating voltage to be supplied to the circuit module from the central processing unit;
A clock generation circuit capable of outputting a clock signal having a frequency according to the control information to the circuit module;
A power circuit capable of outputting an operating voltage of a level according to the control information to the circuit module;
The control unit compares the frequency and operating voltage of the clock signal before the control information is transmitted from the central processing unit with the control information, and the control information increases the frequency of the clock signal and sets the operating voltage. A data processing device characterized in that, in the case of an instruction to reduce the absolute value, it is possible to prohibit the change of the output state of the clock generation circuit and the power supply circuit based on the control information . Further, when the control unit detects control information for reducing the clock signal frequency and reducing the operating voltage in absolute value, the control unit sets a state in which the operating voltage is reduced in absolute value prior to changing the current frequency. When the control information is detected that increases the clock signal frequency and increases the operating voltage in absolute value, the clock signal with the increased frequency is output prior to the absolute increase in operating voltage. 10. The data processing apparatus according to claim 9, wherein the data processing apparatus controls the switching of the output states of the clock generation circuit and the power supply circuit by blocking the state .

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