JP2702743B2 - Electronics - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an electronic device, in particular, a CPU, a ROM, a RAM, and peripheral devices. The present invention relates to an electronic device that performs data input / output.

[Prior Art] Conventionally, in an electronic device in which all circuit elements are configured by a C-MOS LSI, for example, an electronic desk calculator (hereinafter referred to as a calculator) driven by a dry battery or a solar battery, the power consumption operates. A technique has been proposed in which arithmetic processing requiring high-speed processing uses a high-frequency clock because it is proportional to the clock, and uses a low-frequency clock to reduce power consumption when waiting for key input, which may be slow. .

[Problems to be Solved by the Invention] However, the above-described conventional configuration has the following disadvantages.

(1) The ROM built into the calculator LSI has a low capacity and a low speed, cannot support a high frequency clock of a certain level or more, and cannot expect much higher processing speed.

(2) There is no device equivalent to the ROM built into the calculator LSI in the general-purpose ROM of the semiconductor manufacturer. Therefore, when configuring a calculator, the ROM is custom designed, which not only increases the development period but also increases the ROM bit unit.

(3) ROMs from recent semiconductor manufacturers are large-capacity and high-speed access-oriented.
-Even if the MOS ROM is used and the cycle time is delayed,
If the cycle time is 1 μsec or less, power consumption cannot be reduced.

The object of the present invention is to solve the above problems, and to achieve both high-speed processing and low power consumption, and to achieve a low-cost system even when using a ROM in which power consumption does not decrease even when a low-frequency clock is used. Configuration.

[Means for Solving the Problems] In order to solve the above problems, in the present invention, the CP
U, ROM, RAM and peripheral devices
In an electronic device that performs data input / output between the above-described components according to a program stored in a RAM, a unit that switches a frequency of a basic operation clock of the device to a plurality of stages, and is fixedly stored in a ROM at the start of device operation. A routine which is used relatively routinely and which does not require high-speed processing among the programs executed is transferred to the RAM, and then the basic operation clock is switched to a low frequency by the switching means at the time of operation of the routine. Occasionally, a configuration was provided in which control means for inhibiting access to the ROM was provided.

[Operation] According to the above configuration, power consumption is reduced by running the predetermined routine on the RAM and lowering the frequency of the basic operation clock at that time.
ROM with high power consumption by prohibiting M access
However, power consumption can be reduced even when using.

EXAMPLES Hereinafter, the present invention will be described in detail based on examples shown in the drawings.

1 to 4 show a first embodiment of the present invention.

FIG. 1 shows a circuit configuration of an electronic device according to the present invention. Here, a device such as a calculator or a personal computer constituted by a CPU and its peripheral elements is shown.

In FIG. 1, reference numeral 1 denotes a clock generator having two crystal oscillators X1 and X2 so that two kinds of frequencies can be set. Among these, the one indicated by the symbol X1 is a relatively high frequency oscillator, and the symbol X2 is a relatively low frequency oscillator.

The clock generator 1 oscillates the oscillator X2 and supplies its clock when the processing may be relatively slow such as waiting for a key input, and performs relatively high-speed processing such as key processing and display processing. Is required, the oscillator X1 is oscillated to supply its clock.

Reference numeral 2 denotes a C-MOS CPU (here, Z-Log Z-80)
(A product name)), and a reset key K1 and a power-on key K2 are connected to the CPU2. The reset key K1 is used for all initial settings of the electronic apparatus of the present invention, and the power-on key K2 is used for canceling standby (function holding state with minimum power supply).

ROM 3 and RAM 4 are connected to the CPU 2 as storage devices. The ROM 3 stores programs to be executed by the CPU 2 and various data. The RAM 4 is a C-MOS internal synchronous static RAM.

Reference numeral 5 denotes an inverter, which in this embodiment functions as an address decoder of a memory, and controls a chip select signal of the RAM 4. That is, the inverter 5 is connected to the CPU 2
The most significant bit A15 of the address bus (16 bits) is inverted and input to RAM4.
Or select one of RAM4. In this embodiment, the ROM 3
Is set to the low-order address, and ROM3 is selected by the logic "1" of the most significant bit A15 of the address data, and RAM4 is selected by the logic "1" of the same bit.

Reference numeral 6 denotes an input / output address decoder, which decodes address data output from the CPU 2 via the address bus A and selects one of the key input device 7 and the display device 8. The address decoder 6 outputs one of the chip select signals CS1 and CS2 according to the decoding result, and selects the key input device 7 or the display device 8. The address output to the memories (ROM3, RAM4) is directly output without passing through the address decoder 6. Key input device 7
Is constituted by a predetermined key arrangement such as a numeric keypad or a full keyboard, and the display device 8 is constituted by a liquid crystal display or the like.

Reference numerals 9 and 10 denote OR circuits, which supply a read signal R and a write signal W to the key input device 7 and the display device 8, respectively. When performing input / output to / from the key input device 7 and the display device 8, the CPU 2 outputs an input / output address corresponding to any of them, selects one of these via the address decoder 6, and inputs / outputs it. The read signal R and the write signal W are output to the key input device 7 and the display device 8 via the OR circuits 9 and 10 in response to the output.

Reference numerals 11 and 12 are also OR circuits, such as ROM3 and RAM4.
The read signal R and the write signal W are supplied. ROM3,
In the case of input / output to / from the RAM 4, the same read signal R and write signal W are supplied to the ROM 3 and the RAM 4 by the OR circuits 11 and 12.

Whether input / output to / from the memory or input / output to / from the key input device 7 or the display device 8 is controlled by a memory request signal M to an i / o request signal i / o of the CPU 2.

The input / output data itself is controlled by a data bus D common to each device.

The CPU 2, ROM 3, RAM 4, and other peripheral supply control devices (not shown) are composed of C-MOS elements. The problem with the configuration shown above is that elements such as the CPU 2 and the RAM 4 can significantly reduce power consumption by switching the clock to a low frequency by the clock generator 1.
Is that the power consumption hardly changes even with a low frequency clock.

Therefore, it is conceivable that, among the programs stored in the ROM 3, for example, a key input analysis routine that is always used is transferred to the RAM 4, and the processing is executed on the RAM 4. This allows considerable power savings, but in a system that has a dynamic RAM refresh function, such as Z-80, and a direct I / O instruction to peripheral devices, and where input / output to peripheral devices and memory is not clearly distinguished, There are the following problems.

The reason is that specific data is output to the upper 8 bits of the address bus as a side effect at the time of memory refresh and at the time of a direct input / output instruction to peripheral devices. There is that. When the ROM3 is chip-selected, a large current flows through the sense amplifier, which increases power consumption.

In view of the above, in the present embodiment, the processing software is transferred from the ROM to the RAM, and the clock speed is reduced in a routine that does not require high-speed processing.
The chip select of the ROM is completely inhibited at the time of refreshing the data or at the time of input / output to / from a peripheral device.

Hereinafter, the operation in the above configuration will be described in detail.
2 to 4 are flowcharts showing the control procedure of the CPU 2 of FIG. 1. The procedure of FIGS. 2 to 4 is stored in the ROM 3 as a control program of the CPU 2 and transferred to the RAM 4 as described later. It is used.

In the present embodiment, when power is supplied for the first time due to battery replacement or the like, or when the reset key K1 in FIG. 1 is pressed, the CPU 2 is reset, and step S1 in FIG.
The following processing is executed.

In step S1, CPU 2 and RAM 4 and all other i / o devices are initialized, and the process proceeds to step S2.

When the power key K2 is pressed and the CPU 2 enters the standby state, the process proceeds to step S2. Details of step S2 are shown in FIG. Here, the processing of step S2 in FIG. 2 will be described with reference to FIG.

In step S21 in FIG. 3, the initial settings of the i / o device and the RAM 4 are performed, and the process proceeds to step S22. In step S22, ROM3
Key input wait processing program stored in RAM4
Then, in step S23, 0FFH (hexadecimal number) is set in the i-register, which is an internal register of the Z-80, and the selection of the ROM 3 when the CPU 2 outputs the refresh signal is prohibited. This is because Z-80 outputs the contents of the i register to the upper address bus at the time of refresh. Note that i
The register is also used in the Z-80 as a register for storing the upper byte of the interrupt vector.

Referring again to FIG. 2, a key input waiting process is performed in step S3. Here, it operates with a low-frequency clock from the oscillator X2. This processing operates on the RAM 4, and the detailed processing procedure will be described with reference to FIG.

In the processing using the low-speed clock, care is taken so that the ROM 3 is not chip-selected during data input / output. Such a chip select can occur at the time of a direct input / output command as described above.

That is, there are two types of Z-80 i / o access.
One is a direct access method of OUT (n), A in A, (n), and the other is a register indirect access method of OUT (c), A in A, (c). These transfer the contents of the A register to the port addresses 0 to 255 indicated by (n) to (c), but the data output to the address bus A in these input / output instructions is In fact, it looks like this:

That is, the port address is 8 bits from 0 to 255 as described above, and is indicated by the 8-bit data n (immediate data) or the contents of the C register. This data is output to the lower 8 bits of the address bus. At this time, the upper 8 bits of the address bus output the contents of the A register in the direct access method and the contents of the B register in the register indirect access method.

That is, in the Z-80, when peripheral input / output is performed by the IN and OUT instructions, a specific chip in the address space is selected according to the immediate data n or the contents of the B register. Actually, the upper 8 bits of these address data are unnecessary for the IN and OUT instructions, so that the data can be set so that the ROM 3 is not chip-selected.

In this embodiment, the above-mentioned register indirect access is always used at the time of direct input / output, and the contents of the B register are stored in the most significant bit A1 of the address bus prior to the IN and OUT instructions.
Input / output processing such as key scan and key read is performed after 5 is set to a value that is not set to 0 (for example, 1xxxxxxxB (binary number)). In this manner, the activation of the chip select terminal of the ROM 3 during key scan or key read can be prohibited.

In step S31 of FIG. 4, 0FFH is set in the B register, and then in step S32, the i / o address is set in the C register, and the flow shifts to step S3.

In step S33, a key scan signal is output, and the flow shifts to step S34. In step S34, a key line is read to determine whether or not a key has been pressed. If the key has not been pressed, the process proceeds to step S35 to perform cursor processing, and then returns to step S31. If the key of the key input device 7 has been pressed, the process proceeds to step S4 in FIG.

In step S4 of FIG. 2, processing of the pressed key is performed. Subsequently, in step S5, display processing after each key processing is performed, and the process returns to step S3.

According to the above control, the routine used regularly is
By transferring the data to the ROM 3 or the RAM 4 and using it without requiring a speed, the clock speed is reduced, and furthermore, the chip select for the ROM is completely prohibited, so that a thorough reduction in power consumption is possible. Since it is not necessary to use a special type of ROM, the manufacturing cost can be reduced.

In the above embodiment, one ROM and one RAM are used. However, it goes without saying that the same effect can be obtained even if there are a plurality of ROMs and RAMs.

In particular, with regard to RAM, semiconductor manufacturers have internal synchronous static RAM and completely asynchronous static RAM.
In the former case, if the CPU clock is lowered, the power consumption will decrease in proportion to it, whereas in the latter case, it can not be said that the power consumption will decrease in proportion to the decrease in the clock.
Therefore, when such two types of RAMs are mixed, a program waiting for key input is transferred to the former RAM and the processing is performed on the former RAM, and the CPU clock at this time is set to a low frequency. When refreshing the CPU or performing key scans, use the same asynchronous static
If the selection of the RAM or ROM chip select is prohibited, the same effect as in the above embodiment can be obtained.

In the embodiment of FIG. 1, two oscillators are used to change the frequency of the clock supplied to the CPU at the time of waiting for key input and at other times. However, as shown in FIG. The same operation can be performed using only the oscillator.

5 is a high frequency oscillator similar to the oscillator X1 in FIG. 1, and determines the oscillation frequency of the oscillation circuit 1 '. The oscillation circuit 1 'supplies a high frequency clock to the frequency dividing circuit 51 and the lock selecting circuit 52.

The frequency dividing circuit 51 divides the inputted high frequency clock by a factor of 1 to convert it into a low frequency clock, and inputs it to the clock selecting circuit 52. The dividing ratio to be divided by the dividing circuit 51 can be fixed to a specific number, or can be set to an arbitrary number in a program executed by the CPU 2 in FIG. 1 using a preset counter. it can. With such a configuration, either the oscillation circuit 1 'or the clock divided by the frequency dividing circuit 51 can be selected via the clock selecting circuit 52 in accordance with the processing.

The memory map in the embodiment of FIG. 1 is shown in FIG. 6A. If the ROM 3 is set at the lowest level and the RAM 4 is set at the highest level as shown in FIG. Is not implemented, by setting the address of the free area of the memory map in the i register in step S23 of FIG. 3, the refresh of the CPU 2 is performed in the free area, so that the power consumption at the time of refreshing is minimized. Become.

Also, in the case of a memory configuration in which a removable card (or cassette type) RAM area 4 'is set between the ROM 3 and the RAM 4 as shown in FIG. If the refresh address, i.e., the i-register is set according to the processing procedure described above, the power consumption of the CPU 2 at the time of refresh can be made very small.

In FIG. 7, in step S76, arbitrary data is written to the area of the card RAM in order to determine whether or not the card RAM is mounted, and the process proceeds to step S77.

In step S77, the data written in step S76 is read from the card RAM, and it is determined whether the data read in step S78 is correct. If it is not correct, it is determined that the card has not been installed,
The refresh address of PU2 is set in the mounting area 4 'of the card RAM4.

On the other hand, if the correct data is read out in step S78, the refresh address is set in the area of the RAM 4 because the card RAM is mounted and the RAM is not necessarily the C-MOS static RAM of the internal synchronous system.

Here, the card has been described as a RAM card, but the processing procedure is the same even if the card is a ROM card, and the presence or absence of the card may be determined by a keyword on the card.

In the first embodiment, the CPU 2 has been described as a Z-80 for convenience of explanation. However, the embodiment can be similarly applied to a CPU of another C-MOS.

In particular, National Semiconductor's NSC800 (trade name)
In such a CPU, as shown in FIG. 8, the control signals S0 and S1 of the CPU are input to the decoder 13, and the address is decoded only during the input / output period to / from the memory, and the chip is selected. It is possible to prohibit the chip select of the memory from being activated when accessing the i / o device.

The address decoder 13 is an address decoder with a gate, which receives an address signal, a S0 signal, and an S1 signal from the CPU, and reads the ROM 3 or the RAM only during the CPU cycle for the memory.
Activate the chip select signal of 4.

Further, in the embodiment shown in FIG. 1, a configuration was described in which the current consumption of the RAM was reduced in proportion to the slowing down of the clock of the CPU. If it is possible to use the CPU, a program for performing a process of waiting for a key input is stored in this ROM instead of the RAM of the first embodiment. Power can be reduced.

Further, in the embodiment of FIG. 1, a processing program waiting for key input is executed from the ROM 3 by the RA only in step S22 of FIG.
Although transferred to M4, step S5 in FIG. 2 and step S35 in FIG. 3 are followed by step S2 in FIG.
2, the same program transfer processing as in S23 may be inserted. Further, the same processing as steps S22 and S23 in FIG. 3 may be executed at regular intervals by a timer interrupt or the like.

[Effects of the Invention] As is clear from the above, according to the present invention, the CPU, the RO
ROM or RAM composed of M, RAM and peripheral devices
Means for switching the frequency of the basic operation clock of the device to a plurality of stages in an electronic device that performs data input / output between the above-described components according to a program stored in the ROM, and fixedly stored in a ROM at the start of device operation. A routine that is used relatively routinely and does not require high-speed processing is transferred to the RAM, and then the basic operation clock is switched to a low frequency by the switching means during the operation of the routine. The RO
Since a configuration having control means for prohibiting access to M is adopted, power consumption is reduced by running a predetermined routine on RAM and lowering the frequency of a basic operation clock at that time. During operation, power consumption can be reduced by prohibiting ROM access. Even if a ROM that does not reduce power consumption even if a low-frequency clock is used can be expected to sufficiently reduce power consumption, there is no risk of increasing the manufacturing cost. In addition, when high-speed processing is required, the clock can be switched to a high frequency as appropriate, and there is an excellent effect that processing efficiency is not reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an electronic device according to the present invention, FIGS. 2 to 4 are flowcharts showing processing procedures of the electronic device in FIG. 1, and FIG. 6 (A) to 6 (C) are block diagrams showing an embodiment.
Is a memory map diagram for explaining another embodiment according to the present invention, FIG. 7 is a flowchart showing another embodiment according to the present invention, and FIG. 8 is a block diagram showing still another embodiment according to the present invention. DESCRIPTION OF SYMBOLS 1 ... Clock generator, 2 ... CPU 3 ... ROM, 4 ... RAM 5 ... Inverter 6, 13 ... Address decoder 7 ... Key input device, 8 ... Display device 13 ... Address decoder

Claims (1)

(57) [Claims] 1. An electronic apparatus comprising a CPU, a ROM, a RAM, and a peripheral device and performing data input / output between the respective components according to a program stored in the ROM or the RAM, the frequency of a basic operation clock of the apparatus. Means for switching to a plurality of stages, and a routine which is used relatively regularly among programs fixedly stored in the ROM at the start of operation of the apparatus and which does not require high-speed processing is transferred to the RAM. An electronic apparatus, comprising: a control unit that switches a basic operation clock to a low frequency by the switching unit and that prohibits access to the ROM during the operation of the routine.